Pulse width modulation system, method and microcontroller

Abstract

The invention relates to a pulse width modulation system, a pulse width modulation method and a microcontroller. The method includes generating, by a first timer, a drive (QA) signal and an event signal indicating timing of the QA signal based on a primary timer signal. The method includes providing the event signal to a second timer to cause the second timer to store the event signal to generate a stored event signal. The method includes maintaining a fixed phase difference between a QA signal and a QC signal by generating, by a second timer, a drive (QC) signal based on a main timer signal and an event signal during a first set of periods of the QA signal. The method includes applying a current to the load based on a fixed phase difference between the QA signal and the QC signal.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of U.S. Provisional Application No. 63 / 667,042, entitled “Generating Complex PWM Sequences for Power Control Applications”, filed July 2, 2024, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of electronics, and more particularly to systems and methods for generating complex pulse width modulation (PWM) sequences for power control applications. Background Technology

[0004] A microcontroller is a compact integrated circuit designed to manage specific operations in embedded systems. Microcontrollers typically include a processor, memory, and input / output peripherals on a single chip, making them ideal for controlling devices such as home appliances, automotive systems, and industrial machinery. Pulse width modulation (PWM) waveforms are a key feature of many microcontrollers, enabling them to control the power delivered to various components. By adjusting the duty cycle of the PWM signal, microcontrollers can efficiently manage motor speed, battery charging, and other analog functions. This technique is highly efficient because it minimizes power loss and heat generation, making it a popular choice in digital control systems. Overall, the combination of microcontrollers and PWM waveforms enables precise and efficient control in a wide range of applications. Summary of the Invention

[0005] According to one aspect of the present invention, a method is provided, comprising: generating a drive (QA) signal and an event signal indicating the timing of the QA signal by a first timer based on a master timer signal; providing the event signal to a second timer such that the second timer stores the event signal to generate a stored event signal; maintaining a fixed phase difference between the QA signal and the QC signal by generating a drive (QC) signal by the second timer based on the master timer signal and the event signal during a first set of periods of the QA signal; and applying a current to a load based on the fixed phase difference between the QA signal and the QC signal.

[0006] According to another aspect of the present invention, a microcontroller is provided, comprising: a first timer; a second timer; and a master timer coupled to the first timer and the second timer, wherein the master timer is configured to provide a master timer signal to the first timer, wherein the first timer is configured to: generate a drive (QA) signal and an event signal indicating the timing of the QA signal based on the master timer signal; and provide the event signal to the second timer; wherein the second timer is configured to: maintain a fixed phase difference between the QA signal and the QC signal by generating a drive (QC) signal based on the master timer signal and the event signal during a first set of cycles of the QA signal; and a PWM generator configured to apply current to a load based on the fixed phase difference between the QA signal and the QC signal.

[0007] According to another aspect of the present invention, a pulse width modulation (PWM) system is provided, the PWM system comprising: a plurality of timers, the plurality of timers including a counter; and one or more multiplexers coupled among the plurality of timers, wherein the plurality of timers are configured to: generate a drive (QA) signal and an event signal indicating the timing of the QA signal; and store the event signal in the counter; maintain a fixed phase difference between the QA signal and the QC signal by generating a drive (QC) signal based on the event signal in the counter during a first set of cycles of the QA signal; and apply a current to a load based on the fixed phase difference between the QA signal and the QC signal. Attached Figure Description

[0008] The disclosure is illustrated by way of example rather than limitation in the accompanying drawings, in which similar reference numerals refer to similar elements, and in the accompanying drawings:

[0009] Figure 1 A block diagram of an example phase-shifted full-bridge on-board charger (PSFB-OBC) system according to some implementations is shown.

[0010] Figure 2 The following are examples of implementations from [the document / method / etc.]. Figure 1 The signal diagram of the controller in the middle for generating the four-stage drive signals (QA-QD) for a single cycle;

[0011] Figure 3 A signal diagram of the drive signals (QA-QD) when the power output level changes, according to some embodiments, is shown;

[0012] Figure 4 The following are illustrated according to some embodiments. Figure 1A block diagram of the controller in the diagram; and

[0013] Figure 5 The diagram illustrates different events occurring at various locations according to some implementation methods. Figure 4 The signal diagram of the output signal of each timer in the timer. Detailed Implementation

[0014] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of the various implementations of the techniques described herein for generating complex pulse width modulation (PWM) sequences for power control applications. However, it will be apparent to those skilled in the art that at least some implementations can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the techniques described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the scope of this disclosure.

[0015] Phase-shifted full-bridge (PSFB) drivers require two complementary PWM channels operating synchronously to generate a precise phase difference. Low-cost microcontrollers often struggle to accomplish this task for several reasons. First, their standard PWM channels lack multi-channel synchronization features, making it impossible to synchronize the start of the timer using only software. Second, it is difficult to modify the PWM period of the control signal during phase transitions. Third, the PWM sequence must be maintained even during phase transitions between control signals, but conventional timers cannot be stopped. Fourth, even if the timer stops and is quickly restarted with a new cycle, the dead time generation is not negligible. Fifth, stopping and restarting the timer every PWM cycle requires a per-PWM-cycle interrupt and extremely high CPU frequency to update the parameters. Sixth, using interrupts as an alternative is unreliable because it can lead to unpredictable delays. The inability of conventional systems to maintain the necessary accuracy results in inefficiencies and potential problems in the power conversion process.

[0016] This disclosure addresses the aforementioned and other shortcomings by generating complex pulse width modulation (PWM) sequences for power control applications based on one or more multiplexers (e.g., one or more trigger multiplexers) and multiple timers. This embodiment uses a combination of a standard PWM channel and another peripheral device, referred to as a "trigger multiplexer," to synchronize the PWM channel and perform automatic phase and duty cycle updates. This solution can be implemented entirely in hardware and is interrupt-independent. By using a combination of two types of peripheral devices (e.g., timers and trigger multiplexers), this embodiment generates complex signals with accurate periods.

[0017] This implementation can have several applications, including but not limited to active rectifiers, asymmetric converters, motor control, various custom H-bridge topologies, multiphase converters, inverters, state machines for timing sequences, and continuously variable signal and current control logic.

[0018] In an illustrative embodiment, the microcontroller includes a first timer, a second timer, and a master timer. The master timer is configured to provide a master timer signal to the first timer. The first timer is configured to generate a drive (QA) signal and an event signal indicating the timing of the QA signal based on the master timer signal. The first timer is configured to provide the event signal to the second timer. The second timer is configured to maintain a fixed phase difference between the QA and QC signals by generating a drive (QC) signal based on the master timer signal and the event signal during a first set of cycles of the QA signal. The microcontroller includes a PWM generator for applying current to a load based on the fixed phase difference between the QA and QC signals. For example, the PWM generator can charge a battery according to a specific charging rate based on the fixed phase difference between the QA and QC signals.

[0019] In another illustrative embodiment, the microcontroller includes an arrangement of multiple identical timers. A master timer (sometimes referred to as Timer-1) generates signals for a second timer (sometimes referred to as Timer-2), a third timer (sometimes referred to as Timer-3), a fourth timer (sometimes referred to as Timer-4), and a fifth timer (sometimes referred to as Timer-5). A sixth timer (sometimes referred to as Timer-6) generates drive signals QA and QB based on signals from the second timer. A seventh timer (sometimes referred to as Timer-7) generates drive signals QC and QD based on signals from the second and fourth timers.

[0020] One purpose of the disclosed trigger multiplexer is to transfer signals from one timer to another. The creation or action of any signal event is programmed in the timer configuration, which can be changed in real time. During normal operation, the sixth and seventh timers can continuously generate a fixed phase difference and deliver a fixed amount of power to charge the battery. When a change in power level is required, the processor can set the timer configuration in a phase adjuster (which comprises multiple timers) that receives its inputs in real time from one or more analog-to-digital converters (ADCs) and the desired control topology (e.g., proportional-integral-derivative (PID)). These values ​​are stored in a timer configuration buffer until each individual timer performs its operation within its own time, thus maintaining the output in the desired sequence. Drive signals QA, QB, QC, and QD (sometimes referred to herein as output signals QA, QB, QC, and QD) can be used to drive the electrical devices controlling different steps in the charging of the EV battery.

[0021] Figure 1 A block diagram of an example phase-shifted full-bridge on-board charger (PSFB-OBC) system according to some embodiments is shown. The PSFB-OBC system 100 includes a signal source 101 electrically coupled to a rectifier circuit 103. The rectifier circuit 103 is electrically coupled to a power factor correction circuit 130. The power factor correction circuit 130 is electrically coupled to a high-voltage storage capacitor 116. The high-voltage storage capacitor 116 is electrically coupled to a PSFB 106. The PSFB 106 is electrically coupled to a load 150. In some embodiments, the load 150 may be a battery for an electric vehicle.

[0022] PSFB 106 includes transistors 107 (Q1), 108 (Q2), 109 (Q3), 110 (Q4), 111 (SR1), 112 (SR2), 113 (SR3), and 114 (SR4). Transistors 107 through 114 can be based on any conventional transistor technology, including, for example, silicon carbide metal-oxide-semiconductor field-effect transistors (SiCMOSFETs). PSFB 106 includes inductors 125 (Lw) and 120 (Lo). PSFB 106 includes a power supply 127, a capacitor 118, and a transformer 128. The specific implementation depends on the design goals and may include various additional sub-circuits.

[0023] The PSFB-OBC system 100 includes a controller 102 (e.g., a microcontroller) electrically coupled to an AC / DC power factor correction circuit 130 and a drive isolator 104. The drive isolator 104 is electrically coupled to the PSFB 106.

[0024] Controller 102 receives signals from an interface such as a Controller Area Network (CAN) bus. Controller 102 and AC / DC power factor correction circuit 130 send and receive power factor correction (PFC) signals to and from each other. Controller 102 sends drive signals (QA-QD) to PSFB 106. Specifically, controller 102 sends a QA signal to transistor 107 (Q1), a QC signal to transistor 108 (Q2), a QB signal to transistor 110 (Q4), and a QD signal to transistor 109 (Q3). Controller 102 also sends rectified signals to transistors 111 (SR1), 112 (SR2), 113 (SR3), and 114 (SR4).

[0025] Therefore, the PSFB-OBC system 100 integrates two advanced technologies to enhance electric vehicle (EV) charging. The PSFB 106 is a high-efficiency DC-DC converter that uses phase-shift control to achieve zero-voltage switching, minimizing switching losses and improving overall efficiency. The on-board charger (OBC) is used to convert AC power to DC power, which can then be used to charge the EV's battery. By combining these technologies, the PSFB-OBC system ensures efficient and safe power conversion. This integration not only optimizes the charging process but also contributes to the sustainability and performance of electric vehicles.

[0026] Figure 2 The following are examples of implementations from [the document / method / etc.]. Figure 1 The controller in the diagram is used to generate (e.g., produce) four stages of drive signals for a single cycle. Specifically, signal diagram 200 shows the QA, QB, QC, and QD signals. The QB signal is the complement of the QA signal, and the QD signal is the complement of the QC signal.

[0027] Signal diagram 200 also shows the four different stages through transistors QA-QD ( Figure 1 The directions of the current in transistors 107 to 110 are: (1) forward phase; (2) forward freewheeling phase; (3) reverse phase; and (4) reverse freewheeling phase. In some embodiments, this sequence can be maintained sequentially for proper operation. Signal diagram 200 shows a phase difference between the rising edge of the QA signal and the rising edge of the QC signal. Controller 102 adjusts this phase difference to regulate the current driven by PSFB 106 to load 150. In some embodiments, this current may be referred to as the transformer primary current because it is generated at transformer 128 and directed toward load 150. Refer below to Figure 4 Additional details describe the technique used by controller 102 to adjust the phase difference.

[0028] In addition, in an embodiment where the load 150 is a battery, the controller 102 can adjust the phase difference to adjust the rate at which the PSFB 106 charges the battery. For example, the controller 102 can increase the phase difference to increase the rate at which the PSFB 106 charges the battery, and decrease the phase difference to decrease the rate at which the PSFB 106 charges the battery.

[0029] Figure 3 A signal diagram of drive signals (QA - QD) when the power output level changes according to some embodiments is shown. Note that, according to some embodiments, it is shown on a time scale larger than Figure 2 to show how phase updates can occur. The phase difference between signals QA and QD is indicated by D. The signal diagram 300 shows four repeated stages that occur four times from 11 to 14, 21 to 24, 31 to 34, and 41 to 44. In each cycle, the first stage corresponds to the forward stage (i.e., 11, 21, 31, 41), the second stage corresponds to the forward freewheeling stage (i.e., 12, 22, 32, 42), the third stage corresponds to the reverse stage (i.e., 13, 23, 33, 43), and the fourth stage corresponds to the reverse freewheeling stage (i.e., 14, 24, 34, 44).

[0030] A new phase is activated at time slot 31, where the phase difference D changes to D'. The time period of the drive signal QC is shown by the period T. When preparing to update the phase from 31, the period of QC changes only within one cycle (22 to 31) as shown by t' < T.

[0031] The signal diagram 300 shows that the PSFB 106 charges the battery during a specific time period within each of the four stages. When the phase difference occurs at time slot 31, different currents start to flow.

[0032] Figure 4 shown according to some embodiments Figure 1 ​​A block diagram of the controller is shown below. Controller 102 includes an analog-to-digital converter (ADC) 408 and a central processing unit (CPU) 409. As discussed herein, controller 102 includes multiple timers. Specifically, controller 102 includes a master timer 401 configured to generate a continuous signal (e.g., a master control signal). Controller 102 includes a phase generator 402 configured to generate a phase difference between a first drive signal (e.g., QA signal, QB signal) and a second drive signal (e.g., QC signal, QD signal). Controller 102 includes a phase updater 403 configured to function as a phase updater. Controller 102 includes a period switcher 404 configured to function as a period switcher. Controller 102 includes an update request 405 configured to function as an update request timer. Controller 102 includes a PWM generator 406, which is configured to function as a timer for the PWM generator 406. Controller 102 also includes a PWM generator 407, which is configured to function as a timer for the PWM generator 407. In some embodiments, the phase generator 402, phase updater 403, period switcher 404, update request 405, PWM generator 406, and PWM generator 407 may each be configured as a one-shot circuit, such that they each generate a single output pulse of a specified duration in response to an input trigger signal.

[0033] Figure 4 Each timer shown is configured to receive multiple input signals and generate multiple output signals according to its configuration. Input signals can indicate start or stop events, period changes, duty cycle changes, etc. Output signals can be complementary PWM, period-matched signals, duty cycle-matched signals, interrupt signals, etc. Each timer includes its own internal counter to allow the timer to keep track of the time associated with events. Figure 4 As shown, apart from each timer being configured to perform a different function, all timers (e.g., Timer-1, Timer-2, ..., Timer-7) are symmetrical. Below is about... Figure 4 Additional description of the timer.

[0034] Phase updater 403 loads the next duty cycle (from CPU 409) for phase generator 402 to perform phase updates. Cycle switcher 404 loads temporary cycles and recovery values ​​(e.g., calculated timing value 1 and calculated timing value 2), which are reloaded after a specific delay from update request 405.

[0035] Specifically, controller 102 uses fast and frequent calibration. For example, one PWM cycle can be 3.8 microseconds. Controller 102 performs calibration every 10 PWM cycles, resulting in a normal sequence (e.g., Figure 5 Event 1) occurs 260,000 times per second, and the update sequence (e.g., Figure 5 Event 6) occurs 26,000 times per second. These rapid phase updates (known as feedback control loops) are used to correct errors caused by voltage fluctuations, voltage surges, noise, and / or temperature drift.

[0036] CPU 409 calculates error and load timer values. That is, once the update sequence is complete (e.g., ...). Figure 5 Events 6 to 13 in the table), update request 405 sets an interrupt for CPU 409 (e.g., Figure 5 Event 14 in the code prepares for the next update. Once CPU 409 has no other tasks, it attempts an interrupt, calculates the error, and calculates a timer value for future updates (e.g., for...). Figure 5 Timers 2, 3, 4, 7, etc. in the system, which include transition / temporary states (e.g., Figure 5 Events 9 to 13 in the text.

[0037] Next, CPU 409 preloads the configuration into the shadow register of each timer (e.g., timers 2, 3, 4, 7, etc.). This can happen at any time after point 14 due to the lengthy / complex mathematics involved. Once loaded, CPU 409 is again free to perform other tasks. This is one of the key advantages compared to hardware interrupt-based technologies, which require a very fast CPU to complete calculations within a very short time window (known as cycle-by-cycle). However, CPU 409 in controller 102 is allowed to handle interrupts at its own time start point 14 and in the next update sequence (e.g., ... Figure 5 Event 6) in the process is completed before it begins. Therefore, the slow CPU 409 is sufficient to perform these operations.

[0038] When the next update sequence is from Figure 5 When event 6 begins, an automatic triggering of the event occurs in phase adjuster 440, which triggers the shadow register to take effect at the end of the event, thus causing... Figure 5 Point 13 (or Figure 3 A new phase difference begins at time slot 31.

[0039] Update request 405 initiates the next phase update procedure by generating an interrupt / ADC trigger.

[0040] Controller 102 includes a PWM generator 406 that generates a positive drive signal and a negative / complementary drive signal with dead time, both of which are used for control. Figure 1 The transistors in PSFB 106 (e.g., transistors 107, 108, 109, 110, 111, 112). Controller 102 includes a PWM generator 407 that generates a positive drive signal and a negative / complementary drive signal, both of which are also used for control. Figure 1 The transistor in the PSFB 106 is driven by a PWM signal.

[0041] In some implementations, phase generator 402, phase updater 403, cycle switcher 404, update request 405, PWM generator 406 and / or PWM generator 407 may each be configured to generate a timer with a precise time delay or interval based on its input signal.

[0042] The controller includes a trigger multiplexer (mux) 430 for use in Figure 4 Signals are transmitted between each of the components shown. Trigger multiplexer 430 is a digital bus system configured to use a multiplexing addressing system to transmit signals from one component (e.g., a timer, ADC, CPU) to another component. Trigger multiplexer 430 is also configured to route signals from one point to another.

[0043] Controller 102 can support two operating modes: normal sequence and update sequence. In the normal sequence, controller 102 operates master timer 401, phase generator 402, PWM generator 406, and PWM generator 407. In the update sequence, controller 102 operates phase updater 403, period switcher 404, and update request 405 to load new values ​​into one or more timers.

[0044] Still refer to Figure 4 Phase generator 402 receives a master timer signal (T_1_X) from master timer 401. Phase generator 402 generates two signals (e.g., T_2_6, T_2_7) based on the master timer signal (T_1_X). Phase generator 402 provides event signals to PWM generators 407, 406 via trigger multiplexer 430 to induce pulse width modulation. PWM generators 406, 407 store values ​​that result in PWM outputs (e.g., QA-QC signals) with different delays.

[0045] During the normal sequence, PWM generators 406 and 407 generate QA-QC signals based on the master timer signal and event signals to maintain a fixed phase difference between the QA and QC signals during the first set of cycles. Controller 102 charges the battery according to a specific charging rate based on the fixed phase difference between the QA and QC signals.

[0046] During the update sequence, controller 102 adjusts the phase difference between the QA and QC signals by loading values ​​into phase adjuster 440 and PWM generator 407. This adjustment is activated according to a timing event chain in phase update 403, cycle switcher 404, update request 405, and PWM generator 407. After the update, a new phase difference is seen in the QA-QC signal. This new phase difference charges the battery with a different current than in the previous cycle.

[0047] In some implementations, the PWM generator 407 and the phase adjuster 440 can receive an event signal during the period in which they actively generate the QC signal. For example, the PWM generator 407 may be in the middle of its generation cycle when it receives the event signal, and can optionally delay activation to maintain sequence order, such as... Figure 3 As shown.

[0048] Phase adjuster 440 generates signals T_5_ADC, T_4_7A, T_4_7B, T_3_1, and T_5_X based on the master timer signal. The generation of these multiple signals causes a phase update sequence to occur (e.g., ...). Figure 3 (As shown in time slot 31). Signal T_5_X causes phase updater 403 and period switcher 404 to start counting, resulting in the generation of signals T_4_7A, T_4_7B, and T_3_1 based on the value loaded by CPU 408. In response to receiving signal T_3_1, phase generator 402 generates signal T_2_7, which causes the generation of QC signal. Furthermore, as Figure 3 As shown in time slots 22 to 32, signals T_4_7A and T_4_7B cause periodic transitions in the QC signal.

[0049] Phase adjuster 440 generates a third trigger signal (T_3_1) and a fourth trigger signal (T_4_7A) based on the master timer signal (T_1_X) and a second delay value. Phase adjuster 440 provides the third trigger signal to phase generator 402 and the fourth trigger signal to PWM generator 407.

[0050] During the next cycle of the second set of cycles of the QA signal, controller 102 generates the QA signal from phase generator 402 based on the master timer signal and the third trigger signal, maintaining a fixed phase difference between the QA signal and the QC signal. PWM generator 407 generates the QC signal based on the master timer signal, the fourth trigger signal, and / or stored event signals.

[0051] Figure 5 This illustrates the different events occurring at various locations according to some implementation methods. Figure 4 The signal diagram shows the output signals of each timer in the diagram. Event 1 (the falling edge of the master timer 401) starts the phase generator 402. Event 2 (the rising edge of the phase generator 402) starts the PWM generator 406. Event 3 is the start signal for the PWM generator 406. Event 4 (the falling edge of the phase generator 402) starts the PWM generator 407. Events 3 and 5 correspond to the start of the PWM generators 406 and 407, respectively.

[0052] When a phase change is required, the update sequence is activated. Event 6, which occurs as the rising edge of the master timer 401 (e.g., this only occurs at the end of the cycle of the phase updater 403 and / or the cycle switcher), initiates the next update process in the phase generator 402 and the PWM generator 407 by using the phase updater 403 and the cycle switcher 404 as intermediate signals.

[0053] Event 6, occurring as the rising edge of the master timer 401, initiates the counting process in the phase updater 403. Event 7 occurs after a delay. Event 7, occurring as the rising edge of the phase updater 403, initiates a second delay, resulting in event 10.

[0054] Event 6 also initiates the counting process in phase switcher 404. Event 8 occurs after the delay. Event 8, which is the rising edge of phase switcher 404, begins the second delay, leading to event 12.

[0055] Event 10, which is the falling edge of phase updater 403, causes event 11. Event 11 loads a new duty cycle into phase generator 402. Event 8, which is the rising edge of cycle switcher 404, causes event 9. Event 9 loads a new cycle into PWM generator 407 and stores the current value (switch).

[0056] Event 12, which is the falling edge of the cycle switch 404, triggers event 13. Event 13, which is the rising edge of the PWM generator 407, causes a swap back to the previously stored value from event 9.

[0057] Event 14 occurs when an interrupt is generated for CPU 409 for ADC sampling and other control processes such as proportional-integral-derivative (PID) control. The next update value is loaded into the timer (this will take effect in the next event 6).

[0058] In the above description, some parts of the specific implementation are presented according to the algorithms and symbolic representations of operations on analog signals and / or digital signals or data bits in non-transitory storage media. These algorithmic descriptions and representations are means used by those skilled in the art of data processing to most effectively convey the essence of their work to others skilled in the art. Here, an algorithm is generally conceived as a self-consistent sequence of steps that produces a desired result. These steps require physical operations on physical quantities. Although not mandatory, these quantities are usually in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for general reasons.

[0059] In the description, references to "implementation," "one implementation," "example implementation," "some implementations," and "various implementations" indicate that a particular feature, structure, step, operation, or characteristic described in connection with an implementation is included in at least one implementation of this disclosure. Furthermore, the appearance of the phrases "implementation," "one implementation," "example implementation," "some implementations," and "various implementations" in various positions in the specification does not necessarily refer to the same (one or more) implementations.

[0060] The specification includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Combinations of embodiments may be made, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0061] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless specifically stated as is evident from the above discussion, it should be understood that throughout the description, discussions using terms such as “receive,” “determine,” “generate,” “provide,” “maintain,” “charge,” etc., refer to the actions and processes of an integrated circuit (IC) controller or similar electronic device that manipulate data represented as physical (e.g., electronic) quantities in the controller’s registers and memories and convert that data into other data similarly represented as physical quantities in the controller’s memory or registers or other such non-transitory information storage media.

[0062] The terms “example” or “exemplary” are used herein to mean as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concept in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or becomes clear from the context, “X comprises A or B” is intended to mean any natural substitution of inclusion. That is, if X comprises A; X comprises B; or X comprises both A and B, then “X comprises A or B” is satisfied in any of the foregoing cases. Additionally, unless otherwise specified or clearly indicated by the context to be a singular form, unmodified terms as used in this application and claims should generally be interpreted as “one or more.” Furthermore, the use of the terms “implementation” or “an embodiment” or “implementation” throughout the document is not intended to mean the same implementation or implementation unless so described.

[0063] The embodiments described herein may also relate to means for performing the operations described herein (e.g., AC-DC converters and / or ESD protection systems / circuits). Such means may be specifically constructed for desired purposes or may include firmware or hardware logic selectively activated or reconfigured by the means. Such firmware may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "computer-readable medium" should also be considered to include any medium capable of storing, encoding, or carrying instructions that are executed by a machine and cause the machine to perform any one or more of the methods of this embodiment. The term "computer-readable storage medium" should therefore be considered to include, but is not limited to, solid-state memory, optical media, magnetic media, and any medium capable of storing a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of this embodiment.

[0064] The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of several embodiments of this disclosure. It should be understood that the foregoing description is intended to be illustrative and not restrictive. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the foregoing description. Therefore, the scope of this disclosure should be determined by reference to the claims and the full scope of their equivalents.

Claims

1. A method comprising: generating, by a first timer based on a master timer signal, a drive (QA) signal and an event signal indicative of timing of the QA signal; providing the event signal to a second timer to cause the second timer to store the event signal to generate a stored event signal; maintaining a fixed phase difference between the QA signal and a drive (QC) signal during a first set of cycles of the QA signal by generating, by the second timer based on the master timer signal and the event signal, the QC signal; and applying current to a load based on the fixed phase difference between the QA signal and the QC signal.

2. The method of claim 1, wherein, Applying current to the load further comprises charging a battery according to a particular charging rate, and the method further comprises: adjusting a phase of the QC signal to produce a different fixed phase difference between the QA signal and the QC signal after the first set of cycles of the QA signal; maintaining the different fixed phase difference between the QA signal and the QC signal during a second set of cycles of the QA signal after the first set of cycles of the QA signal; and charging the battery according to a lower charging rate based on the different fixed phase difference.

3. The method of claim 1, wherein, The second timer receives the event signal when the second timer is actively generating cycles of the QC signal.

4. The method of claim 2, wherein, The second set of cycles of the QA signal includes a first cycle and a next cycle after the first cycle, and the method further comprises: calculating, by a processing device, a first delay value specific to the first cycle in the second set of cycles and a second delay value specific to the next cycle in the second set of cycles; and providing, by the processing device to a phase adjuster, a phase update signal including the first delay value and the second delay value.

5. The method of claim 4, further comprising: generating, by the phase adjuster based on the master timer signal and the first delay value, a first trigger signal and a second trigger signal; and providing the first trigger signal to the first timer and the second trigger signal to the second timer.

6. The method of claim 5, further comprising: maintaining the different fixed phase difference between the QA signal and the QC signal during the first cycle in the second set of cycles of the QA signal by: generating, by the first timer based on the master timer signal and the first trigger signal, the QA signal; and generating, by the second timer based on the master timer signal, the second trigger signal, and the stored event signal, the QC signal.

7. The method of claim 4, further comprising: generating, by the phase adjuster based on the master timer signal and the second delay value, a third trigger signal and a fourth trigger signal; and providing the third trigger signal to the first timer and the fourth trigger signal to the second timer.

8. The method of claim 7, further comprising: ​ ​ ​ during a next cycle of a second set of cycles of the QA signal, the different fixed phase difference between the QA signal and the QC signal is maintained by: generating, by the first timer, the QA signal based on the master timer signal and the third trigger signal; and generating, by the second timer, the QC signal based on the master timer signal, the fourth trigger signal, and the stored event signal.

9. The method of claim 4, wherein, The second delay value offsets the first delay value's previous effect on at least one of the QA signal or the QC signal.

10. The method of claim 1, wherein, The event signal is provided to the second timer via one or more multiplexers.

11. A microcontroller comprising: a first timer; a second timer; and a master timer coupled to the first timer and the second timer, wherein the master timer is configured to provide a master timer signal to the first timer, wherein the first timer is configured to: generate a drive (QA) signal and an event signal indicative of a timing of the QA signal based on the master timer signal; and provide the event signal to the second timer; wherein the second timer is configured to: during a first set of cycles of the QA signal, maintain a fixed phase difference between the QA signal and a drive (QC) signal by generating the QC signal based on the master timer signal and the event signal; and a PWM generator configured to apply a current to a load based on the fixed phase difference between the QA signal and the QC signal.

12. The microcontroller of claim 11, wherein, To apply the current to the load, the PWM generator is further to charge a battery according to a particular charging rate, and the microcontroller further comprises: a phase adjuster configured to adjust a phase of the QC signal to produce a different fixed phase difference between the QA signal and the QC signal after the first set of cycles of the QA signal; and wherein the second timer is further configured to: maintain the different fixed phase difference between the QA signal and the QC signal during a second set of cycles of the QA signal after the first set of cycles of the QA signal; and wherein the PWM generator is further configured to: charge the battery according to a lower charging rate based on the different fixed phase difference.

13. The microcontroller of claim 11, wherein, The second timer is further configured to: receive the event signal when the second timer is actively generating a cycle of the QC signal.

14. The microcontroller of claim 12, wherein, The second set of cycles of the QA signal includes a first cycle and a next cycle after the first cycle, and the microcontroller further comprises a processing device configured to: calculate a first delay value specific to the first cycle of the second set of cycles and a second delay value specific to the next cycle of the second set of cycles; and provide a phase update signal comprising the first delay value and the second delay value to the phase adjuster. The phase adjuster is further configured to:

15. The microcontroller of claim 14, wherein, generate a first trigger signal and a second trigger signal based on the master timer signal and the first delay value; and generate a third trigger signal based on the master timer signal and the second delay value. providing the first trigger signal to the first timer and the second trigger signal to the second timer.

16. The microcontroller of claim 15, wherein, the first timer is further configured to generate the QA signal based on the master timer signal and the first trigger signal; and the second timer is further configured to generate the QC signal based on the master timer signal, the second trigger signal, and the event signal.

17. The microcontroller of claim 14, wherein, the phase adjuster is further configured to: generate a third trigger signal and a fourth trigger signal based on the master timer signal and the second delay value; and provide the third trigger signal to the first timer and the fourth trigger signal to the second timer.

18. The microcontroller of claim 17, wherein, the first timer is further configured to generate the QA signal based on the master timer signal and the third trigger signal; and the second timer is further configured to generate the QC signal based on the master timer signal, the fourth trigger signal, and the event signal.

19. The microcontroller of claim 11, wherein, the first timer provides the event signal to the second timer via one or more multiplexers.

20. A pulse width modulation (PWM) system, the pulse width modulation system comprising: a plurality of timers including a counter; and one or more multiplexers coupled between the plurality of timers, wherein the plurality of timers are configured to: generate a drive (QA) signal and an event signal indicative of a timing of the QA signal; and store the event signal in the counter; maintain a fixed phase difference between the QA signal and a drive (QC) signal during a first set of cycles of the QA signal by generating the QC signal based on the event signal in the counter; and apply a current to a load based on the fixed phase difference between the QA signal and the QC signal.

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