Groove type power device and preparation method thereof

Abstract

The invention relates to a groove type power device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; the substrate internally comprises gate trench structures and source trench structures which are alternately arranged along a first direction parallel to the first surface of the substrate; the gate trench structure comprises a gate oxide layer located on the inner surface of the gate trench and a conductive material layer filled in the residual gate trench; forming side wall structures located on the side surface of the conductive material layer and first grooves located between the adjacent side wall structures on the first surface; the top surface of the gate oxide layer is located in the bottom surface of the side wall structure; after an etching protection layer is formed in the first groove, removing part of the conductive material layer between the adjacent side wall structures to form a gate conductive layer and a second groove with the bottom surface lower than the first surface; after the etching protection layer is removed, a dielectric layer at least filling the second groove is formed; and forming a front metal layer on the first surface and the top surface of the dielectric layer. The reliability of the device and the consistency of parameters can be effectively improved, and the process manufacturing difficulty is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a trench power device and its fabrication method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) have advantages such as fast switching speed, low loss, and simple driving circuits, and are widely used in fields such as new energy conversion, motor drive, and high-frequency power supply.

[0003] In fields requiring high voltage, high frequency, high power, high temperature, and radiation resistance, SiC materials, due to their excellent properties, demonstrate strong application potential in high-power devices, making them the preferred substrate material for fabricating high-performance power MOSFETs. With the continuous iteration of semiconductor process technology, the structural design of silicon carbide MOSFETs has gradually completed the technological upgrade from planar gate to trench gate, further breaking through the bottleneck of device performance.

[0004] However, the current development of silicon carbide MOSFETs is moving towards smaller size, higher power, and better performance: the continuous miniaturization of the physical size of the device leads to a continuous reduction in the photolithographic feature size of the cell region, which can easily lead to poor gate oxide reliability or process stability, thereby affecting the core performance of the device such as reliability and current transmission stability, and in severe cases, even causing device failure. Summary of the Invention

[0005] Therefore, it is necessary to provide a trench-type power device and its fabrication method to address the technical problems in the existing technology, which can at least improve the integrity of the device structure while reducing the difficulty of manufacturing process.

[0006] In a first aspect, this application provides a method for fabricating a trench-type power device, comprising: providing a substrate; the substrate including gate trench structures and source trench structures alternately arranged along a first direction parallel to a first surface of the substrate; the gate trench structure including a gate oxide layer located on the inner surface of the gate trench, and a conductive material layer filling the remaining gate trenches; the top surface of the conductive material layer being higher than the first surface;

[0007] On the first surface, a sidewall structure is formed on the side surface of the conductive material layer, and a first groove is formed between adjacent sidewall structures; the top surface of the gate oxide layer is located inside the bottom surface of the sidewall structure.

[0008] After forming an etched protective layer in the first groove, a portion of the conductive material layer located between adjacent sidewall structures is removed to form a gate conductive layer and a second groove with a bottom surface lower than the first surface.

[0009] After removing the etched protective layer, a dielectric layer is formed that at least fills the second groove;

[0010] A front metal layer is formed on the top surface of the first surface and the dielectric layer.

[0011] In the fabrication method described above, a sidewall structure is formed by utilizing the height difference between the conductive material layer filling the gate trench structure and the source trench structure. On one hand, this sidewall structure can directly physically shield the gate oxide layer, preventing damage from subsequent processes. On the other hand, it provides a clear reference for the filling position of the etching protective layer. When a partial removal process is performed on the conductive material layer within the gate trench structure, the gate oxide layer and the source trench structure can effectively avoid etching damage, ensuring the integrity of the structure.

[0012] In some embodiments, the substrate includes a source region and a body region arranged sequentially along a direction toward the substrate via a first surface;

[0013] The formation of the gate trench structure includes:

[0014] A source trench structure is formed in the substrate, extending through the source region and the body region in a direction toward the substrate, and arranged at intervals in a first direction;

[0015] After forming a mask stack on the first surface between adjacent source trench structures, the mask stack is patterned.

[0016] Based on the mask stack, after forming a gate trench structure in the substrate, the mask stack is removed.

[0017] In some embodiments, the mask stack includes a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked along a direction away from the substrate;

[0018] The material of the first oxide layer is the same as that of the gate oxide layer.

[0019] In some embodiments, forming a dielectric layer that fills the second groove includes:

[0020] A dielectric material layer is formed in the first surface and the second groove. A planarization process is used to remove part of the dielectric material layer, and the remaining dielectric material layer covers the first surface and fills the second groove to form a dielectric layer.

[0021] In some embodiments, forming a front metal layer includes removing a portion of the dielectric layer using self-aligned etching, such that the dielectric layer remains only in the second groove.

[0022] A front metal layer is formed covering the first surface, the top surface of the dielectric layer, and the outer surface of the sidewall structure.

[0023] In some embodiments, forming a front metal layer includes:

[0024] A contact hole is formed that penetrates the dielectric layer in the direction toward the substrate, and the bottom surface contacts the first surface. The orthographic projection of the contact hole on the first surface is located within the first surface between adjacent sidewall structures.

[0025] A front metal layer is formed on the top surface of the dielectric layer and inside the contact hole.

[0026] In some embodiments, the sidewall structure is removed before the dielectric layer is formed;

[0027] Forming a dielectric layer that at least fills the second groove includes:

[0028] A dielectric material layer is formed within the first surface and the second groove;

[0029] Remove the dielectric material layer whose top surface is higher than the first surface, and use the remaining dielectric material layer to form the dielectric layer.

[0030] In some embodiments, after the gate trench is formed, the thickness of the remaining mask stack ranges from 3000 Å to 5500 Å;

[0031] The bottom width of the sidewall structure ranges from 0.1μm to 0.2μm.

[0032] In some embodiments, the substrate further includes:

[0033] The shielding region surrounds the contact interface between the source trench structure and the substrate, and its top surface is in contact with the bottom surface of the bulk region.

[0034] The bottom surface of the source trench structure is lower than the bottom surface of the gate trench structure;

[0035] The bottom surface of the grid trench structure is lower than the bottom surface of the body region;

[0036] The top surface of the gate conductive layer is not lower than the top surface of the body region.

[0037] Secondly, this application also provides a trench-type power device, fabricated using the method described in any of the above embodiments. In the above embodiments, the sidewall structure simplifies the precision dependence of processes such as photolithography and etching, reduces the impact of minute deviations on the overall device, improves manufacturing tolerance, and effectively improves the yield of mass production of the device, providing reliable process support for the development of trench-type power devices towards smaller size and higher integration.

[0038] The trench-type power device and its fabrication method provided in this application have the following unexpected technical effects:

[0039] In fabricating the gate conductive layer, compared to the related processes of directly etching away excess conductive material, this application utilizes the height difference between the conductive material layer filling the gate trench structure and the source trench structure to form a sidewall structure that directly physically shields the gate oxide layer, avoiding damage during the removal of the conductive material layer, effectively avoiding etching damage, and ensuring the integrity of the structure. Furthermore, by employing a self-aligned etching process or the sidewall structure itself, the distance between the contact holes and the channel is limited, ensuring the consistency and stability of device parameters while effectively reducing the dependence on photolithographic overlay accuracy and simplifying the manufacturing process.

[0040] Furthermore, the trench-type device provided in this application improves the electric field distribution inside the device by adding a shielding region at the bottom of the source trench, thus alleviating the problem of electric field concentration in the gate oxide layer at the bottom of the gate trench and mitigating the electric field concentration problem in the gate oxide layer from a structural perspective. This device structural design works synergistically with the above-mentioned fabrication method to further reduce the risk of gate oxide layer breakdown due to excessively high electric fields, ultimately significantly improving gate oxide reliability. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a flowchart of a method for fabricating a trench-type power device provided in one embodiment;

[0043] Figure 2a This is a cross-sectional schematic diagram of the structure obtained after forming the body region and the source region in step S1022 of the preparation method provided in one embodiment;

[0044] Figure 2b This is a cross-sectional schematic diagram of the structure obtained after forming the shielding area in step S1022 of the preparation method provided in one embodiment;

[0045] Figure 3 This is a schematic cross-sectional view of the structure obtained after forming the source trench structure in step S1024 of the preparation method provided in one embodiment;

[0046] Figure 4 This is a schematic cross-sectional view of the structure obtained after the patterned mask is stacked in step S1026 of the preparation method provided in one embodiment;

[0047] Figure 5a This is a schematic cross-sectional view of the structure obtained after forming the gate trench in step S1028 of the preparation method provided in one embodiment;

[0048] Figure 5b This is a schematic cross-sectional view of the structure obtained after removing the mask stack in step S1028 of the preparation method provided in one embodiment;

[0049] Figure 6 This is a schematic cross-sectional view of the structure obtained after forming the sidewall structure in step S104 of the preparation method provided in one embodiment;

[0050] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming an etched protective layer in step S106 of the preparation method provided in one embodiment;

[0051] Figure 8 This is a schematic cross-sectional view of the structure obtained after forming the dielectric layer in step S1082 of the preparation method provided in one embodiment;

[0052] Figure 9 This is a cross-sectional schematic diagram of the structure obtained after partially removing the dielectric layer in step S1084 of the preparation method provided in one embodiment;

[0053] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the front metal layer in step S110 of the preparation method provided in one embodiment;

[0054] Figure 11 This is a cross-sectional schematic diagram of the structure obtained after forming a contact hole in step S110 of the preparation method provided in another embodiment;

[0055] Figure 12 for Figure 11 A cross-sectional schematic diagram of the structure obtained after the front metal layer is formed;

[0056] Figure 13 This is a schematic cross-sectional view of the structure obtained after removing the sidewall structure in step S106 of the preparation method provided in another embodiment;

[0057] Figure 14 for Figure 13 A schematic diagram of the cross-section of the structure after the formation of the dielectric layer;

[0058] Figure 15 for Figure 14 A cross-sectional schematic diagram of the structure obtained after the front metal layer is formed;

[0059] Figure 16 This application provides an internal electric field distribution diagram for a trench-type power device.

[0060] Figure 17 The breakdown voltage curve of the trench power device provided in this application;

[0061] Figure 18The transfer characteristic curve of the trench power device provided in this application;

[0062] Figure 19 The output characteristic curve of the trench-type power device provided in this application.

[0063] Explanation of reference numerals in the attached figures:

[0064] 1. Initial substrate; 2. Epitaxial layer; 10. Substrate; 21. Bulk region; 22. Source region; 23. Shielding region; 301. Source trench; 30. Source trench structure; 31. Insulating layer; 32. Filling layer; 40. Mask stack; 41. First oxide layer; 42. Nitride layer; 43. Second oxide layer; 501. Gate trench; 50. Gate trench structure; 51. Gate oxide layer; 521. Conductive material layer; 52. Gate conductive layer; 61. Sidewall structure; 62. First groove; 63. Etching protection layer; 64. Second groove; 65. Dielectric layer; 70. Front metal layer. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0068] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0071] Please see Figure 1 This application provides a method for fabricating a trench-type power device, comprising: steps S102-S110.

[0072] Step S102: Provide a substrate; the substrate includes gate trench structures and source trench structures arranged alternately along a first direction parallel to the first surface of the substrate; the gate trench structure includes a gate oxide layer located on the inner surface of the gate trench, and a conductive material layer filled in the remaining gate trenches; the top surface of the conductive material layer is higher than the first surface.

[0073] Step S104: On the first surface, a sidewall structure located on the side surface of the conductive material layer and a first groove located between adjacent sidewall structures are formed; the top surface of the gate oxide layer is located inside the bottom surface of the sidewall structure.

[0074] Step S106: After forming an etched protective layer in the first groove, remove part of the conductive material layer located between adjacent sidewall structures to form a gate conductive layer and a second groove with a bottom surface lower than the first surface.

[0075] Step S108: After removing the etched protective layer, a dielectric layer is formed that at least fills the second groove.

[0076] Step S110: Form a front metal layer on the top surface of the first surface and the dielectric layer.

[0077] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0078] The above steps are explained in detail with reference to the attached diagram.

[0079] For ease of understanding, in this embodiment, the substrate may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a first direction parallel to the first surface of the substrate and a second direction toward the substrate are defined. The first and second directions are perpendicular to each other. The first direction is defined as the Y-axis direction, the direction toward the substrate is defined as the Z-axis direction, and depth and thickness are used to characterize the dimensions along the OZ direction, while width is used to characterize the dimensions along the OY direction.

[0080] Example 1

[0081] Please see Figures 2a-5b In step S102, the extension step includes:

[0082] Step S1022: An N-type doped epitaxial layer 2 is formed on the top surface of the initial substrate 1 to form substrate 10. Subsequently, the body region 21 and source region 22 of the MOS device are formed by ion implantation, as shown in the specific structure. Figure 2a As shown. Source trenches 301 connected to source region 22 are etched using a mask to form source trenches 301 spaced apart along the OY direction and penetrating source region 22 and body region 21 along the OZ direction; then, P-type ion implantation is performed within the source trenches 301 to form shielding region 23; then, a carbon film (not shown) is deposited, followed by furnace tube annealing. The specific structure is as follows. Figure 2b As shown.

[0083] For example, the doping concentration and thickness of epitaxial layer 2 depend on the device breakdown voltage requirements; body region 21 can be formed by implanting p-type ions, such as aluminum (Al), with implantation energies of 40 keV-900 keV and doses of 1e12cm. -3 -1e14cm -3 Angle 0°, temperature 500℃, number of injections 3-8, injection depth 0.8μm-1.0μm; source region 22 can be formed by implanting N-type ions, such as nitrogen (N) and phosphorus (P), with an implantation energy of 25keV-250keV and a dose of 1e14cm. -3 -1e16cm -3The implantation angle is 0°, the temperature is 500℃, the number of implantations is 3-8, the implantation depth is 0.4μm-0.6μm, and the P-type doping concentration at the boundary with the source region is controlled at 1e17cm. -3 -3e17cm -3 It should be understood that when the epitaxial layer is P-type doped, the above method can be used as a reference, simply by interchangeing "P" and "N" in each step of the above method.

[0084] For example, the material of substrate 10 can be replaced according to the specific power device. In this embodiment, the material of substrate 10 is silicon carbide (SiC).

[0085] For example, the source trench 301 has an etching depth of 2.0 μm-3.0 μm, a width of 0.35 μm-0.7 μm, and an angle of 88.5°-90°, preferably 89.5°. In some embodiments, the sidewalls of the source trench 301 can be repaired using a sacrificial oxygen process and / or a hydrogen (H2) repair process; wherein the sacrificial oxygen process temperature is 1100°C-1200°C, and the H2 repair process temperature is 1350°C-1450°C.

[0086] For example, the ion implantation energy for forming the shielding region 23 is 40 keV-120 keV, and the dose is 5e14cm. -3 -5e15cm -2 Angle 0°-7°, temperature 500℃, number of injections 2-5, injection depth at the bottom of source trench 301 0.5μm-1.0μm.

[0087] For example, the annealing temperature is 1650℃-2000℃, the annealing time is 5min-30min, and the carbon film is removed after annealing.

[0088] Step S1024: An insulating layer 31 covering the inner surface of the source trench 301 is formed by a deposition process, followed by a filling layer 32 to fill the remaining gaps. Then, an etch-back process is performed to remove the insulating layer 31 and the filling layer 32 on the first surface 10a, thus forming the source trench structure 30. The specific structure is as follows: Figure 3 As shown.

[0089] For example, the above structure was formed using chemical vapor deposition (CVD).

[0090] For example, in this embodiment, the insulating layer 31 is made of silicon oxide (SiO2) with a thickness of 800 Å-1500 Å; the filling layer 32 is made of polycrystalline silicon with a thickness of 4000 Å-8000 Å.

[0091] Step S1026: After depositing and forming a mask stack 40 on the first surface 10a between adjacent source trench junctions 30, the mask stack is etched and patterned using patterned photoresist, and then the photoresist is removed. The specific structure is as follows. Figure 4 .

[0092] For example, the mask stack 40 includes a first oxide layer 41, a nitride layer 42, and a second oxide layer 43 sequentially stacked along the ZO direction. The first oxide layer 41 is made of silicon oxide (SiO2) with a thickness of 20 Å-100 Å; the nitride layer 42 is made of silicon nitride (SiN) with a thickness of 500 Å-1000 Å; and the second oxide layer 43 is also made of silicon oxide (SiO2) with a thickness of 1 μm-2 μm.

[0093] Step S1028: Using the mask stack 40 as an etching mask for the gate trench 501, a portion of the substrate 10 is removed to form the gate trench 501, as shown in the specific structure. Figure 5a Subsequently, the gate trench sidewalls are repaired using sacrificial oxygen and / or H2 repair processes. After forming the gate oxide layer 51 and conductive material layer 521 through thermal oxidation or atomic layer deposition (ALD), the conductive material layer 521 is etched back or chemical mechanical polishing (CMP) is used to make it flush with the mask stack. Finally, the mask stack is etched away. The specific structure is as follows: Figure 5b As shown.

[0094] For example, the spacing between the gate trench 501 and the source trench structure 30 along the OY direction is 0.3μm-0.6μm, the depth is 1.3μm-1.6μm, the width is 0.35μm-0.7μm, and the angle is 88.5°-90°. In this embodiment, the angle is 89.5°. Additionally, it is necessary to ensure that the depth of the gate trench 501 is greater than the depth of the body region 21 by 0.3μm, and the depth difference between the gate trench 501 and the source trench structure 30 is between 0.7μm and 1.4μm.

[0095] It should be understood that the specific height of the conductive material layer within the gate trench 501 is related to the thickness of the mask stack 40, while the thickness of the sidewall structure 61 material subsequently filled within the conductive material layer is related to the height difference between the conductive material layer and the first surface. That is, the greater the height difference, the thicker the sidewall structure 61 material, and the larger the bottom width of the remaining sidewall structure 61 during the isotropic etching process. In this embodiment, the total thickness of the remaining mask stack 40 after etching the gate trench 501 is 3000Å-5500Å, ensuring that the bottom width of the subsequent sidewall structure 61 is 0.1μm-0.2µm.

[0096] For example, in this embodiment, the gate oxide layer 51 is made of silicon oxide (SiO2) with a thickness of 500 Å-800 Å; the conductive material layer 521 is made of N-type doped polysilicon with a thickness of 4000 Å-8000 Å before being etched back, and the recess depth of the polysilicon after etching back is less than 500 Å. The conductive material layer 521 and the gate oxide layer 51 are used to form the gate trench structure 50.

[0097] For example, the second oxide layer 43, the nitride layer 42, and the first oxide layer 41 within the mask stack 40 are removed sequentially using dry or wet etching. If the gate oxide layer 51 is etched excessively, it can be improved or eliminated by increasing the thickness of the nitride layer 42.

[0098] The extended step of step S104 includes: forming a silicon nitride layer on the first surface 10a and etching it back to form a sidewall structure 61 located on the side surface of the conductive material layer 521, and a first groove 62 located between adjacent sidewall structures 61, as shown in the specific structure. Figure 6 As shown.

[0099] In the extended step of step S106, an etching protective layer 63 is formed in the first groove 62, and then a portion of the conductive material layer 521 is removed by dry or wet etching to form a gate conductive layer 52 and a second groove 64 with a bottom surface lower than the first surface 10a. The specific structure is as follows: Figure 7 As shown.

[0100] For example, an etch protection layer 63 can be formed using a spin coating process, the material of which includes, but is not limited to, a low-viscosity polymer or a photoresist. Due to the height difference, the etch protection layer 63 is confined to the first surface 10a not covered by the sidewall structure 61 and the top surface of the source trench structure 30, and the filler layer 32 (i.e., polysilicon) within the source trench structure 30 is not removed.

[0101] For example, the top surface of the gate conductive layer 52 is 0.15 μm lower than the first surface and 0.1 μm higher than the junction of the source region 22 and the body region 21.

[0102] In the above embodiments, compared to the related technologies that directly etch the polysilicon material within the gate trench using a mask stack and then remove the mask stack, the process steps provided in this application effectively avoid damage to the gate oxide layer when removing the silicon oxide material within the mask stack. Simultaneously, the sidewall structure enhances the protection of the gate oxide layer during etching, thereby ensuring the overall quality of the gate oxide layer and preventing premature breakdown or other gate oxide reliability issues caused by gate oxide layer defects.

[0103] The extension step of step S108 includes:

[0104] Step S1082: After removing the etched protective layer 63, a dielectric material layer is formed in the first surface and the second groove 64, and reflow densification is performed at a temperature of 900℃-950℃ for 20min-40min; subsequently, a planarization process is used to remove part of the dielectric material layer, and the remaining dielectric material layer covers the first surface 10a and fills the second groove for the dielectric layer 65, as shown in the specific structure. Figure 8 As shown.

[0105] For example, the thickness of the dielectric material layer is 6000Å-10000Å.

[0106] Step S1084: A portion of the dielectric layer 65 is removed using self-aligned etching, leaving the dielectric layer 65 only within the second groove. The specific structure is as follows: Figure 9 As shown.

[0107] In the extension step of step S110, a front metal layer 70 is formed covering the first surface 10a, the top surface of the dielectric layer 65, and the outer surface of the sidewall structure 61. The specific structure is as follows: Figure 10 As shown. In the above embodiments, the sidewall structure ensures that the distance between the contact hole and the channel is consistent, guaranteeing the consistency and stability of device parameters.

[0108] In some embodiments, after step S110, the trench-type power device is subjected to conventional thinning and deposition of a back metal layer. For example, the material of the back metal layer (not shown) includes, but is not limited to, titanium (Ti), nickel (Ni), or silver (Ag). Of course, a contact resistance improvement process is also included before the formation of the back metal surface; however, since this is a standard procedure in the art, it will not be elaborated upon here.

[0109] Example 2

[0110] Please see Figures 11-12 , Figure 11 This illustrates a trench-type power device obtained in step S110 of another embodiment, which is identical to steps S102, S104, S106, and S108 of Embodiment 1. In this embodiment, during the fabrication of the front metal layer, a contact hole is formed that penetrates the dielectric layer 65 along the OZ direction and contacts the first surface 10a at its bottom surface. Figure 11 As shown, the orthographic projection of the contact hole onto the first surface 10a lies within the first surface 10a between adjacent sidewall structures 61; subsequently, a front metal layer is formed on the top surface of the dielectric layer 65 and within the contact hole, as shown in the specific structure. Figure 12 As shown.

[0111] Compared to Embodiment 1, the sidewall structure 61 indirectly increases the process window of the front metal layer 70, ensuring that the gate trench structure 50 and the source region 22 will not be short-circuited.

[0112] Example 3

[0113] Please see Figure 13 , Figure 13 This demonstrates a trench-type power device obtained in step S106 of another embodiment. Similar to steps S102 and S104 of Embodiment 1, after forming the body region 21 and source region 22 within the substrate 10, a source trench structure 30, a gate trench structure 50, a sidewall structure, and an etch-protected layer 63 covering the first surface 10a between adjacent sidewall structures 61 are formed. In the extended step of step S106, the sidewall structure is removed using a wet process to obtain the following... Figure 13 The trench-type power device shown.

[0114] Similar to steps S108 and S110 in Embodiment 1, the difference is that in Embodiment 3, after removing the etched protective layer, a dielectric material layer is formed on the first surface 10a and in the second groove, and then reflow densification is performed; subsequently, a planarization process is used to remove part of the dielectric material layer, its surface is ground flat, and then the dielectric material layer is etched by self-alignment so that only the second groove remains for the dielectric layer 65, the specific structure is as follows. Figure 14 A front-side metal layer is deposited based on the above structure, the specific structure of which is as follows: Figure 15 As shown.

[0115] Compared to Example 1, Example 3 uses a self-aligned hole etching process to ensure that the distance from the contact hole to the channel is consistent.

[0116] In some embodiments, this application also provides a trench-type power device, fabricated using the fabrication method described in any of the foregoing embodiments. Please refer to... Figures 16-19 ,in, Figure 16 The diagram shows the internal electric field distribution of the trench power device provided in this application. As can be seen from the figure, in the blocking state, the highest electric field is distributed at the bottom of the source trench structure, which effectively protects the oxide layer at the bottom of the trench gate. At the same time, the thickness of the insulating layer in the source trench is greater than that of the gate oxide layer, which improves the reliability of the device. Figure 17 correspond Figure 16 The breakdown voltage curve of the trench power device shown in the figure; Figure 18 This is the transfer characteristic curve of the trench power device; Figure 19 The output characteristic curve of this trench power device is shown when the gate voltage (Vg) is set to 15V.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of manufacturing a trench power device, characterized by, The method comprises: providing a substrate; the substrate comprises gate trench structures and source trench structures arranged alternately along a first direction parallel to a first surface of the substrate; the gate trench structure comprises a gate oxide layer on an inner surface of a gate trench, and a conductive material layer filled in the rest of the gate trench; a top surface of the conductive material layer is higher than the first surface; on the first surface, a side wall structure is formed on a side surface of the conductive material layer, and a first recess is formed between adjacent side wall structures; a top surface of the gate oxide layer is inside a bottom surface of the side wall structure; after forming an etching protection layer in the first recess, a part of the conductive material layer between adjacent side wall structures is removed, forming a gate conductive layer, and a second recess with a bottom surface lower than the first surface; after removing the etching protection layer, a dielectric layer is formed to fill the second recess; a front metal layer is formed on the first surface and a top surface of the dielectric layer.

2. The production method according to claim 1, characterized by, the substrate comprises a source region and a body region arranged sequentially through the first surface in a direction towards the substrate; forming the gate trench structure comprises: forming source trench structures in the substrate, extending through the source region and the body region in a direction towards the substrate, and arranged spacedly along the first direction; after forming a mask stack on the first surface between adjacent source trench structures, the mask stack is patterned; based on the mask stack, the gate trench structure is formed in the substrate, and then the mask stack is removed.

3. The preparation method according to claim 2, characterized in that, the mask stack comprises a first oxide layer, a nitride layer, and a second oxide layer stacked sequentially in a direction away from the substrate; the material of the first oxide layer is the same as that of the gate oxide layer.

4. The preparation method according to claim 3, characterized in that, forming the dielectric layer to fill the second recess comprises: forming a dielectric material layer on the first surface and in the second recess; part of the dielectric material layer is removed by a planarization process, and the remaining dielectric material layer covers the first surface and fills the second recess to form the dielectric layer.

5. The preparation method according to claim 4, characterized in that, forming the front metal layer comprises: part of the dielectric layer is removed by a self-aligned etching, so that the dielectric layer only remains in the second recess; a front metal layer is formed to cover the first surface, a top surface of the dielectric layer, and an outer surface of the side wall structure.

6. The preparation method according to claim 4, characterized in that, forming the dielectric layer and the front metal layer comprises: forming a contact hole through the dielectric layer in a direction towards the substrate, with a bottom surface in contact with the first surface; a projection of the contact hole on the first surface is inside the first surface between adjacent side wall structures; the front metal layer is formed on a top surface of the dielectric layer and in the contact hole.

7. The preparation method according to claim 3, characterized in that, before forming the dielectric layer, the side wall structure is removed; forming the dielectric layer to fill the second recess comprises: forming a dielectric material layer on the first surface and in the second recess; the dielectric material layer with a top surface higher than the first surface is removed, and the remaining dielectric material layer is used to form the dielectric layer.

8. The method of any one of claims 2-7, wherein, after forming the gate trench, the thickness of the remaining mask stack ranges from 3000 Å to 5500 Å; The bottom width of the side wall structure ranges from 0.1 μm to 0.2 μm.

9. The method of any one of claims 2-7, wherein, The substrate further comprises: a shielding region surrounding the contact interface between the source trench structure and the substrate, and the top surface of the shielding region is in contact with the bottom surface of the body region; the bottom surface of the source trench structure is lower than the bottom surface of the gate trench structure; the bottom surface of the gate trench structure is lower than the bottom surface of the body region; the top surface of the gate conductive layer is not lower than the top surface of the body region.

10. A trench power device, characterized by, The semiconductor device is prepared by the preparation method of any one of claims 1-9.

Images