Method and device for evaluating state of computing chip, equipment and storage medium

Abstract

The application relates to a computing power chip state evaluation method and device, equipment and a storage medium. The method comprises the following steps: obtaining a target reference test frequency of a target computing power chip; based on the target reference test frequency, determining a first calculation result of an operator set of the target computing power chip according to a predetermined standard voltage, and determining a second calculation result of the operator set of the target computing power chip according to a gradient voltage bias condition; according to the first calculation result and the second calculation result, determining an error count and a first error voltage when the test operator is running; according to the error count and the first error voltage, calculating a voltage margin factor and a maximum fitting slope between an error probability and a voltage point; and according to the voltage margin factor and the maximum fitting slope of the error probability, and in combination with a state evaluation parameter priority, performing computing power chip state evaluation. The application can accurately capture data that occurs calculation errors when different voltage biases are applied, and is more conducive to improving the accuracy of computing power chip state evaluation grading.

Description

Technical Field

[0001] This application relates to the field of chip testing and evaluation technology, and in particular to methods, apparatus, equipment and storage media for evaluating the status of computing chips. Background Technology

[0002] The correct logic function of computing chips (such as GPUs) requires their supply voltage to be higher than the minimum stable voltage Vmin determined by the circuit switching speed. Vmin is affected by various factors such as process variations, voltage and temperature, and aging effects. To ensure reliable operation of the chip throughout its lifecycle under various operating conditions, suppliers adopt a worst-case voltage setting strategy, that is, setting the nominal supply voltage to the level required by Vmin after meeting the worst process corner, highest operating temperature, maximum voltage noise, and aging effects. However, this strategy results in a static and excessively redundant voltage protection band, which is applied as a uniform value to all chips shipped from the factory. For most chips in the statistical distribution of typical or fast process corners, their actual Vmin is much lower than the nominal voltage set for the worst case, resulting in a huge difference between the nominal supply voltage and the actual Vmin required by the individual chip.

[0003] To enable precise Vmin characteristic analysis and screening of large-scale, individual chips after manufacturing, existing methods primarily assess chip condition through software benchmark testing, physical probe testing (such as burn-in stress testing), and aging experiments during the manufacturing phase. However, typical software tests are not designed for Vmin characteristic analysis, cannot distinguish chip condition, are extremely difficult to elicit and observe silent data corruption, and have low evaluation accuracy. Burn-in stress testing is a destructive test designed to assess future performance; it cannot accurately measure Vmin and cannot determine the actual remaining voltage margin. Chip probe station testing directly and physically measures the precise delay of critical signal paths within the chip for design verification, failure analysis, or model calibration to address delay issues caused by manufacturing process deviations. However, it is extremely complex, costly, slow, and often destructive, making it completely unsuitable for large-scale mass production testing of packaged finished chips.

[0004] Therefore, in order to ensure that the chip works reliably throughout its entire life cycle and under various operating conditions, there is an urgent need to provide a method for evaluating the status of computing chips to solve the problem of low evaluation accuracy of computing chips in existing technologies. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for evaluating the status of computing chips, in order to solve the problem of low evaluation accuracy of computing chips in the prior art.

[0006] According to one aspect of the embodiments of this application, this application provides a state evaluation method for a computing chip, the method comprising: obtaining a target reference test frequency for a target computing chip; determining a first calculation result of an operator set for the target computing chip based on the target reference test frequency and a predetermined standard voltage, and determining a second calculation result of the operator set for the target computing chip based on a gradient voltage bias condition, the operator set including multiple test operators; determining an error count and a first error voltage during the operation of the test operators of the target computing chip based on the first calculation result and the second calculation result; calculating a voltage margin factor and a maximum fitting slope between the error probability and the voltage point for the target computing chip based on the error count and the first error voltage during the operation of the test operators; and performing a state evaluation of the computing chip based on the voltage margin factor and the maximum fitting slope of the error probability of the test operators, combined with the priority of state evaluation parameters of the target computing chip.

[0007] Optionally, obtaining the target reference test frequency of the target computing chip includes: obtaining a voltage-frequency curve based on the characteristic parameters of the target computing chip; and selecting the highest frequency at which the target computing chip does not drop frequency during operation as the target reference test frequency according to the voltage-frequency curve within the voltage operating range of the target computing chip.

[0008] Optionally, the gradient voltage bias condition includes a first voltage bias gradient and a second voltage bias gradient. The step of determining the first calculation result of the operator set of the target computing chip based on the target reference test frequency and a predetermined standard voltage, and determining the second calculation result of the operator set of the target computing chip based on the gradient voltage bias condition, includes: running test operators in the operator set based on the target reference test frequency and the predetermined standard voltage to obtain the first calculation result of the target computing chip; running test operators in the operator set based on the first voltage bias gradient based on the target reference test frequency and a preset voltage adjustment range of the target computing chip, and running the erroneous test operator based on the second voltage bias gradient when the run test operator fails, to obtain the second calculation result of the target computing chip.

[0009] Optionally, after determining the first calculation result of the operator set of the target computing chip based on the target reference test frequency and a predetermined standard voltage, and determining the second calculation result of the operator set of the target computing chip based on the gradient voltage bias condition, the method further includes: reading the first calculation result and storing the first calculation result in bits to a reference file in a target format; reading the second calculation result and storing the second calculation result in bits to a test file in the target format.

[0010] Optionally, the error count includes the total number of failed runs of the test operator and the total number of bit errors. The step of determining the error count and initial error voltage of each test operator of the target computing chip based on the first calculation result and the second calculation result includes: comparing the first calculation result of the same test operator in the reference file with the second calculation result in the test file bit by bit, detecting whether the bits in the second calculation result are flipped relative to the bits in the first calculation result, wherein each bit in the second calculation result corresponds to a voltage point; if the bits are flipped, running the test operator based on the voltage point corresponding to the bit to obtain the total number of failed runs of the test operator; collecting the number of bit flips when the test operator fails in a single run, and calculating the total number of bit errors of the test operator based on the number of bit flips; obtaining the voltage point corresponding to the first failed run of the test operator, and using the voltage point corresponding to the first failed run as the initial error voltage of the test operator.

[0011] Optionally, the step of calculating the voltage margin factor and the maximum fitting slope between the error probability and the voltage point of the target computing chip based on the error count and the first error voltage during the operation of the test operator includes: determining the failure probability of the test operator based on the total number of failures and the preset total number of runs; determining the bit error rate of the test operator based on the total number of bit errors, the preset total number of runs, and the output length of the test operator; calculating the mean failure probability and the mean bit error rate of the test operator based on the failure probability and the bit error rate after multiple runs; performing piecewise linear fitting based on the voltage point, the mean failure probability, and the mean bit error rate to obtain the maximum fitting slope of the error probability in the fitted curve, wherein the maximum fitting slope of the error probability includes: the maximum fitting slope between the voltage point and the mean failure probability and the maximum fitting slope of the mean bit error rate at the voltage point; and calculating the voltage margin factor based on the predetermined standard voltage and the first error voltage of the test operator.

[0012] Optionally, the step of evaluating the computing chip status based on the voltage margin factor of the test operator and the maximum fitting slope of the error probability, combined with the priority of the status evaluation parameters of the target computing chip, includes: calculating the target voltage margin factor of the target computing chip based on the voltage margin factors of all test operators; determining the status level corresponding to the target voltage margin factor based on the priority of the status evaluation parameters and a preset chip status allocation level; and adjusting the status level corresponding to the target voltage margin factor based on the pre-allocated slope weight, the maximum fitting slope of the voltage point and the mean of the running failure probability, and the maximum fitting slope of the mean of the bit error rate at the voltage point, to determine the status evaluation result of the target computing chip.

[0013] According to another aspect of the embodiments of this application, this application provides a state evaluation apparatus for a computing power chip. The apparatus includes: an acquisition module, configured to acquire a target reference test frequency for a target computing power chip; a first calculation module, configured to determine a first calculation result of an operator set of the target computing power chip based on the target reference test frequency and a predetermined standard voltage, and to determine a second calculation result of the operator set of the target computing power chip based on a gradient voltage bias condition, wherein the operator set includes multiple test operators; a second calculation module, configured to determine the error count and first error voltage during the operation of the test operators of the target computing power chip based on the first calculation result and the second calculation result; a third calculation module, configured to calculate a voltage margin factor and a maximum fitting slope between the error probability and the voltage point of the target computing power chip based on the error count and the first error voltage during the operation of the test operators; and a state evaluation module, configured to perform a state evaluation of the computing power chip based on the voltage margin factor and the maximum fitting slope of the error probability of the test operators, combined with the priority of the state evaluation parameters of the target computing power chip.

[0014] According to another aspect of the embodiments of this application, this application provides a computer device, including: a processor, a memory, and a network interface. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory through the network interface, and the processor executes the machine-readable instructions to perform the steps of the computing chip state evaluation method as described above.

[0015] According to another aspect of the embodiments of this application, this application provides a computer-readable medium having processor-executable non-volatile program code, the program code causing the processor to perform the steps of the state assessment method for the computing chip.

[0016] Compared with related technologies, the technical solutions provided in this application have the following advantages:

[0017] This application provides a state assessment method for computing chips. By obtaining a target reference test frequency as a deterministic parameter for subsequent assessments, it ensures that all subsequent tests are performed at the exact same frequency, making voltage the only variable and thus guaranteeing the accuracy and comparability of the calculation results. By running each test operator of the target computing chip at a fixed frequency based on gradient voltage bias conditions, the difference from the first calculation result can be accurately captured in the second calculation result. This allows for precise statistical analysis of the error count and first error voltage of each test operator, and further precise calculation of the maximum fitting slope and voltage margin factor of the error probability of the test operator. This method not only considers the voltage margin but also expresses the sensitivity of the error rate to voltage decrease through the maximum fitting slope, making the final assessment results more accurate. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the hardware environment for the state assessment method of a computing chip provided according to an embodiment of this application;

[0021] Figure 2 This is a flowchart illustrating an optional state assessment method for a computing chip according to an embodiment of this application.

[0022] Figure 3 This is a flowchart illustrating an optional step S206 provided according to an embodiment of this application;

[0023] Figure 4 This is a fitted curve of the error probability as a function of voltage points for an optional test operator provided according to an embodiment of this application;

[0024] Figure 5 This is a flowchart illustrating another optional state assessment method for a computing chip provided according to an embodiment of this application.

[0025] Figure 6 This is a schematic diagram of an optional computing chip state assessment device provided according to an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of an optional computer device structure provided for an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] To address the problems mentioned in the background art, according to one aspect of the embodiments of this application, an embodiment of a state evaluation method for computing power chips is provided.

[0029] like Figure 1 As shown, the above-mentioned state assessment method for computing chips can be applied to, for example... Figure 1 The hardware environment shown is a system architecture 100 that includes a terminal device 101 and a server 103. The server 103 is connected to the terminal device 101 via a network and can be used to provide services to the terminal or clients installed on the terminal. A database 105 can be set up on or independently of the server 103 to provide data storage services for the server 103. The network can include various connection types, such as wired, wireless communication links, or fiber optic cables, etc.

[0030] Users can use terminal device 101 to interact with server 103 via a network to receive or send messages, etc. Various communication client applications can be installed on terminal device 101, such as web browser applications, search applications, instant messaging tools, etc. Terminal device 101 can be various electronic devices with a display screen that support web browsing, including but not limited to smartphones, tablets, laptops, e-book readers, MP3 players (Moving Picture Experts Group Audio Layer III), MP4 players (Moving Picture Experts Group Audio Layer IV), laptops, and desktop computers, etc.

[0031] Server 103 can be a server providing various services, such as a backend server supporting the pages displayed on terminal device 101. The test program for the computing chip status assessment method can run directly on the server where the target computing chip is installed. It adjusts the power supply voltage and computational tasks required for the computing chip status assessment method during testing by utilizing standard, publicly available application programming interfaces provided by the chip driver or operating system. Furthermore, the computing chip status assessment method can be executed directly in the final system environment (such as a data center server) without removing the target computing chip from the motherboard. This supports regular, batch screening of the chip throughout its entire lifecycle, providing data support for characterizing chip aging trends.

[0032] It should be noted that the state assessment method for computing power chips provided in this application embodiment is generally executed by a server and / or terminal device, and correspondingly, the state assessment device for computing power chips is generally set in the server and / or terminal device.

[0033] like Figure 2 As shown, Figure 2 This is a flowchart illustrating a state assessment method for a computing chip provided in an embodiment of the present invention. Taking an example where the state assessment method for a computing chip is executed by a state assessment system jointly constructed by a host and a device, the state assessment method for a computing chip includes the following steps:

[0034] Step S202: Obtain the target reference test frequency of the target computing chip.

[0035] In this embodiment, the state assessment method for computing chips is described using the state assessment of a single computing chip. In addition, it can also be used for state assessment and screening of batch computing chips in the final use system, which can identify the aging degree of different computing chips and the voltage margin factor for continuous detection of safety in the production environment.

[0036] Because computing chips dynamically adjust their internal voltage and operating frequency according to the load (DVFS, Dynamic Voltage and Frequency Scaling) to balance performance and power consumption, allowing such dynamic adjustments during testing would result in unreliable test results. Therefore, to achieve state assessment of computing chips based on bias voltage, it is necessary to first determine the target reference test frequency for the target computing chip and create a static test environment. The target computing chip can refer to the chip requiring state assessment, and the target reference test frequency is a fixed frequency used as a quantitative measure for subsequent testing. This frequency can be specifically obtained from the voltage-frequency curve of the target computing chip.

[0037] Step S204: Based on the target reference test frequency, determine the first calculation result of the operator set of the target computing chip according to the predetermined standard voltage, and determine the second calculation result of the operator set of the target computing chip according to the gradient voltage bias condition. The operator set includes multiple test operators.

[0038] In some optional embodiments, after step S202, the method further includes creating and running a set of operators for the target computing chip. The set of operators can be general-purpose testing software or a custom set, and includes different test operators. In this embodiment, a custom set of operators is selected, including some small, standardized computational tasks. These can be selected based on an analysis of current mainstream AI models, choosing the most frequently used and representative basic computational operations to form a common set of operators. Mainstream AI models can include large language models, image recognition models, etc., and the test operators include, but are not limited to, arithmetic operations, logical operations, commonly used special functions, matrix multiplication, etc. Furthermore, the operator set adheres to the following principles: low resource consumption: each operator is designed to consume as few computational resources and memory as possible, and can be executed simultaneously on the computational units it is used in; high parallelism: the design goal is to allow the same operator to be loaded onto thousands of computational units on the chip for parallel execution, ensuring test coverage and applying pressure to all parts of the chip simultaneously; repeated execution: each operator is executed repeatedly to amplify small, sporadic computational errors caused by voltage instability, improving the detectability of errors. Each operator represents a test of a specific type of hardware path or functional unit.

[0039] Furthermore, to avoid limitations in testing, the input data required for the test operators is dynamically generated by a pseudo-random number generator. This prevents the use of fixed, patterned data from inadvertently circumventing potential hardware defects, making the testing more universal and rigorous. By running the operator set before use, potential problems such as conflicts can be identified and corrected in advance, ensuring the feasibility of each test operator and laying the foundation for the accurate and efficient operation of subsequent test operator sets.

[0040] The aforementioned predetermined standard voltage can refer to the default standard voltage of the target computing chip, or it can be understood as no voltage bias applied. The first and second calculation results include the values ​​calculated by each test operator, including scalar calculations or matrix calculations of integers, single-precision floating-point numbers, and double-precision floating-point numbers. After obtaining the target reference test frequency and running the operator set of the target computing chip, to demonstrate the change brought about by applying a voltage bias relative to not applying a voltage bias, the test operators in the operator set can first be run based on the predetermined standard voltage to generate the first calculation result, which serves as a reference value for the second calculation result.

[0041] The gradient voltage bias condition can be a voltage step-side strategy, which can be understood as applying the supply voltage in the form of a gradient, i.e., voltage bias. The gradient voltage bias condition can include at least one gradient voltage bias and corresponds to a set voltage adjustment range, for example, applying a voltage bias between 1.0V and 0.5V. Based on the obtained target reference test frequency, the supply voltage of the target computing chip can be set to the current voltage value via instructions. Each test operator is run completely once at each voltage value, thereby obtaining the second calculation result of each test operator at each voltage value.

[0042] Step S206: Based on the first calculation result and the second calculation result, determine the error count and first error voltage during the operation of the test operator of the target computing chip.

[0043] By comparing the second calculation result of each test operator corresponding to each supply voltage with the first calculation result generated without applying a supply voltage, the differences between the second and first calculation results can be collected and identified as calculation errors. This allows for the statistical counting of error counts in the second calculation results of the test operators under each supply voltage. While such errors may be masked at the application level, they expose the instability of the hardware under the current voltage. Of course, this can also be statistically analyzed through counting.

[0044] In some examples, the first error voltage can refer to the voltage value at which the test operator first experiences an operator-level failure event, which is the minimum voltage point that satisfies at least K failures in N runs. For example, if the same test operator is run 10 times at voltages of 0.95V, 0.9V, and 0.8V respectively, and at least 3 runs fail in each run, then the first error voltage is 0.8V.

[0045] In other examples, if the lower limit of the preset voltage adjustment range is detected without error, the lower limit voltage value can be retained as the first error voltage. The minimum reliable voltage at which the computing chip can operate normally is the maximum value of the first error voltage among the calculation results of all test operators.

[0046] Step S208: Based on the error count and the first error voltage during the test operator's operation, calculate the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point.

[0047] The voltage margin factor refers to the safe deviation from a predetermined standard voltage. A larger voltage margin factor indicates a larger voltage margin, meaning higher chip stability at the corresponding voltage. Conversely, a steeper fitting slope indicates lower chip stability at the corresponding voltage, as it is more sensitive to voltage fluctuations and experiences a significant increase in error rate with even slight voltage drops.

[0048] In this embodiment, the error probability of the test operator can be calculated based on the error count of each test operator during multiple repeated runs at each supply voltage, i.e., at each adjusted voltage point. Furthermore, the voltage margin factor can be calculated based on the total number of runs and the initial error voltage of each test operator during multiple repeated runs. Linear fitting is then performed based on the error probability at each voltage point, allowing the selection of the maximum fitting slope from the fitted results. The chip exhibits the worst stability at the maximum fitting slope.

[0049] Step S210: Based on the voltage margin factor and the maximum fitting slope of the error probability of the test operator, and in conjunction with the priority of the state evaluation parameters of the target computing chip, the state of the computing chip is evaluated.

[0050] In this embodiment, the voltage margin factor and the maximum fitting slope of the error probability are used as parameters for chip state evaluation. Based on the priority of the state evaluation parameters for the target computing power chip, the final evaluation level of the target computing power chip can be determined. The priority of the state evaluation parameters constrains the voltage margin factor to have a higher priority than the maximum fitting slope of the error probability. That is, during state evaluation, the voltage margin factor is used as the dominant parameter. The state evaluation is first performed based on the voltage margin factor to determine the basic level, and then adjustments are made based on the maximum fitting slope of the error probability. To maintain parameter consistency during level evaluation, both the voltage margin factor and the maximum fitting slope of the error probability can be expressed as percentages. For example, σ is the voltage margin factor, K is the maximum fitting slope of the error probability, and level A must satisfy σ% + K% ≥ 20%.

[0051] In some examples, the status assessment level of the computing chip can be divided into four levels: Level A (Excellent), Level B (Good), Level C (Average), and Level D (Poor). The calculation result of the maximum fitting slope between the voltage margin factor and the error probability is expressed as M. When M ≥ M1, the assessment is Level A; when M2 ≤ M < M1, the assessment is Level B; when M3 ≤ M < M2, the assessment is Level C; and when M < M3, the assessment is Level D. M is expressed as a percentage, and M1, M2, M3, and M4 decrease in that order.

[0052] In this embodiment, the gradient voltage bias condition during the evaluation test is explored at the lower limit of the safe operating voltage range of the chip design, rather than using extreme pressure methods such as ultra-high voltage or ultra-high temperature, thus possessing non-destructive characteristics. Furthermore, since the entire testing process is explored at the lower limit of the safe operating voltage range of the chip design, it can also be used to reduce power consumption by applying lower supply voltages to computing chips without sacrificing stability, thereby achieving energy saving.

[0053] In this embodiment of the invention, by obtaining the target reference test frequency as a deterministic parameter for subsequent evaluation, it is ensured that all subsequent tests are performed at the exact same frequency, making voltage the only variable, thereby guaranteeing the accuracy and comparability of the calculation results. By running each test operator of the target computing chip at a fixed frequency based on gradient voltage bias conditions, the difference relative to the first calculation result can be accurately captured in the second calculation result, so as to accurately count the error count and the first error voltage of each test operator, and then accurately calculate the maximum fitting slope and voltage margin factor of the error probability of the test operator. This not only takes into account the voltage margin, but also expresses the sensitivity of the error rate to voltage decrease through the maximum fitting slope, so as to make the final evaluation result more accurate.

[0054] In some optional embodiments, step S202 above includes:

[0055] S2021, Obtain the voltage-frequency curve based on the characteristic parameters of the target computing chip;

[0056] S2022, within the voltage operating range of the target computing chip, select the highest frequency at which the target computing chip does not drop frequency during operation as the target reference test frequency based on the voltage-frequency curve.

[0057] In this embodiment, to determine the voltage-frequency correlation, characteristic parameters corresponding to the model of the target computing chip can be obtained first, including tools or standard interfaces provided by the supplier. Based on the obtained characteristic parameters, the voltage-frequency curve of the target computing chip can be queried or actually measured. This curve describes the relationship between voltage and frequency within the allowable voltage operating range of the target computing chip. Furthermore, the voltage-frequency curve has a positive correlation, with each frequency point corresponding to a specific voltage.

[0058] Furthermore, based on the aforementioned relationship between voltage and frequency, the highest frequency at which the target computing chip does not drop during the entire operation can be selected from the curve. For example, the operating frequency range of computing chip U1 is 210MHz-3100MHz, but in actual operation, the highest frequency can only reach 2800MHz. Higher frequencies cannot be reached, or frequency drops will occur if they are reached. Therefore, 2800MHz will be used as the highest frequency at which the target computing chip does not drop during operation, which is also the target reference test frequency for chip U1.

[0059] In this embodiment, by first determining the voltage-frequency curve of the target computing chip, and then selecting the highest frequency at which the target computing chip does not drop frequency during the entire operation process based on the curve within the voltage operating range as the target reference test frequency, it can be ensured that all subsequent tests are conducted at the exact same frequency, making voltage the only variable, thereby ensuring the accuracy and comparability of the test results.

[0060] In some optional embodiments, step S204 above includes:

[0061] S2041, Based on the target reference test frequency, run the test operators in the operator set according to the predetermined standard voltage to obtain the first calculation result of the target computing chip;

[0062] S2042, based on the target reference test frequency and the preset voltage adjustment range of the target computing chip, run the test operators in the operator set according to the first voltage bias gradient, and when the run test operator fails, run the test operator that failed according to the second voltage bias gradient to obtain the second calculation result of the target computing chip.

[0063] In this embodiment, under a fixed target reference test frequency, without applying any voltage bias, all test operators in the operator set of the target computing chip are run through once at a preset standard voltage, and the value of each test operator is obtained. Each value is stored based on the same storage format, including binary, hexadecimal, etc., and finally the first calculation result of the target computing chip is obtained.

[0064] In this embodiment, the aforementioned gradient voltage bias conditions include a first voltage bias gradient and a second voltage bias gradient. The first voltage bias gradient can be used to perform a coarse scan by adjusting the voltage. The second voltage bias gradient can be set near the voltage at which the error occurred after the first error is detected in the test operator, based on the coarse scan. The second voltage bias gradient has a smaller voltage adjustment range and a smaller voltage gradient change compared to the first voltage bias gradient. For example, starting from the default standard voltage of 1.0V, the preset voltage adjustment range is 1.0V~0.5V, and a coarse scan is performed with a gradient of 0.05V; if the first error is observed at 0.8V, a fine scan is performed within the range of 0.8±0.1V with a gradient of 0.01V, and each test voltage will correspond to a test result. At each voltage point, the power supply voltage of the target computing chip is set to the current voltage value via an instruction. Under this voltage condition, the operator set is run once in its entirety. The test results obtained at each voltage point of the target computing chip are collected and recorded, including the result values ​​of the test operators, the actual operating voltage, frequency, temperature, etc., and it is confirmed that the instruction has been executed correctly.

[0065] In this embodiment, running the test operator based on the target reference test frequency and the predetermined standard voltage can provide a data reference basis for subsequent result comparison; running the test operator based on the first voltage bias gradient can achieve a rapid coarse scan of all test operators, so as to fully cover the detection in a short time and quickly locate the test operators that may have operational errors; when the coarse scan finds that the test operator has operational errors, a fine scan is performed based on the second voltage bias gradient, which can accurately check the error area, thereby improving the overall detection efficiency and ensuring the accurate detection of test operators, and quickly finding the test operators with calculation errors.

[0066] In some optional embodiments, after step S204 above, the method further includes:

[0067] Read the first calculation result and store the first calculation result in bits into the reference file in the target format;

[0068] Read the second calculation result and store it in bits into the test file in the target format.

[0069] In this embodiment, the first calculation result includes the result of each test operator calculated based on a predetermined standard voltage and target reference test frequency, expressed in a target format. For example, the calculation results w1~wn of test operators d1~dn under a predetermined standard voltage V0 and target reference test frequency Hz0; the second calculation result includes the result of each test operator calculated based on different voltage points and target reference test frequencies, expressed in a target format. For example, the calculation results w21~w2n of test operators d1~dn under a supply voltage V1 and target reference test frequency Hz0, the calculation results w31~w3n of test operators d1~dn under a supply voltage V2 and target reference test frequency Hz0, ..., the calculation results w21~w2n of test operators d1~dn under a supply voltage V1 and target reference test frequency Hz0, ..., the calculation results w31~w3n of test operators d1~dn under a supply voltage V2 and target reference test frequency Hz0, ..., the calculation results w21~w2n of test operators d1~dn under a supply voltage V1 and target reference test frequency Hz0, ..., the calculation results w21~w2 ... j The calculation results wj1~wjn of the test operators d1~dn at the target reference test frequency Hz0.

[0070] Furthermore, the first and second calculation results are initially stored in registers. The first and second calculation results can be read from the registers. To ensure absolute accuracy, the first and second calculation results are stored in the original binary or hexadecimal format. The first calculation result is saved to the reference file bit by bit. The reference file represents the correct result that the target computing chip should output under normal conditions and is the benchmark for all subsequent comparisons.

[0071] In this embodiment, the second calculation result is saved bit by bit to the test file. The first and second calculation results are saved in the same target format, including both in binary or both in hexadecimal. For example, under the target reference test frequency and a predetermined standard voltage, an analysis of a precision floating-point addition operator (float32_add) is performed to calculate A+B, where A=1.0, represented in hexadecimal as 0x3F800000, and B=2.0, represented in hexadecimal as 0x40000000. Then the first calculation result is 3.0, which is 0x40400000 in hexadecimal.

[0072] In this embodiment, storing the first calculation result and the second calculation structure bit by bit in the target format can ensure the absolute accuracy of the data, thereby ensuring the accuracy of subsequent result comparison and chip status evaluation.

[0073] In some alternative embodiments, combined with Figure 3 As shown, step S206 above includes:

[0074] S2061, based on bits, compare the first calculation result of the same test operator in the reference file with the second calculation result in the test file bit by bit, and detect whether the bits in the second calculation result are flipped relative to the first calculation result, wherein each bit in the second calculation result corresponds to a voltage point;

[0075] S2062, If the bit is flipped, then the test operator is run based on the voltage point corresponding to the bit to obtain the total number of failed runs of the test operator;

[0076] S2063, Collect the number of bit flips when the test operator fails in a single run, and calculate the total number of bit errors of the test operator based on the number of bit flips;

[0077] S2064, obtain the voltage point corresponding to the first failure of the test operator, and use the voltage point corresponding to the first failure as the first error voltage of the test operator.

[0078] The error count includes the total number of failed runs of the test operator and the total number of bit errors. For the same test operator, the second calculation result includes results measured at different voltage points, represented in binary or hexadecimal. The result measured at each voltage point can be compared bit-by-bit with the calculation result of the same test operator in the first calculation result to determine whether bit flips occur when the test operator is run with a voltage bias applied compared to when no bias is applied. When based on binary representation, both 0 changing to 1 and 1 changing to 0 indicate a bit flip.

[0079] Furthermore, in a single comparison, if even one bit flips, the run is recorded as a failure: E=1; a perfect match is recorded as a pass: E=0. For example, if the first calculation result in the reference file is 0x40400000 and the second calculation result in the test file is 0x40400000, the test passes, E=0; if the first calculation result is 0x40400001, the test fails, E=1, a flip has occurred, and the error count is 1. Therefore, for test operators where bit flips occur, the same test operator O can be repeatedly run under an applied voltage V to obtain the total number of runs N(V, o), the number of passes S(V, o), and the total number of failures F(V, o). Similarly, for test operators where bit flips do not occur, the run can also be repeated multiple times to obtain the corresponding total number of failures. For test operators where bit flips do not occur, the total number of failures obtained from repeated runs is usually 0.

[0080] Furthermore, when the test operator fails, the number of bit flips d(V,o) at that moment is collected, and the total number of bit errors M(V,o) can be obtained by accumulating them. Additionally, the voltage point corresponding to the first failure of the test operator is obtained and used as the first error voltage V_fe of the test operator.

[0081] In this embodiment, by comparing the second calculation result obtained at each voltage point with the first calculation result bit by bit, the total number of bit errors and the total number of running failures of the test operator of the target computing chip can be accurately captured. At the same time, the first error voltage can be accurately obtained, so as to provide accurate data support for the subsequent calculation of the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point, thereby improving the accuracy of chip status assessment.

[0082] In some optional embodiments, step S208 specifically includes:

[0083] S2081, determine the failure probability of the test operator based on the total number of failures and the preset total number of runs;

[0084] S2082, determine the bit error rate of the test operator based on the total number of bit errors of the test operator, the preset total number of runs, and the output length of the test operator;

[0085] S2083, Based on the failure probability and bit error rate of the test operator after multiple runs, calculate the mean failure probability and mean bit error rate of the test operator;

[0086] S2084, perform piecewise linear fitting based on the voltage point, the mean failure probability, and the mean bit error rate to obtain the maximum fitting slope of the error probability in the fitted curve, wherein the maximum fitting slope of the error probability includes: the maximum fitting slope based on the voltage point and the mean failure probability, and the maximum fitting slope based on the mean bit error rate of the voltage point.

[0087] S2085, calculate the voltage margin factor based on the predetermined standard voltage and the first error voltage of the test operator.

[0088] In this embodiment, for a single test operator, the failure probability P_f(V,o) is calculated based on the total number of failed runs F(V,o) and the preset total number of runs N(V,o), where P_f(V,o) = F(V,o) / N(V,o). The bit error rate P_b(V,o) of the test operator is calculated based on the total number of bit errors M(V,o), the preset total number of runs N(V,o), and the output length L_o of the test operator, where P_b(V,o) = M(V,o) / (N(V,o) * L_o), and L_o is the output length of the corresponding test operator, meaning each output is considered as L_o independent bits.

[0089] Furthermore, the average values ​​of P_f(V,o) and P_b(V,o) obtained after multiple runs of a single test operator are calculated to obtain P_f_avg(V) and P_b_avg(V). Since the supply voltage is applied based on a gradient during testing, piecewise linear fitting can be performed based on each applied voltage point and the calculated average values ​​to obtain the maximum fitting slope k_f based on the voltage point and the average failure probability, and the maximum fitting slope k_b based on the voltage point and the average bit error rate. During fitting, the voltage is expressed as a percentage. k_f and k_b are used, respectively, at the macroscopic and microscopic levels, to characterize the sensitivity of the error rate to voltage decrease. The voltage margin factor can refer to the safe deviation from the voltage V_op. After calculating the voltage margin factor σ for each test operator based on σ=(V_op-V_fe) / V_op, the average voltage margin factor can be calculated as the final voltage margin factor for the target computing chip.

[0090] Combination Figure 4 As shown, Figure 4 This is a schematic diagram showing the error probability of different test operators as a function of voltage points, provided in this embodiment. Figure 4In the diagram, P_f(V) and P_b(V) can represent the fitted curve of the voltage point versus the mean failure probability, or the fitted curve of the mean bit error rate at the voltage point. “□” represents the operator FFT2D (Two-Dimensional Fast Fourier Transform), “△” represents the operator cuBLAS-MM (CUDA Basic Linear Algebra Subprograms Matrix Multiplication), “☆” represents the operator Histogram, and “○” represents the operator Black-Scholes. During the voltage decrease, P_f(V) and P_b(V) show similar trends, remaining close to 0 until approaching a certain voltage value, after which they rise rapidly. For example... Figure 4 In the tests, the error probability of the FFT2D operator increases rapidly after 8.37% of the voltage percentage; the cuBLAS-MM operator increases rapidly after 13.02% of the voltage percentage; the BlackScholes operator increases slowly after 9.3% of the voltage percentage, and then increases rapidly after 13.02%; the Histogram operator increases slowly after 9.3% of the voltage percentage, and then increases rapidly after 12.09% of the voltage. When performing linear fitting, the maximum slope of the rising segment of the test operator's curve is obtained, which is the slope corresponding to the segment with the largest increase between two voltage points.

[0091] In this embodiment, the failure probability and bit error rate of each test operator are calculated. The error rate reflects the operational reliability of the test operator. The mean values ​​of the failure probability and bit error rate obtained after multiple runs are calculated as linear fitting data, reflecting the overall data level. This analysis is fast and highly reliable. Piecewise linear fitting is used, selecting the maximum slope. The chip is more sensitive to voltage fluctuations at the maximum slope, indicating poorer chip stability. This is used for chip status assessment, improving the accuracy of the assessment results.

[0092] In some optional embodiments, step S210 above includes:

[0093] S2101, Calculate the target voltage margin factor of the target computing chip based on the voltage margin factors of all test operators;

[0094] S2102, Based on the priority of the state evaluation parameters, determine the state level corresponding to the target voltage margin factor according to the preset chip state allocation level;

[0095] S2103, based on the pre-allocated slope weight, the maximum fitting slope of the voltage point and the mean of the running failure probability, and the maximum fitting slope of the mean of the bit error rate of the voltage point, the state level corresponding to the target voltage margin factor is adjusted to determine the state evaluation result of the target computing chip.

[0096] In this embodiment, the mean of the voltage margin factors of all test operators can be calculated, and this can be used as the target voltage margin factor for the target computing chip to be used for state assessment. Of course, the mean in the above embodiment can also be replaced by the standard deviation, etc., and is not limited here.

[0097] Among the priority parameters for state assessment, the voltage margin factor has a higher priority than the maximum fitting slope of the error probability. The assessment is first performed based on the voltage margin factor, and then the assessment results are further adjusted based on the maximum fitting slope of the error probability on the basis of the voltage margin factor.

[0098] In some examples, the aforementioned preset chip state allocation levels may refer to pre-assigning the chip state to several levels. The voltage margin factor σ reflects the "safety margin" by which the chip can withstand voltage drops below the standard voltage V_op while still maintaining correct operation. For a chip, when operating at a higher frequency, bit flipping errors are more likely to occur at lower voltages. A larger σ indicates a wider threshold distribution and the operating point is further from the failure boundary; a smaller σ indicates that transistor parameters have deteriorated, with less tolerance, such as threshold drift and increased leakage. Therefore, when evaluating based on the priority of state assessment parameters, initial classification is based on σ, dividing the chip into four levels. The threshold can be adjusted according to the actual application, specifically including: Level A (Excellent): σ ≥ 10%, indicating good chip condition with sufficient safety margin, suitable for long-term high-intensity use. Level B (Good): 5% ≤ σ < 10%. Good chip condition with moderate safety margin, suitable for general use. Level C (Average): 1% ≤ σ < 5%. Poor chip condition with small safety margin; monitoring or frequency reduction is recommended. Grade D (Poor): σ < 1%. The chip is in poor condition, with insufficient safety margin, and may be about to fail. Replacement or restriction of use is recommended.

[0099] Furthermore, after calculating k_f and k_b for each test operator, the average values ​​k_f_vag and k_b_vag of all test operators for the target computing chip can be calculated separately. Based on σ evaluation, k_f_vag and k_b_vag are added to the results for adjustment. k_f has a higher priority than k_b, indicating that system-level errors are sensitive to voltage fluctuations. Slope weights can be pre-assigned to k_f_vag and k_b_vag, with the sum of their weights being 1. For example, the slope weight of k_f_vag is 0.9, and the slope weight of k_b_vag is 0.1. Then, the results of these two indicators, K = 0.9k_f_vag + 0.1k_b_vag, are used to fine-tune σ. That is, σ + K represents the final state level of the target computing chip, i.e., the state evaluation result.

[0100] In some examples, when classifying chips in the same batch, a smaller slope indicates greater stability and a higher grade. If σ is the same, chips with larger slopes k_f and k_b are classified as lower grades. For example, chips belonging to grade B but with larger k_f and k_b are considered B-, while those with smaller k_f and k_b are considered B+. Here, - can indicate a half-grade reduction, and + can indicate a half-grade increase. Grades can also be further subdivided; for example, the top 25% of chips with a slope k value are increased by half a grade, and the bottom 25% are decreased by half a grade. Here, k_f and k_b are refinements within the same grade range, not completely different grades.

[0101] In this embodiment, since the voltage margin factor reflects the "safety margin" of how much voltage the chip can drop below the standard voltage V_op while still maintaining correct operation, it is used as the dominant parameter to initially determine the state level, which can more accurately guide the state evaluation results of the target computing chip. By combining k_f, k_b and their corresponding slope weights, fine-tuning can be performed on the initially determined state level, which can reflect the sensitivity of the error rate as the voltage decreases at both macroscopic and microscopic levels. The multi-dimensional parameter evaluation improves the accuracy of the evaluation results.

[0102] Combination Figure 5 As shown, Figure 5This is a schematic flowchart of an optional state assessment method for a computing chip provided by an embodiment of the present invention. By measuring the chip's voltage-frequency curve, the target reference test frequency of the locking core is further determined. After testing the test operator without applying a voltage bias, a first calculation result is obtained as a reference result, and a reference file is generated and stored. By setting a buck scanning strategy, a gradient scan is performed within a preset voltage range, thereby obtaining a second calculation result and generating a test file. By comparing the two files bit by bit, it is possible to determine whether the bits corresponding to each voltage point have flipped and whether the test operator is operating normally. This allows for the acquisition of relevant data on operational failures, including the total number of failures. Finally, based on the results, the voltage margin factor of the test operator and the maximum fitting slope of the error probability are calculated to assess the chip's state level. According to the state assessment method for computing chips provided in this embodiment, the difference between the second calculation result and the first calculation result can be accurately captured. This allows for precise statistical analysis of the error count and first error voltage of each test operator, and further precise calculation of the maximum fitting slope and voltage margin factor of the error probability of the test operator. This method not only considers the voltage margin but also expresses the sensitivity of the error rate to voltage decrease through the maximum fitting slope, thus making the final assessment result more accurate.

[0103] According to another aspect of the embodiments of this application, such as Figure 6 As shown, corresponding to the state assessment method of the computing chip in the above embodiments, this embodiment provides a state assessment device for the computing chip, the device comprising:

[0104] The acquisition module 601 is used to acquire the target reference test frequency of the target computing chip;

[0105] The first calculation module 603 is used to determine a first calculation result of the operator set of the target computing chip based on the target reference test frequency and a predetermined standard voltage, and to determine a second calculation result of the operator set of the target computing chip based on gradient voltage bias conditions. The operator set includes multiple test operators.

[0106] The second calculation module 605 is used to determine the error count and first error voltage during the operation of the test operator of the target computing chip based on the first calculation result and the second calculation result.

[0107] The third calculation module 607 is used to calculate the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point based on the error count and the first error voltage during the operation of the test operator.

[0108] The state evaluation module 609 is used to evaluate the state of the computing chip based on the voltage margin factor and the maximum fitting slope of the error probability of the test operator, combined with the priority of the state evaluation parameters of the target computing chip.

[0109] It should be noted that, in this embodiment, the model acquisition module 601 can be used to execute step S202 in this application embodiment, the first calculation module 603 in this embodiment can be used to execute step S204 in this application embodiment, the second calculation module 605 in this embodiment can be used to execute step S206 in this application embodiment, the third calculation module 607 in this embodiment can be used to execute step S208 in this application embodiment, and the state evaluation module 609 in this embodiment can be used to execute step S210 in this application embodiment.

[0110] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules, as part of the system, can run in the hardware environment of the computing chip's state assessment device, and can be implemented in software or hardware.

[0111] According to another aspect of the embodiments of this application, this application provides a computer device, such as... Figure 7 As shown, it includes a memory 701, a processor 703, a communication interface 705, and a communication bus 707. The memory 701 stores a computer program that can run on the processor 703. The memory 701 and the processor 703 communicate through the communication interface 705 and the communication bus 707. When the processor 703 executes the computer program, it implements the steps of the above-mentioned computing chip state evaluation method.

[0112] The memory and processor in the aforementioned computer equipment communicate with each other via a communication bus and a communication interface. The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc.

[0113] The aforementioned memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0114] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0115] According to another aspect of the embodiments of this application, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of the state assessment method for the computing chip in any of the above embodiments.

[0116] Optionally, in this embodiment, the computer-readable medium is configured to store program code for the processor to execute the steps of the state evaluation method for the computing chip described in the above embodiments, wherein the steps of the state evaluation method for the computing chip specifically include:

[0117] S202. Obtain the target reference test frequency of the target computing chip;

[0118] S204. Based on the target reference test frequency, determine the first calculation result of the operator set of the target computing power chip according to the predetermined standard voltage, and determine the second calculation result of the operator set of the target computing power chip according to the gradient voltage bias condition. The operator set includes multiple test operators.

[0119] S206. Based on the first calculation result and the second calculation result, determine the error count and first error voltage during the operation of the test operator of the target computing chip;

[0120] S208. Based on the error count and the first error voltage during the operation of the test operator, calculate the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point.

[0121] S210. Based on the voltage margin factor and the maximum fitting slope of the error probability of the test operator, and in conjunction with the priority of the state evaluation parameters of the target computing chip, the state of the computing chip is evaluated.

[0122] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments, and will not be repeated here. Furthermore, in the specific implementation of this application embodiment, the above embodiments can be consulted, and corresponding technical effects can be achieved.

[0123] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof. For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. Software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0124] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0125] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0126] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0127] It should be noted that, in this document, relational terms such as "first," "second," etc., are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprises a…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0128] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for assessing the state of a computing chip, characterized in that, The method includes: Obtain the target reference test frequency for the target computing chip; Based on the target reference test frequency, a first calculation result of the operator set of the target computing chip is determined according to a predetermined standard voltage, and a second calculation result of the operator set of the target computing chip is determined according to a gradient voltage bias condition. The operator set includes multiple test operators. Based on the first calculation result and the second calculation result, determine the error count and first error voltage during the operation of the test operator of the target computing chip; Based on the error count and the first error voltage during the test operator's operation, calculate the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point; Based on the voltage margin factor and the maximum fitting slope of the error probability of the test operator, the state of the target computing chip is evaluated in combination with the priority of the state evaluation parameters of the target computing chip. The error count includes the total number of failed runs of the test operator and the total number of bit errors. The step of calculating the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point based on the error count during the test operator's operation and the initial error voltage includes: determining the failure probability of the test operator based on the total number of failed runs and a preset total number of runs; determining the bit error rate of the test operator based on the total number of bit errors, the preset total number of runs, and the output length of the test operator; calculating the mean failure probability and mean bit error rate of the test operator based on the failure probability and bit error rate after multiple runs; performing piecewise linear fitting based on the voltage point, the mean failure probability, and the mean bit error rate to obtain the maximum fitting slope of the error probability in the fitted curve, wherein the maximum fitting slope of the error probability includes: the maximum fitting slope between the voltage point and the mean failure probability, and the maximum fitting slope of the mean bit error rate at the voltage point; and calculating the voltage margin factor based on the predetermined standard voltage and the initial error voltage of the test operator.

2. The state assessment method for computing chips according to claim 1, characterized in that, The acquisition of the target reference test frequency of the target computing chip includes: The voltage-frequency curve is obtained based on the characteristic parameters of the target computing chip; Within the voltage operating range of the target computing chip, the highest frequency at which the target computing chip does not drop frequency during operation is selected as the target reference test frequency based on the voltage-frequency curve.

3. The state assessment method for a computing chip according to claim 1, characterized in that, The gradient voltage bias condition includes a first voltage bias gradient and a second voltage bias gradient. The first calculation result of determining the operator set of the target computing chip based on the target reference test frequency and a predetermined standard voltage, and the second calculation result of determining the operator set of the target computing chip based on the gradient voltage bias condition, include: Based on the target reference test frequency, test operators in the operator set are run according to the predetermined standard voltage to obtain the first calculation result of the target computing chip; Based on the target reference test frequency and the preset voltage adjustment range of the target computing chip, test operators in the operator set are run according to the first voltage bias gradient, and when the run test operator fails, the test operator that fails is run according to the second voltage bias gradient to obtain the second calculation result of the target computing chip.

4. The state assessment method for a computing chip according to claim 3, characterized in that, After determining the first calculation result of the operator set of the target computing chip based on the target reference test frequency and a predetermined standard voltage, and the second calculation result of the operator set of the target computing chip based on the gradient voltage bias condition, the method further includes: Read the first calculation result and store the first calculation result in bits into the reference file in the target format; Read the second calculation result and store it in bits into the test file in the target format.

5. The state assessment method for a computing chip according to claim 4, characterized in that, The step of determining the error count and first error voltage of each test operator of the target computing chip based on the first calculation result and the second calculation result includes: Based on bits, the first calculation result of the same test operator in the reference file and the second calculation result in the test file are compared bit by bit to detect whether the bits in the second calculation result are flipped relative to the first calculation result, wherein each bit in the second calculation result corresponds to a voltage point. If a bit is flipped, the test operator is run based on the voltage point corresponding to the bit to obtain the total number of failed runs of the test operator. Collect the number of bit flips when the test operator fails in a single run, and calculate the total number of bit errors of the test operator based on the number of bit flips. Obtain the voltage point corresponding to the first failure of the test operator, and use the voltage point corresponding to the first failure as the first error voltage of the test operator.

6. The state assessment method for a computing chip according to claim 1, characterized in that, In the priority of the state evaluation parameters, the voltage margin factor has a higher priority than the maximum fitting slope of the error probability. The process of evaluating the state of the computing chip based on the voltage margin factor and the maximum fitting slope of the error probability of the test operator, combined with the priority of the state evaluation parameters of the target computing chip, includes: Calculate the target voltage margin factor of the target computing chip based on the voltage margin factors of all test operators; Based on the priority of the state evaluation parameters, the state level corresponding to the target voltage margin factor is determined according to the preset chip state allocation level. Based on the pre-assigned slope weights, the maximum fitting slope between the voltage point and the mean of the failure probability, and the maximum fitting slope between the mean of the bit error rate at the voltage point, the state level corresponding to the target voltage margin factor is adjusted to determine the state evaluation result of the target computing chip.

7. A state assessment device for a computing chip, used to implement the state assessment method for a computing chip as described in any one of claims 1 to 6, characterized in that, The device includes: The acquisition module is used to acquire the target reference test frequency of the target computing chip; The first calculation module is used to determine a first calculation result of the operator set of the target computing chip based on the target reference test frequency and a predetermined standard voltage, and to determine a second calculation result of the operator set of the target computing chip based on gradient voltage bias conditions. The operator set includes multiple test operators. The second calculation module is used to determine the error count and first error voltage during the operation of the test operator of the target computing chip based on the first calculation result and the second calculation result. The third calculation module is used to calculate the voltage margin factor of the target computing chip and the maximum fitting slope between the error probability and the voltage point based on the error count and the first error voltage during the operation of the test operator. The status assessment module is used to assess the status of the computing chip based on the voltage margin factor and the maximum fitting slope of the error probability of the test operator, combined with the priority of the status assessment parameters of the target computing chip.

8. A computer device, comprising: A processor, a memory, and a network interface, wherein the memory stores machine-readable instructions executable by the processor, characterized in that: when the computer device is running, the processor communicates with the memory via the network interface, and the processor executes the machine-readable instructions to perform the steps of the state assessment method for a computing chip as described in any one of claims 1 to 6.

9. A computer-readable medium having processor-executable non-volatile program code, characterized in that, The program code causes the processor to execute the steps of the state assessment method for the computing chip according to any one of claims 1 to 6.

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