Multi-core system concurrency control method, device and equipment, readable storage medium, program product and chip

Abstract

The invention relates to a multi-core system concurrency control method and device, computer equipment, a computer readable storage medium, a computer program product and a chip. The method comprises the steps that a first core and a second core are determined according to the working states of all cores in the multi-core system when the same resources are concurrently processed, and the block processing duration of the first core is larger than that of the second core; when the multi-core system concurrently processes the target resource, splitting a first block operation instruction of the first core into a plurality of first meta-operation instructions, and splitting a second block operation instruction of the second core into a plurality of second meta-operation instructions; according to the execution sequence of the first meta-operation instructions, time delay instructions are inserted between the adjacent first meta-operation instructions, and discontinuous operation instructions are generated; and executing the discontinuous operation instruction, and in the execution process of the delay instruction in the discontinuous operation instruction, sequentially scheduling the second meta-operation instruction to be executed until the execution is finished. By adopting the method, the overall operation efficiency of the multi-core system can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, computer device, computer-readable storage medium, computer program product, and chip for concurrent control of a multi-core system. Background Technology

[0002] In a multi-core system, different cores usually run programs independently, but there may be situations where multiple cores access the same resource at the same time. In this case, if the accessed resource does not support concurrency, they will queue up and mutually exclude each other, which will slow down the operation of one or more cores and affect the timing of one or more cores. There are several ways to deal with this: (1) Each core executes independently and is scheduled by the resource manager (such as the bus), but it is impossible to accurately predict and control the execution time of each core's corresponding steps, resulting in greater uncertainty and the possibility that other cores may have to wait too long. (2) Set different priorities for different cores so that the resource access priority of a certain core is higher, but due to the complexity of resource management, the core with higher priority may not need to be prioritized every time it uses the resource, resulting in other cores having to wait too long. (3) The core that accesses the resource first preempts it until the access is completed, and other cores access it after the core that preempts the resource releases it. In this case, if the core that preempts the resource takes a long time, it will also cause other cores to wait too long.

[0003] Therefore, in the event of resource usage conflicts in a multi-core system, the current operation control method has the problem of causing other cores to wait for too long, which in turn leads to a decrease in the overall operating efficiency of the multi-core system. Summary of the Invention

[0004] Therefore, it is necessary to provide a multi-core system concurrency control method, device, computer equipment, computer-readable storage medium, computer program product, and chip that can improve the overall operating performance of multi-core systems, in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a method for concurrency control in a multi-core system, including:

[0006] The system obtains the working status of multiple cores in a multi-core system when they are concurrently processing the same resources, and determines the first core and the second core from among the multiple cores based on their working status; the block processing time of the first core is greater than that of the second core.

[0007] When a multi-core system processes target resources concurrently, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions.

[0008] Based on the execution order of multiple first-order operation instructions, delay instructions are inserted between adjacent first-order operation instructions to generate intermittent operation instructions;

[0009] Execute intermittent operation instructions, and during the execution of the delay instructions in the intermittent operation instructions, sequentially schedule the execution of the second-level operation instructions until the first-level operation instructions and the second-level operation instructions have been completed.

[0010] In one embodiment, determining the first core and the second core from the multiple cores based on their operating states includes:

[0011] Based on the working status of multiple cores, if it is determined that there are operational conflicts among multiple cores, the block type used by each core is determined; the block type includes Class I blocks and Class II blocks, and the block processing time of the core using Class I blocks is greater than the block processing time of the core using Class II blocks.

[0012] The core of type 1 blocks will be used as the first core, and the core of type 2 blocks will be used as the second core.

[0013] In one embodiment, when a multi-core system concurrently processes a target resource, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions, including:

[0014] When a multi-core system processes target resources concurrently, it obtains the first block operation instructions executed by the first core, the second block operation instructions executed by the second core, and a preset instruction quantity.

[0015] Based on the execution timing of the first block operation instruction, the first block operation instruction is split into multiple first meta-operation instructions arranged in the first execution order, and the number of first meta-operation instructions is equal to the preset instruction quantity.

[0016] Based on the execution timing of the second block operation instructions, the second block operation instructions are split into multiple second-level operation instructions arranged in a second execution order, and the number of second-level operation instructions is equal to the preset instruction quantity.

[0017] In one embodiment, the delay instruction is generated in the following manner:

[0018] Obtain the latency coefficient, and set the expected latency based on the latency coefficient and the block processing time of the second core;

[0019] Generate a delay instruction based on the desired delay duration.

[0020] In one embodiment, the intermittent operation instructions include: a plurality of first-level operation instructions arranged in a first execution order, and a delay instruction inserted between adjacent first-level operation instructions; the plurality of second-level operation instructions are arranged in a second execution order;

[0021] Execute intermittent operation instructions, and during the execution of the delay instructions within the intermittent operation instructions, sequentially schedule the execution of second-order operation instructions until the first-order and second-order operation instructions have been completed, including:

[0022] The control intermittent operation instructions are executed starting from the first primary operation instruction, and the execution process monitors whether a delayed instruction is executed;

[0023] During the execution of the delayed instruction, the unexecuted second-ary operation instructions are scheduled to begin execution in the second execution order until the execution of multiple first-ary operation instructions and multiple second-ary operation instructions is completed.

[0024] In one embodiment, the multi-core system concurrency control method further includes:

[0025] After the first-order operation instruction and the second-order operation instruction are executed, the scheduling result of the second-order operation instruction during the execution process of each delayed instruction is statistically analyzed.

[0026] Based on the scheduling results of the second-order operation instructions during the execution of each delayed instruction, count the valid delayed instructions that have schedulable second-order operation instructions during the execution process, and the idle delayed instructions that do not have schedulable second-order operation instructions during the execution process.

[0027] Based on the statistical results of effective delay instructions and idle delay instructions, the concurrency control delay duration of the first core and the second core is determined.

[0028] Secondly, this application also provides a multi-core system concurrency control device, comprising:

[0029] The concurrency control core determination module is used to obtain the working status of multiple cores in a multi-core system when they are concurrently processing the same resources, and to determine the first core and the second core from the multiple cores based on the working status of the multiple cores; the block processing time of the first core is greater than the block processing time of the second core.

[0030] The operation instruction splitting module is used to split the first block operation instruction executed by the first core into multiple first meta operation instructions when the multi-core system concurrently processes the target resource, and to split the second block operation instruction executed by the second core into multiple second meta operation instructions.

[0031] The delay instruction insertion module is used to insert delay instructions between adjacent first-ary operation instructions according to the execution order of multiple first-ary operation instructions, thereby generating intermittent operation instructions.

[0032] The instruction execution control module is used to execute intermittent operation instructions, and during the execution of the delayed instructions in the intermittent operation instructions, it sequentially schedules the execution of the second-level operation instructions until the first-level operation instructions and the second-level operation instructions are completed.

[0033] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0034] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0035] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0036] Sixthly, this application also provides a chip, which includes a processor and a data interface. The processor reads instructions stored in a memory through the data interface and is able to execute the steps of the method in any of the above embodiments.

[0037] The aforementioned multi-core system concurrency control method, apparatus, computer equipment, computer-readable storage medium, computer program product, and chip can determine the first core and the second core based on the working state of multiple cores in a multi-core system concurrently processing the same resource, wherein the block processing time of the first core is longer than that of the second core. When the multi-core system concurrently processes the target resource, the first block operation instruction executed by the first core is split into multiple first-level operation instructions, and the second block operation instruction executed by the second core is split into multiple second-level operation instructions. Then, according to the execution order of the multiple first-level operation instructions, delay instructions are inserted between adjacent first-level operation instructions to generate intermittent operation instructions. Then, the intermittent operation instructions are executed, and during the execution of the delay instructions in the intermittent operation instructions, the second-level operation instructions are scheduled to be executed sequentially until the first-level operation instructions and the second-level operation instructions are completed. The process first distinguishes between two types of cores with different block processing times. Then, delay instructions are inserted into multiple first-order operation instructions with longer block processing times to generate intermittent operation instructions. This allows for the sequential execution of multiple first-order operation instructions while simultaneously interleaving multiple second-order operation instructions with shorter block processing times, preventing the second cores with shorter block processing times from waiting for extended periods. Based on this, the overall performance of the multi-core system can be improved. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is an application environment diagram of a multi-core system concurrency control method in one embodiment;

[0040] Figure 2 This is a flowchart illustrating a multi-core system concurrency control method in one embodiment;

[0041] Figure 3 This is a flowchart illustrating the breakdown of operation instructions in one embodiment;

[0042] Figure 4 This is a schematic diagram of meta-operation instructions and delay instructions in one embodiment;

[0043] Figure 5 This is a flowchart of a multi-core system concurrency control system with quantifiable latency analysis in one embodiment;

[0044] Figure 6This is a block diagram of a multi-core system concurrency control device in one embodiment;

[0045] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] The multi-core system concurrency control method provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, server 102 can be deployed with a multi-core system and specialized tools for monitoring the multi-core CPU status. The multi-core system has multiple cores, and server 102 can use the specialized tools to monitor the multi-core CPU status to obtain the working status of multiple cores in the multi-core system when concurrently processing the same resource. Furthermore, server 102 can determine the first core 104 and the second core 106 from among the multiple cores based on their working status. The block processing time of the first core 104 is greater than that of the second core 106. When the multi-core system concurrently processes the target resource, the first block operation instruction executed by the first core 104 is split into multiple first-level operation instructions, and the second block operation instruction executed by the second core 106 is split into multiple second-level operation instructions. Then, based on the execution order of multiple first-ary operation instructions, delay instructions are inserted between adjacent first-ary operation instructions to generate intermittent operation instructions. The execution of the intermittent operation instructions is then controlled, and during the execution of the delay instructions in the intermittent operation instructions, the second-ary operation instructions are scheduled to be executed sequentially until the first-ary operation instructions and the second-ary operation instructions are completed.

[0048] Server 102 can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. A multi-core system refers to a computing architecture that integrates two or more independent, complete computing cores on a physical processor chip (CPU). Core block processing time specifically refers to the efficiency of a core in processing a basic unit of work. A delay instruction can specifically be a NOP (NoOperation) instruction; the main purpose of a delay instruction is to serve as a placeholder for a "no-operation".

[0049] In one exemplary embodiment, such as Figure 2 As shown, a method for concurrent control of a multi-core system is provided, which can be applied to... Figure 1Taking server 102 as an example, the explanation includes the following steps 202 to 208. Wherein:

[0050] Step 202: Obtain the working status of multiple cores in the multi-core system when they are concurrently processing the same resources, and determine the first core and the second core from the multiple cores based on the working status of the multiple cores; the block processing time of the first core is greater than the block processing time of the second core.

[0051] The phrase "multiple cores concurrently processing the same resource" specifically refers to the following scenario: multiple cores access the same resource simultaneously, leading to operational conflicts between cores and a decrease in the performance of a multi-core system. A "block" specifically refers to a unit of data or a unit of task being processed. The block processing time of the first core can be greater than a preset time, indicating that the first core is responsible for handling computationally intensive, complex, or large-data-volume tasks. The block processing time of the second core can be less than or equal to the preset time, indicating that the second core is responsible for handling simple or small-data-volume tasks. The first core can refer to one or more cores, and the second core can also refer to one or more cores.

[0052] Optionally, the server can use specialized tools to monitor the working status of multiple cores in a multi-core system when concurrently processing the same resources. If a core's program execution slows down significantly—for example, if the core's execution time increases several times compared to its normal operation—it can be determined that multiple cores are conflicting due to simultaneous access to the same resource, causing queuing cores and thus slowing down their execution. Furthermore, the server can designate cores with block processing times exceeding a preset time as "first cores" and cores with block processing times less than or equal to the preset time as "second cores," ensuring that the block processing time of the first core is greater than that of the second core. Based on this, two types of cores with differing block processing times can be distinguished.

[0053] Step 204: When the multi-core system processes the target resource concurrently, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions.

[0054] Specifically, a block operation instruction refers to a set of operations on resources that need to be performed at the core level, which may include multiple operation steps. A meta-operation instruction refers to the basic, indivisible operation steps that constitute a block operation instruction. The number of multiple first meta-operation instructions and multiple second meta-operation instructions can be flexibly configured according to the splitting requirements of the application scenario; this embodiment does not limit this.

[0055] Optionally, when a multi-core system processes the target resource concurrently, considering the resource access conflicts between multiple cores, the server can determine the splitting targets for the first block operation instruction and the second operation instruction according to the preset splitting rules. Thus, according to the splitting targets for the first block operation instruction and the second operation instruction, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions.

[0056] For example, taking a memset with a first block operation instruction of 10K as an example, the first block operation instruction can be split into 10 memsets of 1k each (10 first meta operation instructions).

[0057] Step 206: Based on the execution order of multiple first-ary operation instructions, insert delay instructions between adjacent first-ary operation instructions to generate intermittent operation instructions.

[0058] Specifically, the delay instruction can be a Nop instruction. In this embodiment, the Nop instruction is inserted to introduce a delay in order to avoid conflicts in the instruction pipeline.

[0059] Optionally, after splitting the first block operation instructions, the server can obtain multiple first-level operation instructions arranged in execution order. Furthermore, starting with the first adjacent pair of first-level operation instructions, the server can sequentially insert delay instructions between adjacent first-level operation instructions to introduce controllable execution delays and generate intermittent operation instructions.

[0060] For example, if the number of multiple first-order operation instructions is N, the server can insert N-1 delay instructions between the multiple first-order operation instructions. For instance, 9 Nop instructions can be inserted between 10 1k memsets so that multiple second-order operation instructions of the second core can be scheduled to execute during the execution of the Nop instructions.

[0061] Step 208: Execute the intermittent operation instruction, and during the execution of the delay instruction in the intermittent operation instruction, sequentially schedule the execution of the second-level operation instruction until the first-level operation instruction and the second-level operation instruction are completed.

[0062] The intermittent operation instructions include: multiple first-order operation instructions arranged in a first execution order, and delay instructions inserted between the multiple first-order operation instructions.

[0063] Optionally, the server can control the execution of intermittent operation instructions. Specifically, it can control the execution of intermittent operation instructions to start from the first primary operation instruction, and then execute the other primary operation instructions and delay instructions in the intermittent operation instructions one by one, while monitoring whether the delay instructions are executed during the execution process. During the execution of the delay instructions, the server can schedule the unexecuted secondary operation instructions to start execution in a second execution order among the multiple secondary operation instructions, until all the primary operation instructions and multiple secondary operation instructions have been executed.

[0064] The aforementioned multi-core system concurrency control method determines the first and second cores based on the working status of multiple cores concurrently processing the same resource in a multi-core system, wherein the block processing time of the first core is longer than that of the second core. When the multi-core system concurrently processes the target resource, the first block operation instruction executed by the first core is split into multiple first-level operation instructions, and the second block operation instruction executed by the second core is split into multiple second-level operation instructions. Then, according to the execution order of the multiple first-level operation instructions, delay instructions are inserted between adjacent first-level operation instructions to generate intermittent operation instructions. These intermittent operation instructions are then executed, and during the execution of the delay instructions within the intermittent operation instructions, second-level operation instructions are sequentially scheduled for execution until both the first and second-level operation instructions are completed. The process first distinguishes between two types of cores with different block processing times. Then, delay instructions are inserted into multiple first-order operation instructions with longer block processing times to generate intermittent operation instructions. This allows for the sequential execution of multiple first-order operation instructions while simultaneously interleaving multiple second-order operation instructions with shorter block processing times, preventing the second cores with shorter block processing times from waiting for extended periods. Based on this, the overall performance of the multi-core system can be improved.

[0065] In an exemplary embodiment, determining a first core and a second core from multiple cores based on their operating states includes:

[0066] Based on the working status of multiple cores, if it is determined that there are operational conflicts among multiple cores, the block type used by each core is determined; the block type includes Class I blocks and Class II blocks, and the block processing time of the core using Class I blocks is greater than the block processing time of the core using Class II blocks.

[0067] The core of type 1 blocks will be used as the first core, and the core of type 2 blocks will be used as the second core.

[0068] Optionally, the server can determine whether any core's program execution is significantly slower based on the working status of multiple cores. For example, whether a core's execution time is several times longer than normal. If so, it can be determined that there is a running conflict among multiple cores. If a running conflict is determined, the server can determine the block type used by each core based on a comparison between the core's block processing time and a preset time. For example, cores with block processing times greater than the preset time are designated as cores using type one blocks (i.e., the first core), while cores with block processing times less than or equal to the preset time are designated as cores using type two blocks (i.e., the second core).

[0069] In this embodiment, two types of cores (the first core and the second core) with different block processing times can be distinguished based on the working status of cores with operational conflicts. This allows for the subsequent scheduling and execution of multiple first-level operation instructions from the second core, which has a shorter block processing time, during the sequential execution of multiple first-level operation instructions from the first core. This avoids the second core waiting for a long time, thereby improving the overall operating efficiency of the multi-core system.

[0070] In one embodiment, when a multi-core system concurrently processes a target resource, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions, including:

[0071] When a multi-core system processes target resources concurrently, it obtains the first block operation instructions executed by the first core, the second block operation instructions executed by the second core, and a preset instruction quantity.

[0072] Based on the execution timing of the first block operation instruction, the first block operation instruction is split into multiple first meta-operation instructions arranged in the first execution order, and the number of first meta-operation instructions is equal to the preset instruction quantity.

[0073] Based on the execution timing of the second block operation instructions, the second block operation instructions are split into multiple second-level operation instructions arranged in a second execution order, and the number of second-level operation instructions is equal to the preset instruction quantity.

[0074] The preset instruction quantity indicates the number of meta-operation instructions obtained when splitting block operation instructions, ensuring that the number of first meta-operation instructions and second meta-operation instructions are the same. The value of the preset instruction quantity can be flexibly configured according to the actual application scenario's splitting requirements; this embodiment does not limit this. Multiple first meta-operation instructions have the same block processing time, such as m nanoseconds, and multiple second meta-operation instructions have the same block processing time, such as n nanoseconds.

[0075] Optionally, when a multi-core system concurrently processes target resources, it can allocate tasks to each core, allowing each core to execute the block operation instructions corresponding to its respective task. Based on this, the server can first obtain the first block operation instruction executed by the first core and the second block operation instruction executed by the second core. To accurately split the block operation instructions, the server can also obtain a preset instruction quantity from pre-set parameters. Further, the server can decompose the first block operation instruction to determine the multiple first-level operation instructions contained within it, and their execution order (i.e., the execution timing of the first block operation instruction). Then, based on the execution timing and the preset instruction quantity, the first block operation instruction is split into multiple first-level operation instructions arranged in a first execution order. At the same time, the server can decompose the second block operation instruction to determine the multiple second meta-operation instructions contained in the second block operation instruction, as well as the execution order of the multiple second meta-operation instructions (that is, the execution timing of the second block operation instruction). Then, according to the execution timing and preset instruction quantity in the second block operation instruction, the second block operation instruction is split into multiple second meta-operation instructions arranged in a second execution order.

[0076] For example, taking a preset instruction quantity of 5 and the first block operation instruction as executing a graphics rendering task, the server can decompose the first block operation instruction to determine the multiple first-level operation instructions arranged in a first execution order. Then, the server can split the first block operation instruction into multiple first-level operation instructions arranged in the first execution order according to the execution timing of the first block operation instruction: "vertex transformation", "lighting calculation", "clipping", "rasterization", and "pixel shading".

[0077] For example, such as Figure 3 As shown, a schematic diagram of operation instruction breakdown is provided. Figure 3 In this code, C1 represents the first block operation instruction, C2 represents the second block operation instruction, core1 represents a single first-level operation instruction, and core2 represents a single second-level operation instruction. With a default instruction count of 5, the server can split the first block operation instruction C1 into 5 first-level operation instructions (core1), and the second block operation instruction C2 into 5 second-level operation instructions (core2), with the block processing time of the first-level operation instruction (core1) being greater than the block processing time of the second-level operation instruction (core2).

[0078] In this embodiment, coarse-grained "block operation instructions" can be decomposed into fine-grained, indivisible "meta-operation instructions" to enable more precise concurrent scheduling.

[0079] In one embodiment, the delay instruction is generated in the following manner:

[0080] Obtain the latency coefficient, and set the expected latency based on the latency coefficient and the block processing time of the second core;

[0081] Generate a delay instruction based on the desired delay duration.

[0082] The delay coefficient can be one or two, and can be flexibly configured according to the delay requirements of the actual application scenario. The delay duration indicated by the delay command is equal to the expected delay duration.

[0083] Optionally, to set a delay command, the server can obtain a pre-configured delay coefficient. If there is only one delay coefficient, the server can multiply the delay coefficient k by the block processing time m of the second core, and use this product as the expected delay duration t. gap Then, based on the expected delay duration t gap This generates a delay instruction gap. With two delay coefficients, the server can set the desired delay duration t based on the delay coefficients (k1 and k2, where k1 < k2) and the block processing time m of the second core. gap The value range is (k1×m ~ k2×m), and a value within this range is selected as the expected delay duration t. gap Therefore, based on the expected delay duration t gap Generate a delay instruction gap.

[0084] For example, a high-precision timestamp counter can be used to precisely control the delay duration indicated by the delay instruction to be equal to the expected delay duration, thus ensuring the accuracy of the delay duration.

[0085] In this embodiment, the delay duration indicated by the delay instruction can be flexibly configured according to the delay requirements of the actual application scenario, so that the second-level operation instruction can be flexibly scheduled to execute during the delay of the first-level operation instruction. Based on this, during the operation of the slow (longer block processing time) first core, a period of bus time can be given up to allow the fast (shorter block processing time) second core to complete its operation as quickly as possible.

[0086] In one embodiment, an intermittent operation instruction is executed, and during the execution of the delayed instruction within the intermittent operation instruction, a second-level operation instruction is sequentially scheduled for execution until the first-level and second-level operation instructions are completed, including:

[0087] The control intermittent operation instructions are executed starting from the first primary operation instruction, and the execution process monitors whether a delayed instruction is executed;

[0088] During the execution of the delayed instruction, the unexecuted second-ary operation instructions are scheduled to begin execution in the second execution order until the execution of multiple first-ary operation instructions and multiple second-ary operation instructions is completed.

[0089] The intermittent operation instructions include: a plurality of first-level operation instructions arranged in a first execution order, and a delay instruction inserted between adjacent first-level operation instructions, and a plurality of second-level operation instructions arranged in a second execution order.

[0090] Optionally, for intermittent manipulation instructions, the server can first determine the execution order of multiple first-level operation instructions and multiple delay instructions within the intermittent operation instructions. This allows the server to control the execution of the intermittent operation instructions to begin with the first first-level operation instruction, followed by the sequential execution of the remaining first-level operation instructions and delay instructions. During execution, the server monitors whether a delay instruction has been executed. During the execution of the delay instructions, the server can, according to the second execution order of multiple second-level operation instructions, sequentially schedule the unexecuted second-level operation instructions to begin execution, until all first-level and second-level operation instructions have been executed.

[0091] Specifically, when a delayed instruction is executed: (1) If there is an unexecuted second-order operation instruction, it can be scheduled to be executed in the second execution order within the delay duration of the delayed instruction. If the scheduled second-order operation instruction has been executed before the delay duration of the delayed instruction ends, it can wait until the delay duration of the delayed instruction ends before executing the next first-order operation instruction immediately following the delayed instruction. If the scheduled second-order operation instruction has not been executed before the delay duration of the delayed instruction ends, it can continue to execute the scheduled second-order operation instruction core2 until the scheduled second-order operation instruction is executed, and then execute the next first-order operation instruction immediately following the delayed instruction. (2) If there is no unexecuted second-order operation instruction, it can wait until the delay duration of the delayed instruction ends before executing the next first-order operation instruction immediately following the delayed instruction.

[0092] For example, such as Figure 4 The diagram illustrates a meta-operation instruction and a delay instruction. The first block operation instruction is divided into five first meta-operation instructions (core1, with a block processing time of m nanoseconds), and the second block operation instruction is divided into five second meta-operation instructions (core2, with a block processing time of n nanoseconds). If we set the delay coefficients k1=2 and k2=3, then the delay duration t of the delay instruction gap is... gap The range of values ​​for is: 2n < t gap<3n. Based on this, the server can execute the following process: (1) Control the execution of the first core1 and monitor whether the gap is reached during the execution process. (2) When the first core1 is completed, execute the first gap. During the execution of the first gap, schedule the first 3 core2s to execute in sequence (time takes 3n). Because t gap <3n, when the delay of the first gap ends, the third core2 that was scheduled has not finished executing, and can continue to execute the third core2 until the third core2 is completed, and then execute the next core1 that immediately follows the gap, that is, prepare to execute the second core1. (3) When the second core1 is completed, execute the second gap. During the execution of the second gap, the remaining two core2 are scheduled to be executed in sequence (time taken 2n). Because t gap >2n, before the delay of the second gap ends, the two scheduled core2s have been executed. We can wait for the delay of the second gap to end before executing the next core1 immediately following the gap, that is, preparing to execute the third core1. (4) When the third core1 is executed, the third gap is executed. Since the five core2s have been executed, there are no unexecuted core2s that can be scheduled. We wait until the delay of the third gap ends before executing the next core1 immediately following the gap, that is, preparing to execute the fourth core1. (5) When the fourth core1 is executed, the fourth gap is executed. Since there are no unexecuted core2s that can be scheduled, we wait for the delay of the fourth gap to end before executing the next core1 immediately following the gap, that is, preparing to execute the fifth core1. (6) When the fifth core1 is executed, it is confirmed that all five core1s and five core2s have been executed.

[0093] In this embodiment, delay instructions can be interspersed during the operation of the slow (longer block processing time) first core, and the fast (shorter block processing time) second core can be scheduled to complete the operation as soon as possible during the delay, so as to avoid the fast second core waiting for too long, thereby improving the overall operating performance of the multi-core system.

[0094] In one embodiment, the multi-core system concurrency control method further includes:

[0095] After the first-order operation instruction and the second-order operation instruction are executed, the scheduling result of the second-order operation instruction during the execution process of each delayed instruction is statistically analyzed.

[0096] Based on the scheduling results of the second-order operation instructions during the execution of each delayed instruction, count the valid delayed instructions that have schedulable second-order operation instructions during the execution process, and the idle delayed instructions that do not have schedulable second-order operation instructions during the execution process.

[0097] Based on the statistical results of effective delay instructions and idle delay instructions, the concurrency control delay duration of the first core and the second core is determined.

[0098] Optionally, after the first and second meta-operation instructions are executed, the server can statistically analyze the scheduling results of the second meta-operation instructions during the execution of each delayed instruction. For example, it can determine whether there are any schedulable second meta-operation instructions during the execution of the delayed instructions. Based on this, the server can statistically analyze the effective delayed instructions (i.e., during the delay of effective delayed instructions, a second meta-operation instruction is scheduled for execution) and the idle delayed instructions (i.e., during the delay of idle delayed instructions) based on the statistical results of effective and idle delayed instructions. This allows for the quantitative determination of the concurrent control delay duration for each of the first and second cores.

[0099] For example, with Figure 4 Taking the intermittent operation instructions and binary operation instructions as examples, the first block operation instruction is split into 5 first-ary operation instructions (core1), and the second block operation instruction is split into 5 second-ary operation instructions (core2). Four delay instructions (gap) can be inserted between the 5 core1 instructions. If the delay coefficient k1=2, the delay coefficient k2=3, the block processing time of core1 is m nanoseconds, and the block processing time of core2 is n nanoseconds, then 2n < the expected delay time t. gap <3n. Based on this, Figure 4 The complete sequence of executing intermittent operation instructions and scheduling second-order operation instructions is as follows: (1) Execute the first core1, which takes m nanoseconds; (2) During the execution of the first gap, schedule the execution of 3 core2s, which take t gap <3n nanoseconds, this process takes 3n nanoseconds to complete the execution of the 3 scheduled core2s; (3) Execute the second core1, which takes m nanoseconds; (4) During the execution of the second gap, schedule the remaining 2 core2s to be executed, because t gap If the time exceeds 2n ​​nanoseconds, then the delay of the second gap must be waited for to end, and this process takes t seconds. gap(5) Execute the third core1, taking m nanoseconds; (6) Execute the third gap. Since all core2 has been executed, we only need to wait for the delay of the third gap to end, taking t seconds. gap (7) Execute the fourth core1, taking m nanoseconds; (8) Execute the fourth gap, waiting for the delay of the fourth gap to end, taking t seconds. gap (9) Execute the fifth core1, which takes m nanoseconds.

[0100] Based on this, targeting Figure 4 In the scenario shown, the first and second delayed instructions can be considered as valid delayed instructions, while the third, fourth, and fifth delayed instructions can be considered as idle delayed instructions. After multiple first-block operation instructions and multiple second-block operation instructions have been executed, the concurrent control delay duration of the first core = 5m + 3n + 3t. gap The concurrency control latency of the second core is 5n + 2m. Without using the multi-core system concurrency control method in this embodiment, if only the first core's first-level operation instructions and the second core's second-level operation instructions alternately occupy the bus for execution, then the concurrency control latency of the first core is 5m + 4n, and the concurrency control latency of the second core is 5n + 5m. Therefore, it can be seen that after using the multi-core system concurrency control method in this embodiment, although the concurrency control latency of the first core increases slightly, the concurrency control latency of the second core is reduced by 3m, which greatly improves the waiting time of the second core, facilitating faster (shorter block processing time) completion by the second core.

[0101] For example, taking the first block operation instruction as being split into x first-ary operation instructions core1 and the second block operation instruction as being split into y second-ary operation instructions core2, if the block processing time of core1 is m nanoseconds and the block processing time of core2 is n nanoseconds, the estimated concurrent control latency of the first core can be calculated as x*m + (x-1)*t. gap It can also estimate the concurrent control latency of the first core = y*n+m*(x-t) gap / n). Although the concurrency control latency of the first core increased slightly, the concurrency control latency of the second core decreased significantly, and t gap The larger / n is, the more the latency of the second core is reduced.

[0102] In this embodiment, the improvement effect of the concurrency control latency of the second core can be quantitatively analyzed so that the fast (shorter block processing time) second core can complete the task as soon as possible.

[0103] In a specific application scenario, such as Figure 5As shown, a multi-core system concurrent control flowchart with quantifiable latency analysis is provided, mainly including the following steps:

[0104] Step 502: Obtain the working status of multiple cores in a multi-core system when they are concurrently processing the same resources;

[0105] If, based on the working status of multiple cores, it is determined that there is a running conflict between multiple cores, step 504 is executed to determine the block type of the block used by each core;

[0106] Step 506: The core of type 1 blocks will be used as the first core, and the core of type 2 blocks will be used as the second core; the block processing time of the first core is greater than that of the second core.

[0107] Step 508: When the multi-core system concurrently processes the target resource, obtain the first block operation instruction executed by the first core, the second block operation instruction executed by the second core, and the preset instruction quantity;

[0108] Step 510: The first block operation instruction is split into multiple first meta-operation instructions, and the second block operation instruction is split into multiple second meta-operation instructions; the number of first meta-operation instructions is equal to the preset instruction quantity, and the multiple first meta-operation instructions are arranged in a first execution order; the number of second meta-operation instructions is equal to the preset instruction quantity, and the multiple second meta-operation instructions are arranged in a second execution order.

[0109] Step 512: Obtain the delay coefficient and set the expected delay time based on the delay coefficient and the block processing time of the second core;

[0110] Step 514: Generate a delay instruction based on the desired delay duration;

[0111] Step 516: Based on the execution order of multiple first-ary operation instructions, insert delay instructions between adjacent first-ary operation instructions to generate intermittent operation instructions.

[0112] Step 518: Control the execution of intermittent operation instructions. When the delay instruction in the intermittent operation instruction is executed, the unexecuted second-level operation instructions are scheduled to start execution in sequence according to the second execution order until multiple first-level operation instructions and multiple second-level operation instructions are executed.

[0113] Step 520: Based on the scheduling results of the second-order operation instructions during the execution of each delayed instruction, count the valid delayed instructions that have schedulable second-order operation instructions during the execution process, and the idle delayed instructions that do not have schedulable second-order operation instructions during the execution process.

[0114] Step 522: Based on the statistical results of valid delay instructions and idle delay instructions, determine the concurrency control delay duration of the first core and the second core respectively.

[0115] In this embodiment, when there are time-critical tasks, a delay period can be controlled during the slow operation of the first core, allowing the fast second core to complete its task as quickly as possible within that delay period. Furthermore, the concurrent control delay durations of the first and second cores can be quantitatively analyzed. Applying this method to a chip can both identify multi-core conflicts and ensure the critical timing of the multi-core system, enabling its smooth operation.

[0116] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0117] Based on the same inventive concept, this application also provides a multi-core system concurrency control device for implementing the multi-core system concurrency control method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more embodiments of the multi-core system concurrency control device provided below can be found in the limitations of the multi-core system concurrency control method described above, and will not be repeated here.

[0118] In one exemplary embodiment, such as Figure 6 As shown, a multi-core system concurrency control device is provided, including: a concurrency control core determination module 602, an operation instruction splitting module 604, a delay instruction insertion module 606, and an instruction execution control module 608, wherein:

[0119] The concurrency control core determination module is used to obtain the working status of multiple cores in a multi-core system when they are concurrently processing the same resources, and to determine the first core and the second core from the multiple cores based on the working status of the multiple cores; the block processing time of the first core is greater than the block processing time of the second core.

[0120] The operation instruction splitting module is used to split the first block operation instruction executed by the first core into multiple first meta operation instructions when the multi-core system concurrently processes the target resource, and to split the second block operation instruction executed by the second core into multiple second meta operation instructions.

[0121] The delay instruction insertion module is used to insert delay instructions between adjacent first-ary operation instructions according to the execution order of multiple first-ary operation instructions, thereby generating intermittent operation instructions.

[0122] The instruction execution control module is used to execute intermittent operation instructions, and during the execution of the delayed instructions in the intermittent operation instructions, it sequentially schedules the execution of the second-level operation instructions until the first-level operation instructions and the second-level operation instructions are completed.

[0123] The aforementioned multi-core system concurrency control device can determine the first core and the second core based on the working status of multiple cores in the multi-core system when concurrently processing the same resource, wherein the block processing time of the first core is longer than that of the second core. When the multi-core system concurrently processes the target resource, the first block operation instruction executed by the first core is split into multiple first-level operation instructions, and the second block operation instruction executed by the second core is split into multiple second-level operation instructions. Then, according to the execution order of the multiple first-level operation instructions, delay instructions are inserted between adjacent first-level operation instructions to generate intermittent operation instructions. Then, the intermittent operation instructions are executed, and during the execution of the delay instructions in the intermittent operation instructions, the second-level operation instructions are scheduled to be executed sequentially until the first-level operation instructions and the second-level operation instructions are completed. The process first distinguishes between two types of cores with different block processing times. Then, delay instructions are inserted into multiple first-order operation instructions with longer block processing times to generate intermittent operation instructions. This allows for the sequential execution of multiple first-order operation instructions while simultaneously interleaving multiple second-order operation instructions with shorter block processing times, preventing the second cores with shorter block processing times from waiting for extended periods. Based on this, the overall performance of the multi-core system can be improved.

[0124] In one embodiment, the concurrency control core determination module includes:

[0125] The block type determination unit is used to determine the block type used by each core when there is a running conflict among multiple cores based on their working status. The block type includes Class I blocks and Class II blocks. The block processing time of a core using Class I blocks is greater than that of a core using Class II blocks.

[0126] The concurrency control core differentiation unit is used to designate the cores that use type 1 blocks as the first cores and the cores that use type 2 blocks as the second cores.

[0127] In one embodiment, the operation instruction splitting module includes:

[0128] The instruction acquisition unit is used to acquire the first block operation instruction executed by the first core, the second block operation instruction executed by the second core, and a preset instruction quantity when the multi-core system concurrently processes the target resource;

[0129] The first instruction splitting unit is used to split the first block operation instruction into multiple first meta-operation instructions arranged in a first execution order according to the execution timing of the first block operation instruction, and the number of first meta-operation instructions is equal to the preset instruction quantity.

[0130] The second instruction splitting unit is used to split the second block operation instruction into multiple second-level operation instructions arranged in a second execution order according to the execution timing of the second block operation instruction, and the number of second-level operation instructions is equal to the preset instruction quantity.

[0131] In one embodiment, the multi-core system concurrency control device further includes a delay instruction generation module, which includes:

[0132] The parameter acquisition unit is used to acquire the delay coefficient and set the expected delay time based on the delay coefficient and the block processing time of the second core.

[0133] The delay instruction generation unit is used to generate delay instructions according to the expected delay duration.

[0134] In one embodiment, the intermittent operation instructions include: a plurality of first-level operation instructions arranged in a first execution order, and delay instructions inserted between adjacent first-level operation instructions; the plurality of second-level operation instructions are arranged in a second execution order. Based on this, the instruction execution control module includes:

[0135] The execution monitoring unit is used to control the execution of intermittent operation instructions from the first primary operation instruction, and to monitor whether a delayed instruction is executed during the execution process;

[0136] The instruction scheduling unit is used to schedule the execution of unexecuted second-ary operation instructions in a second execution order during the execution of delayed instructions, until multiple first-ary operation instructions and multiple second-ary operation instructions have been executed.

[0137] In one embodiment, the multi-core system concurrency control device further includes:

[0138] The scheduling result statistics unit is used to count the scheduling results of the second-order operation instructions during the execution process of each delayed instruction after the first-order operation instruction and the second-order operation instruction have been executed.

[0139] The delay instruction differentiation unit is used to count the valid delay instructions that have schedulable second-level operation instructions during the execution process and the idle delay instructions that do not have schedulable second-level operation instructions during the execution process, based on the scheduling result of the second-level operation instructions in the execution process of each delay instruction.

[0140] The delay data analysis unit is used to determine the concurrent control delay duration of the first core and the second core based on the statistical results of valid delay instructions and idle delay instructions.

[0141] Each module in the aforementioned multi-core system concurrent control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0142] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores concurrent control data for the multi-core system. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a multi-core system concurrent control method.

[0143] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0144] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0145] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0146] In one embodiment, this application may also provide a chip or chip module, which includes a processor and a data interface. The processor reads instructions stored in the memory through the data interface, thereby executing the steps of the method in any of the above embodiments.

[0147] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0148] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0149] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this application. The above embodiments only illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of this application. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for concurrent control of a multi-core system, characterized in that, The method includes: The system obtains the working status of multiple cores in a multi-core system when they concurrently process the same resources, and determines a first core and a second core from the multiple cores based on their working status; the block processing time of the first core is greater than the block processing time of the second core. When the multi-core system concurrently processes the target resource, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions; Based on the execution order among multiple first-element operation instructions, delay instructions are inserted between adjacent first-element operation instructions to generate intermittent operation instructions. The intermittent operation instruction is executed, and during the execution of the delay instruction in the intermittent operation instruction, the second meta-operation instruction is scheduled to be executed sequentially until the first meta-operation instruction and the second meta-operation instruction are completed.

2. The method according to claim 1, characterized in that, The step of determining the first core and the second core from the plurality of cores based on their working states includes: If, based on the working status of multiple cores, it is determined that there is a running conflict among the multiple cores, the block type used by each core is determined; the block type includes Class I blocks and Class II blocks, and the block processing time of the core using Class I blocks is greater than the block processing time of the core using Class II blocks; The core of the first type of block will be used as the first core, and the core of the second type of block will be used as the second core.

3. The method according to claim 1, characterized in that, When the multi-core system concurrently processes the target resource, the first block operation instruction executed by the first core is split into multiple first meta-operation instructions, and the second block operation instruction executed by the second core is split into multiple second meta-operation instructions, including: When the multi-core system processes the target resource concurrently, it acquires the first block operation instruction executed by the first core, the second block operation instruction executed by the second core, and a preset instruction quantity. According to the execution timing of the first block operation instruction, the first block operation instruction is split into a plurality of first meta-operation instructions arranged in a first execution order, and the number of the first meta-operation instructions is equal to the preset instruction quantity. Based on the execution timing of the second block operation instruction, the second block operation instruction is split into multiple second meta-operation instructions arranged in a second execution order, and the number of the second meta-operation instructions is equal to the preset instruction quantity.

4. The method according to claim 1, characterized in that, The intermittent operation instructions include: a plurality of first meta-operation instructions arranged in a first execution order, and delay instructions inserted between adjacent first meta-operation instructions; the delay instructions are generated in the following manner: obtaining a delay coefficient, and setting an expected delay duration based on the delay coefficient and the block processing time of the second core, and generating a delay instruction according to the expected delay duration; the plurality of second meta-operation instructions are arranged in a second execution order; The execution of the intermittent operation instruction, and the sequential scheduling of the second meta-operation instruction during the execution of the delay instruction within the intermittent operation instruction, until the first meta-operation instruction and the second meta-operation instruction are completed, includes: The intermittent operation instructions are controlled to be executed starting from the first primary operation instruction, and the execution process is monitored to see if the delayed instruction is executed; During the execution of the delay instruction, the second meta-operation instructions that have not yet been executed are scheduled to be executed in sequence according to the second execution order, until the multiple first meta-operation instructions and the multiple second meta-operation instructions have been executed.

5. The method according to claim 1, characterized in that, The method further includes: After the first meta-operation instruction and the second meta-operation instruction are executed, the scheduling result of the second meta-operation instruction during the execution process of each of the delayed instructions is statistically analyzed. Based on the scheduling result of the second-order operation instruction during the execution of each of the delay instructions, count the valid delay instructions that have schedulable second-order operation instructions during the execution process, and the idle delay instructions that do not have schedulable second-order operation instructions during the execution process. Based on the statistical results of the effective delay instructions and the idle delay instructions, the concurrent control delay duration of the first core and the second core is determined respectively.

6. A concurrent control device for a multi-core system, characterized in that, The device includes: The concurrency control core determination module is used to obtain the working status of multiple cores in a multi-core system when they are concurrently processing the same resources, and to determine a first core and a second core from the multiple cores based on the working status of the multiple cores; the block processing time of the first core is greater than the block processing time of the second core; The operation instruction splitting module is used to split the first block operation instruction executed by the first core into multiple first meta-operation instructions and the second block operation instruction executed by the second core into multiple second meta-operation instructions when the multi-core system concurrently processes the target resource. The delay instruction insertion module is used to insert delay instructions between adjacent first element operation instructions according to the execution order of multiple first element operation instructions, thereby generating intermittent operation instructions. The instruction execution control module is used to execute the intermittent operation instruction, and during the execution of the delay instruction in the intermittent operation instruction, to sequentially schedule the execution of the second meta-operation instruction until the first meta-operation instruction and the second meta-operation instruction are completed.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

10. A chip, characterized in that, The chip includes a processor and a data interface. The processor reads instructions stored in the memory through the data interface and can execute the steps of the method according to any one of claims 1 to 5.

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