Method and apparatus for dividing vsg failure phase

Abstract

The disclosure provides a VSG fault stage division method and device, and relates to the technical field of power system relay protection. The VSG fault stage division method comprises the following steps: determining a plurality of division factors according to the voltage drop amplitude variation characteristics in the VSG transient process, and the variation characteristics of the active power instruction value and the reactive power instruction value; and based on the plurality of division factors, the fault stage in the VSG transient process is divided into the LVRT control strategy non-response stage, the LVRT control strategy dynamic change stage, the LVRT control strategy steady state stage and the fault steady state stage in turn. The disclosure divides the VSG fault stage into four stages with clear characteristics, clarifies the dominant role of the detection delay and the control strategy on the fault characteristics in each stage, reveals the physical nature of the transient process in each stage, and provides a theoretical basis and guidance for the VSG fault transient analysis.

Description

Technical Field

[0001] This disclosure relates to the field of power system relay protection technology, specifically to a method and apparatus for dividing VSG fault stages. Background Technology

[0002] Virtual Synchronous Generator (VSG) technology has been widely used in the industry because it can simulate the external characteristics of traditional synchronous generators, such as inertia and damping, effectively improving grid stability. However, when grid faults such as voltage dips occur, the dynamic response process of VSG is extremely complex. Factors such as the switching of its control strategies (e.g., Low-Voltage Ride-Through, LVRT) and the dynamic adjustment of reference values ​​all pose difficulties for the accurate analysis and modeling of fault characteristics.

[0003] Existing VSG fault transient analysis methods typically retain only a portion of the transient process or even completely ignore the fault transient process, considering only the steady-state process, in order to obtain analytical expressions. This leads to discrepancies between the analysis results and the actual system response, as well as unclear physical meaning. Therefore, how to conduct fault transient analysis based on a full consideration of the VSG dynamic response process has become an urgent problem to be solved. Summary of the Invention

[0004] This disclosure addresses the problems existing in the prior art by providing a method and apparatus for dividing VSG fault stages, which can partially or completely solve the aforementioned problems existing in the prior art.

[0005] To achieve the above objectives, the technical solution adopted in this disclosure is as follows:

[0006] A first aspect of this disclosure provides a method for dividing VSG fault phases, comprising: acquiring voltage sag amplitude, active power command value, and reactive power command value during VSG transient processes; when the voltage sag amplitude fluctuates and exceeds the lower limit threshold of the fluctuation range, marking the first fluctuation moment of the fluctuation range as a first dividing factor; under the condition that the voltage sag amplitude continues to drop to the LVRT control switching threshold: marking the moment when the voltage sag amplitude is first less than or equal to the LVRT control switching threshold as a second dividing factor; and marking the moment when the fluctuation amplitude of the voltage sag amplitude is continuously less than or equal to the first threshold within a set sliding window. The last moment when the value and duration are equal to the set duration is marked as the third dividing factor; and the last moment when the deviation between the active power command value and the active power measurement value, and the deviation between the reactive power command value and the reactive power measurement value are both continuously less than or equal to the second threshold and the duration is equal to the set duration is marked as the fourth dividing factor; based on the first dividing factor, the second dividing factor, the third dividing factor and the fourth dividing factor, the fault stages in the VSG transient process are divided into: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady state stage and fault steady state stage.

[0007] In one possible implementation, the method further includes: if the voltage drop amplitude does not continue to drop to the LVRT control switching threshold, the mark of the first division factor is cleared until the voltage drop amplitude fluctuates again and exceeds the lower limit threshold of the fluctuation range, at which point the first fluctuation moment of the fluctuation range is remarked as the first division factor.

[0008] In one possible implementation, based on a first dividing factor, a second dividing factor, a third dividing factor, and a fourth dividing factor, the fault stages in the VSG transient process are sequentially divided into: an LVRT control strategy non-response stage, an LVRT control strategy dynamic change stage, an LVRT control strategy steady-state stage, and a fault steady-state stage. This includes: based on the first and second dividing factors, an LVRT control strategy non-response stage is obtained, which is the fault stage corresponding to the first to second dividing factors; wherein, the LVRT control strategy non-response stage has the following characteristics: the voltage drop amplitude is greater than the LVRT control switching threshold; the active power command value is the active power reference value before the fault; and the reactive power command value is the reactive power reference value before the fault.

[0009] In one possible implementation, based on a first dividing factor, a second dividing factor, a third dividing factor, and a fourth dividing factor, the fault stages in the VSG transient process are sequentially divided into: an LVRT control strategy non-response stage, an LVRT control strategy dynamic change stage, an LVRT control strategy steady-state stage, and a fault steady-state stage. This includes: based on the second and third dividing factors, an LVRT control strategy dynamic change stage is obtained, where the LVRT control strategy dynamic change stage corresponds to the fault stages from the second to the third dividing factors; wherein, the LVRT control strategy dynamic change stage has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the active power command value is the active power reference value for LVRT control; and the reactive power command value is the reactive power reference value for LVRT control.

[0010] In one possible implementation, based on a first dividing factor, a second dividing factor, a third dividing factor, and a fourth dividing factor, the fault stages in the VSG transient process are sequentially divided into: an LVRT control strategy non-response stage, an LVRT control strategy dynamic change stage, an LVRT control strategy steady-state stage, and a fault steady-state stage. This includes: based on the third and fourth dividing factors, a steady-state stage of the LVRT control strategy is obtained, where the steady-state stage corresponds to the fault stages defined by the third to fourth dividing factors. The steady-state stage of the LVRT control strategy possesses the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the fluctuation amplitude of the voltage drop amplitude is less than or equal to the first threshold within a set sliding window; the active power command value is the active power reference value for LVRT control; and the reactive power command value is the reactive power reference value for LVRT control.

[0011] In one possible implementation, based on a first dividing factor, a second dividing factor, a third dividing factor, and a fourth dividing factor, the fault stages in the VSG transient process are sequentially divided into: an LVRT control strategy non-response stage, an LVRT control strategy dynamic change stage, an LVRT control strategy steady-state stage, and a fault steady-state stage. This includes: based on the fourth dividing factor, a fault steady-state stage is obtained, which is the fault stage corresponding to the stage after the fourth dividing factor. The fault steady-state stage possesses the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the fluctuation amplitude of the voltage drop amplitude is less than or equal to the first threshold within a set sliding window; and the deviations between the active power command value and the active power measurement value, and between the reactive power command value and the reactive power measurement value, are less than or equal to the second threshold.

[0012] A second aspect of this disclosure provides a VSG fault phase segmentation device, comprising: an acquisition unit for acquiring voltage sag amplitude, active power command value, and reactive power command value during a VSG transient process; a marking unit for marking the first fluctuation moment of the fluctuation range as a first segmentation factor when the voltage sag amplitude fluctuates and exceeds the lower limit threshold of the fluctuation range; and for marking the moment when the voltage sag amplitude is first less than or equal to the LVRT control switching threshold as a second segmentation factor when the voltage sag amplitude continues to drop to the LVRT control switching threshold; and for marking the moment when the voltage sag amplitude is continuously less than or equal to the LVRT control switching threshold within a set sliding window as a second segmentation factor. The last moment when the value of the active power command value and the active power measurement value are both equal to or equal to the first threshold and the duration is equal to the set duration is marked as the third dividing factor; and the last moment when the deviation between the active power command value and the active power measurement value and the deviation between the reactive power command value and the reactive power measurement value are both continuously less than or equal to the second threshold and the duration is equal to the set duration is marked as the fourth dividing factor; the dividing unit is used to divide the fault stage in the VSG transient process into the following stages based on the first dividing factor, the second dividing factor, the third dividing factor and the fourth dividing factor: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady state stage and fault steady state stage.

[0013] A third aspect of this disclosure provides a method for transient analysis of VSG faults, comprising: dividing the VSG fault stage into four stages using the VSG fault stage division method provided in the first aspect or any possible implementation thereof: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady-state stage, and fault steady-state stage; and performing transient analysis on the VSG fault stage based on the characteristics of each stage.

[0014] A fourth aspect of this disclosure provides a computer device, comprising: a memory for storing instructions; and a processor for invoking the instructions stored in the memory to execute the VSG fault stage division method provided in the first aspect or any possible implementation thereof.

[0015] A fifth aspect of this disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, perform the VSG fault stage division method provided in the first aspect or any possible implementation thereof.

[0016] Compared with the prior art, this disclosure has the following beneficial effects:

[0017] This disclosure clarifies the dominant role of detection delay and control strategy in the fault characteristics of VSG by dividing the VSG fault stage into four distinct stages, and reveals the physical nature of the transient process in each stage, providing a theoretical basis and guidance for the transient analysis of VSG faults. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a VSG stand-alone grid-connected model provided according to an embodiment of this disclosure;

[0019] Figure 2 This is a VSG steady-state and LVRT control block diagram provided according to an embodiment of the present disclosure;

[0020] Figure 3 This is a schematic diagram of the voltage drop amplitude detection output voltage and LVRT control strategy operation according to an embodiment of the present disclosure;

[0021] Figure 4 This is a flowchart illustrating a method for dividing VSG fault stages according to an embodiment of this disclosure;

[0022] Figure 5 This is a schematic diagram of the operation of another voltage drop amplitude detection output voltage and LVRT control strategy according to an embodiment of this disclosure;

[0023] Figure 6 This is a schematic diagram illustrating the division of VSG fault stages according to an embodiment of this disclosure;

[0024] Figure 7 This is a flowchart illustrating a VSG fault transient analysis method provided according to an embodiment of this disclosure;

[0025] Figure 8 This is a structural block diagram of a VSG fault stage division device provided according to an embodiment of the present disclosure. Detailed Implementation

[0026] The present disclosure will now be further described with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present disclosure and should not be construed as limiting the scope of protection of the present disclosure. It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application.

[0027] The acquisition, transmission, storage, use, and processing of data in this disclosed technical solution comply with relevant national laws and regulations. In the embodiments of this disclosure, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this disclosure, and do not imply that the applicant has already used or necessarily used such solutions.

[0028] All terms used in this disclosure have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as having idealized or highly formalized meanings, unless expressly defined herein.

[0029] In recent years, with the large-scale integration of power electronic equipment into the power grid, their inherent low inertia and weak damping characteristics have posed a severe challenge to the stability of traditional power systems dominated by synchronous machines. Virtual synchronous generator (VSG) technology, due to its ability to simulate the inertia and damping characteristics of traditional synchronous generators, effectively improves grid stability and has been widely adopted in the industry. For example... Figure 1 As shown, a circuit diagram of a VSG standalone grid-connected model is illustrated. In the diagram, U dc The DC side voltage of the VSG, u sabc and i sabc These are the VSG output voltage and VSG output current, respectively. pcc L is the voltage amplitude detected at the point of common coupling (PCC). f C f These are the filter inductor and filter capacitor, R. f L is the parasitic resistance of the filter inductor. g R g These are the line inductance and the line resistance, respectively.

[0030] However, when faults such as voltage dips occur in the power grid, the dynamic response process of the VSG is extremely complex. Factors such as the switching of its control strategy and the dynamic adjustment of reference values ​​make accurate analysis and modeling of fault characteristics difficult. Specifically, for example... Figure 2 As shown, a VSG steady-state and LVRT control block diagram is illustrated, including a virtual synchronization loop, a virtual impedance loop, and a current inner loop. When the voltage drop amplitude is greater than 0.9 pu, it operates in steady-state control mode; when the voltage drop amplitude is less than or equal to 0.9 pu, it switches to LVRT control mode. Figure 2 In the middle, ω N P is the virtual speed rating of the VSG. ref0 Q ref0 E* and P represent the active power reference value, reactive power reference value, and voltage reference value under normal operating conditions (i.e., before the fault), respectively. e and Q e These are the measured values ​​of active power and reactive power, respectively, P LVRT and Q LVRTThese are the active power reference value and reactive power reference value under the LVRT control strategy, respectively. U is the PCC voltage amplitude detection value. During low voltage ride-through, to limit fault current, the voltage reference value switches to U. The virtual synchronization loop includes an active power control branch and a reactive power control branch. In the active power control branch: the reference active power P... ref0 / P LVRT With measurement of active power P e The deviation is processed by an integrator (simulating the moment of inertia J of the synchronous machine) and a damping element (simulating the damping coefficient D) to output a virtual electric angular velocity ω, which is then integrated to obtain the virtual power angle θ. ref In the reactive power control branch: refer to reactive power Q. ref0 / Q LVRT The deviation from the measured reactive power Qe is processed by a proportional element (k q (Reactive power - voltage droop coefficient), combined with voltage feedforward E* / E * LVRT Output virtual electromotive force amplitude E ref After that, θ ref and E ref The output potential e of the virtual synchronization loop is obtained through coordinate transformation (abc→dq). d and e q Furthermore, the output e of the virtual synchronization ring... d and e q In the input virtual impedance loop, through the virtual resistor R V and virtual inductance L V Output reference current i * d and i * q Furthermore, the output i of the virtual impedance loop... * d and i * q In the inner loop of the input current, after passing through the proportional-integral controller (PI), combined with u d and u q Output reference voltage u * sd and u * sq Then, through coordinate transformation (dq→abc), u is obtained. * abc Finally, it is output via sinusoidal pulse width modulation (SPWN).

[0031] Against this backdrop, existing VSG fault transient analysis methods typically retain only a portion of the transient process or even completely ignore the fault transients and only consider the steady-state process in order to obtain analytical expressions. This leads to discrepancies between the analysis results and the actual system response, as well as unclear physical meaning. Therefore, how to conduct fault transient analysis based on a full consideration of the VSG dynamic response process has become an urgent problem to be solved.

[0032] Considering the inherent temporal relationships of the dominant factors in the VSG during the fault transient process, a feasible approach is to analyze the dynamic characteristics during the fault period in segments. Existing similar methods generally treat the fault transient stage as the smallest unit of division, treating it alongside the pre-fault and post-fault steady-state stages, such as... Figure 3 As shown, assume the voltage drop amplitude U at time t. pcc.f If the value equals 0.9 pu, then the LVRT control action at time t changes from 0 to 1, that is, the LVRT control strategy is activated, dividing the period before time t into the pre-fault phase and the period after time t into the post-fault phase. However, there is little research on segmentation methods that focus on the transient phase of VSG faults (referred to as the VSG fault phase in this disclosure).

[0033] In summary, to address the issues of insufficient accuracy and unclear physical meaning in existing VSG fault characteristic analysis methods, it is necessary to conduct research on a method that considers the dynamic response characteristics during the fault period and performs refined segmentation, providing theoretical guidance for more in-depth fault characteristic analysis.

[0034] Based on this, this disclosure provides a method for dividing VSG fault stages. Figure 4 This is a flowchart illustrating a method for dividing VSG fault stages according to an embodiment of this disclosure, as shown below. Figure 4 As shown, the method for dividing the VSG fault stages includes steps S11 to S14.

[0035] Step S11: Obtain the voltage drop amplitude, active power command value, and reactive power command value during the VSG transient process.

[0036] It should be noted that the voltage drop amplitude is the per-unit value of the voltage amplitude detection value at the PCC point, for example... Figure 1 u in pcc The per-unit value is the ratio of the detected voltage amplitude at the PCC point to the rated voltage amplitude. The active power command value and reactive power command value are P and Q input in the virtual synchronization loop, for example... Figure 2 P in ref0 / P LVRT Q ref0 / Q LVRT .

[0037] Step S12: When the voltage drop amplitude fluctuates and exceeds the lower limit threshold of the fluctuation range, mark the first fluctuation moment of the fluctuation range as the first dividing factor.

[0038] In one possible implementation, the lower threshold of the fluctuation range can be 0.95 pu to 0.99 pu. For example, in a specific embodiment, such as... Figure 5 As shown, the lower threshold of the fluctuation range is set to 0.95pu, assuming a voltage drop amplitude U pcc.f The first voltage drop (fluctuation) occurs at time t0, and the voltage continues to drop within the fluctuation range of 0.95 pu to 1 p.u. Then, when the voltage drop amplitude U pcc.f When the value exceeds 0.95 pu, trace back to time t0 and mark time t0 as the first dividing factor.

[0039] Step S13: Under the condition that the voltage drop amplitude continues to drop to the LVRT control switching threshold: mark the moment when the voltage drop amplitude is first less than or equal to the LVRT control switching threshold as the second dividing factor; mark the last moment when the fluctuation amplitude of the voltage drop amplitude is continuously less than or equal to the first threshold within the set sliding window and the duration is equal to the set duration as the third dividing factor; and mark the last moment when the deviation between the active power command value and the active power measurement value, and the deviation between the reactive power command value and the reactive power measurement value are both continuously less than or equal to the second threshold and the duration is equal to the set duration as the fourth dividing factor.

[0040] It should be noted that a sliding window refers to an analysis window that continuously slides forward from the current moment, always using the current moment as the endpoint. The fluctuation amplitude is calculated as the difference between the maximum and minimum values ​​within the time window, and is used to characterize the maximum range of signal change within that time period.

[0041] In one possible implementation, stability is determined when the signal fluctuation amplitude remains below a set threshold (±2% to ±5% of the rated value) for 20ms within a 10ms sliding window. The last moment of this stability determination is then marked as the third dividing factor. Before the third dividing factor, the LVRT control strategy has not reached a steady state; after the third dividing factor, the LVRT control strategy reaches a steady state.

[0042] In one possible implementation, if the voltage drop amplitude does not continue to drop to the LVRT control switching threshold, the mark of the first division factor is cleared until the voltage drop amplitude fluctuates again and exceeds the lower limit threshold of the fluctuation range, at which point the first fluctuation moment of the fluctuation range is remarked as the first division factor.

[0043] Step S14: Based on the first dividing factor, the second dividing factor, the third dividing factor, and the fourth dividing factor, the fault stages in the VSG transient process are sequentially divided into: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady-state stage, and fault steady-state stage.

[0044] In one possible implementation, based on various dividing factors, the fault stages in the VSG transient process are sequentially divided into: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady-state stage, and fault steady-state stage. This division can be carried out through the following steps.

[0045] Step 1: Based on the first and second division factors, the LVRT control strategy non-response stage is determined. The LVRT control strategy non-response stage is the fault stage corresponding to the first to the second division factors. The LVRT control strategy non-response stage has the following characteristics: the voltage drop amplitude is greater than the LVRT control switching threshold; the active power command value is the active power reference value before the fault; and the reactive power command value is the reactive power reference value before the fault.

[0046] For example, in one specific embodiment, such as Figure 5 As shown, t0-t1 corresponds to the LVRT control strategy non-response stage. During this stage, the LVRT control action is 0, meaning the LVRT control strategy is not activated. In this stage, the voltage drop amplitude U pcc.f The power command value remains between 0.9 pu and 1 p.u., and remains at the pre-fault level.

[0047] Step 2: Based on the second and third division factors, the dynamic change stage of the LVRT control strategy is determined. The dynamic change stage of the LVRT control strategy is the fault stage corresponding to the second to third division factors. The dynamic change stage of the LVRT control strategy has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the active power command value is the active power reference value of the LVRT control; the reactive power command value is the reactive power reference value of the LVRT control; and the voltage command value is the voltage reference value of the LVRT control.

[0048] For example, in one specific embodiment, such as Figure 5 As shown, t1-t2 corresponds to the dynamic change stage of the LVRT control strategy. At this time, the LVRT control action is 1, that is, the LVRT control strategy has been activated. During this stage, the voltage drop amplitude U pcc.f Located in E m1 The power command value varies dynamically under the LVRT control strategy, ranging from ~0.9 pu.

[0049] Step 3: Based on the third and fourth division factors, the steady-state stage of the LVRT control strategy is determined. The steady-state stage of the LVRT control strategy is the fault stage corresponding to the third to fourth division factors. The steady-state stage of the LVRT control strategy has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the fluctuation amplitude of the voltage drop amplitude is less than or equal to the first threshold within the set sliding window; the active power command value is the active power reference value of the LVRT control; and the reactive power command value is the reactive power reference value of the LVRT control.

[0050] For example, in one specific embodiment, such as Figure 5 As shown, t2-t3 corresponds to the steady-state stage of the LVRT control strategy. At this time, the LVRT control action is 1, and the LVRT control strategy enters the steady-state stage. In this stage, the voltage drop amplitude U pcc.f It remains almost unchanged, that is, the voltage drop magnitude U pcc.f It enters the corresponding steady-state error band (usually within ±2% to ±5% of the rated value, such as...). Figure 5 E shown m1 (within a fluctuation range of ±2% to ±5%), the power measurement value continuously tracks the power command value under the LVRT control strategy.

[0051] Step 4: Based on the fourth division factor, the fault steady-state stage is obtained. The fault steady-state stage is the fault stage corresponding to the fourth division factor. The fault steady-state stage has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the fluctuation amplitude of the voltage drop amplitude is less than or equal to the first threshold within the set sliding window; the deviation between the active power command value and the active power measurement value, and the deviation between the reactive power command value and the reactive power measurement value are less than or equal to the second threshold.

[0052] For example, in one specific embodiment, such as Figure 5 As shown, the period after t4 is divided into the fault steady-state stage. At this time, the LVRT control action is 1, the LVRT control strategy has reached steady state, and the fault stage as a whole enters the steady-state stage. In this stage, the voltage drop amplitude U pcc.f It has entered the corresponding steady-state error band (usually within ±2% to ±5% of the rated value, such as...). Figure 5 E shown m1 The power measurement value fluctuates within a range of ±2% to ±5%, and the deviation between the power measurement value and the power command value gradually decreases. In other words, the power measurement value tracks the power command value and enters the corresponding steady-state error band (i.e., within ±2% to ±5% of the command value).

[0053] This disclosure aims to divide the complex VSG fault response process into several well-defined stages based on time sequence and dominant factors, and to clarify how detection delay and control strategies dominate the fault characteristics of each stage, thereby providing guidance for establishing a simplified analysis model for each stage.

[0054] The VSG fault transient analysis method provided in this disclosure divides the entire VSG short-circuit fault process into four distinct stages based on the dynamic changes in voltage drop amplitude and various command values: the LVRT control strategy non-response stage, the LVRT control strategy dynamic change stage, the LVRT control strategy steady-state stage, and the fault steady-state stage. This method clarifies the dominant role of detection delay and control strategy in the fault characteristics of each stage, reveals the physical nature of the transient process in each stage, and provides a theoretical basis and guidance for establishing accurate analysis models, optimizing low-voltage ride-through control strategies, and suppressing fault current.

[0055] For ease of understanding, the following example illustrates a division result obtained using the VSG fault stage division method provided in the above embodiments of this disclosure.

[0056] like Figure 6 As shown, assuming t0 is the first dividing factor, t1 is the second dividing factor, t2 is the third dividing factor, and t3 is the fourth dividing factor, the VSG fault stage is divided into four stages: t0-t1 is the first stage, i.e., the LVRT control strategy unresponsive stage; t1-t2 is the second stage, i.e., the LVRT control strategy dynamic change stage; t2-t3 is the third stage, i.e., the LVRT control strategy steady-state stage; and t3 onwards is the fourth stage, i.e., the fault steady-state stage. In the first stage, the dominant factors of the transient process are: the actual fault state + the pre-fault control strategy; in the second stage, the dominant factors are: the dynamic process of the LVRT control strategy reference value + the dynamic process of the actual value tracking the reference value; in the third stage, the dominant factor is: the dynamic process of the LVRT control actual value tracking the reference value; and in the fourth stage, the dominant factor is the arrival of steady state.

[0057] In practical systems, for short-circuit faults, due to the inertia of the voltage drop detection circuit and the time required for the control loop response, the actual implementation of the LVRT strategy often has a certain delay. Figure 5 As shown, this delay triggers a series of transient processes, during which the fault characteristics are significantly affected. Taking a three-phase symmetrical short circuit as an example, the entire fault process is divided into four stages based on the changes in voltage detection amplitude and control reference value. Figure 5 The timeline is marked accordingly, together forming a complete dynamic process of VSG fault characteristics.

[0058] LVRT control strategy non-response phase t0-t1: At time t0, the fault occurs, the grid connection point experiences a symmetrical voltage drop, and the physical system changes instantaneously. However, due to a delay in the control system, the voltage detection output voltage amplitude does not reach the LVRT control switching threshold until time t1, while the power reference value remains unchanged at the pre-fault level. However, because the physical system voltage has already dropped, constrained by power conservation, the VSG output short-circuit current passively increases until entering the next phase. Therefore, the fault characteristics in this phase are dominated by the actual fault state and the pre-fault control strategy, and the VSG output short-circuit current is usually the most severe stage of the entire transient process. During this phase, the fault occurs, but because the LVRT control strategy is not switched to within a short time, the fault characteristics are dominated by the actual fault state and the pre-fault control strategy. The fault current passively depends on the large voltage difference between the inverter port (still under normal control strategy) and the fault point. Therefore, this phase usually has the largest short-circuit current amplitude during the entire fault transient process.

[0059] During the dynamic change phase of the LVRT control strategy (t1-t2): At time t1, the output voltage amplitude of the voltage drop detection circuit reaches the LVRT control switching threshold (typically 0.9 pu), and the LVRT control strategy is activated. Figure 5 It can be seen that during this stage, the voltage drop detection stage continues to track the actual fault voltage, and the output voltage amplitude continues to change. The duration of this dynamic process is related to the voltage drop depth, and the VSG control strategy is shown in equations (1)-(3):

[0060] (1);

[0061] (2);

[0062] (3)

[0063] In the formula, P ref0 Q ref0 E * U represents the active power, reactive power, and voltage reference values ​​under normal operating conditions, and U is the voltage amplitude detected at the PCC point. * I is the per-unit value of the voltage amplitude detection value at the PCC point (i.e., the voltage drop amplitude). N i is the virtual current rating of VSG. d0 I is the reference value for the d-phase current. max This is the inverter's withstand current value, typically taken as 1.5 times I. N .

[0064] When operating normally, when U * When P is in the range of 0.9 to 1 p.u. ref Q ref E refCorresponding to the active power reference value, reactive power reference value, and voltage reference value under normal operating conditions; during low-voltage ride-through, i.e., when U * When it enters the 0.2~0.9 pu range, E ref The corresponding voltage amplitude detection value at the PCC point, i.e., E ref =U,P ref and Q ref Corresponding active power reference values ​​and reactive power reference values ​​for fault transients; when U * When entering the 0~0.2pu range, VSG off-network handover is triggered.

[0065] According to the above formula, when the detected voltage amplitude U at point PCC... * When the voltage drops to the 0.2~0.9 pu range, VSG will switch to LVRT control strategy. The change in the output voltage amplitude of the voltage drop detection stage will cause a transient change in the reference value of LVRT control. Therefore, the fault characteristics at this stage are jointly dominated by the dynamic process of the reference value of LVRT control strategy and the dynamic process of the actual value tracking the reference value. Accordingly, the deeper the voltage drop, the longer the transient process of voltage drop detection stage, and the longer the dynamic change time of LVRT control strategy.

[0066] The fault characteristics at this stage are jointly dominated by the dynamic process of the reference value in the LVRT control strategy and the dynamic process of the actual value tracking the reference value.

[0067] Steady-state phase t2-t3 of LVRT control strategy: At time t2, the output voltage amplitude of the voltage drop detection loop reaches a steady state, and the actual value of the LVRT control strategy reference value also reaches a steady state. Affected by the response time of the power outer loop and the virtual impedance loop, the actual power value will track the reference value in a transient process. Therefore, the fault characteristics in this phase are only dominated by the dynamic process of the LVRT control actual value tracking the reference value.

[0068] After the fault steady-state phase t3: At time t3, the fault transient process ends, and the system reaches a steady state. During this phase, the LVRT control actual value tracks the reference value, the transient process ends, and the system enters steady state.

[0069] In other words, the VSG fault stage division method provided in this disclosure effectively takes into account the impact of LVRT strategy activation delay caused by voltage detection delay and power reference value changes when dividing the VSG fault characteristic stages. For the first time, it divides the complex VSG fault response process into four distinct stages based on time sequence and dominant factors. Compared with existing VSG fault characteristic analysis methods that retain some transient processes or even completely ignore fault transients and only consider steady-state processes, this disclosure retains the transient characteristics of each VSG fault to the greatest extent, providing a theoretical basis and guidance for establishing accurate analysis models, optimizing low-voltage ride-through control strategies, and suppressing fault currents.

[0070] Based on this, this disclosure also provides a method for transient analysis of VSG faults. Figure 7 This is a flowchart illustrating a VSG fault transient analysis method provided according to an embodiment of this disclosure, as shown below. Figure 7 As shown, the VSG fault transient analysis method includes steps S21 to S22.

[0071] Step S21: Divide the VSG fault stage into four stages: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady state stage, and fault steady state stage.

[0072] In this embodiment of the disclosure, the VSG fault stage is divided into four stages by adopting the VSG fault stage division method provided in the above embodiments.

[0073] Step S22: Perform transient analysis on the VSG fault stage based on the characteristics of each stage.

[0074] It should be noted that, since each stage of the VSG failure process has different characteristics, analyzing the characteristics of each stage can enable more accurate transient analysis of the VSG failure process.

[0075] In one possible implementation, a VSG transient analysis model can be further established based on the transient analysis results; in another possible implementation, the low-pressure ride-through control strategy can be further optimized based on the transient analysis results.

[0076] For specific details and benefits of the VSG fault transient analysis method provided in the embodiments of this disclosure, please refer to the above description of the method for dividing VSG fault stages, which will not be repeated here.

[0077] Based on this, the present disclosure also provides a device for dividing VSG fault stages. Figure 8 This is a structural block diagram of a VSG fault stage division device provided according to an embodiment of the present disclosure, such as... Figure 8As shown, the device 100 includes an acquisition unit 110, a marking unit 120, and a division unit 130.

[0078] The acquisition unit 110 is used to acquire the voltage drop amplitude, active power command value and reactive power command value during the VSG transient process;

[0079] The marking unit 120 is used to mark the first fluctuation moment of the fluctuation range as a first dividing factor when the voltage drop amplitude fluctuates and exceeds the lower limit threshold of the fluctuation range; and to mark the moment when the voltage drop amplitude is first less than or equal to the LVRT control switching threshold as a second dividing factor when the voltage drop amplitude continues to drop to the LVRT control switching threshold; to mark the last moment when the fluctuation amplitude of the voltage drop amplitude is continuously less than or equal to the first threshold and the duration is equal to the set duration as a third dividing factor; and to mark the last moment when the deviation between the active power command value and the active power measurement value, and the deviation between the reactive power command value and the reactive power measurement value are both continuously less than or equal to the second threshold and the duration is equal to the set duration as a fourth dividing factor.

[0080] The partitioning unit 130 is used to divide the fault stage in the VSG transient process into the following stages based on the first partitioning factor, the second partitioning factor, the third partitioning factor, and the fourth partitioning factor: the LVRT control strategy non-response stage, the LVRT control strategy dynamic change stage, the LVRT control strategy steady-state stage, and the fault steady-state stage.

[0081] For details and benefits of the VSG fault stage division device provided in the embodiments of this disclosure, please refer to the above description of the VSG fault stage division method, which will not be repeated here.

[0082] Based on this, the present disclosure also provides a computer device, including: a memory for storing instructions; and a processor for calling the instructions stored in the memory to execute the VSG fault stage division method provided in the above embodiments.

[0083] For specific details and benefits of the computer equipment provided in this disclosure, please refer to the above description of the method for dividing VSG fault stages, which will not be repeated here.

[0084] Based on this, the present disclosure also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, perform the VSG fault stage division method provided in the embodiments.

[0085] For specific details and benefits of the computer-readable storage medium provided in this disclosure, please refer to the above description of the method for dividing VSG fault stages, which will not be repeated here.

[0086] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0087] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0088] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0089] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0090] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0091] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0092] It should also be noted that the terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Terms such as "including" or "contains" mean that the element preceding the word covers the element listed after the word, and do not exclude the possibility of covering other elements as well.

[0093] Although operations are described in a specific order in the accompanying drawings in this disclosure, it should not be construed as requiring these operations to be performed in the specific order or serial order shown, or requiring all of the shown operations to obtain the desired result. In certain environments, multitasking and parallel processing may be advantageous.

[0094] Finally, it should be noted that the above content is only used to illustrate the technical solution of this disclosure, and is not intended to limit the scope of protection of this disclosure. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of this disclosure do not depart from the substance and scope of the technical solution of this disclosure.

Claims

1. A method of partitioning VSG fault phases, characterized by, Comprising: acquiring a voltage drop amplitude, an active power instruction value and a reactive power instruction value in a VSG transient process; when the voltage drop amplitude fluctuates and exceeds a lower threshold of a fluctuation interval, marking a first fluctuation time of the fluctuation interval as a first division factor; under the condition that the voltage drop amplitude continuously drops to an LVRT control switching threshold: marking a time when the voltage drop amplitude is first less than or equal to the LVRT control switching threshold as a second division factor; marking a last time when the fluctuation amplitude of the voltage drop amplitude is continuously less than or equal to a first threshold in a set sliding window and the continuous duration is equal to a set duration as a third division factor; and marking a last time when the deviation of the active power instruction value and the active power measurement value, the deviation of the reactive power instruction value and the reactive power measurement value are both continuously less than or equal to a second threshold and the continuous duration is equal to a set duration as a fourth division factor; based on the first division factor, the second division factor, the third division factor and the fourth division factor, sequentially dividing a fault stage in the VSG transient process into: an LVRT control strategy non-response stage, an LVRT control strategy dynamic change stage, an LVRT control strategy steady state stage and a fault steady state stage, specifically comprising: based on the first division factor and the second division factor, the LVRT control strategy non-response stage is obtained, which is the fault stage corresponding to the first division factor to the second division factor; based on the second division factor and the third division factor, the LVRT control strategy dynamic change stage is obtained, which is the fault stage corresponding to the second division factor to the third division factor; based on the third division factor and the fourth division factor, the LVRT control strategy steady state stage is obtained, which is the fault stage corresponding to the third division factor to the fourth division factor; based on the fourth division factor, the fault steady state stage is obtained, which is the fault stage corresponding to the fourth division factor.

2. The method of claim 1, wherein, Further comprising: if the voltage drop amplitude does not continuously drop to the LVRT control switching threshold, the marking of the first division factor is cleared, and the first fluctuation time of the fluctuation interval is re-marked as the first division factor when the voltage drop amplitude fluctuates and exceeds the lower threshold of the fluctuation interval next time.

3. The method of partitioning VSG failure phases according to claim 1 or 2, characterized in that, the LVRT control strategy non-response stage has the following characteristics: the voltage drop amplitude is greater than the LVRT control switching threshold; the active power instruction value is the active power reference value before the fault; and the reactive power instruction value is the reactive power reference value before the fault.

4. The method of partitioning VSG failure phases according to claim 1 or 2, characterized in that, the LVRT control strategy dynamic change stage has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the active power instruction value is the active power reference value under LVRT control; and the reactive power instruction value is a reactive power reference value of LVRT control.

5. The method of partitioning VSG failure phases according to claim 1 or 2, characterized in that, The LVRT control strategy steady-state stage has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the fluctuation amplitude of the voltage drop amplitude is less than or equal to the first threshold within a set sliding window; the active power instruction value is an active power reference value of LVRT control; and the reactive power instruction value is a reactive power reference value of LVRT control.

6. The method of VSG failure phase partitioning according to claim 1 or 2, c h a r a c t e r i z e d b y, The fault steady-state stage has the following characteristics: the voltage drop amplitude is less than or equal to the LVRT control switching threshold; the fluctuation amplitude of the voltage drop amplitude is less than or equal to the first threshold within a set sliding window; The deviation of the active power instruction value from the active power measurement value and the deviation of the reactive power instruction value from the reactive power measurement value are less than or equal to the second threshold.

7. An apparatus for partitioning VSG failure phases, characterized by Comprise: An acquisition unit is configured to acquire a voltage drop amplitude, an active power instruction value and a reactive power instruction value in a VSG transient process; A marking unit is configured to mark a first fluctuation time of a fluctuation interval as a first division factor when the voltage drop amplitude fluctuates and exceeds a lower threshold of the fluctuation interval; and for the condition that the voltage drop amplitude continues to drop to the LVRT control switching threshold: mark a time when the voltage drop amplitude is less than or equal to the LVRT control switching threshold for the first time as a second division factor; mark a last time when the fluctuation amplitude of the voltage drop amplitude continues to be less than or equal to the first threshold within a set sliding window and the duration is equal to a set duration as a third division factor; and mark a last time when the deviation of the active power instruction value from the active power measurement value and the deviation of the reactive power instruction value from the reactive power measurement value are both less than or equal to the second threshold and the duration is equal to a set duration as a fourth division factor; A division unit is configured to sequentially divide a fault stage in the VSG transient process into an LVRT control strategy non-response stage, an LVRT control strategy dynamic change stage, an LVRT control strategy steady-state stage and a fault steady-state stage based on the first division factor, the second division factor, the third division factor and the fourth division factor, specifically comprising: Based on the first division factor and the second division factor, the LVRT control strategy non-response stage is obtained, which is a fault stage corresponding to the first division factor to the second division factor; Based on the second division factor and the third division factor, the LVRT control strategy dynamic change stage is obtained, which is a fault stage corresponding to the second division factor to the third division factor; Based on the third division factor and the fourth division factor, the LVRT control strategy steady-state stage is obtained, which is a fault stage corresponding to the third division factor to the fourth division factor; Based on the fourth division factor, the fault steady-state stage is divided, and the fault steady-state stage is a fault stage corresponding to the fourth division factor.

8. A method of VSG fault transient analysis, characterized by, Comprise: By using the VSG fault stage division method in any one of claims 1-6, the VSG fault stage is divided into four stages: LVRT control strategy non-response stage, LVRT control strategy dynamic change stage, LVRT control strategy steady-state stage and fault steady-state stage; Based on the characteristics of each stage of the VSG fault stage, the transient analysis of the VSG fault stage is performed.

9. A computer device, comprising: Comprise: Memory for storing instructions; And Processor for calling the instructions stored in the memory to execute the VSG fault stage division method in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions, and the computer executable instructions are executed by the processor to execute the VSG fault stage division method in any one of claims 1-6.

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