A method for dynamic balancing of temperature rise of an active neutral point clamped three-level inverter

Abstract

The application discloses a temperature rise dynamic balancing method of an active neutral point clamped three-level inverter, first analyzes different zero state paths, obtains ANPC-3L inverter switch loss distribution states, then according to the distribution characteristics of local energy concentration of device switching, carries out short-time averaging on power pulses in the pulse area of device opening and closing energy concentration, thereby guaranteeing the authenticity of device temperature rise fluctuation, balancing the contradiction between accuracy and calculation complexity. On this basis, the application deduces a switch loss calculation method based on power pulse short-time equivalence, uses the loss calculation method, adopts the device fundamental frequency junction temperature balancing idea, improves the inverter output capacity and cross-condition adaptability, and guarantees the dynamic balance of the three-level inverter temperature rise.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electric drive of new energy vehicles, and particularly relates to a temperature rise dynamic balancing method for an active neutral point clamped three-level inverter. BACKGROUND

[0002] The vehicle-mounted inverter, which is the core energy conversion unit of the electric drive system, is facing the urgent demand of continuously improving the output power and energy density. However, the continuous increase in power demand also makes the thermal management problem of the power devices inside the inverter increasingly severe. In the traditional neutral point clamped three-level inverter, due to the inherent characteristics of the topology structure and the modulation strategy, the power loss distribution among the power switching devices is uneven, which leads to a significant temperature rise imbalance in actual operation. This problem not only limits the continuous output capability of the inverter as a whole, but also poses a serious threat to the long-term operation reliability of the power devices including IGBT and diode, thereby affecting the power performance and service life of the whole vehicle. The ANPC-3L (active neutral point clamped three-level) topology replaces the clamping diode of each phase with a fully controlled switch, providing design freedom for the device temperature rise balancing strategy. Therefore, the research on the device temperature rise balancing method of the ANPC-3L inverter is of great significance for the development of new energy special vehicles using pure electric drive.

[0003] By improving the modulation strategy and actively selecting different zero-state paths, the problem of uneven temperature rise of inverter devices can be improved. Literature [Floricau D, Floricau E, Dumitrescu M. Natural doubling of apparent switching frequency using ANPC type converter. International Conference on Non-Sinusoidal Currents and Compensation, Lagow, 2008: 1-6] introduces an additional phase-shifted 180° carrier to achieve natural frequency doubling, obtaining the driving signals of the inner and outer tubes in one switching cycle, so that the two tubes are alternately turned on and off, each bearing a switching loss. Literature [Lou X T, Zhang L, Chen Y W. Loss balancing and efficiency optimization modulation strategy for 4-SiC ANPC-3L inverter. Proceedings of the Chinese Society of Electrical Engineering, 2022, 42(05): 1925-1933] improves the device loss distribution by configuring asymmetric double modulation waves and rotating the selection of zero-state paths. However, such methods mostly use fixed zero-state selection methods, which are difficult to adapt to dynamic demands under different working conditions.

[0004] To improve the dynamic performance, the literature [TAN Guojun, JING Wei. Active clamp three-level inverter and its junction temperature balance control. Transactions of China Electrotechnical Society, 2012, 27(02): 97-102] dynamically selects the zero state path according to the temperature feedback of the switching device, but this method has the problem of frequent switching of zero state in the power frequency cycle. The literature [L. Ma, T. Kerekes, P. Rodriguez, X. Jin, R. Teodorescu, M. Liserre. A novel PWM strategy for grid-connected half-bridge ANPC converter with loss distribution balancing mechanism. IEEE Transactions on Power Electronics, 2015, vol. 30, no. 9: 5331-5340] proposes a switching loss balancing strategy based on power frequency cycle control, which adjusts the time allocation ratio of ANPC-1 and ANPC-2 online to improve the dynamic balancing ability of device loss, which provides a new idea for ANPC-3L inverter device temperature rise balancing, but the selection of the proportion coefficient still lacks theoretical basis.

[0005] Therefore, the thermal balancing strategy of the current ANPC-3L inverter needs to be improved in different working conditions; how to design a dynamic adjustment method to effectively balance the temperature rise of power devices in different working conditions and improve the output capacity of the inverter is still challenging. SUMMARY

[0006] In view of the above, the present application provides a temperature rise dynamic balancing method of an active neutral point clamped three-level inverter, which can realize the device temperature rise balancing of the active neutral point clamped three-level inverter under dynamic working conditions.

[0007] A temperature rise dynamic balancing method of an active neutral point clamped three-level inverter, comprising the following steps:

[0008] (1) Analyzing different zero state paths to obtain the switching loss distribution state of the ANPC-3L inverter;

[0009] (2) According to the switching loss distribution state, determining the related devices with switching loss and conduction loss and the highest temperature rise under the commutation mode of ANPC-1 and ANPC-2;

[0010] (3) According to the distribution characteristics of local energy concentration of device switching, the power pulses in the pulse area with intensive on and off energy are respectively short-time averaged, and the switching loss of the related devices under the two commutation modes is calculated; at the same time, the conduction loss of the related devices under the two commutation modes is calculated according to the conduction current, the initial conduction voltage drop and the conduction resistance;

[0011] (4) The Foster thermal network model of the device is established, and the junction temperature of the related device is calculated according to the conduction loss and the switching loss;

[0012] (5) According to the device fundamental frequency junction temperature balancing idea, the action time of the two commutation modes is dynamically adjusted to minimize the highest temperature rise of the device in the bridge arm in the fundamental period, so as to ensure the dynamic balance of the ANPC-3L inverter temperature rise.

[0013] Any phase bridge arm of the ANPC-3L inverter contains six switching tubes S a1 ~S a6 , S a1 ~S a6 respectively with anti-parallel diode D a1 ~D a6 , wherein the collector of S a1 is connected to the positive pole of the DC bus voltage, the emitter of S a1 is connected to the collector of S a2 , and the collector of S a5 is connected to the emitter of S a2 , the emitter of S a3 is connected to the collector of S a5 as the output port of the phase bridge arm, the emitter of S a6 is connected to the collector of S a3 and connected to the three-phase center, the emitter of S a4 is connected to the collector of S a6 and the emitter of S a4 , the emitter of S a1 is connected to the negative pole of the DC bus voltage, the gate of S a6 is connected to the driving signal provided by the control system; the bridge arm has six switching states:

[0014] In switching state P, S a1 , S a2 , S a6 are turned on, and the other switching tubes are turned off;

[0015] In switching state OU 245 , S a2 , S a4 , S a5 are turned on, and the other switching tubes are turned off;

[0016] In switching state OU 25 , S a2 , S a5 are turned on, and the other switching tubes are turned off;

[0017] In switching state OL 136 , S a1 , S a3 , S a6On, others off

[0018] Switching state OL 36 Down, S a3 , S a6 On, others off

[0019] Switching state N Down, S a3 , S a4 , S a5 On, others off

[0020] Switching state P With OU 25 , and N with OL 36 , the near end commutation is defined as ANPC-1 commutation mode, switching state P with OL 136 , and N with OU 245 , the far end commutation is defined as ANPC-2 commutation mode.

[0021] Further, according to the switching loss distribution state of ANPC-3L inverter in step (2), in ANPC-1 commutation mode, S a1 , D a1 , S a5 , D a5 bear switching loss and conduction loss, S a2 , D a2 only bear conduction loss, the device with the highest temperature rise appears in S a1 , D a1 , S a5 , D a5 ; in ANPC-2 commutation mode, S a2 , D a2 bear switching loss and conduction loss, S a1 , D a1 , S a5 , D a5 only bear conduction loss, the device with the highest temperature rise appears in S a2 , D a2 ; thus the highest temperature rise in ANPC-1 commutation mode T j_max1 and the highest temperature rise in ANPC-2 commutation mode T j_max2 are defined as:

[0022]

[0023]

[0024] Wherein: , , , 、 、 the junction temperature of S a1 , D a1 , S a2 , D a2 , S a5 , D a5 .

[0025] Further, the step (3) for the related devices S a1 , D a1 , S a2 , D a2 , S a5 , D a5 , the calculation expression of the conduction loss and the switching loss of these devices in the fundamental period under two commutation modes is as follows:

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034] wherein: and are the conduction loss and the switching loss of the switch tube in the fundamental period under the ANPC-1 commutation mode, and are the conduction loss and the switching loss of the switch tube in the fundamental period under the ANPC-2 commutation mode, and are the conduction loss and the reverse recovery loss of the diode in the fundamental period under the ANPC-1 commutation mode, and are the conduction loss and the reverse recovery loss of the diode in the fundamental period under the ANPC-2 commutation mode, is the power factor angle, is the current angle and , t represents time, is the angular frequency and , T For the fundamental period, This is the initial saturation voltage drop of the switching transistor. This is the on-resistance of the switching transistor. Current angle The conduction current of the lower switching transistor. This represents the initial saturation voltage drop of the diode. This is the on-resistance of the diode. Current angle The conduction current of the lower diode, Current angle The adjustment system, and These are the single-turn-on energy and single-turn-off energy of the switching transistor (obtained through a double-pulse test). This represents the single reverse recovery energy of the diode (obtained through a double-pulse test). The equivalent duration is set.

[0035] Furthermore, in step (4), the heat transfer characteristics of any power device (switch or diode) are characterized using the Foster thermal network model, which consists of multiple RC units connected in series; and then S is calculated using the following expression. a1 D a1 S a2 D a2 S a5 D a5 Their respective junction temperatures:

[0036]

[0037]

[0038] in: and These are the junction temperatures of the switching transistor and the diode, respectively. k This represents the ratio of the duration of the ANPC-1 converter mode to that of the ANPC-2 converter mode within the fundamental frequency period. and In the Foster thermal network model of the switching transistor, the first... n Thermal resistance and thermal time constant of each RC unit and In the Foster thermal network model of diodes, the first... n Thermal resistance and thermal time constant of each RC unit For ambient temperature, m This represents the number of RC units connected in series in the Foster thermal network model (the number of units connected in series varies depending on the device).

[0039] Furthermore, in step (5), S is first compared. a2 With D a2 The junction temperature of the two devices is used to define the device with the higher junction temperature as X; compare S. a1 D a1 S a5 D a5 The junction temperature of the four components is considered, and the device with the highest junction temperature among these four is defined as Y; then, the following expression is used to calculate the device that satisfies... T j_max1 = T j_max2 time k value, and according to this k The duration of the two commutation modes is dynamically adjusted.

[0040]

[0041]

[0042]

[0043]

[0044]

[0045] in: T 1~ T 4 is an intermediate variable. and These represent the conduction loss and switching loss (or reverse recovery loss) of device X during the fundamental cycle in ANPC-1 commutation mode, respectively. and These represent the conduction loss and switching loss (or reverse recovery loss) of device X during the fundamental cycle in ANPC-2 commutation mode, respectively. and These represent the conduction loss and switching loss (or reverse recovery loss) of device Y in the fundamental cycle during the ANPC-1 commutation mode, respectively. and These represent the conduction loss and switching loss (or reverse recovery loss) of device Y in the fundamental cycle during the ANPC-2 commutation mode, respectively. and The Foster thermal network model of device X is respectively the first... n Thermal resistance and thermal time constant of each RC unit and The Foster thermal network model of device Y is respectively the first n Thermal resistance and thermal time constant of each RC unit.

[0046] Further, the step (5) is adjusted in real time by the difference between the value of the step (4) and the value of the step (3) to the value of the step (2) to realize the device temperature rise balance of the ANPC-3L inverter under the dynamic working condition by adjusting the slope of the value of the step (2) to increase or decrease the response speed. T j_max1 And the difference between the value of the step (4) and the value of the step (3) is adjusted in real time to the value of the step (2) to adjust the response speed by adjusting the slope of the value of the step (2) to increase or decrease, so that the device temperature rise balance of the ANPC-3L inverter under the dynamic working condition is realized. T j_max2 And the difference between the value of the step (4) and the value of the step (3) is adjusted in real time to the value of the step (2) to adjust the response speed by adjusting the slope of the value of the step (2) to increase or decrease, so that the device temperature rise balance of the ANPC-3L inverter under the dynamic working condition is realized. k The value of the step (2) is adjusted in real time by the difference between the value of the step (4) and the value of the step (3) to the value of the step (2) to realize the device temperature rise balance of the ANPC-3L inverter under the dynamic working condition by adjusting the slope of the value of the step (2) to increase or decrease the response speed. k The value of the step (2) is adjusted in real time by the difference between the value of the step (4) and the value of the step (3) to the value of the step (2) to realize the device temperature rise balance of the ANPC-3L inverter under the dynamic working condition by adjusting the slope of the value of the step (2) to increase or decrease the response speed.

[0047] A computer device comprises a memory and a processor, the memory has a computer program stored therein, and the processor is used to execute the computer program to realize the temperature rise dynamic balance method of the active neutral point clamped three-level inverter.

[0048] A computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the temperature rise dynamic balance method of the active neutral point clamped three-level inverter.

[0049] The present application improves the switching loss calculation method and the commutation path switching method from the two dimensions of switching period and fundamental period on the basis of the existing switching loss balance strategy, and proposes an ANPC-3L inverter output capacity improvement control strategy: first, different zero state paths are analyzed to obtain the switching loss distribution state of the ANPC-3L inverter; then, according to the distribution characteristics of the local energy concentration of the device switching time, the power pulses in the energy intensive pulse area of the device turn-on and turn-off are respectively short-time averaged, so as to balance the contradiction between accuracy and calculation complexity while ensuring the authenticity of the device temperature rise fluctuation. On this basis, the present application derives a switching loss calculation method based on the short-time equivalent of the power pulse, and uses the device fundamental frequency junction temperature balance idea to ensure the dynamic balance of the three-level inverter temperature rise. Therefore, the present application has the following beneficial technical effects:

[0050] 1. According to the distribution characteristics of the local energy concentration of the device switching time, the power pulses in the energy intensive pulse area of the device turn-on and turn-off are respectively short-time averaged, so as to balance the contradiction between accuracy and calculation complexity while ensuring the authenticity of the device temperature rise fluctuation.

[0051] 2. The present application designs an ANPC-3L inverter temperature rise dynamic balance method using the loss calculation method, adopts the device fundamental frequency junction temperature balance idea, takes minimizing the highest temperature rise of the 12 devices of a single bridge arm of the inverter in the fundamental period as the purpose, and takes dynamically adjusting the action time ratio of the two commutation modes as the means to ensure the dynamic balance of the three-level inverter temperature rise. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1The topological structure diagram of the ANPC-3L inverter in the embodiment of the application is shown.

[0053] Figure 2 The structure diagram of the Foster thermal network model is shown.

[0054] Figure 3 The schematic diagram of the modulation wave, the carrier wave and the driving pulse waveforms of each switching device in the embodiment of the application is shown.

[0055] Figure 4 The flowchart of the real-time temperature rise negative feedback regulation value according to the application is shown. k

[0056] Figure 5 The schematic diagram of the highest temperature rise of the a-phase device under different working conditions of the three modulation methods in the application is shown.

[0057] Figure 6 The schematic diagram of the distribution of the calculated value under different working conditions of the application is shown. k DETAILED DESCRIPTION

[0058] In order to describe the application more specifically, the technical solutions of the application are described in detail below in combination with the drawings and specific embodiments.

[0059] The ANPC-3L inverter topological structure in the embodiment is shown in Figure 1 Each phase bridge arm has six full-controlled switching devices S a1 ~S a6 with anti-parallel diodes (D a1 ~D a6 ) and the DC bus voltage is V dc C1 and C2 are support capacitors, i a ~ i c The output current of the three-phase bridge arm is V dc / 2, 0 and V dc / 2, which are respectively represented by P, O and N.

[0060] The specific implementation process of the temperature rise dynamic balancing method for the ANPC-3L inverter topology is as follows:

[0061] (1) The switching loss distribution of different commutation paths is obtained by analyzing the commutation paths of different P, N and O states.

[0062] ​​Taking phase A as an example, the switching status table of the ANPC three-level inverter is shown in Table 1, where "1" indicates that the switch is on and "0" indicates that the switch is off; OU indicates that the output is zero through the upper half-bridge arm during the positive half-cycle, and OL indicates that the output is zero through the lower half-bridge arm during the positive half-cycle. The subscript number is the number of the switch transistor that is turned on; the inverter switching status during the negative half-cycle can be obtained symmetrically through the positive half-cycle.

[0063] Table 1

[0064]

[0065] P↔OU 25 and N↔OL 36 This is called near-end converter mode, or simply ANPC-1 mode; P↔OL 136 and N↔OU 245 This is called the remote converter mode, or ANPC-2 mode for short. The switching loss distribution in the two modes is shown in Table 2:

[0066] Table 2

[0067]

[0068] (2) The heat transfer characteristics of power devices are described using the Foster thermal network model.

[0069] The continuous, distributed actual thermal structure of power devices is approximated as an electrical equivalent network composed of multiple series-connected RC units, such as... Figure 2 As shown, the power loss P sum Equivalent to a current source, temperature rise Δ T Equivalent to voltage, thermal resistance R th Equivalent to resistance, heat capacity C th Equivalent to a capacitor, T j For device junction temperature, T c The ambient temperature.

[0070] The Foster thermal network model uses the superposition of multiple RC circuits with different time constants to accurately fit the macroscopic transient thermal impedance characteristics of the entire device from junction to case. The junction temperature expression for the power device under the Foster thermal network model is:

[0071]

[0072] In the formula: m The number of thermal resistors in the device's thermal model. τ n For power devicesn Thermal time constant of each RC unit P sum The total power consumption of a single power device (switching transistor or anti-parallel diode), including switching losses. P sw and conduction loss P cond ,in P sw This refers to the switching loss of the switching transistor or the reverse recovery loss of the freewheeling diode.

[0073]

[0074] Power device conduction losses P cond The calculation formula is:

[0075]

[0076] In the formula: v 0 represents the initial saturation voltage drop of the power device. r This represents the on-resistance of the power device. I This represents the average on-state current flowing through the device during the switching cycle.

[0077] (3) Perform a double-pulse test on the power device to obtain the single-turn-on energy of the power device. E on Power device single turn-off energy E off and diode single reverse recovery energy E rec The characteristic curve, namely:

[0078]

[0079] In the formula: k 1. k 2. k 3 are respectively E on , E off and E rec Correction factor for device junction temperature, A 1~ A 3. B 1~ B 3. C 1~ C 3 is the fitting coefficient. U base For testing voltage, U CE The actual voltage that the device withstands. i This is the on-state current of the device. is the measured value of the device junction temperature.

[0080] (4) The energy consumed by single turn-on or turn-off is evenly distributed in t eff the calculation time (set equivalent time), then the device turn-on loss P on is:

[0081]

[0082] Similarly, the device turn-off loss P off and the reverse recovery loss of the freewheeling diode P rec is:

[0083]

[0084] (5) Since the switch tubes used in the positive and negative half cycles of the output voltage are different, it is necessary to switch the commutation path once in the positive and negative half waves of the modulation wave respectively, and the duration of each switching is 0.5 kT , T is the fundamental period, k is the ratio of the action time of ANPC-1 mode to ANPC-2 mode in the fundamental period.

[0085] Because the time of current flowing through IGBT and freewheeling diode is different under different power factors, the phase 90° of the modulation wave is selected as the switching point, as shown in Figure 3 , the modulation wave u s1 and u s2 is adopted SPWM modulation, and a third harmonic wave is superimposed on the basis of the sine wave, u c is the carrier wave, VS a1 ~VS a6 corresponds to the driving signal of S a1 ~S a6 .

[0086] (6) In ANPC-1 commutation mode, S a1 , D a1 , S a5 , D a5 bear switching loss and conduction loss, S a2 , D a2 only bear conduction loss, and the device with the highest temperature rise will appear in S a1 , D a1 , S a5 , D a5 ; in ANPC-2 commutation mode, Sa2 D a2 S bears the switching loss and conduction loss. a1 D a1 S a5 D a5 The device that only bears the conduction loss and has the highest temperature rise will appear in S. a2 D a2 Therefore, the maximum temperature rise of the two sets of devices is defined as:

[0087]

[0088]

[0089] but T j_max1 = T j_max2 The ratio of time k It can be used as the ratio of the duration of the two commutation modes.

[0090] (7) With S a1 and D a1 For example, when the power factor is The adjustment system is D ( α When, in ANPC-1 converter mode S a1 and D a1 Conduction loss during the fundamental period and Switching losses Reverse recovery loss The expression is:

[0091]

[0092]

[0093]

[0094]

[0095] ANPC-2 converter mode S a1 and D a1 Conduction loss during the fundamental period and Switching losses Reverse recovery loss The expression is:

[0096]

[0097]

[0098]

[0099]

[0100] Then S a1 and D a1 The junction temperature expression is:

[0101]

[0102]

[0103] Similarly, S can be derived. a2 D a2 S a5 D a5 The expression for temperature rise.

[0104] (8) Assuming that within a certain fundamental frequency period, , ,but T j_max1 = T j_max2 Conditions can be transformed into time k Value is what is required k Value; to simplify calculations, let:

[0105]

[0106]

[0107]

[0108]

[0109] Seeking satisfaction T j_max1 = T j_max2 time k The value is:

[0110]

[0111] (9) In practical applications, due to the influence of stray parameters and other conditions in the hardware circuit, the direct calculation through theory is affected. k Value and reality T j_max1 = T j_max2 The value at time has a deviation, so it can be determined by... T j_max1 and T j_max2 Differences in proportion kPerform real-time negative feedback adjustment, by adjusting k The response speed is adjusted by increasing or decreasing the slope of the value, thereby achieving device temperature rise balance under dynamic operating conditions for the three-level ANPC. The specific feedback control process is as follows: Figure 4 As shown.

[0112] To verify the effectiveness and superiority of the method of the present invention, we conducted experimental verification. The parameters of the surface-mounted high-speed permanent magnet synchronous motor used as an example in the experiment are shown in Table 3:

[0113] Table 3

[0114]

[0115] Under the method of this invention, when the power factor varies from 0.1 to 1 and the modulation index varies from 0.05 to 0.95, the maximum device temperature rise of the three modulation strategies under different operating conditions is as follows: Figure 5 As shown, the proportions under different working conditions k Values ​​such as Figure 6 As shown, the maximum temperature rise of the power device increases with the increase of the power factor and decreases with the increase of the modulation index. When the power factor is low and the modulation index is high, the system mainly operates in the ANPC-1 modulation strategy. Under other operating conditions, the temperature rise dynamic equalization modulation strategy of this invention can effectively reduce the maximum temperature rise of the device in the three-level ANPC system.

[0116] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A method for dynamic temperature rise balancing of an active neutral-point clamped three-level inverter, characterized in that, Includes the following steps: (1) Analyze different zero-state paths to obtain the switching loss distribution of the ANPC-3L inverter. ANPC-3L represents the active neutral clamp three-level. (2) Based on the switching loss distribution, determine the relevant devices with switching losses and conduction losses and the maximum temperature rise in ANPC-1 and ANPC-2 commutation modes; (3) Based on the distribution characteristics of local energy concentration when the device is switched, the power pulse is averaged for a short time in the pulse region where the device is turned on and off, respectively, and the switching loss of the relevant device under the two commutation modes is calculated; at the same time, the conduction loss of the relevant device under the two commutation modes is calculated based on the conduction current, initial conduction voltage drop and conduction resistance. (4) Establish the Foster thermal network model of the device and calculate the junction temperature of the relevant device based on the conduction loss and switching loss; (5) Based on the idea of ​​equalizing the junction temperature of the device at the fundamental frequency, with the goal of minimizing the maximum temperature rise of the device in the bridge arm during the fundamental frequency cycle, the duration of the two commutation modes is dynamically adjusted to ensure the dynamic balance of the temperature rise of the ANPC-3L inverter. Each phase arm of the ANPC-3L inverter contains six switching transistors S. a1 ~S a6 S a1 ~S a6 Each has an anti-parallel diode D a1 ~D a6 S a1 The collector is connected to the positive terminal of the DC bus voltage, S a1 The emitter and S a2 The collector and S a5 The collectors are connected, S a2 The emitter and S a3 The collector of S is connected as the output port of this phase bridge arm. a5 The emitter and S a6 The collectors are connected to the three-phase center point, S a3 The emitter and S a4 The collector and S a6 The emitters are connected, S a4 The emitter is connected to the negative terminal of the DC bus voltage, S a1 ~S a6 The gate is connected to the drive signal provided by the control system; the bridge arm has 6 switching states: In switch state P, S a1 S a2 S a6 When the transistor is turned on, other switches are turned off. Switch status OU 245 Below, S a2 S a4 S a5 When the transistor is turned on, other switches are turned off. Switch status OU 25 Below, S a2 S a5 When the transistor is turned on, other switches are turned off. Switch status OL 136 Below, S a1 S a3 S a6 When the transistor is turned on, other switches are turned off. Switch status OL 36 Below, S a3 S a6 When the transistor is turned on, other switches are turned off. In switch state N, S a3 S a4 S a5 When the transistor is turned on, other switches are turned off. Switch states P and OU 25 Between and N and OL 36 The near-end commutation between them is defined as ANPC-1 commutation mode, with the switching states P and OL. 136 Between and between N and OU 245 The remote switching between them is defined as ANPC-2 switching mode.

2. The method for dynamic temperature rise balancing of an active neutral-point clamped three-level inverter according to claim 1, characterized in that: In step (2), based on the switching loss distribution of the ANPC-3L inverter, in ANPC-1 commutation mode, S a1 D a1 S a5 D a5 S bears the switching loss and conduction loss. a2 D a2 The device that only bears the conduction loss and has the highest temperature rise appears in S. a1 D a1 S a5 D a5 In the ANPC-2 converter mode, S a2 D a2 S bears the switching loss and conduction loss. a1 D a1 S a5 D a5 The device that only bears the conduction loss and has the highest temperature rise will appear in S. a2 D a2 Therefore, the maximum temperature rise in the ANPC-1 converter mode is defined. T j_max1 The highest temperature rise in ANPC-2 converter mode T j_max2 for: ; ; in: , , , , , S a1 D a1 S a2 D a2 S a5 D a5 The junction temperature.

3. The method for dynamic temperature rise balancing of an active neutral-point clamped three-level inverter according to claim 2, characterized in that: In step (3), for the relevant devices S with switching losses and conduction losses a1 D a1 S a2 D a2 S a5 D a5 The calculation expressions for the conduction loss and switching loss of these devices during the fundamental cycle under the two commutation modes are as follows: ; in: and These represent the conduction loss and switching loss of the switching transistor during the fundamental cycle in ANPC-1 commutation mode, respectively. and These represent the conduction loss and switching loss of the switching transistor during the fundamental cycle in ANPC-2 commutation mode, respectively. and These represent the conduction loss and reverse recovery loss of the diode during the fundamental cycle in ANPC-1 commutation mode, respectively. and These represent the conduction loss and reverse recovery loss of the diode during the fundamental cycle in ANPC-2 commutation mode, respectively. The power factor angle, It is the current angle and , t Indicates time, Angular frequency and , T For the fundamental period, This is the initial saturation voltage drop of the switching transistor. The on-resistance of the switching transistor is... Current angle The conduction current of the lower switching transistor. This represents the initial saturation voltage drop of the diode. This is the on-resistance of the diode. Current angle The conduction current of the lower diode, Current angle The adjustment system, and These are the single-turn-on energy and single-turn-off energy of the switching transistor, respectively. This refers to the single reverse recovery energy of the diode. The equivalent duration is set.

4. The method for dynamic temperature rise balancing of an active neutral-point clamped three-level inverter according to claim 3, characterized in that: In step (4), the heat transfer characteristics of any power device are characterized using a Foster thermal network model, which consists of multiple RC units connected in series. Then, S is calculated using the following expression. a1 D a1 S a2 D a2 S a5 D a5 Their respective junction temperatures: ; ; in: and These are the junction temperatures of the switching transistor and the diode, respectively. k This represents the ratio of the duration of the ANPC-1 converter mode to that of the ANPC-2 converter mode within the fundamental frequency period. and In the Foster thermal network model of the switching transistor, the first... n Thermal resistance and thermal time constant of each RC unit and In the Foster thermal network model of diodes, the first... n Thermal resistance and thermal time constant of each RC unit For ambient temperature, m This represents the number of RC elements connected in series in the Foster thermal network model.

5. The method for dynamic temperature rise balancing of an active neutral-point clamped three-level inverter according to claim 4, characterized in that: In step (5), S is first compared. a2 With D a2 The junction temperature of the two devices is used to define the device with the higher junction temperature as X; compare S. a1 D a1 S a5 D a5 The junction temperature of the four components is considered, and the device with the highest junction temperature among these four is defined as Y; then, the following expression is used to calculate the device that satisfies... T j_max1 = T j_max2 time k value, and according to this k The duration of the two commutation modes is dynamically adjusted. ; ; ; ; ; in: T 1~ T 4 is an intermediate variable. and These represent the conduction loss and switching loss of device X during the fundamental cycle in ANPC-1 commutation mode, respectively. and These represent the conduction loss and switching loss of device X during the fundamental cycle in ANPC-2 commutation mode, respectively. and These represent the conduction loss and switching loss of device Y during the fundamental cycle in ANPC-1 commutation mode, respectively. and These represent the conduction loss and switching loss of device Y during the fundamental cycle in ANPC-2 commutation mode, respectively. and The Foster thermal network model of device X is respectively the first... n Thermal resistance and thermal time constant of each RC unit and The Foster thermal network model of device Y is respectively the first n Thermal resistance and thermal time constant of each RC unit.

6. The method for dynamic temperature rise balancing of an active neutral-point clamped three-level inverter according to claim 5, characterized in that: In step (5), through T j_max1 and T j_max2 The difference pair k The value is adjusted in real time using negative feedback. k The response speed is adjusted by increasing or decreasing the slope of the value, so as to achieve the device temperature rise balance of the ANPC-3L inverter under dynamic operating conditions.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: The processor is used to execute the computer program to implement the dynamic temperature rise balancing method for the active midpoint clamped three-level inverter as described in any one of claims 1 to 6.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the processor, it implements the dynamic temperature rise balancing method for the active midpoint clamped three-level inverter as described in any one of claims 1 to 6.

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