A quasi-zero power logic control circuit and method

Abstract

The application discloses a kind of quasi-zero power consumption logic control circuit and method, comprising: data receiving pre-processing part, input end is connected to external data signal, data receiving pre-processing part includes signal shaping unit, for shaping and filtering to input signal;Data sampling and logic judging part, input end is connected to the output end of data receiving pre-processing part, data sampling and logic judging part includes sampling unit and multi-bit data comparison unit, for sampling and judging whether the numerical value of continuous multi-bit meets preset condition after pre-processing signal;Dormancy control signal generation part, input end is connected to the output end of data sampling and logic judging part;Power-off execution part, control end is connected to the output end of dormancy control signal generation part, its power output end is connected to the power supply end of at least one controlled functional module, and power-off execution part includes switch control unit.

Description

Technical Field

[0001] This invention relates to the field of LED constant current control, and more specifically to a method for implementing an ultra-low static power LED logic control circuit. Background Technology

[0002] With the rapid development of the consumer electronics industry, the demand for LED drivers in fields such as LED displays, smart lighting, and portable wearable devices is increasing. LED constant current driver chips, due to their ability to precisely control the LED operating current and ensure brightness stability, have been widely used in various LED display products. However, existing mainstream LED constant current driver chips still suffer from unavoidable power consumption issues in non-operating states (standby mode), severely impacting the standby time of battery-powered products and becoming a critical technical challenge that urgently needs to be addressed in the industry.

[0003] From a technical perspective, the power consumption of existing chips in standby mode stems from the core modules that must continue to operate to maintain basic functions. On one hand, the accuracy of the constant current source depends on the internal bandgap reference circuit, which needs to continuously supply static current to maintain a stable reference voltage. For example, a chip using the LM4040D20IDBZR type bandgap reference source requires 60μA of static current to compensate for temperature drift, ensuring that the output voltage error is ≤±0.4% within the operating range of -40℃ to 85℃. If this circuit is turned off, it takes 50-100μs for the chip to re-establish the reference voltage after waking up, which cannot meet the millisecond-level response requirements of portable devices. On the other hand, the system clock needs to maintain a low frequency to achieve data synchronization and real-time detection. For example, the UCC28730 type driver chip needs to maintain a 32Hz low-frequency clock in standby mode to avoid the high power consumption of high-frequency oscillation and ensure that it can synchronously parse the PWM dimming signal or serial data frame input from the DIN pin. If the oscillation stops completely, the chip will lose its ability to respond to external commands and will require a hardware reset to wake up, making it unsuitable for remote control scenarios such as smart lighting.

[0004] Specifically, the standby power consumption of existing LED constant current driver chips is mainly generated by the superposition of four core modules, and the power consumption performance of different types of chips varies significantly: First, the bandgap reference circuit constitutes the basic power consumption. The static current of ordinary integrated reference sources is generally 10-100μA, which is a necessary price to pay to ensure constant current accuracy. Second, the clock oscillator still has dynamic power consumption even in low-frequency mode. For example, the UCC28730 chip consumes 4mW (corresponding to a current of about 800μA@5V) in standby mode due to the 32Hz clock and associated logic circuit. Third, power devices (such as NMOS / PMOS switches) have inherent reverse leakage current. Taking the MCP9904D multi-channel driver chip as an example, its single-channel leakage current is ≤10μA in the off state. After multiple channels are superimposed, the overall leakage current increases linearly with the number of channels. Fourth, the monitoring circuit of the data receiving front end (such as Schmitt triggers and edge detection modules) needs to work continuously to respond to external signals. Even the optimized WarmCore NS4 The chip still requires 2μA of quiescent current and can only process basic level signals, making it incompatible with complex data frames.

[0005] From the perspective of market product performance, the standby power consumption of existing chips exhibits a clear gradient: basic linear LED constant current driver chips (such as the BCR420 series), relying on simple bias circuits to maintain constant current accuracy, have a standby current of approximately 50μA (corresponding to a power consumption of 250μW@5V); enhanced chips (such as the MCP9904D) reduce the standby current to 6-10μA (corresponding to a power consumption of 30-50μW@5V) through partial module shutdown control, but at the cost of sacrificing some response speed; high-end chips supporting complex functions (such as the UCC28730), due to the need to maintain MCU collaboration and data parsing capabilities, actually see their standby current rise to approximately 800μA, resulting in a significant increase in power consumption. All of the above existing technologies are caught in a contradiction between "standby power consumption and real-time response, and functional integrity"—pursuing low power consumption requires sacrificing response speed or functionality, while ensuring response and functionality makes it difficult to reduce power consumption. This contradiction is particularly pronounced in portable LED devices powered by button batteries or small lithium batteries (such as LED wristbands and micro-display modules), severely limiting the product's battery life. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a quasi-zero power logic control circuit and method, which can completely shut off the power supply of the controlled functional module when certain conditions are met based on the judgment of the input data content, thereby significantly reducing or even eliminating the static power consumption of the chip in the sleep state, while ensuring the necessary wake-up response capability.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] A quasi-zero power logic control circuit includes: a data receiving preprocessing unit, the input of which is connected to an external data signal, the data receiving preprocessing unit including a signal shaping unit for shaping and filtering the input signal; a data sampling and logic judgment unit, the input of which is connected to the output of the data receiving preprocessing unit, the data sampling and logic judgment unit including a sampling unit and a multi-bit data comparison unit for sampling the preprocessed signal and judging whether the values ​​of multiple consecutive bits meet preset conditions; a sleep control signal generation unit, the input of which is connected to the output of the data sampling and logic judgment unit, for generating a sleep control signal when the multi-bit data comparison unit determines that the data meets the preset conditions; and a power-off execution unit, the control terminal of which is connected to the output of the sleep control signal generation unit, and the power output terminal of which is connected to the power supply terminal of at least one controlled functional module, the power-off execution unit including a switch control unit for disconnecting the power supply circuit of the controlled functional module in response to the sleep control signal.

[0009] In some embodiments, at least one of the following technical means is also included:

[0010] The signal shaping unit includes a Schmitt trigger for converting the input signal into a square wave signal with steep edges.

[0011] The data receiving preprocessing unit further includes a digital filtering unit, which includes multiple inverters connected in series and a logic gate, used to filter out signal glitches with a pulse width less than a predetermined value.

[0012] The preset condition is that 48 consecutive bits of data are all logic 0.

[0013] The data sampling and logic judgment unit further includes a reset signal detection unit for detecting a low-level reset signal, the duration of which is greater than or equal to 256 microseconds.

[0014] The switch control unit includes at least one PMOS transistor and / or at least one NMOS transistor, the gate of which receives the sleep control signal or its inverted signal to turn on or off the power supply circuit.

[0015] The controlled functional module includes one or more of the following: a bandgap reference voltage source, a clock oscillator, and a constant current source drive circuit.

[0016] The present invention also adopts the following technical solutions:

[0017] A quasi-zero power consumption logic control method is characterized by comprising the following steps: receiving and processing externally input data signals through a data receiving preprocessing unit, the processing including shaping and filtering the input signals; sampling the processed signals through a data sampling and logic judgment unit, and determining whether the values ​​of multiple consecutive bits meet preset conditions; generating a sleep control signal through a sleep control signal generation unit when the data meets the preset conditions; and disconnecting the power supply circuit of at least one controlled functional module in response to the sleep control signal through a power shutdown execution unit.

[0018] The present invention also adopts the following technical solutions:

[0019] The step of determining whether the preset condition is met is performed after a low-level reset signal with a duration greater than or equal to 256 microseconds is detected.

[0020] Furthermore,

[0021] The steps to disconnect the power supply circuit include: controlling the gate voltage of a PMOS transistor to turn it off, and / or controlling the gate voltage of an NMOS transistor to turn it off.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] The quasi-zero power logic control circuit and method provided by this invention shapes and filters the input signal through a data receiving preprocessing unit, effectively removing noise and glitches from the signal and ensuring the accuracy of subsequent sampling and judgment. By sampling and conditionally judging multiple consecutive bits of data through a data sampling and logic judgment unit, specific sleep commands (such as all-zero codes) can be accurately identified. When the judged data meets preset conditions, a sleep control signal generation unit generates a sleep control signal, which is ultimately responded to by a power-off execution unit, completely disconnecting the power supply circuit of the controlled functional module.

[0024] The aforementioned technical features work together to achieve precise power management triggered by data content. Its most significant benefit is that it enables a near-zero-power sleep state for the chip when there are no active tasks, retaining only extremely weak signal detection capabilities, thereby greatly reducing system static power consumption. Simultaneously, since both sleep and wake-up are controlled by data signals, no complex wake-up circuits or external intervention are required. The system can be quickly woken up upon detecting a valid input signal and resume full functionality, thus achieving an excellent balance between ultra-low power consumption and rapid response.

[0025] Furthermore, the use of a Schmitt trigger for signal shaping enhances the circuit's noise immunity and adaptability to power supply voltage fluctuations.

[0026] Furthermore, by using a digital filter unit that includes an inverter chain and logic gates, narrow pulse glitches can be effectively filtered out, thus improving the reliability of the system.

[0027] Furthermore, setting the preset condition to 48 consecutive logic 0s provides the system with a clear and reliable basis for determining sleep mode.

[0028] Furthermore, by setting up a reset signal detection unit and performing conditional judgments afterward, the system is ensured to make hibernation decisions in a stable state, thus avoiding erroneous operations.

[0029] Furthermore, by using MOS transistors as the actuators of the switch control unit and utilizing their gate voltage to control the on and off states, efficient, fast, and low-loss control of the power supply circuit is achieved.

[0030] Furthermore, the method detects the reset signal, determines the data conditions, and controls the transistor to turn off, thereby achieving precise power consumption control in a streamlined manner. Attached Figure Description

[0031] Figure 1 This is a block diagram of the quasi-zero power logic control circuit provided in an embodiment of the present invention.

[0032] Figure 2 This is a schematic diagram of a specific circuit implementation of the data receiving and preprocessing unit in an embodiment of the present invention.

[0033] Figure 3 This is a schematic diagram of a specific circuit implementation of the digital filtering unit in an embodiment of the present invention.

[0034] Figure 4 This is a detailed circuit diagram illustrating the use of a PMOS transistor to achieve power-off in an embodiment of the present invention.

[0035] Figure 5 This is a detailed circuit diagram illustrating the use of an NMOS transistor to achieve power-off in an embodiment of the present invention.

[0036] Figure 6 This is a timing diagram of the chip data transmission format involved in the embodiments of the present invention.

[0037] Figure 7 This is a schematic diagram of the input and output characteristics of the signal shaping unit involved in an embodiment of the present invention.

[0038] Figure 8 This is a timing diagram of the overall system operation involved in the embodiments of the present invention.

[0039] Figure 9 This is a timing diagram showing a partial magnification of the DIN signal according to an embodiment of the present invention.

[0040] Figure 10This is a schematic diagram of a specific circuit implementation of the data sampling unit in an embodiment of the present invention.

[0041] Figure 11 This is a schematic diagram of a specific circuit implementation of the data judgment and processing unit in an embodiment of the present invention.

[0042] Figure 12 This is an overall logic block diagram of data sampling processing and system shutdown control in an embodiment of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0044] Implementation Concept: The core of this invention lies in determining whether the system has entered a sleep state by monitoring the content of the input data stream. When a specific data pattern (such as multiple consecutive '0' bits) is detected and accompanied by a valid reset signal, it is determined that there is currently no valid task, and a control signal is generated to completely shut down the power supply of the internal high-power functional modules, making their static power consumption approach zero. When new valid data is input, the circuit can quickly respond and wake up the system. To solve the technical problems of high standby power consumption and short battery life of existing LED constant current driver chips, this invention proposes a data-triggered sleep zero-power LED logic control circuit. Through an innovative "data content judgment - functional module power shutdown" mechanism, it completely cuts off the power supply to unnecessary modules during sleep, while keeping only a very low-power signal detection and logic judgment circuit in working state. This overcomes the inherent contradictions of existing technologies and meets the dual requirements of low power consumption and high responsiveness for battery-powered products.

[0045] Example 1

[0046] This embodiment discloses a near-zero power logic control circuit. It achieves ultra-low static power consumption for the chip during sleep mode. In the operating state, the chip receives 48 bits of data (all 0s) from the DIN (Data Input) terminal. Upon receiving a reset signal (≥256µs low level), the system shuts off the power supply to the internal functional modules, causing the chip to enter an ultra-low static power sleep state. At this time, the corresponding static power consumption is approximately 15nW (test conditions: VDD=5V, ambient temperature 25℃, no external signal interference; 15nW is an ideal simulation or test result under specific process, voltage, and low temperature conditions; in actual applications, it may increase due to process deviations, temperature and voltage fluctuations). If no new data is input, the chip continues to maintain this ultra-low power state. When the DIN terminal receives a data signal again, the system... Internal wake-up (2µs internal wake-up refers to the control response time from detecting a valid wake-up signal to turning on the power switch), and controls the power-off actuator to reconnect the power supply circuit. Controlled functional modules (such as bandgap references and oscillators) require a certain stabilization time after power-on before outputting accurate reference voltage and clock signals. Afterward, the system fully recovers to normal operating status and decodes grayscale signals. This significantly reduces ineffective losses. Its implementation framework is as follows: Figure 1 As shown, the specific process includes the following:

[0047] 1. Data enters the chip from the DIN pin and is preprocessed to filter out glitches and interference signals.

[0048] 2. The preprocessed data is latched by the internal sampling logic. Then the judgment logic will judge the value of each data bit. If the 48 bits (binary bits) are all 0 (this bit design ensures that the sleep command has enough uniqueness to be distinguished from the regular brightness control data (usually not all 0) to avoid accidental sleep triggering), an enable signal to shut down the system will be generated.

[0049] 3. The enable signal will shut down all power-consuming modules in the system.

[0050] Chip data transmission and system operation enable instructions:

[0051] Figure 6 This is the chip data transmission format, where the reset signal is a low-level signal >= 256µs (this time is much longer than the duration of a normal data bit (e.g., one data bit cycle is about 3µs), thereby ensuring that the circuit can clearly distinguish between the reset signal and the data signal and prevent misjudgment).

[0052] After a reset, the chip latches the 48 bits of data it needs when receiving data, and then latches them again when the next reset signal arrives.

[0053] The overall system working sequence is as follows Figure 8 , Figure 9 As shown,

[0054] When the DIN signal enters the chip, the sampling signal SAMP_CLK samples the DIN signal on its own rising edge as the first rising edge arrives. When the first rising edge of the DIN signal arrives, the reset sampling signal RESET_SAMP_B will be set to 1. When the DIN signal is low for 256us, the reset signal (RESET_SAMP_B) will be set to 0. When all 48 bits of the signal have been sampled and are all 0, the POWER_OFF_CHECK signal remains 0. At this time, the system always-enabled signal TOP_ENB will be set to 1, shutting down the entire system.

[0055] 1. Data preprocessing:

[0056] like Figure 2 As shown, when a square wave signal with a period of 3µs and a duty cycle of 2.75µs / 1.25µs enters the DIN pin of the chip, it will be shaped by the following circuit:

[0057] Plastic surgery principles:

[0058] Noise with an amplitude <1.5V in the input signal (such as power supply ripple and grounding interference) is directly filtered out. Only signals with an amplitude >3.5V are identified as high-level, and signals with an amplitude <1.5V are identified as low-level. This feature is more adaptable to voltage fluctuation scenarios (such as when VDD drops from 3.3V to 2.7V when powered by battery) – when VDD=3.3V, VT+ automatically adjusts to 2.31V and VT-=0.99V, while still maintaining stable noise suppression capability.

[0059] The high level (3.3-5V) of the target square wave signal is >3.5V when VDD=5V and >2.31V when VDD=3.3V; the low level (0-0.5V) is <VT- under all voltages. After shaping, the signal edge steepness is improved to ≤10ns, laying the foundation for subsequent filtering.

[0060] The input-output transmission characteristics of the signal shaping unit are as follows: Figure 7 As shown. Figure 7The green line represents the input voltage (VIN), and the red line represents the output voltage (VOUT). This characteristic curve clearly demonstrates the hysteresis effect of the Schmitt trigger: when the input voltage increases from low to high, the output voltage transitions from low to high when the input voltage reaches the upper threshold voltage (VT+, approximately 3.5V); conversely, when the input voltage decreases from high to low, the output voltage transitions from high to low only when the input voltage drops to the lower threshold voltage (VT-, approximately 1.5V). The region between VT+ and VT- is the hysteresis window or noise margin; input voltage fluctuations within this region (such as sawtooth waves or noise as shown in the figure) do not cause changes in the output state, thus achieving excellent noise immunity and waveform shaping capabilities. Figure 7 To illustrate the point, a sawtooth wave is used for the input signal to highlight the shaping function. In practice, other waveforms besides the sawtooth wave can be used.

[0061] Digital filtering:

[0062] like Figure 3 As shown,

[0063] The digital filter circuit structure and core component functions include three types of core units:

[0064] Inverter chain:

[0065] It consists of multiple inverters (I112, I111~I106, I104), each inverter (such as a standard CMOS inverter) has a fixed propagation delay (denoted as tpd) used to delay the signal and shape the edges.

[0066] Feedback path:

[0067] The output of I112 is directly connected to one input of the NAND gate (NAND2) to provide a reference for the "original delayed signal".

[0068] NAND gate (NAND2):

[0069] Implement "dual-input logic judgment": output low only when both inputs are high; otherwise, output high.

[0070] Signal delay and filtering principles:

[0071] Each inverter has a propagation delay of 2ns. The main path (I111~I106) contains 6 inverters, so the total delay of the main path is 12ns (this design value is based on the typical pulse width of common external electromagnetic interference (EMI) and internal switching noise, ensuring that noise glitches can be effectively filtered out in most application environments and signal integrity is guaranteed).

[0072] 1.1 Transmission of stable signals

[0073] When the input DINB is a stable high / low level:

[0074] After being inverted by I112, DINB is fed back to one input of NAND2. At the same time, the signal is delayed by the six inverters in the main path and arrives at the other input of NAND2. Since the signal is stable, the "feedback signal" and the "delayed main path signal" eventually have the same level. NAND2 outputs a stable logic level, which is then inverted by I104 to obtain DIN_Work, which has the same logic as DINB but with a steeper edge.

[0075] 1.2 Burr Suppression

[0076] When DNB exhibits pulse spikes (pulse width tw < 6xtpd):

[0077] After the glitch is inverted by I112, it is fed back to one input of NAND2, briefly triggering the glitch level; however, after the delay of the 6 inverters in the main path, the glitch has "disappeared" due to the narrow pulse width (i.e., the main path signal is still at the original stable level); at this time, the two inputs of NAND2 cannot simultaneously maintain the level corresponding to the glitch, so the output of NAND2 will not change with the glitch, and finally the glitch is filtered out, resulting in a clean signal.

[0078] 2. Data sampling and processing:

[0079] like Figure 10 , Figure 11 As shown, the sampling process is as follows:

[0080] The sampling clock SAMP_CLK samples DIN on the rising edge. If a 1 is sampled under the action of SAMP_CLK, S_DIN will be set to 1. If no 1 is sampled, POWER_OFF_CHECK will remain at 0.

[0081] The processing procedure is as follows:

[0082] When the first rising edge of DIN arrives, the reset sampling signal RESET_SAMP_B will be set to 1, enabling the X48 trigger to work. At this time, when the rising edge of the DIN_Work signal arrives, TOP_ENB is set to 0, and the system is working. When all DIN data is 0, the POWER_OFF_CHECK signal remains 0. After 256us of DIN data transmission, RESER_SAMP_B is set to 0, and TOP_ENB is set to 1, shutting down all power-consuming modules.

[0083] In summary, this allows the entire system to be shut down when all received data is 0.

[0084] 3. Enable the control shutdown function module

[0085] By combining data sampling and processing, we obtained an enable signal that sets the input data to 1 when it is all zeros.

[0086] Next, simply add an inverter to this signal to obtain an enable signal that sets the input data to 0 when it is all zero.

[0087] How to disable system branches, such as Figure 4 , Figure 5 As shown:

[0088] MP1 (pull-up transistor) and MP2 (control switch transistor): conventional P-type MOS transistors (PMOS). The conduction condition is that the gate voltage is less than the source voltage (PMOS characteristic: conduction occurs when V_GS < Vth, where Vth is the threshold voltage, which is usually negative).

[0089] VDD: Positive power supply (voltage must be higher than the absolute value of the PMOS threshold voltage to ensure normal operation).

[0090] EN: Enable signal ( Figure 4 The text indicates that EN=0, where "0" represents a low-level logic, which typically corresponds to an actual voltage of 0V or close to ground.

[0091] ILoad: Current load (can be understood as a module that requires power, such as a constant current source, chip, etc., represented by the symbol for current source).

[0092] When EN is low (EN=0):

[0093] MP1 is turned on: The gate of PMOS transistor MP1 is connected to EN=0 (low level), and the source is connected to VDD (high level). This satisfies V_GS = 0 - VDD < Vth (since Vth is negative, the absolute value of V_GS is actually greater than the threshold). MP1 is turned on, pulling the gate of MP2 to VDD.

[0094] MP2 cutoff: The source of MP2 is connected to VDD, and its gate is pulled to VDD by MP1. At this time, V_GS = VDD - VDD = 0.

[0095] At this point, the ID will be 0. This branch is completely closed.

[0096] MN1 (pull-down transistor) and MN2 (control switch transistor): conventional N-type MOS transistors (NMOS). The conduction condition is that the gate voltage > the source voltage + the threshold voltage (i.e., V_GS > Vth, where Vth is positive and is usually around 0.3V~1V).

[0097] VDD: Positive power supply terminal.

[0098] ENB: Enable signal Figure 5 The code indicates that ENB=VDD (high-level logic, corresponding to the actual power supply voltage value, such as 3.3V, 5V, etc.).

[0099] Current source: Figure 5 The circled arrow indicates the load or current path that needs to be controlled. The current Id=0 indicates that no current is flowing through it.

[0100] GND: Ground potential (0V reference point).

[0101] Circuit operating logic (when ENB=VDD):

[0102] When ENB is high (ENB=VDD):

[0103] MN1 conducts: MN1 source is grounded (GND=0V), gate is connected to ENB=VDD, and V_GS = VDD - 0V = VDD. If VDD > Vth (NMOS threshold voltage), MN1 will conduct, pulling its drain potential down to near ground potential (0V).

[0104] MN2 is on: The source of MN2 is grounded (0V), and its gate is connected to the drain of MN1 (because MN1 is on, the potential at this point is 0V). Therefore, V_GS of MN2 = 0V - 0V = 0V. Since 0V < Vth (NMOS requires V_GS > Vth to conduct), MN2 is off.

[0105] Current Id condition: MN2 is cut off, which is equivalent to the current source being disconnected from the ground, so Id=0, and no current flows through the current source.

[0106] In summary, when the control system is shut down, the entire system can be shut down by setting the gate (G) terminal of all P-type MOSFETs (PMOS) in the current-generating branches to 0 and the gate (G) terminal of all N-type MOSFETs (NMOS) to 1.

[0107] Optimal parameter design specifications:

[0108] In this embodiment, the condition of "48 consecutive bits of data being logic 0" as the judgment condition for entering the sleep state, and the condition of "a low level lasting for more than or equal to 256 microseconds" as the effective reset signal are preferred values ​​optimized based on typical application scenarios and system requirements, but are not limitations of the present invention.

[0109] Bit selection for consecutive data (e.g., 48 bits): This value is set to ensure the system can reliably distinguish between valid data frames and invalid or noisy data. A typical data transmission format for a frame (e.g., ...) Figure 6 The data (as shown) contains multiple bits. Setting the sleep condition to a series of consecutive bits (e.g., 48 bits) all equal to 0 can effectively cover the case of an invalid data frame, avoiding system errors that could lead to sleep due to misjudgment of a single bit or a few bits. Those skilled in the art will understand that this value can be adjusted to other quantities, such as 32 bits, 64 bits, etc., depending on the actual communication protocol, data frame length, or anti-interference requirements, as long as the condition of "consecutive bits" is met.

[0110] Minimum duration of the reset signal (e.g., 256 microseconds): This duration is set to reliably distinguish a valid reset signal from noise or glitches that may be present in the environment. A longer duration (e.g., 256µs) ensures that only intentional reset commands are recognized, while brief interference pulses (e.g., ESD, power supply noise) are effectively filtered out. Those skilled in the art will understand that this duration can be adjusted to other values, such as 128µs, 512µs, etc., depending on the system clock frequency, noise environment, or response speed requirements, as long as the "predetermined duration" condition is met.

[0111] Therefore, the specific values ​​of the "preset conditions" and "reset signal" described in this invention can be adjusted according to actual applications. The core of this invention is to achieve reliable sleep control through "continuous multi-bit value judgment" and "signal detection for a certain period of time".

[0112] Example 2

[0113] This embodiment provides a quasi-zero power logic control circuit, which includes: a data receiving preprocessing unit, whose input terminal is connected to an external data signal (such as the DIN pin of a chip), the data receiving preprocessing unit including a signal shaping unit for shaping and filtering the input signal; a data sampling and logic judgment unit, whose input terminal is connected to the output terminal of the data receiving preprocessing unit, the data sampling and logic judgment unit including a sampling unit and a multi-bit data comparison unit for sampling the preprocessed signal and judging whether the values ​​of multiple consecutive bits meet preset conditions; a sleep control signal generation unit, whose input terminal is connected to the output terminal of the data sampling and logic judgment unit, for generating a sleep control signal (such as TOP_ENB) when the multi-bit data comparison unit determines that the data meets the preset conditions; and a power shutdown execution unit, whose control terminal is connected to the output terminal of the sleep control signal generation unit and whose power output terminal is connected to the power supply terminal of at least one controlled functional module, the power shutdown execution unit including a switch control unit for disconnecting the power supply circuit of the controlled functional module in response to the sleep control signal.

[0114] In one specific implementation of this embodiment:

[0115] The signal shaping unit is specifically a Schmitt trigger. This Schmitt trigger can be an integrated circuit (such as a 74HC14) or built from discrete components. Its high threshold voltage VT+ is approximately 3.5V, and its low threshold voltage VT- is approximately 1.5V (under VDD=5V). Input signal amplitudes greater than VT+ are identified as high, and those less than VT- are identified as low; noise in between is effectively suppressed. After shaping, the output signal edges become steeper, for example, the edge time can be less than 10ns.

[0116] The data receiving preprocessing unit further includes a digital filtering unit. This digital filtering unit comprises six inverters (I111, I106, I107, I108, I109, I110) connected in series and a two-input NAND gate (NAND2), preferably a NAND gate. The propagation delay tpd of each inverter is approximately 2 ns. This unit is used to filter out signal glitches with pulse widths less than 12 ns (6 * tpd).

[0117] The preset condition is that 48 consecutive bits of data are logic 0. This value is an optimal value set based on typical data frame length and anti-interference requirements. However, those skilled in the art will understand that as long as the judgment logic of "multiple consecutive bits" is met, the specific number of bits can be adjusted according to the actual protocol.

[0118] The data sampling and logic judgment unit also includes a reset signal detection unit. This unit detects a low-level reset signal, the duration of which is preferably greater than or equal to 256 microseconds. This time threshold is used to reliably distinguish between valid resets and noise, and its specific value can be optimized according to the system clock and noise environment.

[0119] The switch control unit includes a PMOS transistor. For example... Figure 4 As shown, it specifically includes a pull-up PMOS transistor (MP1) and a PMOS transistor (MP2) that serves as the main switch. When the sleep control signal EN is low (0), MP1 is turned on, pulling the gate voltage of MP2 up to VDD, making Vgs of MP2 = 0V, and MP2 is turned off, thereby cutting off the power supply current to the controlled functional module (ILoad).

[0120] The controlled functional module includes a bandgap reference voltage source, a clock oscillator, and a constant current source drive circuit.

[0121] The specific defect addressed by this embodiment is: it solves the problem of excessive static power consumption caused by the continuous operation of the core module in the standby mode of existing LED driver chips.

[0122] Detailed Technical Solution: External data signals are input from the DIN pin. First, the signal passes through a signal shaping unit composed of Schmitt triggers, filtering out noise with amplitudes between VT- and VT+, and shaping the signal into a square wave with steep edges. Subsequently, the square wave signal enters a digital filtering unit composed of a 6-stage inverter and a NAND gate, filtering out glitches with pulse widths less than 12ns. The pre-processed clean signal (DIN_Work) is sent to the data sampling and logic judgment unit. The sampling unit samples and latches DIN_Work on the rising edge of the sampling clock SAMP_CLK.

[0123] A specific implementation circuit of the data sampling unit is as follows: Figure 10 As shown. The sampling clock SAMP_CLK is connected to the clock input CLK of the D flip-flop. The preprocessed data signal DIN_Work is connected to the data input D of the D flip-flop. When the rising edge of the clock arrives, the D flip-flop samples DIN_Work and outputs the sampled data S_DIN. If the sampled value is logic '1', S_DIN is set to high; if no '1' is sampled, the power off check signal POWER_OFF_CHECK generated by subsequent logic will remain low (0).

[0124] Figure 12 This diagram illustrates the overall logic block diagram of data sampling processing and system shutdown control. As shown, the preprocessed data signal DIN_Work is sent to the data sampling and logic judgment unit. The core function of this unit is to sample 48 consecutive bits of data during a valid reset signal (RESET_SAMP_B is high). If all sampled values ​​are logic '0', a valid POWER_OFF_CHECK signal (low level) is generated. Subsequently, when a valid reset end signal arrives (RESET_SAMP_B transitions low), the sleep control signal generation unit combines these two conditions to generate the final sleep control signal TOP_ENB (high level), thereby triggering the system shutdown process. This block diagram clearly summarizes the logical causal relationship from "data judgment" to "generation of shutdown enable".

[0125] A specific implementation circuit of the data judgment and processing unit is as follows: Figure 11As shown. This unit contains a flip-flop (or counter) for detecting the reset signal and a 48-bit data comparison logic for comprehensive judgment. When the first rising edge of the DIN_Work signal arrives (indicating the start of a data frame), flip-flop X48 is enabled (RESET_SAMP_B is set to 1), at which time the system's overall enable signal TOP_ENB is set to an invalid level (e.g., 0), and the system is in normal operating condition. When 48 consecutive bits of data are sampled and determined to be all '0', and a valid reset end signal is subsequently detected (RESET_SAMP_B is set to 0 approximately 256µs after data transmission), the TOP_ENB signal is set to an active level (e.g., 1), instructing the system to shut down all power-consuming modules.

[0126] A multi-bit data comparison unit (e.g., a 48-bit shift register and comparison logic) determines whether all 48 consecutively sampled data bits are '0'. Simultaneously, a reset signal detection unit monitors the DIN signal; when a low level is detected for at least 256µs, a valid reset signal is generated (RESET_SAMP_B is set to 0). Only after a valid reset signal has passed, and the multi-bit data comparison unit determines that all 48 bits are '0', does the sleep control signal generation unit generate a valid sleep control signal (TOP_ENB is set to 1). This signal is sent to the power-off execution unit. The power-off execution unit's switch control unit responds to this high-level signal by controlling the gate voltage of the PMOS transistor MP2 to turn it off, thereby completely disconnecting the power supply circuit of the controlled functional module (such as a bandgap reference source, clock oscillator, etc.), reducing its power consumption to near-zero levels (mainly residual leakage current).

[0127] Component names and connection relationships:

[0128] Schmitt trigger: The input is connected to DIN, and the output is connected to the subsequent filter circuit.

[0129] Inverter chain (I111, I106, I107, I108, I109, I110): connected in series.

[0130] NAND gate (NAND2): One input is connected to the output of a Schmitt trigger (feedback path), and the other input is connected to the output of the end of an inverter chain.

[0131] PMOS transistor MP1: source connected to VDD, gate connected to sleep control signal EN, drain connected to the gate of MP2.

[0132] PMOS transistor MP2: The source is connected to VDD, and the drain is connected to the power supply terminal VCC_Module of the control function module.

[0133] Working principle: By monitoring the data content (all 0 codes) as a sleep command, and combining it with a reset signal to confirm the validity of the command, the power supply of the high-power module is physically cut off through the MOS switch, thus achieving sleep mode with almost zero static power consumption.

[0134] Dimensions:

[0135] Schmitt trigger thresholds: VT+ = 3.5V ± 0.2V, VT- = 1.5V ± 0.2V (VDD=5V).

[0136] Inverter propagation delay: tpd = 2ns ± 0.5ns.

[0137] Reset signal duration: ≥ 256 us ± 10 us.

[0138] PMOS transistor width-to-length ratio (W / L): MP1: 2μm / 0.5μm MP2: 100μm / 0.5μm.

[0139] Implementation steps:

[0140] 1. The system is powered on, and each module is initialized.

[0141] 2. Data signals are input from the DIN pin.

[0142] 3. (Operation: Signal Shaping Unit) Shapes the input signal to suppress noise.

[0143] 4. (Operation: Digital filtering unit) Filter the shaped signal to remove glitches.

[0144] 5. (Condition: The reset signal detection unit detects a low level of ≥256us) The system confirms that it has entered the data frame receiving state.

[0145] 6. (Operation: Sampling Unit) Driven by the sampling clock, the preprocessed signal is sampled 48 times continuously.

[0146] 7. (Operation: Multi-bit data comparison unit) Determine whether all 48 sampled values ​​are logic '0'.

[0147] 8. (Condition: if step 7 is correct) The sleep control signal generation unit generates a sleep control signal (high level).

[0148] 9. (Operation: Switch control unit) In response to a high-level signal, turn off the PMOS switch MP2.

[0149] 10. When the controlled functional module is powered off, the system enters a near-zero power sleep state.

[0150] The overall system working sequence is as follows Figure 8As shown. After the chip powers on, when the DIN pin receives a low-level reset signal with a duration greater than or equal to 256 microseconds, the system enters the data reception preparation state. After the reset signal passes, the chip begins receiving data frames. The specific format of the data frame is as follows: Figure 6 As shown, it includes a reset segment and a data segment.

[0151] Figure 9 A partial magnified view of the DIN signal timing is provided. As shown, after the DIN signal enters the chip, its first rising edge marks the start of the data frame. The internally generated sampling clock SAMP_CLK samples the preprocessed DIN_Work signal on its rising edge. When the first rising edge of DIN arrives, the reset sampling signal RESET_SAMP_B is set to an active level (e.g., logic 1), allowing subsequent data comparison logic to operate. If the DIN signal remains low for 256µs, the reset signal detection unit outputs a valid reset confirmation signal (RESET_SAMP_B is set to 0). When 48 consecutive bits of data have been sampled and are all logic '0', the power off check signal POWER_OFF_CHECK remains low (0). At this time, the system always-enabled signal TOP_ENB is set to an active level (e.g., logic 1), thereby triggering the system shutdown process.

[0152] Experimental verification

[0153] To verify the beneficial effects of this embodiment, performance tests were performed on the circuit described in Embodiment 2:

[0154] Test conditions: VDD = 5.0 V, ambient temperature = 25 °C.

[0155] Measurement parameter: Static current Iq (or power consumption Pstatic) in system sleep mode.

[0156] Comparative example: A similar LED driver chip with a traditional standby mode (model: MCP9904D).

[0157] Expected result: The static power consumption of the circuit in the embodiment of the present invention in sleep mode should be significantly lower than the standby power consumption of the comparative chip.

[0158] Test Project Example 2 Comparative example (MCP9904D) Improvement rate Static power consumption (nW) 15 50000 99.97% Wake-up time (µs) ≤2 50-100 96% (compared to minimum wake-up time) Example

[0159] This embodiment provides a quasi-zero power consumption logic control method, which is applied to the circuit described in Embodiment 2, and includes the following steps: receiving and processing externally input data signals through a data receiving preprocessing unit, the processing including shaping and filtering the input signals; sampling the processed signals through a data sampling and logic judgment unit, and judging whether the values ​​of multiple consecutive bits meet preset conditions; generating a sleep control signal through a sleep control signal generation unit when it is determined that the data meets the preset conditions; and responding to the sleep control signal through a power-off execution unit, disconnecting the power supply circuit of at least one controlled functional module.

[0160] Furthermore, the step of determining whether the preset condition is met is performed after detecting a low-level reset signal with a duration greater than or equal to 256 microseconds (or other predetermined durations set according to system requirements).

[0161] Furthermore, the step of disconnecting the power supply circuit includes: controlling the gate voltage of a PMOS transistor to turn it off, and / or controlling the gate voltage of an NMOS transistor to turn it off.

[0162] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A quasi-zero power logic control circuit, characterized by, The application relates to a power-off control method and device, and the device comprises the following parts: a data receiving preprocessing part, a data sampling and logic judging part, a sleep control signal generating part and a power-off executing part. The data receiving preprocessing part is connected to an external data signal, and comprises a signal shaping unit and a digital filtering unit, which are used for shaping and filtering the input signal to ensure the accuracy of subsequent sampling and judging; the signal shaping unit comprises a Schmitt trigger, which is used for converting the input signal into a square wave signal with steep edges; the digital filtering unit comprises a plurality of inverters connected in series and a logic gate, which are used for filtering out signal glitches with a pulse width less than a predetermined value; The data sampling and logic judging part is connected to the output end of the data receiving preprocessing part, and comprises a sampling unit and a multi-bit data comparison unit, which are used for sampling the preprocessed signal and judging whether the values of continuous multi-bit data meet a preset condition, wherein the preset condition is that 48 continuous data are all logic 0; The sleep control signal generating part is connected to the output end of the data sampling and logic judging part, and is used for generating a sleep control signal when the multi-bit data comparison unit judges that the data meet the preset condition; The power-off executing part is connected to the output end of the sleep control signal generating part, and is connected to the power supply end of at least one controlled functional module; the power-off executing part comprises a switch control unit with MOS transistors, which is used for disconnecting the power supply circuit of the controlled functional module in response to the sleep control signal; the controlled functional module comprises one or more of a band-gap reference voltage source, a clock oscillator and a constant current source driving circuit; The data sampling and logic judging part further comprises a reset signal detecting unit, which is used for detecting a low-level reset signal with a duration greater than or equal to 256 microseconds; the judgment of whether the values of continuous multi-bit data meet the preset condition is performed after the reset signal is detected, so that accurate power consumption control is realized.

2. The quasi-zero power logic control circuit of claim 1, wherein, The switch control unit comprises at least one PMOS transistor and / or at least one NMOS transistor, and the gate of the transistor receives the sleep control signal or an inverse signal of the sleep control signal to turn on or turn off the power supply circuit.

3. A method of quasi-zero power logic control, characterized by, The application relates to a power-off control method and device, and the device comprises the following parts: a data receiving preprocessing part, a data sampling and logic judging part, a sleep control signal generating part and a power-off executing part. The data receiving preprocessing part is connected to an external data signal, and comprises a signal shaping unit and a digital filtering unit, which are used for shaping and filtering the input signal to ensure the accuracy of subsequent sampling and judging; the signal shaping unit comprises a Schmitt trigger, which is used for converting the input signal into a square wave signal with steep edges; the digital filtering unit comprises a plurality of inverters connected in series and a logic gate, which are used for filtering out signal glitches with a pulse width less than a predetermined value; The data sampling and logic judging part is connected to the output end of the data receiving preprocessing part, and comprises a sampling unit and a multi-bit data comparison unit, which are used for sampling the preprocessed signal and judging whether the values of continuous multi-bit data meet a preset condition, wherein the preset condition is that 48 continuous data are all logic 0; The sleep control signal generating part is connected to the output end of the data sampling and logic judging part, and is used for generating a sleep control signal when the multi-bit data comparison unit judges that the data meet the preset condition; The power-off executing part is connected to the output end of the sleep control signal generating part, and is connected to the power supply end of at least one controlled functional module; the power-off executing part comprises a switch control unit with MOS transistors, which is used for disconnecting the power supply circuit of the controlled functional module in response to the sleep control signal; the controlled functional module comprises one or more of a band-gap reference voltage source, a clock oscillator and a constant current source driving circuit; The data sampling and logic judging part further comprises a reset signal detecting unit, which is used for detecting a low-level reset signal with a duration greater than or equal to 256 microseconds; the judgment of whether the values of continuous multi-bit data meet the preset condition is performed after the reset signal is detected, so that accurate power consumption control is realized. The switch control unit comprises at least one PMOS transistor and / or at least one NMOS transistor, and the gate of the transistor receives the sleep control signal or an inverse signal of the sleep control signal to turn on or turn off the power supply circuit. The power-off executing unit comprises a switch control unit using a MOS transistor, and is responsive to the sleep control signal to disconnect the power supply circuit of at least one controlled function module. The step of judging whether the preset condition is met is performed after detecting a low-level reset signal with a duration greater than or equal to 256 microseconds, so that accurate power consumption control is realized.

4. The method of claim 3, wherein, The step of disconnecting the power supply circuit comprises controlling the gate voltage of a PMOS transistor to be off and / or controlling the gate voltage of an NMOS transistor to be off.

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