Mask for deposition and electronic device

Abstract

The invention relates to a mask for deposition and an electronic device. The mask for deposition includes a plurality of cell regions spaced apart from each other and a peripheral region surrounding the cell regions in a plan view; a base layer having a first surface and a second surface opposite to the first surface, the base layer defining a plurality of first openings respectively corresponding to the plurality of unit regions; a pattern insulating layer including a material having a coefficient of thermal expansion greater than a coefficient of thermal expansion of the base layer, the pattern insulating layer having a plurality of pattern portions on the first surface of the base layer corresponding to the plurality of unit regions, respectively, each of the plurality of pattern portions defining a plurality of slits; and a reinforcing pattern in the peripheral region, the reinforcing pattern including a material having a coefficient of thermal expansion different from the coefficient of thermal expansion of the base layer, the reinforcing pattern being covered by the pattern insulating layer.

Description

Technical Field

[0001] Various aspects of embodiments of this disclosure relate to masks for deposition and electronic devices manufactured using masks for deposition. Background Technology

[0002] Flat panel displays are replacing cathode ray tube (CRT) displays as the most common type of display due to their lightweight and thin profile. Liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) displays are some representative examples of this type of flat panel display.

[0003] Thin films of organic emitting layers, such as those in organic light-emitting diode (OLED) display devices, can be formed using various methods. Deposition methods refer to the process of depositing material onto a substrate using a mask with the same pattern as the thin film to be deposited on it. If the mask deforms during the deposition process due to stress induced within it, precise patterning on the substrate may be difficult. Summary of the Invention

[0004] Embodiments of this disclosure provide masks for deposition that enable precise patterning.

[0005] Embodiments of this disclosure also provide electronic devices manufactured using masks for deposition.

[0006] Additional aspects and features of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the described embodiments.

[0007] A deposition mask according to embodiments of the present disclosure includes: a plurality of cell regions spaced apart from each other and a peripheral region surrounding the plurality of cell regions in a plan view; a substrate layer having a first surface and a second surface opposite to the first surface, and the substrate layer defining a plurality of first openings corresponding to the plurality of cell regions; a patterned insulating layer comprising a material having a coefficient of thermal expansion greater than that of the substrate layer, and the patterned insulating layer including a plurality of patterned portions corresponding to the plurality of cell regions on the first surface of the substrate layer; and a reinforcing pattern, in the peripheral region, the reinforcing pattern comprising a material having a coefficient of thermal expansion different from that of the substrate layer, and the reinforcing pattern being covered by the patterned insulating layer. Each of the plurality of patterned portions defines a plurality of slits.

[0008] In this embodiment, the coefficient of thermal expansion of the reinforcing pattern can be greater than that of the substrate layer. The reinforcing pattern can be located on the second surface of the substrate layer.

[0009] In an embodiment, the patterned insulating layer may include: a first portion on a first surface of the substrate layer and may include a plurality of patterned portions; and a second portion on a second surface of the substrate layer and defining a plurality of second openings corresponding to a plurality of cell regions. The reinforcing pattern may be covered by the second portion of the patterned insulating layer.

[0010] In an embodiment, the mask may further include: an alignment pattern, which is on a first surface of the substrate layer in a peripheral region and covered by a first portion of the patterned insulating layer.

[0011] In an embodiment, the reinforcement pattern may be spaced apart from the alignment pattern and the substrate layer may be located between the reinforcement pattern and the alignment pattern.

[0012] In an embodiment, in a plan view, the size of the enhancement pattern may be larger than the size of the alignment pattern.

[0013] In one embodiment, a first portion of the patterned insulating layer may define an alignment opening located in the peripheral region.

[0014] In one embodiment, the enhancement pattern may overlap with the alignment opening in the plan view.

[0015] In one embodiment, the peripheral region may have an alignment opening that extends through the substrate layer, the patterned insulating layer, and the reinforcing pattern in a direction perpendicular to the first surface of the substrate layer.

[0016] In this embodiment, the coefficient of thermal expansion of the reinforcing pattern can be less than that of the substrate layer. The reinforcing pattern can be located on the first surface of the substrate layer.

[0017] In an embodiment, the patterned insulating layer may include: a first portion on a first surface of the substrate layer and including a plurality of patterned portions; and a second portion on a second surface of the substrate layer and defining a plurality of second openings corresponding to a plurality of cell regions. The reinforcing pattern may be covered by the first portion of the patterned insulating layer.

[0018] In an embodiment, the mask may further include an alignment pattern on a first surface of the substrate layer in a peripheral region and covered by a first portion of a patterned insulating layer. The alignment pattern and the reinforcing pattern may comprise the same material.

[0019] In an embodiment, the enhancement pattern and the alignment pattern may be spaced apart from each other.

[0020] In one embodiment, the enhancement pattern may surround the alignment pattern in a planar view.

[0021] In an embodiment, the mask may further include: a cover insulating layer between the substrate layer and the pattern insulating layer in the peripheral region. An reinforcing pattern may be present between the cover insulating layer and the pattern insulating layer.

[0022] In an embodiment, the substrate layer may include silicon, the overlay insulating layer may include silicon oxide, the patterned insulating layer may include silicon nitride, and the reinforcing pattern may include metal or alloy.

[0023] In one embodiment, the reinforcement pattern may be adjacent to the edge of the substrate layer.

[0024] A deposition mask according to another embodiment of the present disclosure includes: a plurality of cell regions spaced apart from each other and a peripheral region surrounding the plurality of cell regions in a plan view; a substrate layer having a first surface and a second surface facing away from the first surface, and the substrate layer defining a plurality of first openings corresponding to the plurality of cell regions; a patterned insulating layer comprising a material having a coefficient of thermal expansion greater than that of the substrate layer, and the patterned insulating layer comprising: a first portion on the first surface of the substrate layer, the first portion comprising a plurality of patterned portions corresponding to the plurality of cell regions; a second portion on the second surface of the substrate layer, the second portion defining a plurality of second openings corresponding to the plurality of cell regions; and a cover insulating layer comprising a material having a coefficient of thermal expansion smaller than that of the substrate layer, the cover insulating layer being between the substrate layer and the first portion of the patterned insulating layer, and the cover insulating layer defining a plurality of third openings corresponding to the plurality of cell regions. Each of the plurality of patterned portions defines a plurality of slits. The first surface of the substrate layer contacts the cover insulating layer, and the second surface of the substrate layer contacts the second portion of the patterned insulating layer.

[0025] In an embodiment, in a plan view, the size of one of the plurality of second openings may be larger than the size of the corresponding one of the plurality of first openings.

[0026] A deposition mask according to another embodiment of the present disclosure includes: a plurality of cell regions spaced apart from each other and a peripheral region surrounding the plurality of cell regions in a plan view; a substrate layer having a first surface and a second surface opposite to the first surface, and the substrate layer defining a plurality of first openings corresponding to the plurality of cell regions; a patterned insulating layer comprising a material having a coefficient of thermal expansion smaller than that of the substrate layer, and the patterned insulating layer comprising: a first portion on the first surface of the substrate layer, and the first portion comprising a plurality of patterned portions corresponding to the plurality of cell regions; a second portion on the second surface of the substrate layer, and the second portion defining a plurality of second openings corresponding to the plurality of cell regions; a reinforcing pattern on the first portion of the patterned insulating layer in the peripheral region, and comprising a material having a coefficient of thermal expansion larger than that of the substrate layer; and an alignment pattern on the first portion of the patterned insulating layer in the peripheral region. Each of the plurality of patterned portions defines a plurality of slits. The alignment pattern and the reinforcing pattern comprise the same material.

[0027] In an embodiment, the enhancement pattern and the alignment pattern may be spaced apart from each other.

[0028] In an embodiment, in a plan view, the enhancement pattern may surround the alignment pattern.

[0029] An electronic device according to another embodiment of the present disclosure includes: a display device including an emitter layer deposited using a mask for deposition; and a processor configured to provide image data signals and input control signals to the display device to control the display device. The mask includes: a plurality of cell regions spaced apart from each other and a peripheral region surrounding the plurality of cell regions in a plan view; a substrate layer having a first surface and a second surface opposite to the first surface, and defining a plurality of first openings corresponding to the plurality of cell regions; a patterned insulating layer comprising a material having a coefficient of thermal expansion greater than that of the substrate layer, and including a plurality of patterned portions corresponding to the plurality of cell regions on the first surface of the substrate layer; and a reinforcing pattern, in the peripheral region, comprising a material having a coefficient of thermal expansion different from that of the substrate layer, and covered by the patterned insulating layer. Each of the plurality of patterned portions defines a plurality of slits.

[0030] According to embodiments of this disclosure, the mask used for deposition achieves precise patterning.

[0031] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of this disclosure as claimed. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, describe aspects and features of the present disclosure.

[0033] Figure 1 This is a cross-sectional view showing a deposition apparatus according to an embodiment.

[0034] Figure 2 This is a top view showing the mask according to an embodiment.

[0035] Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I' in the diagram.

[0036] Figure 4 It is along Figure 2 The cross-sectional view taken from line II-II' in the diagram.

[0037] Figures 5A to 5D This is a bottom view showing some components of the mask according to an embodiment.

[0038] Figures 6A to 6EThis is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0039] Figure 7 and Figure 8 This is a cross-sectional view showing a mask according to an embodiment.

[0040] Figure 9A and Figure 9B This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0041] Figure 10 and Figure 11 This is a cross-sectional view showing a mask according to an embodiment.

[0042] Figures 12A to 12E This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0043] Figure 13 and Figure 14 This is a cross-sectional view showing a mask according to an embodiment.

[0044] Figure 15A and Figure 15B This is a top view showing some components of the mask according to an embodiment.

[0045] Figure 16A and Figure 16B This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0046] Figure 17 and Figure 18 This is a cross-sectional view showing a mask according to an embodiment.

[0047] Figures 19A to 19E This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0048] Figure 20 and Figure 21 This is a cross-sectional view showing a mask according to an embodiment.

[0049] Figure 22 This is a cross-sectional view showing a display device according to an embodiment.

[0050] Figure 23 This is a block diagram describing an electronic device according to an embodiment.

[0051] Figure 24 This is a schematic diagram illustrating an electronic device according to various embodiments. Detailed Implementation

[0052] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some embodiments of this disclosure are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0053] Various modifications and forms may be made in this disclosure, and specific embodiments will be shown in the accompanying drawings and described in detail in the text. However, this is not intended to limit this disclosure to the specific forms disclosed, and it will be understood that all changes, equivalents, or substitutions falling within the spirit and technical scope of this disclosure should be included.

[0054] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediary elements or intermediary layers may be present. When an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly coupled to" another element or layer, no intermediary element or intermediary layer is present. For example, when a first element is described as being "coupled" or "connected" to a second element, the first element may be directly coupled to or connected to the second element, or the first element may be indirectly coupled to or connected to the second element via one or more intermediary elements.

[0055] In the accompanying drawings, the dimensions of various elements, layers, etc., may be exaggerated for clarity of illustration. The same reference numerals denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, when describing embodiments of this disclosure, the use of "may" refers to "one or more embodiments of this disclosure." Expressions such as "at least one of..." and "any one of..." modify the entire list of elements (elements) and not the individual elements (elements) within the list when following a list of elements (elements). For example, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. As used herein, the terms “substantially,” “about,” and similar terms are used as approximations rather than as terms of degree, and are intended to describe the inherent variations in measurements or calculations that will be recognized by one of ordinary skill in the art.

[0056] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or segment from another element, component, area, layer, or segment. Therefore, without departing from the teachings of the exemplary embodiments, the first element, first component, first area, first layer, or first segment discussed below may be referred to as a second element, second component, second area, second layer, or second segment.

[0057] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” are used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” or “above” other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative terms used herein should be interpreted accordingly.

[0058] The terminology used herein is for the purpose of describing embodiments of this disclosure and is not intended to be limiting of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural forms. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “having” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0059] It will be appreciated by those skilled in the art that, in view of the entirety of this disclosure, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable manners, and each embodiment may be implemented independently of one another or in any suitable combination with one another.

[0060] Furthermore, any numerical ranges disclosed and / or enumerated herein are intended to include all subranges with the same numerical precision within the enumerated ranges. For example, the range “1.0 to 10.0” is intended to include all subranges between the enumerated minimum value of 1.0 and the enumerated maximum value of 10.0 (and including both the enumerated minimum value of 1.0 and the enumerated maximum value of 10.0), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit enumerated herein is intended to include all lower numerical limits therein, and any minimum numerical limit enumerated herein is intended to include all higher numerical limits therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly enumerate any subranges within the scope expressly enumerated herein.

[0061] The electronic devices and / or any other related devices or components described herein according to embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, and / or suitable combinations of software, firmware, and hardware. For example, the various components of the electronic device can be formed on a single integrated circuit (IC) chip or separate IC chips. Furthermore, the various components of the electronic device can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on the same substrate as the electronic device. Additionally, the various components of the electronic device can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in memory, which can be implemented in a computing device using a standard memory device such as random access memory (RAM). The computer program instructions can also be stored in a non-transitory computer-readable medium such as an optical disc read-only drive (CD-ROM) or a flash drive. Furthermore, those skilled in the art should recognize that, without departing from the scope of the exemplary embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and will not be interpreted in an idealized or overly formalized sense.

[0063] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0064] Figure 1 This is a cross-sectional view showing a deposition apparatus according to an embodiment.

[0065] Reference Figure 1 The deposition apparatus 1 according to the embodiment may include a deposition chamber 10, a fixing member 20, a deposition source 30 and a mask 40.

[0066] Deposition chamber 10 can provide a space for performing operations on substrate S (e.g., Figure 22 An organic emission layer (e.g., an organic emission layer) is formed on the substrate 110 shown in the figure. Figure 22 The space shown is for the deposition process of a thin film (emitting layer EL). The deposition chamber 10 can be set to a vacuum state for deposition conditions. The deposition chamber 10 may have a bottom surface, a top surface, and sidewalls. The bottom surface of the deposition chamber 10 may be parallel to a plane defined by a first direction DR1 and a second direction DR2 that intersects (e.g., crosses) the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. A third direction DR3 may be defined as a direction orthogonal to (e.g., perpendicular to) the bottom surface of the deposition chamber 10.

[0067] The fixing member 20 can be disposed inside the deposition chamber 10 and above the deposition source 30. The fixing member 20 can be configured to fix (e.g., secure) the mask 40. In embodiments, the fixing member 20 can be mounted on (or fixed to) the top surface of the deposition chamber 10. The fixing member 20 can include magnets, grippers, or robotic arms for fixing the mask 40. For example, the fixing member 20 can magnetically fix the mask 40, thereby ensuring close contact between the mask 40 and the substrate S.

[0068] The deposition source 30 can spray (or emit) a deposition material, such as an organic light-emitting material, as a vapor. The deposition material sprayed from the deposition source 30 can pass through the mask 40 and can be deposited on a surface of the substrate S to form a pattern. For example, the substrate S can be a substrate in an intermediate stage of manufacturing a display panel, but the embodiments are not limited to this.

[0069] The mask 40 can be disposed inside the deposition chamber 10 and above the deposition source 30. The mask 40 can support the substrate S. As described below, the mask 40 can include multiple cell regions, and multiple slits can be defined in each of the multiple cell regions (e.g., Figure 2The slit SL shown is illustrated. Deposition material ejected from deposition source 30 can pass through the slit of mask 40 and can be deposited on a surface of substrate S to form a specific pattern. For example, substrate S can be a master substrate for manufacturing multiple display panels. In such an embodiment, substrate S can include multiple unit regions, and multiple unit regions of mask 40 can each correspond to multiple unit regions of substrate S.

[0070] In this embodiment, a support block or similar component for supporting the mask 40 may be further provided inside the deposition chamber 10.

[0071] Figure 2 This is a top view showing the mask according to an embodiment. Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I' in the diagram. Figure 4 It is along Figure 2 The cross-sectional view taken from line II-II' in the diagram.

[0072] Reference Figures 1 to 4 In an embodiment, the mask 40 may include a substrate layer 410, a cover insulating layer 420, a pattern insulating layer 430, an alignment pattern 440, and a reinforcement pattern 450.

[0073] Mask 40 (or substrate layer 410) may have multiple cell regions DA and peripheral regions PA surrounding the multiple cell regions DA. For example... Figure 2 As shown, multiple cell regions DA can be spaced apart from each other in the plan view. Although Figure 2 An embodiment in which the mask 40 has a circular planar shape is shown, but this is an example and the embodiment is not limited thereto. The mask 40 can have various planar shapes, such as a square, etc.

[0074] The outer perimeter region PA can include a first outer perimeter region PA1 and a second outer perimeter region PA2. The first outer perimeter region PA1 can be defined as the region between adjacent cell regions DA. For example, the first outer perimeter region PA1 can have a grid shape (or lattice shape) in a planar diagram. The second outer perimeter region PA2 can be defined as the region outside cell regions DA and the first outer perimeter region PA1. For example, the second outer perimeter region PA2 can have a ring shape in a planar diagram.

[0075] In an embodiment, the substrate layer 410 may comprise the same material as the substrate S to which the deposition is to be performed. For example, the substrate layer 410 may comprise silicon. For example, the substrate layer 410 may be formed by thinning (or reducing) a silicon wafer. Because the substrate layer 410 and the substrate S comprise the same material (such that the coefficient of thermal expansion of the substrate layer 410 is equal to that of the substrate S), it is possible to prevent the deposition location of the deposited material from being distorted according to the process temperature.

[0076] The substrate layer 410 may have a first surface 411 and a second surface 412 facing away from the first surface 411. The first surface 411 of the substrate layer 410 may be a surface facing the substrate S, which is the object of deposition. The second surface 412 of the substrate layer 410 may be a surface facing the deposition source 30 from which the deposition material is sprayed. A third direction DR3 may be perpendicular to each of the first surface 411 and the second surface 412 of the substrate layer 410. Hereinafter, the first surface 411 may be referred to as the upper surface, and the second surface 412 may be referred to as the lower surface. The outer surface 413 of the substrate layer 410 may connect the first surface 411 and the second surface 412 (e.g., it may extend between the first surface 411 and the second surface 412).

[0077] A cover insulating layer 420 may be disposed between the substrate layer 410 and the pattern insulating layer 430. The cover insulating layer 420 may cover at least a portion of the substrate layer 410. For example, as... Figure 3 and Figure 4 As shown, the insulating layer 420 can cover the first surface 411, the second surface 412 and the outer surface 413 of the substrate layer 410.

[0078] In an embodiment, the covering insulating layer 420 may include a first portion 422 disposed on a first surface 411 of the substrate layer 410, a second portion 424 disposed on a second surface 412 of the substrate layer 410, and a third portion 426 disposed on an outer surface 413 of the substrate layer 410. The first portion 422 and the second portion 424 of the covering insulating layer 420 may be positioned in opposite directions to each other, and the substrate layer 410 is located between the first portion 422 and the second portion 424 of the covering insulating layer 420. For example, the first portion 422, the second portion 424, and the third portion 426 of the covering insulating layer 420 may be connected to each other.

[0079] The first portion 422 of the covering insulating layer 420 can contact the first surface 411 of the substrate layer 410. The second portion 424 of the covering insulating layer 420 can contact the second surface 412 of the substrate layer 410. The third portion 426 of the covering insulating layer 420 can contact the outer surface 413 of the substrate layer 410.

[0080] The overlay insulating layer 420 may comprise a different material than the substrate layer 410. In embodiments, the overlay insulating layer 420 may comprise a material having a smaller coefficient of thermal expansion than the substrate layer 410. For example, the overlay insulating layer 420 may comprise silicon oxide, but this is an example and embodiments are not limited thereto.

[0081] The patterned insulating layer 430 may cover at least a portion of the covering insulating layer 420. For example, as... Figure 3 and Figure 4As shown, the patterned insulating layer 430 may cover the first portion 422, the second portion 424, and the third portion 426 of the covering insulating layer 420. In another embodiment, the patterned insulating layer 430 may cover the first portion 422 and the second portion 424 of the covering insulating layer 420, but may not cover the third portion 426 of the covering insulating layer 420.

[0082] In an embodiment, the patterned insulating layer 430 may include a first portion 432 disposed on a first surface 411 of the substrate layer 410, a second portion 434 disposed on a second surface 412 of the substrate layer 410, and a third portion 436 disposed on an outer surface 413 of the substrate layer 410. The first portion 432 of the patterned insulating layer 430 may be disposed on the upper surface of the first portion 422 of the covering insulating layer 420, and the second portion 434 of the patterned insulating layer 430 may be disposed on the lower surface of the second portion 424 of the covering insulating layer 420. The first portion 432 and the second portion 434 of the patterned insulating layer 430 may be positioned in opposite directions to each other, and the substrate layer 410 and the covering insulating layer 420 are located between the first portion 432 and the second portion 434 of the patterned insulating layer 430. For example, the first portion 432, the second portion 434, and the third portion 436 of the patterned insulating layer 430 may be connected to each other.

[0083] The first portion 432 of the patterned insulating layer 430 can contact the first portion 422 of the covering insulating layer 420. The second portion 434 of the patterned insulating layer 430 can contact the second portion 424 of the covering insulating layer 420. The third portion 436 of the patterned insulating layer 430 can contact the third portion 426 of the covering insulating layer 420.

[0084] The patterned insulating layer 430 may include a plurality of patterned portions PTPs on the first surface 411 of the substrate layer 410, each corresponding to a plurality of cell regions DA. The first portion 432 of the patterned insulating layer 430 may include a plurality of patterned portions PTPs. Each of the plurality of patterned portions PTPs may define a plurality of slits SL. Each of the plurality of slits SL may penetrate (e.g., extend through) the first portion 432 of the patterned insulating layer 430 in a third-direction DR3. For example, each of the plurality of patterned portions PTPs may have a grid shape in a planar view. For example, one patterned portion PTP defining the plurality of slits SL may correspond to one cell region DA.

[0085] like Figure 3 and Figure 4As shown, no other layers may be provided below the patterned portion PTP (e.g., no layers may be provided). The substrate layer 410 may define a plurality of first openings OP1, each corresponding to a plurality of cell regions DA. For example, one first opening OP1 may correspond to one cell region DA. Each of the plurality of first openings OP1 may penetrate the substrate layer 410 in the third direction DR3. The plurality of first openings OP1 may be spaced apart from each other in a planar view.

[0086] The second portion 434 of the patterned insulating layer 430 may define a plurality of second openings OP2 corresponding to a plurality of cell regions DA. For example, one second opening OP2 may correspond to one cell region DA. Each of the plurality of second openings OP2 may penetrate the second portion 434 of the patterned insulating layer 430 in a third-direction DR3. The plurality of second openings OP2 may be spaced apart from each other in a plan view.

[0087] Although the first portion 432 of the patterned insulating layer 430 includes a plurality of patterned portions PTP corresponding to a plurality of cell regions DA, the second portion 434 of the patterned insulating layer 430 defines a plurality of second openings OP2 corresponding to a plurality of cell regions DA, such that in a plan view, the size of the second portion 434 of the patterned insulating layer 430 can be smaller than the size of the first portion 432 of the patterned insulating layer 430.

[0088] The second portion 424 of the covering insulating layer 420 may define a plurality of third openings OP3 corresponding to a plurality of cell regions DA. For example, one third opening OP3 may correspond to one cell region DA. Each of the plurality of third openings OP3 may penetrate the second portion 424 of the covering insulating layer 420 in a third-direction DR3. The plurality of third openings OP3 may be spaced apart from each other in a plan view.

[0089] The first portion 422 of the covering insulating layer 420 may define a plurality of fourth openings OP4 corresponding to a plurality of cell regions DA. For example, one fourth opening OP4 may correspond to one cell region DA. Each of the plurality of fourth openings OP4 may penetrate the first portion 422 of the covering insulating layer 420 in a third-direction DR3. The plurality of fourth openings OP4 may be spaced apart from each other in a plan view. In a plan view, the size of the first portion 422 of the covering insulating layer 420 may approximate the size of the second portion 424 of the covering insulating layer 420.

[0090] like Figure 3 and Figure 4As shown, the first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4, corresponding to a unit region DA, can be connected to each other (e.g., substantially aligned) on the third direction DR3. For example, no other layer may be provided beneath each of the plurality of patterned portions PTP. Thus, the deposited material ejected from the deposition source 30 can pass through the slits SL defined in each of the plurality of patterned portions PTP and can be deposited on a surface of the substrate S to form a pattern.

[0091] In an embodiment, in a plan view, each of the substrate layer 410, the first portion 422 of the covering insulating layer 420, the second portion 424 of the covering insulating layer 420, and the second portion 434 of the patterned insulating layer 430 may overlap with the first peripheral region PA1 and the second peripheral region PA2, and may have a grid shape.

[0092] The patterned insulating layer 430 may comprise a different material than the substrate layer 410 and the cover insulating layer 420. In embodiments, the patterned insulating layer 430 may comprise a material having a coefficient of thermal expansion greater than that of the substrate layer 410. Furthermore, the patterned insulating layer 430 may comprise a transparent or translucent material. For example, the patterned insulating layer 430 may comprise silicon nitride, but this is an example and the embodiments are not limited thereto.

[0093] Alignment pattern 440 can be provided on the first surface 411 of substrate layer 410 in peripheral region PA. Alignment pattern 440 can be provided in second peripheral region PA2. Alignment pattern 440 can be used to align mask 40 and substrate S with each other.

[0094] In an embodiment, the alignment pattern 440 may include a plurality of alignment patterns 440. For example, such as Figure 2 As shown in the diagram, in the plan view, multiple alignment patterns 440 can be respectively arranged on the left, right, upper, and lower sides of the mask 40, but this is an example and the embodiment is not limited thereto. Furthermore, although... Figure 2 An embodiment in which each of the plurality of alignment patterns 440 has a cross-shaped planar shape is shown, but this is an example and the embodiment is not limited thereto. The number and shape of the alignment patterns 440 can be varied.

[0095] Alignment pattern 440 can be disposed between cover insulating layer 420 and pattern insulating layer 430. Alignment pattern 440 can be disposed between first portion 422 of cover insulating layer 420 and first portion 432 of pattern insulating layer 430. For example, alignment pattern 440 can be disposed on the upper surface of first portion 422 of cover insulating layer 420 and can be covered by first portion 432 of pattern insulating layer 430. The thickness of first portion 432 of pattern insulating layer 430 can be greater than the thickness of alignment pattern 440.

[0096] In an embodiment, the alignment pattern 440 may include a metal such as chromium, aluminum, tungsten, or silver, or an alloy thereof. As described above, the pattern insulating layer 430 may include a transparent or translucent material. Therefore, the alignment pattern 440 may be visible from the outside even when the first portion 432 of the pattern insulating layer 430 is covered.

[0097] The reinforcing pattern 450 may be disposed on the second surface 412 of the substrate layer 410 within the peripheral region PA. The reinforcing pattern 450 may be disposed within a portion of the peripheral region PA. The alignment pattern 440 and the reinforcing pattern 450 may be positioned in opposite directions, with the substrate layer 410 and the overlay insulating layer 420 situated between them.

[0098] The reinforcing pattern 450 can be disposed between the cover insulating layer 420 and the pattern insulating layer 430. The reinforcing pattern 450 can also be disposed between the second portion 424 of the cover insulating layer 420 and the second portion 434 of the pattern insulating layer 430. For example, the reinforcing pattern 450 can be disposed on the lower surface of the second portion 424 of the cover insulating layer 420 and can be covered by the second portion 434 of the pattern insulating layer 430. The thickness of the second portion 434 of the pattern insulating layer 430 can be greater than the thickness of the reinforcing pattern 450.

[0099] The reinforcing pattern 450 may include a material having a coefficient of thermal expansion different from that of the substrate layer 410. In one embodiment, the reinforcing pattern 450 may include a material having a coefficient of thermal expansion greater than that of the substrate layer 410. For example, the reinforcing pattern 450 may include metals such as chromium, aluminum, tungsten, or silver, or alloys thereof. In another embodiment, the reinforcing pattern 450 may include an insulating material.

[0100] As described above, because the coefficient of thermal expansion of the patterned insulating layer 430 is greater than that of the substrate layer 410, tensile stress can be induced in the patterned insulating layer 430. Since tensile stress is induced in each of the first portion 432 and the second portion 434 of the patterned insulating layer 430, which are positioned in opposite directions and the substrate layer 410 is located between them, the tensile stress induced in the first portion 432 of the patterned insulating layer 430 may be partially offset by the tensile stress induced in the second portion 434. However, as described above, because the size of the second portion 434 of the patterned insulating layer 430 in the plan view is smaller than that of the first portion 432, the tensile stress induced in the first portion 432 may not be completely offset. Furthermore, because the coefficient of thermal expansion of the covering insulating layer 420 is less than that of the substrate layer 410, compressive stress may be induced in the covering insulating layer 420. However, because the size of the first portion 422 of the covering insulating layer 420 in the planar view can approximate the size of the second portion 424 of the covering insulating layer 420, the tensile stress induced in the first portion 432 of the patterned insulating layer 430 may not be substantially offset by the covering insulating layer 420. In such an embodiment, warping may occur where the mask 40 deforms due to the unoffset tensile stress induced in the first portion 432 of the patterned insulating layer 430, and the deposition location of the deposited material may differ from the target location depending on the mask location, making precise patterning difficult.

[0101] According to embodiments of this disclosure, a reinforcing pattern 450 may be disposed in the peripheral region PA to further counteract the tensile stress induced in the first portion 432 of the patterned insulating layer 430. For example, when the reinforcing pattern 450 comprises a material having a coefficient of thermal expansion greater than that of the substrate layer 410 (e.g., when tensile stress is induced in the reinforcing pattern 450), the reinforcing pattern 450 may be positioned in a direction opposite to the first portion 432 of the patterned insulating layer 430, with the substrate layer 410 interposed between the reinforcing pattern 450 and the first portion 432 of the patterned insulating layer 430. Because the reinforcing pattern 450, which induces tensile stress, is positioned in a direction opposite to the first portion 432 of the patterned insulating layer 430, and the substrate layer 410 is interposed between the reinforcing pattern 450 and the first portion 432 of the patterned insulating layer 430, the tensile stress induced in the first portion 432 of the patterned insulating layer 430 can be counteracted more effectively. Therefore, warpage of the mask 40 can be reduced, and precise patterning can be achieved.

[0102] The reinforcing pattern 450 can have various planar shapes to effectively counteract the tensile stress induced in the first portion 432 of the patterned insulating layer 430. In an embodiment, the reinforcing pattern 450 can be primarily disposed in the outer region of the mask 40.

[0103] Figures 5A to 5D This is a bottom view showing some components of the mask according to an embodiment. For example, Figures 5A to 5D Each of them may show a substrate layer 410 and a reinforcing pattern 450.

[0104] In an embodiment, such as Figures 5A to 5C As shown, the reinforcement pattern 450 may be disposed adjacent to the outer edge of the substrate layer 410. The reinforcement pattern 450 may be disposed in the second peripheral region PA2 and may have a shape surrounding the cell region DA in a plan view. For example, the reinforcement pattern 450 may have a ring shape in a plan view.

[0105] In an embodiment, such as Figure 5D As shown, multiple reinforcement patterns 450 can be spaced apart from each other. For example, some of the multiple reinforcement patterns 450 can be disposed in a first peripheral region PA1, and some of the multiple reinforcement patterns 450 can be disposed in a second peripheral region PA2.

[0106] Figures 5A to 5D The shape of the reinforcing pattern 450 shown is an example, and the embodiment is not limited thereto. The shape and arrangement of the reinforcing pattern 450 can be varied.

[0107] Refer again Figures 2 to 4 In an embodiment, the alignment pattern 440 and the reinforcement pattern 450 may be positioned in opposite directions, with the substrate layer 410 and the cover insulating layer 420 positioned between the alignment pattern 440 and the reinforcement pattern 450. For example, the reinforcement pattern 450 may be spaced apart from the alignment pattern 440, with the substrate layer 410 and the cover insulating layer 420 positioned between the alignment pattern 440 and the reinforcement pattern 450.

[0108] In this embodiment, the coefficient of thermal expansion of the alignment pattern 440 may be greater than that of the substrate layer 410. In a plan view, the size of the reinforcing pattern 450 may be larger than that of the alignment pattern 440. If the size of the reinforcing pattern 450 is smaller than that of the alignment pattern 440, the tensile stress induced in the first portion 432 of the patterned insulating layer 430 may not be effectively counteracted.

[0109] Figures 6A to 6E This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0110] Figures 6A to 6E Each of them can correspond to Figure 3The cross-sectional view shown in the figure. Figures 6A to 6E The above reference can be shown. Figures 2 to 4 The steps of the mask 40 method are described, and repeated descriptions may be omitted or simplified.

[0111] Reference Figure 6A An insulating cover layer 420 may be formed on the substrate layer 410. The insulating cover layer 420 may be formed to cover at least a portion of the substrate layer 410. For example, the insulating cover layer 420 may be formed to cover a first surface 411, a second surface 412, and an outer surface 413 of the substrate layer 410. The insulating cover layer 420 may include a first portion 422 disposed on the first surface 411 of the substrate layer 410, a second portion 424 disposed on the second surface 412 of the substrate layer 410, and a third portion 426 disposed on the outer surface 413 of the substrate layer 410.

[0112] In one embodiment, the overlay insulating layer 420 may be formed by oxidizing the substrate layer 410. For example, the substrate layer 410 may comprise silicon, and the overlay insulating layer 420 may comprise silicon oxide. However, this is an example, and the embodiments are not limited thereto.

[0113] Alignment pattern 440 and reinforcement pattern 450 can be formed on the covering insulating layer 420.

[0114] Alignment pattern 440 can be formed on the upper surface of the first portion 422 of the covering insulating layer 420. For example, after the first thin film is deposited on the upper surface of the first portion 422 of the covering insulating layer 420, the first thin film can be partially removed by photolithography and etching processes to form alignment pattern 440.

[0115] A reinforcing pattern 450 can be formed on the lower surface of the second portion 424 of the covering insulating layer 420. For example, after the second thin film is deposited on the lower surface of the second portion 424 of the covering insulating layer 420, the second thin film can be partially removed by photolithography and etching processes to form the reinforcing pattern 450. The second thin film can be formed by depositing a material (such as a metal or alloy) having a coefficient of thermal expansion greater than that of the substrate layer 410.

[0116] In an embodiment, the reinforcement pattern 450 may be formed primarily on the outer region of the substrate layer 410. In an embodiment, when the substrate layer 410 is formed from a silicon wafer, the crystal orientation of the silicon wafer can be measured, and the shape of the reinforcement pattern 450 can be determined based on the measured crystal orientation of the silicon wafer.

[0117] In one embodiment, the alignment pattern 440 and the reinforcement pattern 450 may not be formed simultaneously (e.g., they may be formed sequentially). For example, the reinforcement pattern 450 may be formed after the alignment pattern 440 is formed. In another embodiment, the alignment pattern 440 may be formed after the reinforcement pattern 450 is formed.

[0118] Reference Figure 6B A patterned insulating layer 430 can be formed on the cover insulating layer 420, the alignment pattern 440, and the reinforcing pattern 450. The patterned insulating layer 430 may include a first portion 432 disposed on the upper surface of the first portion 422 of the cover insulating layer 420, a second portion 434 disposed on the lower surface of the second portion 424 of the cover insulating layer 420, and a third portion 436 disposed on the side surface of the third portion 426 of the cover insulating layer 420. The first portion 432 of the patterned insulating layer 430 may cover the alignment pattern 440. The second portion 434 of the patterned insulating layer 430 may cover the reinforcing pattern 450.

[0119] The patterned insulating layer 430 can be formed by depositing a transparent or translucent material having a coefficient of thermal expansion greater than that of the substrate layer 410. For example, the patterned insulating layer 430 can be formed by depositing silicon nitride via a process such as chemical vapor deposition (“CVD”) or physical vapor deposition (“PVD”), but the embodiments are not limited thereto.

[0120] Reference Figure 6C The first portion 432 of the patterned insulating layer 430 can be partially removed to form multiple patterned portions PTP corresponding to multiple unit regions DA.

[0121] In this embodiment, a first portion 432 of the patterned insulating layer 430 can be partially removed by photolithography and etching processes to form a plurality of slits SL. For example, the plurality of slits SL can be formed by a dry etching process using a first etching gas that selectively etches the patterned insulating layer 430.

[0122] Reference Figure 6D The second portion 434 of the patterned insulating layer 430 can be partially removed to form a plurality of second openings OP2 corresponding to a plurality of cell regions DA, and the second portion 424 of the covering insulating layer 420 can be partially removed to form a plurality of third openings OP3 corresponding to a plurality of cell regions DA.

[0123] In an embodiment, a second portion 434 of the patterned insulating layer 430 can be partially removed by photolithography and etching processes to form a plurality of second openings OP2, and a second portion 424 of the covering insulating layer 420 can be partially removed in the same process to form a plurality of third openings OP3. For example, a plurality of second openings OP2 and a plurality of third openings OP3 can be formed substantially simultaneously (e.g., concurrently) by a dry etching process using a second etching gas that etches both the patterned insulating layer 430 and the covering insulating layer 420.

[0124] Reference Figure 6E The substrate layer 410 can be partially removed to form a plurality of first openings OP1 corresponding to a plurality of unit regions DA.

[0125] In this embodiment, the substrate layer 410 can be partially removed by photolithography and etching processes to form a plurality of first openings OP1. For example, the plurality of first openings OP1 can be formed by a wet etching process using an etchant that selectively etches the substrate layer 410. For example, when the substrate layer 410 comprises silicon, the substrate layer 410 can be etched using tetramethylammonium hydroxide (“TMAH”). In such an embodiment, because the reinforcing pattern 450 is covered by the second portion 434 of the pattern insulating layer 430, damage to the reinforcing pattern 450 by TMAH can be prevented.

[0126] like Figure 3 As shown, a first portion 422 of the covering insulating layer 420 can be partially removed to form a plurality of fourth openings OP4 corresponding to a plurality of cell regions DA, thereby creating a mask 40.

[0127] In this embodiment, a plurality of fourth openings OP4 can be formed by partially removing the first portion 422 of the covering insulating layer 420 through photolithography and etching processes. For example, the plurality of fourth openings OP4 can be formed by a wet etching process using an etchant that selectively etches the covering insulating layer 420.

[0128] Figure 7 and Figure 8 This is a cross-sectional view showing a mask according to an embodiment.

[0129] Figure 7 It can correspond to Figure 3 ,and Figure 8 It can correspond to Figure 4 Except for omitting the alignment pattern and defining the alignment opening 440a therein, Figure 7 and Figure 8 The mask 40a shown can be similar to the one referenced above. Figures 2 to 4 The mask 40 is described. In the following text, the focus will be on... Figures 2 to 4The differences between mask 40 shown in the figure are described for mask 40a, and repeated descriptions between them may be omitted or simplified.

[0130] Reference Figure 7 and Figure 8 In an embodiment, a first portion 432 of the patterned insulating layer 430 may define an alignment opening 440a. The alignment opening 440a may be defined in a second peripheral region PA2 on a first surface 411 of the substrate layer 410. The alignment opening 440a may be used to align the mask 40a and the substrate S (see example...) Figure 1 Alignment openings 440a may penetrate (e.g., extend through) a first portion 432 of the patterned insulating layer 430 on the third-direction DR3.

[0131] The reinforcing pattern 450 may be disposed on the second surface 412 of the substrate layer 410 within the peripheral region PA. The reinforcing pattern 450 may be disposed within a portion of the peripheral region PA. The alignment opening 440a and the reinforcing pattern 450 may be positioned in opposite directions, and the substrate layer 410 and the overlay insulating layer 420 are located between the alignment opening 440a and the reinforcing pattern 450. In an embodiment, as... Figure 7 As shown, the reinforcement pattern 450 can overlap with the alignment opening 440a in the plan view.

[0132] Figure 9A and Figure 9B This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0133] Figure 9A and Figure 9B Each of them can correspond to Figure 7 Cross-sectional view. Figure 9A and Figure 9B The above reference can be shown. Figure 7 and Figure 8 An example of the method described for mask 40a. The following will focus on the method described above. Figures 6A to 6E as well as Figure 3 The differences between the methods for manufacturing mask 40 and the steps of the method for manufacturing mask 40a are described, and repeated descriptions between them may be omitted or simplified.

[0134] Reference Figure 9A A covering insulating layer 420 can be formed on the substrate layer 410. A reinforcing pattern 450 can be formed on the lower surface of the second portion 424 of the covering insulating layer 420. A patterned insulating layer 430 can be formed on the covering insulating layer 420 and the reinforcing pattern 450. The second portion 434 of the patterned insulating layer 430 can cover the reinforcing pattern 450.

[0135] Reference Figure 9B The first portion 432 of the patterned insulating layer 430 can be partially removed to form the patterned portion PTP and the aligned opening 440a.

[0136] In an embodiment, a first portion 432 of the patterned insulating layer 430 can be partially removed by photolithography and etching processes to form a plurality of slits SL and alignment openings 440a. The plurality of slits SL can be formed in each of a plurality of cell regions DA, and the alignment openings 440a can be formed in a second peripheral region PA2. For example, the plurality of slits SL and alignment openings 440a can be formed substantially simultaneously (e.g., concurrently) by a dry etching process using an etching gas that selectively etches the patterned insulating layer 430.

[0137] like Figure 7 As shown, a first opening OP1, a second opening OP2, a third opening OP3, and a fourth opening OP4 can be formed to manufacture a mask 40a.

[0138] Figure 10 and Figure 11 This is a cross-sectional view showing a mask according to an embodiment.

[0139] Figure 10 It can correspond to Figure 3 ,and Figure 11 It can correspond to Figure 4 Aside from omitting the alignment pattern and defining the alignment opening 440b, Figure 10 and Figure 11 The mask 40b shown can be similar to the one referenced above. Figures 2 to 4 The mask 40 is described. In the following text, the focus will be on... Figures 2 to 4 The differences between mask 40 shown in the figure are described for mask 40b, and repeated descriptions between them may be omitted or simplified.

[0140] Reference Figure 10 and Figure 11 In an embodiment, mask 40b may define alignment opening 440b. Alignment opening 440b may be defined within a second peripheral region PA2. Alignment opening 440b may be used to allow mask 40b and substrate S (see example) to... Figure 1 Alignment openings 440b may penetrate (e.g., extend through) the substrate layer 410, the cover insulation layer 420, the patterned insulation layer 430, and the reinforcing pattern 450 on the third-party DR3.

[0141] The substrate layer 410 may define a first through-hole 410H in the second peripheral region PA2. The first through-hole 410H may penetrate the substrate layer 410 in the third direction DR3.

[0142] The first portion 422 of the covering insulating layer 420 may define a second through-hole 422H in the second peripheral region PA2. The second through-hole 422H may penetrate the first portion 422 of the covering insulating layer 420 in the third direction DR3.

[0143] The second portion 424 of the covering insulation layer 420 may define a third through-hole 424H in the second peripheral region PA2. The third through-hole 424H may penetrate the second portion 424 of the covering insulation layer 420 in the third direction DR3.

[0144] The reinforcing pattern 450 can define a fourth through-hole 450H in the second peripheral region PA2. The fourth through-hole 450H can penetrate the reinforcing pattern 450 on the third-direction DR3.

[0145] The first portion 432 of the patterned insulating layer 430 may define a fifth through-hole 432H in the second peripheral region PA2. The fifth through-hole 432H may penetrate the first portion 432 of the patterned insulating layer 430 in the third direction DR3.

[0146] The second portion 434 of the patterned insulating layer 430 may define a sixth through-hole 434H in the second peripheral region PA2. The sixth through-hole 434H may penetrate the second portion 434 of the patterned insulating layer 430 in the third direction DR3.

[0147] like Figure 10 As shown, the first through-hole 410H, the second through-hole 422H, the third through-hole 424H, the fourth through-hole 450H, the fifth through-hole 432H, and the sixth through-hole 434H can be connected to each other (e.g., aligned with each other) on the third-direction DR3 to form an alignment opening 440b. The alignment opening 440b can penetrate the mask 40b on the third-direction DR3.

[0148] Figures 12A to 12E This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0149] Figures 12A to 12E Each of them can correspond to Figure 10 Cross-sectional view. Figures 12A to 12E The above reference can be shown. Figure 10 and Figure 11 The steps of the method for mask 40b are described below. The following will focus on the steps described above. Figures 6A to 6E as well as Figure 3 The methods for manufacturing mask 40 are described in contrast to those for manufacturing mask 40b, and repeated descriptions between them may be omitted or simplified.

[0150] Reference Figure 12AAn insulating cover layer 420 can be formed on the substrate layer 410. A reinforcing pattern 450 defining a fourth via 450H can be formed on the lower surface of the second portion 424 of the insulating cover layer 420. For example, after a thin film is deposited on the lower surface of the second portion 424 of the insulating cover layer 420, the thin film can be partially removed by photolithography and etching processes to form the reinforcing pattern 450 defining the fourth via 450H.

[0151] Reference Figure 12B A patterned insulating layer 430 can be formed on the covering insulating layer 420 and the reinforcing pattern 450. A second portion 434 of the patterned insulating layer 430 can cover the reinforcing pattern 450.

[0152] Reference Figure 12C The first portion 432 of the patterned insulating layer 430 can be partially removed to form the patterned portion PTP and the fifth through-hole 432H.

[0153] In an embodiment, the first portion 432 of the patterned insulating layer 430 can be partially removed by photolithography and etching processes to form a plurality of slits SL and a fifth via 432H. The plurality of slits SL can be formed in each of a plurality of cell regions DA, and the fifth via 432H can be formed in a second peripheral region PA2. For example, the plurality of slits SL and the fifth via 432H can be formed substantially simultaneously (e.g., concurrently) by a dry etching process using a first etching gas that selectively etches the patterned insulating layer 430.

[0154] Reference Figure 12D The second portion 434 of the patterned insulating layer 430 can be partially removed to form a plurality of second openings OP2 and a sixth through hole 434H, and the second portion 424 of the covering insulating layer 420 can be partially removed to form a plurality of third openings OP3 and third through holes 424H.

[0155] In an embodiment, the second portion 434 of the patterned insulating layer 430 can be partially removed by photolithography and etching processes to form a plurality of second openings OP2 and a sixth via 434H, and the second portion 424 of the covering insulating layer 420 can be partially removed in the same process to form a plurality of third openings OP3 and a third via 424H. The plurality of second openings OP2 and the plurality of third openings OP3 can be formed to correspond to a plurality of cell regions DA, and the third via 424H and the sixth via 434H can be formed in a second peripheral region PA2. For example, the plurality of second openings OP2, the plurality of third openings OP3, the third via 424H and the sixth via 434H can be formed substantially simultaneously (e.g., concurrently) by a dry etching process using a second etching gas that etches both the patterned insulating layer 430 and the covering insulating layer 420.

[0156] Reference Figure 12E The substrate layer 410 can be partially removed to form multiple first openings OP1 and first through holes 410H.

[0157] In an embodiment, the substrate layer 410 can be partially removed by photolithography and etching processes to form a plurality of first openings OP1 and first vias 410H. The plurality of first openings OP1 can be formed to correspond to a plurality of cell regions DA, and the first vias 410H can be formed in a second peripheral region PA2. For example, the plurality of first openings OP1 and first vias 410H can be formed substantially simultaneously (e.g., concurrently) by a wet etching process using an etchant that selectively etches the substrate layer 410.

[0158] like Figure 10 As shown, a portion 422 of the covering insulating layer 420 can be partially removed to form a plurality of fourth openings OP4 and a second through-hole 422H.

[0159] In an embodiment, a first portion 422 of the covering insulating layer 420 can be partially removed by photolithography and etching processes to form a plurality of fourth openings OP4 and a second via 422H. The plurality of fourth openings OP4 can each correspond to a plurality of cell regions DA formed, and the second via 422H can be formed in a second peripheral region PA2. For example, the plurality of fourth openings OP4 and the second via 422H can be formed substantially simultaneously (e.g., concurrently) by a wet etching process using an etchant that selectively etches the covering insulating layer 420.

[0160] Figure 13 and Figure 14 This is a cross-sectional view showing a mask according to an embodiment.

[0161] Figure 13 It can correspond to Figure 3 ,and Figure 14 It can correspond to Figure 4 In addition to the reinforcing pattern 450c being disposed on the first surface 411 of the substrate layer 410, Figure 13 and Figure 14 The mask 40c shown can be similar to the one referenced above. Figures 2 to 4 The mask 40 is described. In the following text, the focus will be on... Figures 2 to 4 The differences between mask 40 shown in the figure are described for mask 40c, and repeated descriptions between them may be omitted or simplified.

[0162] In an embodiment, the patterned insulating layer 430 may include a material having a coefficient of thermal expansion that is greater than that of the substrate layer 410.

[0163] Alignment pattern 440c can be formed on the first surface 411 of substrate layer 410 in the second peripheral region PA2. Alignment pattern 440c can be used to align mask 40c and substrate S (see example). Figure 1 Align them with each other.

[0164] The reinforcing pattern 450c may include a material having a coefficient of thermal expansion that is smaller than that of the substrate layer 410. For example, the reinforcing pattern 450c may include an Invar alloy (nickel-iron alloy) or an insulating material.

[0165] Tensile stress can be induced in the first portion 432 of the patterned insulating layer 430, and compressive stress can be induced in the reinforcing pattern 450c. The first portion 432 of the patterned insulating layer 430 and the reinforcing pattern 450c can be disposed on the first surface 411 of the substrate layer 410. For example, both the first portion 432 of the patterned insulating layer 430 and the reinforcing pattern 450c can be positioned above the substrate layer 410. Because the reinforcing pattern 450c, which induces compressive stress, is positioned in the same direction as the first portion 432 of the patterned insulating layer 430 relative to the substrate layer 410, the tensile stress induced in the first portion 432 of the patterned insulating layer 430 can be more effectively counteracted. Therefore, warpage of the mask 40c can be reduced, and precise patterning can be achieved.

[0166] In an embodiment, such as Figure 13 As shown, alignment pattern 440c and reinforcement pattern 450c can be disposed on the same layer and can comprise the same material. Alignment pattern 440c and reinforcement pattern 450c can be disposed between cover insulating layer 420 and pattern insulating layer 430. Alignment pattern 440c and reinforcement pattern 450c can be disposed between first portion 422 of cover insulating layer 420 and first portion 432 of pattern insulating layer 430. For example, alignment pattern 440c and reinforcement pattern 450c can be disposed on the upper surface of first portion 422 of cover insulating layer 420 and can be covered by first portion 432 of pattern insulating layer 430. The thickness of first portion 432 of pattern insulating layer 430 can be greater than each of the thickness of alignment pattern 440c and reinforcement pattern 450c.

[0167] The alignment pattern 440c and the reinforcement pattern 450c may be spaced apart from each other. The reinforcement pattern 450c may have various planar shapes to effectively counteract the tensile stress induced in the first portion 432 of the patterned insulating layer 430. In an embodiment, the reinforcement pattern 450c may be primarily disposed in the outer region of the mask 40c.

[0168] Figure 15A and Figure 15B This is a top view showing some components of the mask according to an embodiment. For example, Figure 15Aand Figure 15B Each of these can show a substrate layer 410, an alignment pattern 440c, and an enhancement pattern 450c.

[0169] In an embodiment, such as Figure 15A As shown, the reinforcing pattern 450c can be disposed in the second peripheral region PA2, and can have a shape surrounding the unit region DA in the plan view. The reinforcing pattern 450c can have a ring shape in the plan view.

[0170] In the plan view, alignment pattern 440c can be positioned inside reinforcement pattern 450c. For example, as Figure 13 and Figure 15A As shown, the reinforcing pattern 450c may define an opening OPc that overlaps with the alignment pattern 440c. In a plan view, the alignment pattern 440c may be disposed within the opening OPc in the reinforcing pattern 450c. The inner surface of the reinforcing pattern 450c defining the opening OPc may be spaced apart from the outer surface of the alignment pattern 440c. For example, in a plan view, the reinforcing pattern 450c may be spaced apart from the alignment pattern 440c and may surround the alignment pattern 440c.

[0171] In an embodiment, such as Figure 15B As shown in the plan view, the alignment pattern 440c may be disposed outside the reinforcing pattern 450c. In such an embodiment, the reinforcing pattern 450c may not have an opening.

[0172] Figure 15A and Figure 15B The shapes of each of the alignment pattern 440c and reinforcement pattern 450c shown are examples, and the embodiments are not limited thereto. In other embodiments, the shape and arrangement of each of the alignment pattern 440c and reinforcement pattern 450c can be varied.

[0173] Figure 16A and Figure 16B This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0174] Figure 16A and Figure 16B Each of them can correspond to Figure 13 Cross-sectional view. Figure 16A and Figure 16B The above reference can be shown. Figure 13 and Figure 14 The steps of the method for mask 40c are described below. The following will focus on the steps described above. Figures 6A to 6E as well as Figure 3 The methods for manufacturing mask 40 are described in contrast to those for manufacturing mask 40c, and repeated descriptions between them may be omitted or simplified.

[0175] Reference Figure 16A An insulating cover layer 420 can be formed on the substrate layer 410. An alignment pattern 440c and a reinforcement pattern 450c can be formed on the upper surface of the first portion 422 of the insulating cover layer 420. For example, after the thin film is deposited on the upper surface of the first portion 422 of the insulating cover layer 420, the thin film can be partially removed by photolithography and etching processes to form the alignment pattern 440c and the reinforcement pattern 450c substantially simultaneously (e.g., concurrently).

[0176] Reference Figure 16B A patterned insulating layer 430 can be formed on the covering insulating layer 420, the alignment pattern 440c, and the reinforcing pattern 450c. A first portion 432 of the patterned insulating layer 430 can cover the alignment pattern 440c and the reinforcing pattern 450c.

[0177] like Figure 13 As shown, a slit SL and a first opening OP1, a second opening OP2, a third opening OP3 and a fourth opening OP4 can be formed to create a mask 40c.

[0178] Figure 17 and Figure 18 This is a cross-sectional view showing a mask according to an embodiment.

[0179] Figure 17 It can correspond to Figure 3 ,and Figure 18 It can correspond to Figure 4 Except for omitting the reinforcing pattern 450 and not placing the insulating layer 420d below the substrate layer 410, Figure 17 and Figure 18 The mask 40d shown can be similar to the one referenced above. Figures 2 to 4 The mask 40 is described. In the following text, the focus will be on... Figures 2 to 4 The differences between mask 40 shown in the figure are described for mask 40d, and repeated descriptions between them may be omitted or simplified.

[0180] A cover insulating layer 420d may be disposed between the substrate layer 410 and the patterned insulating layer 430. The cover insulating layer 420d may cover a portion of the substrate layer 410. For example, as... Figure 17 and Figure 18 As shown, the insulating layer 420d can cover the first surface 411 and the outer surface 413 of the substrate layer 410.

[0181] In an embodiment, the covering insulating layer 420d may include a first portion 422 disposed on a first surface 411 of the substrate layer 410 and a third portion 426 disposed on an outer surface 413 of the substrate layer 410. The covering insulating layer 420d may not cover at least a portion of the second surface 412 of the substrate layer 410. The covering insulating layer 420d may not cover most of the second surface 412 of the substrate layer 410.

[0182] In the first peripheral region PA1, although the covering insulating layer 420d can be disposed on the first surface 411 of the substrate layer 410, the covering insulating layer 420d may not be disposed on the second surface 412 of the substrate layer 410. In the first peripheral region PA1, the first surface 411 of the substrate layer 410 can contact the first portion 422 of the covering insulating layer 420d, and the second surface 412 of the substrate layer 410 can contact the second portion 434 of the patterned insulating layer 430.

[0183] The patterned insulating layer 430 may cover at least a portion of the covering insulating layer 420d. Furthermore, the patterned insulating layer 430 may further cover at least a portion of the second surface 412 of the substrate layer 410 that is not covered by the covering insulating layer 420d.

[0184] In an embodiment, the patterned insulating layer 430 may include a first portion 432 disposed on a first surface 411 of the substrate layer 410, a second portion 434 disposed on a second surface 412 of the substrate layer 410, and a third portion 436 disposed on an outer surface 413 of the substrate layer 410.

[0185] The first portion 432 of the patterned insulating layer 430 may include a plurality of patterned portions PTP corresponding to a plurality of unit regions DA. The first portion 422 of the covering insulating layer 420d may be disposed between the substrate layer 410 and the first portion 432 of the patterned insulating layer 430.

[0186] The second portion 434 of the patterned insulating layer 430 may cover at least a portion of the second surface 412 of the substrate layer 410 that is not covered by the insulating layer 420d.

[0187] No other layers may be provided below the patterned PTP portion. The substrate layer 410 may define a plurality of first openings OP1 corresponding to a plurality of cell regions DA. The second portion 434 of the patterned insulating layer 430 may define a plurality of second openings OP2 corresponding to a plurality of cell regions DA. The first portion 422 of the covering insulating layer 420d may define a plurality of third openings OP3 corresponding to a plurality of cell regions DA.

[0188] In an embodiment, in a plan view, the size of each of the plurality of second openings OP2 can be larger than the size of the corresponding one of the plurality of first openings OP1. For example... Figure 17 and Figure 18 As shown, the second portion 434 of the patterned insulating layer 430 may not cover a portion of the second surface 412 of the substrate layer 410, and may expose said portion of the second surface 412 of the substrate layer 410.

[0189] Each of the overlay insulating layer 420d and the patterned insulating layer 430 may comprise a different material than the substrate layer 410. In an embodiment, the overlay insulating layer 420d may comprise a material having a smaller coefficient of thermal expansion than the substrate layer 410, and the patterned insulating layer 430 may comprise a material having a larger coefficient of thermal expansion than the substrate layer 410. For example, the substrate layer 410 may comprise silicon, the overlay insulating layer 420d may comprise silicon oxide, and the patterned insulating layer 430 may comprise silicon nitride.

[0190] Compressive stress can be induced in the overlay insulating layer 420d, and tensile stress can be induced in the patterned insulating layer 430. Because the overlay insulating layer 420d is disposed only on the first surface 411 of the substrate layer 410 and not on the second surface 412 of the substrate layer 410, the tensile stress induced in the first portion 432 of the patterned insulating layer 430 can be effectively offset by the compressive stress induced in the overlay insulating layer 420d. Therefore, warpage of the mask 40d can be reduced, and precise patterning can be achieved.

[0191] Figures 19A to 19E This is a cross-sectional view illustrating the steps of a method for manufacturing a mask according to an embodiment.

[0192] Figures 19A to 19E Each of them can correspond to Figure 17 Cross-sectional view. Figures 19A to 19E The above reference can be shown. Figure 17 and Figure 18 The steps of the mask 40d method are described below. The following will focus on the steps described above. Figures 6A to 6E as well as Figure 3 The methods for manufacturing mask 40 are described in the way that the steps of the methods for manufacturing mask 40d differ, and repeated descriptions between them may be omitted or simplified.

[0193] Reference Figure 19AAn insulating layer 420d' can be formed on the substrate layer 410. The insulating layer 420d' can be formed to cover the entire substrate layer 410. For example, the insulating layer 420d' can be formed to cover the first surface 411, the second surface 412, and the outer surface 413 of the substrate layer 410. In an embodiment, the insulating layer 420d' can be formed by oxidizing the substrate layer 410.

[0194] Reference Figure 19B This allows for partial removal of the insulation layer 420d' (see [reference]). Figure 19A The insulating layer 420d and multiple insulating patterns 420p are formed. The insulating layer 420d' can be partially removed from the second surface 412 of the substrate layer 410 to form openings OPd corresponding to the peripheral region PA. For example, the openings OPd can have a grid shape in a plan view. Therefore, multiple insulating patterns 420p spaced apart from each other can be formed on the second surface 412 of the substrate layer 410. The insulating layer 420d can cover the first surface 411 and the outer surface 413 of the substrate layer 410.

[0195] Multiple insulating patterns 420p can overlap with multiple unit regions DA, respectively. In an embodiment, the width of the opening OPd can be smaller than the width of the first peripheral region PA1. For example, in a plan view, the size of each of the multiple insulating patterns 420p can be larger than the size of the corresponding one of the multiple unit regions DA, and each of the multiple insulating patterns 420p can further overlap with a portion of the adjacent peripheral region PA.

[0196] Reference Figure 19C An alignment pattern 440 may be formed on the upper surface of the first portion 422 of the covering insulating layer 420d, and a patterned insulating layer 430 may be formed on the covering insulating layer 420d, the insulating pattern 420p, and the alignment pattern 440. The first portion 432 of the patterned insulating layer 430 may cover the alignment pattern 440. The second portion 434 of the patterned insulating layer 430 may cover the second surface 412 of the substrate layer 410 exposed by the insulating pattern 420p and the opening OPd.

[0197] Further reference Figure 19D The first portion 432 of the patterned insulating layer 430 can be partially removed to form a slit SL.

[0198] The second portion 434 of the patterned insulating layer 430 can be partially removed to form the initial second opening OP2' and the insulating pattern 420p can be removed (see...). Figure 19C ).

[0199] In an embodiment, the second portion 434 of the patterned insulating layer 430 can be partially removed by photolithography and etching processes to form a preliminary second opening OP2', and the insulating pattern 420p can be removed in the same process. In an embodiment, as... Figure 19D As shown, each of the plurality of insulating patterns 420p may not be completely removed (e.g., may be only partially removed), and a portion 420p' of the insulating pattern 420p overlapping with the peripheral region PA of each of the plurality of insulating patterns 420p (hereinafter also referred to as the residual insulating pattern 420p') may be retained, thereby forming each of the plurality of residual insulating patterns 420p' having an annular shape in the plan view.

[0200] Reference Figure 19E The substrate layer 410 can be partially removed to form a plurality of first openings OP1 corresponding to a plurality of unit regions DA.

[0201] like Figure 17 As shown, the first portion 422 covering the insulating layer 420d can be partially removed to form a plurality of third openings OP3. At this time, the remaining insulating pattern 420p' on the second surface 412 of the substrate layer 410 and the portion of the second portion 434 of the patterned insulating layer 430 positioned below the remaining insulating pattern 420p' can be removed together.

[0202] Figure 20 and Figure 21 This is a cross-sectional view showing a mask according to an embodiment.

[0203] Figure 20 It can correspond to Figure 3 ,and Figure 21 It can correspond to Figure 4 In addition to the reinforcing pattern 450e being disposed on the first surface 411 of the substrate layer 410 and the covering insulating layer 420 and the patterned insulating layer 430 being replaced by the patterned insulating layer 420e, Figure 20 and Figure 21 The mask 40e shown can be similar to the one referenced above. Figures 2 to 4 The mask 40 is described. In the following text, the focus will be on... Figures 2 to 4 The differences between mask 40 shown in the figure are described for mask 40e, and repeated descriptions between them may be omitted or simplified.

[0204] In an embodiment, the patterned insulating layer 420e may cover at least a portion of the substrate layer 410. For example, as... Figure 20 and Figure 21 As shown, the patterned insulating layer 420e can cover the first surface 411, the second surface 412 and the outer surface 413 of the substrate layer 410.

[0205] In an embodiment, the patterned insulating layer 420e may include a first portion 422e disposed on a first surface 411 of the substrate layer 410, a second portion 424e disposed on a second surface 412 of the substrate layer 410, and a third portion 426e disposed on an outer surface 413 of the substrate layer 410. The first portion 422e and the second portion 424e of the patterned insulating layer 420e may be positioned in opposite directions to each other, and the substrate layer 410 is located between the first portion 422e and the second portion 424e of the patterned insulating layer 420e. For example, the first portion 422e, the second portion 424e, and the third portion 426e of the patterned insulating layer 420e may be connected to each other.

[0206] The first portion 422e of the patterned insulating layer 420e can contact the first surface 411 of the substrate layer 410. The second portion 424e of the patterned insulating layer 420e can contact the second surface 412 of the substrate layer 410. The third portion 426e of the patterned insulating layer 420e can contact the outer surface 413 of the substrate layer 410.

[0207] The patterned insulating layer 420e and the substrate layer 410 may comprise different materials. In an embodiment, the patterned insulating layer 420e may comprise a material having a smaller coefficient of thermal expansion than the substrate layer 410. For example, the patterned insulating layer 420e may comprise silicon oxide, but this is an example and the embodiment is not limited thereto.

[0208] The patterned insulating layer 420e may include a plurality of patterned portions PTPe, each patterned portion PTPe corresponding to a plurality of cell regions DA on the first surface 411 of the substrate layer 410. A first portion 422e of the patterned insulating layer 420e may include a plurality of patterned portions PTPe. Each of the plurality of patterned portions PTPe may define a plurality of slits SL. Each of the plurality of slits SL may penetrate (e.g., extend through) the first portion 422e of the patterned insulating layer 420e in a third-direction DR3.

[0209] like Figure 20 and Figure 21 As shown, no other layer may be disposed beneath each of the plurality of patterned portions PTPe. The substrate layer 410 may define a plurality of first openings OP1 corresponding to a plurality of cell regions DA. The second portion 424e of the patterned insulating layer 420e may define a plurality of second openings OP2 corresponding to a plurality of cell regions DA.

[0210] Although the first portion 422e of the patterned insulating layer 420e includes a plurality of patterned portions PTPe corresponding to a plurality of cell regions DA respectively, the second portion 424e of the patterned insulating layer 420e defines a plurality of second openings OP2 corresponding to a plurality of cell regions DA respectively, such that in a plan view, the size of the second portion 424e of the patterned insulating layer 420e can be smaller than the size of the first portion 422e of the patterned insulating layer 420e.

[0211] Alignment pattern 440e can be formed on the first surface 411 of substrate layer 410 in the second peripheral region PA2. Alignment pattern 440e can be used to align mask 40e and substrate S (see example). Figure 1 Align them with each other.

[0212] The reinforcing pattern 450e may include a material having a coefficient of thermal expansion greater than that of the substrate layer 410. For example, the reinforcing pattern 450e may include metals such as chromium, aluminum, tungsten, or silver, or alloys thereof.

[0213] Compressive stress can be induced in the first portion 422e of the patterned insulating layer 420e, and tensile stress can be induced in the reinforcing pattern 450e. The first portion 422e of the patterned insulating layer 420e and the reinforcing pattern 450e can be disposed on the first surface 411 of the substrate layer 410. For example, both the first portion 422e of the patterned insulating layer 420e and the reinforcing pattern 450e can be positioned above the substrate layer 410. Because the reinforcing pattern 450e, which induces tensile stress, is positioned in the same direction as the first portion 422e of the patterned insulating layer 420e relative to the substrate layer 410, the compressive stress induced in the first portion 422e of the patterned insulating layer 420e can be more effectively counteracted. Therefore, warpage of the mask 40e can be reduced, and precise patterning can be achieved.

[0214] In an embodiment, such as Figure 20 As shown, alignment pattern 440e and reinforcement pattern 450e can be disposed on the same layer and can comprise the same material. Alignment pattern 440e and reinforcement pattern 450e can be disposed on the upper surface of the first portion 422e of patterned insulating layer 420e.

[0215] Alignment pattern 440e and reinforcement pattern 450e may be spaced apart from each other. Reinforcement pattern 450e may have various planar shapes (see, for example) Figure 15A and Figure 15B The shape of the reinforcing pattern 450c is used to effectively counteract the tensile stress caused in the first portion 422e of the patterned insulating layer 420e.

[0216] Figure 22 This is a cross-sectional view showing a display device according to an embodiment.

[0217] Figure 22 The display device 100 shown can be manufactured using any of the above-described masks 40, 40a, 40b, 40c, 40d and 40e.

[0218] Reference Figure 22 In an embodiment, the display device 100 may include a substrate 110, a buffer layer 120, a plurality of pixels, insulating layers 132, 134, 136 and 138, a pixel defining layer 140, and an encapsulation layer 150. Each of the plurality of pixels may include a transistor TR, a capacitor CAP, and a light-emitting element LED.

[0219] The substrate 110 may be an insulating substrate comprising transparent or non-transparent materials or formed of transparent or non-transparent materials.

[0220] A buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 can prevent or reduce the penetration of impurities such as oxygen or moisture through the substrate 110 into the upper portion of the substrate 110. The buffer layer 120 may include an inorganic material. In an embodiment, for example, the buffer layer 120 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO2) x C y ), silicon carbide (SiC) x N y ), aluminum oxide (AlO) x ), aluminum nitride (AlN) x ), tantalum oxide (TaO) x ), hafnium oxide (HfO) x Zirconium oxide (ZrO) x ) or titanium dioxide (TiO) x These materials can be used alone or in combination. The buffer layer 120 can have a single-layer structure or a multi-layer structure including multiple insulating layers.

[0221] Transistor TR and capacitor CAP can be disposed on buffer layer 120. Transistor TR may include active layer AL, gate electrode GE, source electrode SE, and drain electrode DE.

[0222] An active layer AL can be disposed on the buffer layer 120. The active layer AL can include oxide semiconductors, silicon semiconductors, or organic semiconductors, etc. In embodiments, for example, the oxide semiconductor can include at least one oxide selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor can include amorphous silicon or polycrystalline silicon, etc. The active layer AL can have a source region, a drain region, and a channel region located between the source region and the drain region.

[0223] The first insulating layer 132 may be disposed on the active layer AL. The first insulating layer 132 may cover the active layer AL on the buffer layer 120. The first insulating layer 132 may include an inorganic insulating material.

[0224] The gate electrode GE can be disposed on the first insulating layer 132. The gate electrode GE can overlap with the channel region of the active layer AL. The gate electrode GE can include a conductive material, such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive material. In embodiments, for example, the gate electrode GE can include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum-containing alloys, silver-containing alloys, copper-containing alloys, molybdenum-containing alloys, and aluminum nitride (AlN). x ), Tungsten nitride (WN) x Titanium nitride (TiN) x ), Chromium nitride (CrN) x ), Tantalum nitride (TaN) x ), SrRuO x ), zinc oxide (ZnO) x Indium tin oxide (ITO), tin oxide (SnO) x Indium oxide (InO) x Gallium oxide (GaO) x Materials such as indium zinc oxide (IZO) or other similar materials can be used alone or in combination. The gate electrode (GE) can have a single-layer structure or a multilayer structure comprising multiple conductive layers.

[0225] The second insulating layer 134 may be disposed on the gate electrode GE. The second insulating layer 134 may cover the gate electrode GE on the first insulating layer 132. The second insulating layer 134 may include an inorganic insulating material.

[0226] The capacitor electrode CPE can be disposed on the second insulating layer 134. The capacitor electrode CPE can overlap with the gate electrode GE. The gate electrode GE, the second insulating layer 134, and the capacitor electrode CPE can form a capacitor CAP.

[0227] The third insulating layer 136 may be disposed on the capacitor electrode CPE. The third insulating layer 136 may cover the capacitor electrode CPE on the second insulating layer 134. The third insulating layer 136 may include an inorganic insulating material.

[0228] The source electrode SE and drain electrode DE can be disposed on the third insulating layer 136. The source electrode SE and drain electrode DE can be connected to the source region and drain region of the semiconductor layer ACT, respectively. Each of the source electrode SE and drain electrode DE can include a conductive material.

[0229] A fourth insulating layer 138 may be disposed on the source electrode SE and the drain electrode DE. The fourth insulating layer 138 may include an organic insulating material. In embodiments, for example, the fourth insulating layer 138 may include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, or epoxy resin, etc. These materials may be used alone or in combination.

[0230] The pixel electrode PE can be disposed on the fourth insulating layer 138. The pixel electrode PE may include a conductive material. The pixel electrode PE can be connected to the drain electrode DE through contact holes (e.g., contact openings) defined or formed in the fourth insulating layer 138. Furthermore, the pixel electrode PE can be electrically connected to the transistor TR.

[0231] A pixel defining layer 140 may be disposed on a pixel electrode PE. The pixel defining layer 140 may cover the peripheral portion of the pixel electrode PE and may define a pixel opening exposing the central portion of the pixel electrode PE. The pixel defining layer 140 may include an organic insulating material.

[0232] The emitting layer EL can be disposed on the pixel electrode PE. The emitting layer EL can be disposed in a pixel opening in the pixel defining layer 140. In an embodiment, the emitting layer EL may include an organic light-emitting material. The emitting layer EL can be formed by deposition using any of the masks 40, 40a, 40b, 40c, 40d, and 40e described above.

[0233] In the embodiments, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. Examples of low-molecular-weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine, or tris(8-hydroxyquinoline)aluminum, etc. Examples of high-molecular-weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylene oxide, or polyfluorene, etc. These materials may be used alone or in combination.

[0234] The common electrode CE can be disposed on the emitter layer EL. The common electrode CE can also be disposed on the pixel defining layer 140. The common electrode CE may include a conductive material. The pixel electrode PE, the emitter layer EL, and the common electrode CE can form a light-emitting element (LED).

[0235] The encapsulation layer 150 may be disposed on the common electrode CE. The encapsulation layer 150 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer 150 may include a first inorganic encapsulation layer 152 disposed on the common electrode CE, an organic encapsulation layer 154 disposed on the first inorganic encapsulation layer 152, and a second inorganic encapsulation layer 156 disposed on the organic encapsulation layer 154. Furthermore, various functional layers, such as a touch sensing layer, a color filter layer, or a light collecting layer, may be additionally disposed on the encapsulation layer 150.

[0236] Figure 23 This is a block diagram describing an electronic device according to an embodiment.

[0237] Reference Figure 23 The electronic device 1000 may include a display module 1100, a processor 1200, a memory 1300, and a power module 1400.

[0238] The display device according to the embodiment (e.g., Figure 22 The display device 100 shown can be applied to various electronic devices 1000. The electronic device 1000 may include the aforementioned display device and may also include modules or devices with additional functions other than the display device.

[0239] The processor 1200 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0240] The memory 1300 can store data information required for the operation of the processor 1200 or the display module 1100. When the processor 1200 executes the application program stored in the memory 1300, image data signals and / or input control signals can be transmitted to the display module 1100, and the display module 1100 can process the received signals and output image information through the display screen. In other words, the processor 1200 can provide image data signals and / or input control signals to the display device to control the display device.

[0241] The power module 1400 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 1000.

[0242] At least one of the components of the electronic device 1000 described above may be included in the display device according to the above embodiment. Furthermore, some modules that are functionally included in a single module may be included in the display device, while other components may be provided separately from the display device. For example, the display device may include a display module 1100, and the processor 1200, memory 1300, and power module 1400 may be provided as other devices within the electronic device 1000 instead of the display device.

[0243] Figure 24 This is a schematic diagram illustrating an electronic device according to various embodiments.

[0244] Reference Figure 24 Various electronic devices 1000 that can be used with the display device according to the embodiment (see [reference]) Figure 23 This can include not only image display electronic devices such as smartphones 1000_1a, tablet PCs 1000_1b, laptop computers 1000_1c, televisions (TVs) 1000_1d, and desktop monitors 1000_1e, but also display modules 1100 including smart glasses 1000_2a, head-mounted displays 1000_2b, and smartwatches 1000_2c (see also...). Figure 23 Wearable electronic devices or vehicle electronic devices 1000_3, such as car dashboards, central instrument panels, central information displays (“CID”) mounted on the dashboard, and rearview mirror displays, including display modules 1100.

[0245] The foregoing is illustrative of the embodiments and should not be construed as limiting the embodiments. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the described embodiments without substantially departing from the scope and spirit of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims and their equivalents.

Claims

1. A mask for deposition, wherein, The mask used for deposition includes: Multiple unit regions spaced apart from each other and a peripheral region surrounding the multiple unit regions in the plan view; A substrate layer having a first surface and a second surface facing away from the first surface, the substrate layer defining a plurality of first openings corresponding to the plurality of unit regions respectively; A patterned insulating layer comprising a material having a coefficient of thermal expansion greater than that of the substrate layer, the patterned insulating layer having a plurality of patterned portions corresponding to the plurality of unit regions on the first surface of the substrate layer, each of the plurality of patterned portions defining a plurality of slits; and The reinforcing pattern, in the peripheral region, comprises a material having a coefficient of thermal expansion different from that of the substrate layer, and the reinforcing pattern is covered by the patterned insulating layer.

2. The mask for deposition according to claim 1, wherein, The coefficient of thermal expansion of the reinforcing pattern is greater than the coefficient of thermal expansion of the substrate layer, and The reinforcing pattern is located on the second surface of the substrate layer.

3. The mask for deposition according to claim 2, wherein, The patterned insulating layer has: The first part is on the first surface of the substrate layer and includes the plurality of patterned portions; and The second part defines a plurality of second openings on the second surface of the substrate layer, respectively corresponding to the plurality of unit regions, and The reinforcing pattern is covered by the second portion of the patterned insulating layer.

4. The mask for deposition according to claim 3, wherein, The mask for deposition further includes: an alignment pattern, on the first surface of the substrate layer in the peripheral region and covered by the first portion of the patterned insulating layer.

5. The mask for deposition according to claim 4, wherein, The enhancement pattern is spaced apart from the alignment pattern, and the substrate layer is located between the enhancement pattern and the alignment pattern.

6. The mask for deposition according to claim 4, wherein, In the plan view, the size of the enhancement pattern is larger than the size of the alignment pattern.

7. The mask for deposition according to claim 3, wherein, The first portion of the patterned insulating layer defines an alignment opening positioned in the peripheral region.

8. The mask for deposition according to claim 7, wherein, The enhancement pattern overlaps with the alignment opening in the plan view.

9. The mask for deposition according to claim 3, wherein, The peripheral region has an alignment opening that extends through the substrate layer, the patterned insulating layer, and the reinforcing pattern in a direction perpendicular to the first surface of the substrate layer.

10. The mask for deposition according to claim 1, wherein, The coefficient of thermal expansion of the reinforcing pattern is less than the coefficient of thermal expansion of the substrate layer, and The reinforcement pattern is located on the first surface of the substrate layer.

11. The mask for deposition according to claim 10, wherein, The patterned insulating layer has: The first part is on the first surface of the substrate layer and includes the plurality of patterned portions; and The second part defines a plurality of second openings on the second surface of the substrate layer, respectively corresponding to the plurality of unit regions, and The reinforcing pattern is covered by the first portion of the patterned insulating layer.

12. The mask for deposition according to claim 11, wherein, The mask for deposition further includes: an alignment pattern, on the first surface of the substrate layer in the peripheral region and covered by the first portion of the patterned insulating layer. The alignment pattern and the enhancement pattern both consist of the same material.

13. The mask for deposition according to claim 12, wherein, The enhancement pattern and the alignment pattern are spaced apart from each other.

14. The mask for deposition according to claim 13, wherein, The enhancement pattern surrounds the alignment pattern in the plan view.

15. The mask for deposition according to claim 1, wherein, The mask for deposition further includes: a covering insulating layer, located in the peripheral region between the substrate layer and the patterned insulating layer. The reinforcing pattern is located between the covering insulating layer and the patterned insulating layer.

16. The mask for deposition according to claim 15, wherein, The substrate layer comprises silicon, the overlay insulating layer comprises silicon oxide, the patterned insulating layer comprises silicon nitride, and the reinforcing pattern comprises metal or alloy.

17. The mask for deposition according to claim 1, wherein, The enhancement pattern is adjacent to the edge of the substrate layer.

18. A mask for deposition, wherein, The mask used for deposition includes: Multiple unit regions spaced apart from each other and a peripheral region surrounding the multiple unit regions in the plan view; A substrate layer having a first surface and a second surface facing away from the first surface, the substrate layer defining a plurality of first openings corresponding to the plurality of unit regions respectively; The patterned insulating layer comprises a material having a coefficient of thermal expansion greater than that of the substrate layer, the patterned insulating layer having: A first portion, on the first surface of the substrate layer, includes a plurality of patterned portions corresponding to the plurality of unit regions, each of the plurality of patterned portions defining a plurality of slits; and The second portion, on the second surface of the substrate layer, defines a plurality of second openings corresponding to the plurality of unit regions; and A covering insulating layer, comprising a material having a coefficient of thermal expansion smaller than that of the substrate layer, is located between the substrate layer and the first portion of the patterned insulating layer, and defines a plurality of third openings corresponding to the plurality of unit regions. The first surface of the substrate layer contacts the covering insulating layer, and the second surface of the substrate layer contacts the second portion of the patterned insulating layer.

19. The mask for deposition according to claim 18, wherein, In the plan view, the size of one of the plurality of second openings is larger than the size of the corresponding one of the plurality of first openings.

20. An electronic device, wherein, The electronic device includes: A display device, comprising an emitting layer deposited using a mask for deposition; and The processor is configured to provide image data signals and input control signals to the display device to control the display device. The mask used for deposition includes: Multiple unit regions spaced apart from each other and a peripheral region surrounding the multiple unit regions in the plan view; A substrate layer having a first surface and a second surface facing away from the first surface, the substrate layer defining a plurality of first openings corresponding to the plurality of unit regions respectively; A patterned insulating layer comprising a material having a coefficient of thermal expansion greater than that of the substrate layer, the patterned insulating layer comprising, on the first surface of the substrate layer, a plurality of patterned portions corresponding to the plurality of unit regions, each of the plurality of patterned portions defining a plurality of slits; and The reinforcing pattern, in the peripheral region, comprises a material having a coefficient of thermal expansion different from that of the substrate layer, and the reinforcing pattern is covered by the patterned insulating layer.

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