Signal transmission unit insertion method based on double-sided transistor
By inserting a signal transmission unit (STC) into a double-sided transistor chip design, constructing an optimization model, and performing a validation operation, the problem of optimizing the double-sided net length was solved, improving the chip's performance and the accuracy of the PPA model.
Patent Information
- Application Number
- CN202511457416.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-01-13
AI Technical Summary
Existing technologies cannot effectively optimize the line length of the net in chip design based on double-sided transistors, leading to a decrease in chip performance. Furthermore, existing methods are not precise in net segmentation for double-sided transistors, affecting the accuracy of chip performance, power consumption, and area (PPA) models.
A signal transmission unit (STC) insertion method is constructed. By inserting STCs through an optimized model, the bus length of the double-sided net is reduced. The optimized model is assigned using STCs and a legalization operation is performed to ensure the usability of the design results and the optimization of the line length.
It effectively reduces the line length of double-sided nets, improves the accuracy of chip performance, power consumption, and area (PPA) models, and optimizes the bus length of chip design.
Smart Images
Figure CN121328458A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip design technology, and relates to double-sided transistor wiring technology, and more particularly to a method for inserting a signal transmission unit based on a double-sided transistor. Background Technology
[0002] In chip design based on double-sided transistors, double-sided nets still exist after the standard cell selection algorithm. These nets are relatively long, leading to a decrease in the chip's power-to-average performance (PPA). Signal transmission units need to be inserted to further improve the PPA. Currently, there is no algorithm for inserting signal transmission units based on double-sided transistors. This method, based on novel double-sided transistor technology, utilizes signal transmission units to further reduce the line length in double-sided transistor-based designs.
[0003] Existing work, based on single-sided transistors and nTSV processes, employs net partitioning algorithms to maximize the utilization of nets to back-side metal interconnects. It designs net partitioning algorithms based on the pin distribution of timing-critical nets, inserting nTSVs at the partitioning locations to assign nets to the front or back side. However, existing technologies only support standard cells with single-sided pins, where all nets are initially located on the same side of the chip. For standard cells with double-sided pins based on double-sided transistors, the pins of the nets to be processed are distributed on both sides of the chip, and current methods do not accurately estimate the cost of different net partitioning methods. This makes current optimization methods unsuitable for chip designs based on double-sided transistors. Furthermore, existing technologies do not balance the design costs of nTSV resistors and capacitors with the benefits of net length optimization, resulting in low accuracy in modeling the final power-to-average (PPA). Summary of the Invention
[0004] To overcome the shortcomings of the prior art, this invention provides a signal transmission unit insertion method based on double-sided transistors. For back-end designs of circuits based on double-sided transistors, where double-sided nets still appear after the standard cell selection algorithm, the method further reduces the bus length of the double-sided nets and improves chip performance by inserting signal transmission units (STCs).
[0005] For convenience, the full Chinese and English names of some technical terms involved in this invention are as follows: FFET: Flip Field Effect Transistor STC: Signal Transfer Cell PPA: Performance, Power, and Area HPWL: A half-perimeter wirelength model. FS: Describes the front side of a double-sided chip. BS: Describes the backside of a double-sided chip. nTSV: Nano Through Silicon Via The core of this invention is the modeling of a novel optimization problem. The objective of the optimization model is to minimize the double-sided bus length after inserting STCs. The STCs are considered as equivalent wire lengths based on their capacitance and resistance values and are factored into the objective function. The solution to the optimization model must satisfy constraints on the total number of STCs, the number of STCs used per net, and the validity of the STCs. The solution process includes scheduling planning for STC usage (determining the STC usage of double-sided nets by constructing an approximation problem) and STC insertion and validity operations (minimizing wire length as much as possible during the validity process). This invention can be applied to the back-end design of circuits based on double-sided transistors, and can be used after standard cell selection algorithms to further reduce the bus length of double-sided designs and improve chip performance.
[0006] Taking a standard cell based on a double-sided transistor as an example, after the standard cell selection algorithm, its input pins will still be distributed on the front and back sides of the chip according to the optimization results. This will result in the line length of some nets not being fully optimized. This invention utilizes STC insertion to further optimize the line length of double-sided nets. This invention first models a new optimization problem. In the step of solving the objective function, this invention first constructs an approximation problem of the original problem based on the properties of double-sided net length, and then solves for the use of STC for double-sided nets. Then, this invention uses STC insertion and legalization operations to obtain the final STC insertion optimization result.
[0007] The technical solution provided by this invention is: A method for inserting a signal transmission unit based on a double-sided transistor includes the following steps: 1) Construct an optimization model for the allocation of signal transmission unit (STC). The goal of the optimization model is to optimize the length of the double-sided bus after the insertion of STC (minimize the length of the double-sided bus after the insertion of STC). The capacitance and resistance values of STC are regarded as equivalent line lengths and included in the objective function of the optimization model. The objective function of the constructed signal transmission unit (STC) allocation optimization model is expressed as: Among them, c e C is the number of STCs used per net e; tot This is the upper limit of the total number of STCs; Ce This is the upper limit of the number of STCs used for each net e, corresponding to the number of pins that need to be flipped. A collection of double-sided wire meshes; A set of integers, representing It is an integer; DWL(e) represents the front and back line lengths of each net after standard cell selection; DWL(e') represents the front and back line lengths of each net after STC insertion; η represents the equivalent line length of STC; This represents the total equivalent length of the STC used for each net.
[0008] 2) Solve the STC allocation optimization model, including: Scheduling and planning of STC usage: Based on the properties of double-sided wire mesh length, the usage of STC for double-sided wire mesh is determined by constructing an approximate problem; The results obtained by solving the optimization model satisfy the constraints on the total number of STCs and the number of STCs used in each wire mesh.
[0009] The process of solving the STC allocation optimization model includes: Construct line length relative optimization degree variable θ e ,satisfy: The lower bound of DWL(e') is WL(e); WL(e) is the line length of a net based on half the perimeter, assuming that all driven pins of a net are on the same side of the chip. The optimization model for STC (Signal Transmission Unit) allocation is transformed into the following linear programming optimization model: θ e Set the number of STCs allocated to nets with a value greater than 0 to 0; set the remaining θ... e Sort the wires and assign C to each wire e in order. e One STC, until the total number of STCs C is violated. tot The limitations are thus determined, resulting in the STC allocation for each net.
[0010] 3) Through STC insertion and legalization operations, the line length is minimized as much as possible during the legalization process to obtain the final STC insertion optimization result. Specifically, firstly, the STC and pin are connected to construct a new subnet, and the initial position of each STC is set to the position of the connected pin; then, through the legalization algorithm, empty spaces not occupied by other standard cells are searched around the initial position, and the total double-sided line length is reduced to finally determine the legal position of the STC.
[0011] The above steps enable the insertion of a signal transmission unit based on a double-sided transistor.
[0012] Compared with the prior art, the beneficial effects of the present invention are: This invention provides a signal transmission unit (STC) insertion method based on double-sided transistors. For chip designs based on double-sided transistors, a new STC allocation optimization model is constructed using the STC insertion algorithm. An approximate problem for solving the STC allocation problem is also developed, and STC insertion and validation operations are designed. This method can be applied to the back-end design of circuits based on double-sided transistors and used after the standard cell selection algorithm to further reduce the bus length of double-sided designs and improve chip performance. The technical advantages of this invention include: This invention further reduces the line length of double-sided nets by inserting STCs. Furthermore, by solving the STC allocation problem, it considers the usage of STCs while reducing line length, thus improving the final PPA of the chip.
[0013] This invention uses the STC legalization algorithm to ensure the usability of the design results, and takes into account the impact on the length of the double-sided net during the legalization process, further optimizing the final net length.
[0014] This invention can be applied to the back-end design of circuits based on double-sided transistors. It can be used after the standard cell selection algorithm to further reduce the bus length of double-sided designs and improve chip performance. Attached Figure Description
[0015] Figure 1 This is a flowchart of the method of the present invention.
[0016] Figure 2 This is a schematic diagram illustrating the optimization of line length using STC insertion in a specific embodiment of the present invention; Sub-figure (1) shows that "without an STC inserted, the double-sided net is longer"; sub-figure (2) shows that "with an STC inserted, the net is shorter". In sub-figure (2), an STC is inserted, which reduces the net length while maintaining the original interconnection of the pins on the net. Detailed Implementation
[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments, but the scope of the invention is not limited in any way.
[0018] This invention provides a signal transmission unit insertion method based on double-sided transistors. For the back-end design of circuits based on double-sided transistors, after the standard unit selection algorithm, the bus length of the double-sided net is further reduced by inserting signal transmission units (STCs).
[0019] In chip design based on double-sided transistors, double-sided nets still exist after the standard cell selection algorithm. These nets have relatively long line lengths, leading to a decrease in the chip's power-to-average performance (PPA). Further optimization of the line length is needed by inserting signal transmission units (STCs). This invention provides a method for inserting STCs based on double-sided transistors. After the standard cell selection of the double-sided transistor, STC insertion is used to further optimize the line length of the double-sided nets. This invention first models a new optimization problem. In solving the objective function, this invention first constructs an approximation problem based on the properties of double-sided net line length, and then solves for the use of STCs for the double-sided nets. Then, this invention uses STC insertion and validation operations to obtain the final STC insertion optimization result. Figure 1 As shown, the specific implementation of the present invention includes the following steps: Step 1: Modeling the optimization problem of the double-sided wire mesh, i.e., constructing the signal transmission unit (STC) allocation optimization model: Construct an optimization model for signal transmission unit (STC) allocation. The goal of the optimization model is to optimize the length of the double-sided bus after inserting STCs. The capacitance and resistance values of the STCs are taken as the equivalent line length and included in the objective function of the optimization model. The objective function is to minimize the sum of the line length increments of all double-sided nets and the equivalent line lengths using STCs. The constraints of the objective function include: the total number of STCs, the number of STCs used in each net, and the validity of the STCs. For double-sided nets in chip design based on double-sided transistors, which exist after the selection of standard cells, the constraints of the net length optimization problem include the total number of signal transmission units (STCs) and the number of STCs used in each net. Furthermore, solving this optimization problem also requires ensuring the validity of the STCs, maintaining the original circuit's logic function, and avoiding overlap with existing standard cells in the physical layout.
[0020] The objective function of this optimization problem is expressed as: Among them, c e C is the number of STCs used in each wire e. tot C is the upper limit of the total number of STCs in the entire design. e It is the upper limit of the number of STCs used for each net e, and corresponds to the number of pins that need to be flipped. A collection of double-sided wire meshes; To represent the set of integers, it means These are integers. DWL(e) represents the line length (front + back) of each net after standard cell selection, which is a known constant in this optimization problem. DWL(e') represents the line length (front + back) of each net after STC insertion. η represents the equivalent line length of an STC. This represents the total equivalent line length of the STC used for each net. DWL(e) is introduced because the impact of inserting an STC on the objective is different for different nets e, which helps to construct an auxiliary approximate optimization problem to solve the STC allocation problem. Therefore, the optimization objective of this problem can be expressed as minimizing the sum of the line length increments (DWL(e') - DWL(e)) of all double-sided nets and the equivalent line lengths using STCs.
[0021] Step 2: Solve for the STC allocation optimization of the signal transmission unit: Here, a variable θ representing the relative optimization degree of line length is constructed. e ,satisfy The lower bound of DWL(e') is WL(e). WL(e) is the half-perimeter-based line length (HPWL) of a net assuming all driven pins of the net are on the same side of the chip. Combined with θ e The following relationship can be obtained. Therefore, solving the following integer linear programming problem can yield the STC allocation for each network.
[0022] To solve this problem, θ e The STC number for nets with a value greater than 0 is set to 0 because it does not provide any optimization for net length. Next, the remaining θ... e Sort the nets from smallest to largest and assign C to each net e in order. e One STC, until the total number of STCs C is violated. tot Restrictions.
[0023] Step 3 involves STC insertion and legalization to achieve the insertion of a signal transmission unit based on a double-sided transistor: After STC allocation, a portion of the network allocation (used) C e Each STC corresponds to a pin that needs to be flipped. This invention first connects the STCs and pins to construct a new subnet, and sets the initial position of each STC to the location of the connected pin. Next, a validation algorithm searches for unoccupied spaces around the initial position and minimizes the total double-sided line length as much as possible, ultimately determining the valid position of the STC.
[0024] In one specific embodiment of the present invention, the chip design is based on a double-sided collective transistor architecture, in which the input pins of the standard cells are distributed on both the front and back sides of the chip, which inevitably leads to the appearance of double-sided nets. Figure 2Sub-figure (1) "No STC inserted, double-sided net length is large" contains three double-sided standard cells. In sub-figure (1), each standard cell has two input pins A and B (located on the front or back) and one output pin O (located on the front and back). The dashed lines in sub-figure (1) represent the dividing lines between the front and back areas, and the solid black lines represent double-sided nets. Sub-figure (2) "STC inserted, net length reduced" also contains three standard cells, and the pin and dashed line positions of the standard cells are defined in the same way as in sub-figure (1). However, there is one STC in sub-figure (2), whose insertion reduces the net length while maintaining the original pin interconnections on the net. Figure 2 As shown, this net drives two pins, one on the front and one on the back, resulting in a relatively long net length. When an STC is inserted, the pin on the back can be transmitted to the front via the STC, changing the structure of the double-sided net. For a typical double-sided net, where pins are distributed on both the front and back of the chip, this method can reduce the net length by up to 50%. Even considering the cost of the STC's capacitance and resistance, this method still effectively reduces the net's equivalent length. Such double-sided nets are prevalent in actual chip designs based on double-sided transistors. Therefore, this method can optimize the bus length of the circuit design, thereby optimizing the power-to-average (PPA).
[0025] In summary, this invention provides a novel mathematical model for the STC insertion algorithm in chip design based on double-sided transistors, constructs an approximate solution to the STC allocation problem, and designs STC insertion and legalization operations. It can be applied to the back-end design of circuits based on double-sided transistors, and used after the standard cell selection algorithm to further reduce the bus length of double-sided designs and improve chip performance.
[0026] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
Claims
1. A method for inserting a signal transmission unit based on a double-sided transistor, characterized in that, Includes the following steps: 1) Construct an optimization model for signal transmission unit (STC) allocation; The goal of the optimization model is to optimize the double-sided bus length after the STC is inserted, and the capacitance and resistance values of the STC are taken as the equivalent line length and included in the objective function of the optimization model. The objective function is to minimize the sum of the line length increments of all double-sided nets and the equivalent line length using STC; The constraints of the objective function include: the total number of STCs, the number of STCs used in each net, and the validity of the STCs. 2) Solve the STC allocation optimization model to obtain the STC allocation for each wire network; including: 21) Schedule and plan the usage of STC: Based on the length of the double-sided wire mesh, determine the usage of STC for the double-sided wire mesh by constructing an approximate model; 22) The results obtained from solving the optimization model satisfy the constraints on the total number of STCs and the number of STCs used in each wire mesh; 3) By performing STC insertion and legalization operations, the line length is reduced during the legalization process to obtain the final STC insertion optimization result, thereby realizing the insertion of signal transmission units based on double-sided transistors.
2. The signal transmission unit insertion method based on double-sided transistors as described in claim 1, characterized in that, The objective function of the signal transmission unit (STC) allocation optimization model constructed in step 1) is expressed as: Among them, c e C is the number of STCs used per net e; tot This is the upper limit of the total number of STCs; C e This is the upper limit of the number of STCs used for each net e, corresponding to the number of pins that need to be flipped. A collection of double-sided wire meshes; A set of integers, representing It is an integer; DWL(e) represents the front and back line lengths of each net after standard cell selection; DWL(e') represents the front and back line lengths of each net after STC insertion; η represents the equivalent line length of STC; This represents the total equivalent length of the STC used for each net.
3. The signal transmission unit insertion method based on double-sided transistors as described in claim 2, characterized in that, Step 2) Solve the STC allocation optimization model, including: Construct line length relative optimization degree variable θ e ,satisfy: The lower bound of DWL(e') is WL(e); WL(e) is the line length of a net based on half the perimeter, assuming that all driven pins of a net are on the same side of the chip. The optimization model for STC (Signal Transmission Unit) allocation is transformed into the following linear programming optimization model: θ e Set the number of STCs allocated to nets with a value greater than 0 to 0; set the remaining θ... e Sort the wires and assign C to each wire e in order. e One STC, until the total number of STCs C is violated. tot The limitations are thus determined, resulting in the STC allocation for each net.
4. The signal transmission unit insertion method based on double-sided transistors as described in claim 3, characterized in that, In step 3), the STC and pins are first connected to form a new subnet, and the initial position of each STC is set to the position of the pin connection. Then, the validation algorithm searches for empty spaces around the initial position that are not occupied by other standard cells, and reduces the total double-sided line length to finally determine the valid position of the STC.