Display panel, driving method thereof, driving circuit and display device

Abstract

The application provides a display panel, a driving method and circuit thereof, and a display device. The display panel comprises a plurality of scanning lines, a plurality of data lines, a plurality of enable signal lines and a plurality of pixel units arranged in an array. Each pixel unit comprises a first thin film transistor, a storage capacitor, an impedance circuit, a liquid crystal capacitor and an adjustable impedance circuit connected in sequence. When a row scanning signal is input, the initial gray scale voltage input by each of two adjacent pixel units in each row has opposite polarity, and the initial gray scale voltage input by each pixel unit or the absolute value of the initial gray scale voltage input by each of two adjacent pixel units in each row is equal. Therefore, the coupling effect of the gray scale voltage of each pixel unit in the same row on the common electrode is offset, the common electrode voltage is maintained unchanged, then, an enable signal is input, and the voltage of the liquid crystal capacitor is changed by the impedance circuit and the adjustable impedance circuit to be regulated to a corresponding target gray scale voltage, so that normal picture display is realized.

Description

Technical Field

[0001] This invention belongs to the field of display panel technology, and particularly relates to a display panel and its driving method, driving circuit and display device. Background Technology

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is one of the main types of flat panel displays and has become an important display platform in modern IT and visual products.

[0003] To avoid liquid crystal polarization, the grayscale voltage applied to the liquid crystal is flipped in a frame-flipping mode, such as... Figure 1 and Figure 2 As shown, the grayscale voltage polarity of a pixel unit is different in the previous frame and the next frame.

[0004] Meanwhile, display panels typically have a common electrode to provide a common electrode voltage signal. When the display panel's driving circuit outputs display data, the common electrode may experience voltage changes due to coupling with specific image display data, thus causing horizontal crosstalk. For example... Figure 1 and Figure 2 As shown, adjacent pixel units receive grayscale voltages with opposite polarities. When the difference between the two grayscale voltages and the common electrode voltage is not equal, the coupling effect on the common electrode is inconsistent, which in turn leads to a coupling deviation in the common electrode voltage.

[0005] To stabilize the common electrode voltage, the conventional approach is to set up an operational amplifier compensation circuit. This circuit detects the common electrode voltage in the plane, performs calculations to compensate, and then outputs a compensation signal to the common electrode, thereby controlling the common electrode voltage to stabilize at a preset voltage.

[0006] However, as display devices develop towards higher refresh rates and larger sizes, the frequency of interline voltage switching is high, exceeding the frequency threshold of the operational amplifier compensation circuit. This causes the temperature of the operational amplifier compensation circuit to rise, and may even lead to abnormal output voltage, resulting in abnormal picture. Furthermore, due to the difference in line impedance at different positions, the difference in compensation effect between the near and far ends of the operational amplifier compensation circuit is more obvious during compensation. There is a problem of over-compensation at the near end and under-compensation at the far end, which can also lead to abnormal picture.

[0007] Therefore, the operational amplifier compensation circuit cannot solve the problem of voltage coupling changes at the common electrode. Summary of the Invention

[0008] The purpose of this invention is to provide a display panel that solves the problem of traditional common electrode voltage being coupled and changed by grayscale voltage.

[0009] A first aspect of the present invention provides a display panel including multiple scan lines, multiple data lines, multiple enable signal lines, and pixel units arranged in an array, wherein the pixel units in the same row are connected to the same scan line, and the pixel units in the same column are respectively connected to the same data line and the same enable signal line; The pixel unit includes: Storage capacitor; A first thin-film transistor is connected to the corresponding data line, the scan line and the storage capacitor respectively. The first thin-film transistor is used to trigger conduction according to the received row scan signal and store the initial gray level voltage input by the data line into the storage capacitor. The initial gray level voltage input by each two adjacent pixel units in each row has opposite polarities and the absolute value of the voltage difference compared with the common electrode voltage is equal. An impedance circuit, wherein the first terminal of the impedance circuit is connected to the storage capacitor, and the impedance circuit has a preset impedance; A liquid crystal capacitor, wherein the liquid crystal capacitor is connected to the second terminal of the impedance circuit; An adjustable impedance circuit is connected to the liquid crystal capacitor, the enable signal line, and the positive voltage terminal, respectively. The adjustable impedance circuit is used to adjust the target impedance of the output matching size according to the corresponding size of the enable signal input by the enable signal line, so as to reduce the voltage difference between the initial gray level voltage and the standard voltage of the positive voltage terminal to the target gray level voltage. The phase of the enable signal lags behind the row scan signal of the current row.

[0010] Optionally, the impedance circuit includes a resistor, a second thin-film transistor, and a capacitor; The first end of the resistor and the first end of the second thin-film transistor are connected to form the first end of the impedance circuit. The second end of the resistor, the control terminal of the second thin-film transistor and the first end of the capacitor are connected. The second end of the second thin-film transistor and the second end of the capacitor are connected to form the second end of the impedance circuit.

[0011] Optionally, the resistor is the parasitic resistance of the second thin-film transistor.

[0012] Optionally, the adjustable impedance circuit includes a third thin-film transistor; The first terminal of the third thin-film transistor is connected to the second terminal of the impedance circuit and the liquid crystal capacitor, respectively. The control terminal of the third thin-film transistor is connected to the enable signal line. The second terminal of the third thin-film transistor is used to input a standard voltage. The third thin-film transistor operates in the variable resistance region.

[0013] Optionally, the aspect ratio of the third thin-film transistor is greater than that of the second thin-film transistor.

[0014] A second aspect of this invention provides a driving method for a display panel, applicable to the display panel described above, the driving method comprising: Obtain the target grayscale voltage of each pixel unit in the frame to be output, and compare and calculate the target grayscale voltage of each pixel unit in each target display area with the common electrode voltage respectively; The target gray level voltage with the largest voltage difference from the common electrode voltage among the target gray level voltages of the pixel units in each target display area is taken as the first initial gray level voltage of the pixel units in each target display area, and the second initial gray level voltage of the pixel units in each target display area is calculated. The second initial gray level voltage has the opposite polarity to the first initial gray level voltage and the absolute value of the voltage difference with the common electrode voltage is equal. Output the grayscale voltage of the current frame, and output the line scanning signal during the first time period of scanning each line, and output the first initial grayscale voltage and the second initial grayscale voltage corresponding to each target display area to each pixel unit of each line corresponding to the polarity; In the second time period of scanning each row, multiple enable signals are output to adjust the voltage of each pixel unit in each row to the corresponding target gray level voltage. The second time period lags behind the first time period.

[0015] Optionally, the target display area is one of the pixel units of the display panel, the pixel units of each row of the display panel, or each pair of adjacent pixel units in each row of the display panel.

[0016] A fourth aspect of this invention provides a driving circuit for a display panel, applicable to the display panel described above, wherein the driving circuit for the display panel includes: A gate driving circuit, connected to multiple scan lines of the display panel, is used to output a row scan signal according to a first control signal; The source driving circuit is connected to multiple data lines of the display panel and is used to output the corresponding first initial gray level voltage and second initial gray level voltage to the corresponding pixel unit according to the second control signal. The timing controller is connected to the gate driving circuit, the source driving circuit and the multiple enable signal lines respectively. The timing controller is used to output the first control signal, the second control signal and the enable signal based on the above-described display panel driving method.

[0017] Optionally, the driving circuit of the display panel further includes: A power management integrated circuit is connected to the positive voltage terminal of each pixel unit, and the power management integrated circuit is used to output a standard voltage to the positive voltage terminal of the pixel unit.

[0018] A fifth aspect of the present invention provides a display device, including a driving circuit for a display panel as described above and a display panel as described above, wherein the driving circuit for the display panel is connected to the display panel.

[0019] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned display panel includes multiple scan lines, multiple data lines, multiple enable signal lines, and pixel units arranged in an array. Each pixel unit includes a first thin-film transistor, a storage capacitor, an impedance circuit, a liquid crystal capacitor, and an adjustable impedance circuit connected in sequence. When a row scan signal is input, the polarity of the initial gray level voltage input to two adjacent pixel units in each row is opposite, and the absolute value of the initial gray level voltage input to each pixel unit or the initial gray level voltage input to two adjacent pixel units in each row is equal. Therefore, the coupling effect of the gray level voltage of each pixel unit in the same row on the common electrode cancels each other out, and the voltage of the common electrode remains unchanged. Then, an enable signal is input, and the voltage of the liquid crystal capacitor is adjusted to the corresponding target gray level voltage through the impedance circuit and the adjustable impedance circuit to achieve normal image display. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the first polarity of each pixel unit in a traditional display panel; Figure 2 This is a schematic diagram of the second polarity of each pixel unit in a traditional display panel; Figure 3 This is a schematic diagram of a first structure of a display panel provided in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of a second structure of the display panel provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the structure of a pixel unit provided in Embodiment 2 of the present invention; Figure 6 This is a flowchart illustrating the driving method for the display panel provided in Embodiment 3 of the present invention; Figure 7 This is a schematic diagram of a first structure of the driving circuit and display device for the display panel provided in Embodiments 4 and 5 of the present invention; Figure 8 This is a second structural schematic diagram of the driving circuit and display device for the display panel provided in Embodiments 4 and 5 of the present invention.

[0021] The figures in the diagram are labeled as follows: 100. Display panel; 200. Driving circuit for display panel; 10. Pixel unit; 11. Impedance circuit; 12. Adjustable impedance circuit; 210. Source driving circuit; 220. Gate driving circuit; 230. Timing controller; 240. Power management integrated circuit; T1, First thin-film transistor; T2, Second thin-film transistor; T3, Third thin-film transistor; Cst, Storage capacitor; Clc, Liquid crystal capacitor; Cs, Capacitor; R1, Resistor; AVcom, First common electrode layer; CFcom, Second common electrode layer; V0, standard voltage; EN, enable signal. Detailed Implementation

[0022] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0023] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] Example 1 A first aspect of the present invention provides a display panel 100, such as... Figure 3 As shown, it includes multiple scan lines, multiple data lines, multiple enable signal lines EN, and pixel units 10 arranged in an array. Pixel units 10 in the same row are connected to the same scan line, and pixel units 10 in the same column are connected to the same data line and the same enable signal line EN, respectively.

[0025] The scan line is connected to the corresponding gate drive circuit 220 and is used to input the line scan signal to the pixel unit 10 of the display panel 100 line by line. The data line is connected to the corresponding source drive circuit 210 and is used to input multiple grayscale voltages to the pixel unit 10 of the display panel 100. The enable signal line EN is connected to the corresponding signal source and is used to input the enable signal of the corresponding voltage magnitude.

[0026] The display panel 100 consists of an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. Pixel units 10, data lines, scan lines, and enable signal lines EN are disposed on the array substrate. A first common electrode layer AVcom is also disposed on the array substrate. A color filter layer and a second common electrode layer CFcom are disposed on the color filter substrate. The first common electrode layer AVcom and the second common electrode layer CFcom are provided with common electrode voltage by a power management integrated circuit 240 or a common electrode generation circuit, and the voltages on the two are equal.

[0027] Among them, such as Figure 4 As shown, pixel unit 10 includes: Storage capacitor Cst; The first thin-film transistor T1 is connected to the corresponding data line, scan line and storage capacitor Cst respectively. The first thin-film transistor T1 is used to trigger conduction according to the received row scan signal and store the initial gray level voltage input by the data line into the storage capacitor Cst. The initial gray level voltage input by each two adjacent pixel units 10 in each row has opposite polarities and the absolute value of the voltage difference compared with the common electrode voltage is equal. Impedance circuit 11, the first end of impedance circuit 11 is connected to storage capacitor Cst, and impedance circuit 11 has a preset impedance; Liquid crystal capacitor Clc is connected to the second terminal of impedance circuit 11. The adjustable impedance circuit 12 is connected to the liquid crystal capacitor Clc, the enable signal line EN and the positive voltage terminal respectively. The adjustable impedance circuit 12 is used to adjust the target impedance of the output matching size according to the corresponding size of the enable signal input to the enable signal line EN, so as to reduce the voltage difference between the initial gray level voltage and the standard voltage V0 of the positive voltage terminal to the target gray level voltage. The phase of the enable signal lags behind the current row scan signal.

[0028] In this embodiment, when the pixel unit 10 is scanning line by line, a time period for inputting an enable signal is reserved between two adjacent line scan signals. That is, when the pixel unit 10 is scanning line by line, it alternately works in the first time period and the second time period. The line scan signal is input in the first time period and the enable signal is input in the second time period. For example, the first scan line inputs the line scan signal to each pixel unit 10 of the first row in the first time period and inputs the enable signal to each pixel unit 10 of the first row in the second time period. Then, the second scan line inputs the line scan signal of the next row to each pixel unit 10 of the second row in the next first time period and inputs the enable signal to each pixel unit 10 of the second row in the next second time period, and so on.

[0029] The first thin-film transistor T1, the storage capacitor Cst, the impedance circuit 11, the liquid crystal capacitor Clc, and the adjustable impedance circuit 12 are sequentially connected to form a pixel unit 10. The storage capacitor Cst is formed by a pixel electrode and a first common electrode layer AVcom disposed on the array substrate, and the liquid crystal capacitor Clc is formed by a pixel electrode and a second common electrode layer CFcom. That is, the first electrode of the storage capacitor Cst is the pixel electrode and the second electrode is the first common electrode layer AVcom, and the first electrode of the liquid crystal capacitor Clc is the pixel electrode and the second electrode is the second common electrode layer CFcom.

[0030] In each row, every two adjacent pixel units 10 input initial grayscale voltages with opposite polarities and equal absolute values ​​of voltage differences relative to the common electrode voltage during the first time period. For example, the two pixel units 10 in the first column and the second column of the first row input positive and negative initial grayscale voltages, respectively. Positive and negative polarities are relative to the common electrode voltage. Grayscale voltages greater than the common electrode voltage are positive grayscale voltages, and grayscale voltages less than the common electrode voltage are negative grayscale voltages. The absolute values ​​of the positive and negative initial grayscale voltages are equal, that is, the absolute value of the voltage difference between the positive grayscale voltage and the common electrode voltage is equal to the absolute value of the voltage difference between the negative grayscale voltage and the common electrode voltage. For example, if the common electrode voltage is 6.4V and the positive initial grayscale voltage is 12V, then the negative initial grayscale voltage is 0.8V. Both have opposite polarities and equal absolute values ​​of voltage differences relative to the common electrode voltage, which is 5.6V.

[0031] Similarly, the initial grayscale voltages input to the two pixel units 10 in the third and fourth columns of the first row have opposite polarities and the absolute values ​​of the voltage differences relative to the common electrode voltage are equal. The initial grayscale voltages of each pixel unit 10 in each row corresponding to the positive polarity can be equal or unequal, and the initial grayscale voltages of each pixel unit 10 in each row corresponding to the negative polarity can be equal or unequal.

[0032] For example, in the first frame, the pixel units 10 in the odd-numbered columns of each row receive equal positive grayscale voltages, and the pixel units 10 in the even-numbered columns of each row receive equal negative grayscale voltages. In the second frame, the pixel units 10 in the odd-numbered columns of each row receive equal negative grayscale voltages, and the pixel units 10 in the even-numbered columns of each row receive equal positive grayscale voltages.

[0033] In each frame, the initial grayscale voltage of each pixel unit 10 corresponding to the positive polarity may be equal or unequal, and the initial grayscale voltage of each pixel unit 10 corresponding to the negative polarity may be equal or unequal. For example, when scanning the first row and the second row respectively, the pixel unit 10 of the first row and the first column of the second row both input a positive polarity grayscale voltage with equal voltage, and the pixel unit 10 of the first row and the second column of the second row both input a negative polarity grayscale voltage with equal voltage.

[0034] The polarity of each pixel unit 10 of the display panel 100 input in the first time period can be set according to the requirements. Among them, at least in each row, the polarity of the initial gray level voltage input to each two adjacent pixel units 10 is opposite and the absolute value of the voltage difference relative to the common electrode voltage is equal.

[0035] Pixel unit 10 operates in a first time period and a second time period. Taking the pixel unit 10 in the first row, first column and second column as an example, in the first time period, the first scan line inputs the row scan signal to the two first thin film transistors T1 of the pixel unit 10 in the first row, first column and second column, and simultaneously inputs a positive initial gray level voltage to the first thin film transistor T1 of the pixel unit 10 in the first row, first column and inputs a negative initial gray level voltage to the second thin film transistor T2 of the pixel unit 10 in the first row, second column.

[0036] The positive initial grayscale voltage is stored in the storage capacitor Cst of the pixel unit 10 in the first row and first column, and the negative initial grayscale voltage is stored in the storage capacitor Cst of the pixel unit 10 in the first row and second column. Since the positive and negative initial grayscale voltages have opposite polarities and the absolute values ​​of their voltage differences relative to the common electrode voltage are equal, the two initial grayscale voltages have the same coupling ability to the common electrode voltage and are opposite in direction, thus canceling each other out. The common electrode voltage remains stable at its original value, without causing additional coupling deviation, and without crosstalk, ensuring the display effect of the display panel 100.

[0037] Furthermore, it eliminates the need for additional operational amplifier compensation circuitry, simplifying the circuit structure and reducing design costs.

[0038] Then, in order to input the target grayscale voltage required by the liquid crystal capacitor Clc of the actual pixel unit 10, in the second time period, the pixel unit 10 in the first row and first column and the pixel unit 10 in the first row and second column respectively input enable signals of corresponding magnitudes. For example, their initial grayscale voltages are 12V and 0.8V respectively, the common electrode voltage is 6.4V, the target grayscale voltage of the pixel unit 10 in the first row and first column is 11V, and the target grayscale voltage of the pixel unit 10 in the first row and second column is 5.9V. Therefore, it is necessary to adjust the 12V to 11V and the 0.8V to 5.9V. The pixel unit 10 in the first row and first column inputs... A corresponding enable signal controls the impedance change of the adjustable impedance circuit 12. The impedance circuit 11 and the adjustable impedance circuit 12 form a voltage divider circuit, which divides the voltage difference between the initial grayscale voltage and the standard voltage V0, thereby adjusting the initial grayscale voltage to the target grayscale voltage. That is, adjusting the positive initial grayscale voltage to the positive target grayscale voltage, or adjusting the negative initial grayscale voltage to the negative target grayscale voltage. For example, adjusting the positive initial grayscale voltage of 12V to the positive target grayscale voltage of 11V, or adjusting the negative initial grayscale voltage of 0.8V to the negative target grayscale voltage of 5.9V.

[0039] The corresponding pixel unit 10 receives the target gray level voltage of the corresponding polarity in the second time period, and forms a driving voltage with the common electrode voltage to display the required display image. This avoids the coupling of the data line to the common electrode layer, prevents screen crosstalk, and improves the display effect.

[0040] As can be seen from the above analysis, the initial gray level voltage and the target gray level voltage received by the same pixel unit 10 before and after the first time period and the second time period have the same polarity, but there is a possibility of voltage rise or voltage fall. In order to ensure that the polarity is the same and that the corresponding voltage rise or voltage fall is achieved, in an optional embodiment, the standard voltage V0 is equal to the common electrode voltage.

[0041] The initial grayscale voltage and target grayscale voltage received by the same pixel unit 10 before and after the first and second time periods can be the same or different, depending on the requirements.

[0042] In an optional embodiment, in order to reduce the number of voltage charging and discharging of pixel units 10, among the two initial gray level voltages corresponding to each row of two adjacent pixel units 10, the target gray level voltage of the pixel unit 10 with the largest voltage difference from the common electrode voltage is taken as the first initial gray level voltage, and the second initial gray level voltage of the other pixel unit 10 is calculated.

[0043] For example, the target grayscale voltages of pixel unit 10 in the first row and first column and pixel unit 10 in the first row and second column are 12V and 5.9V respectively, and the common electrode voltage is 6.4V. Then, the target grayscale voltage of pixel unit 10 in the first row and first column is used as its first initial grayscale voltage, and the second initial grayscale voltage of pixel unit 10 in the first row and first column is calculated based on the initial grayscale voltage of pixel unit 10 in the first row and first column. That is, the calculated second initial grayscale voltage is 0.8V. In the second time period, the first row and first column... An enable signal is input to the adjustable impedance circuit 12 of pixel unit 10. The adjustable impedance circuit 12 remains on and its impedance is zero. The first initial gray level voltage is transferred to the liquid crystal capacitor Clc without voltage division. The pixel unit 10 in the first row and second column inputs an enable signal, and the impedance of its adjustable impedance circuit 12 changes accordingly. The voltage difference between the standard voltage V0 and the second initial gray level voltage is divided between the impedance circuit 11 and the adjustable impedance circuit 12. The voltage of the liquid crystal capacitor Clc gradually rises until it reaches its target gray level voltage of 5.9V.

[0044] For example, if the target grayscale voltages of pixel unit 10 in the first row and first column and pixel unit 10 in the first row and second column are 6.7V and 1V respectively, and the common electrode voltage is 6.4V, then the target grayscale voltage of pixel unit 10 in the first row and second column is used as its first initial grayscale voltage, and the second initial grayscale voltage of pixel unit 10 in the first row and second column is calculated based on the initial grayscale voltage of pixel unit 10 in the first row and second column. That is, the calculated second initial grayscale voltage is 11.8V. In the second time period, the pixel unit 10 in the first row and second column... When the adjustable impedance circuit 12 of unit 10 receives an enable signal, it remains on and has zero impedance. The first initial grayscale voltage of 1V is transmitted to the liquid crystal capacitor Clc without voltage division. When the first row and first column pixel unit 10 receives an enable signal, the impedance of its adjustable impedance circuit 12 changes accordingly. The voltage difference between the standard voltage V0 and the second initial grayscale voltage is divided between the impedance circuit 11 and the adjustable impedance circuit 12. The voltage of the liquid crystal capacitor Clc gradually decreases from 11.8V until it reaches its target grayscale voltage of 6.7V.

[0045] Among them, the impedance circuit 11 can be a corresponding resistor or a thin film transistor, and the adjustable impedance circuit 12 can be a corresponding variable resistor structure.

[0046] Example 2 In an alternative embodiment, such as Figure 5 As shown, the impedance circuit 11 includes a resistor R1, a second thin-film transistor T2, and a capacitor Cs; The first end of resistor R1 and the first end of the second thin-film transistor T2 are connected to form the first end of impedance circuit 11. The second end of resistor R1, the control terminal of the second thin-film transistor T2 and the first end of capacitor Cs are connected. The second end of the second thin-film transistor T2 and the second end of capacitor Cs are connected to form the second end of impedance circuit 11.

[0047] The adjustable impedance circuit 12 includes a third thin-film transistor T3; The first terminal of the third thin-film transistor T3 is connected to the second terminal of the impedance circuit 11 and the liquid crystal capacitor Clc, respectively. The control terminal of the third thin-film transistor T3 is connected to the enable signal line EN. The second terminal of the third thin-film transistor T3 is used to input the standard voltage V0. The third thin-film transistor T3 operates in the variable resistance region.

[0048] In this embodiment, during the first time period, the pixel unit 10 inputs a row scanning signal to the first thin-film transistor T1, and the initial grayscale voltage is input to the storage capacitor Cst through the first thin-film transistor T1 and stored. Moreover, the polarity of the initial grayscale voltage input to each of the two adjacent pixel units 10 in each row is opposite, and the coupling ability of the two initial grayscale voltages to the common electrode voltage is the same and the direction is opposite, thus canceling each other out. The common electrode voltage is stabilized at the original value, without causing additional coupling deviation, and without crosstalk, thus ensuring the display effect of the display panel 100.

[0049] Then, in the second time period, the third thin-film transistor T3 receives an enable signal of the corresponding magnitude and turns on. At this time, the standard voltage V0 is transmitted to the liquid crystal capacitor Clc and through the capacitor Cs to the second thin-film transistor T2, which turns on. The initial grayscale voltage is transmitted to the liquid crystal capacitor Clc through the second thin-film transistor T2. At the same time, the third thin-film transistor T3 operates in the variable resistance region, generating an impedance of the corresponding magnitude. The third thin-film transistor T3 and the second thin-film transistor T2 form a voltage divider circuit. The initial grayscale voltage charges the liquid crystal capacitor Clc, or the standard voltage V0 charges the liquid crystal capacitor Clc. The liquid crystal capacitor Clc gradually changes to the target grayscale voltage. For example, the standard voltage V0 charges the liquid crystal capacitor Clc, causing it to rise from the initial grayscale voltage of 0.8V to the target grayscale voltage of 5.9V, or the initial grayscale voltage charges the liquid crystal capacitor Clc, causing it to drop from the initial grayscale voltage of 11.8V to 6.7V.

[0050] In order to simplify the structure of the array substrate, its resistor R1 is the parasitic resistance of the second thin film transistor T2. The second thin film transistor T2 is formed on the array substrate in an interlayer structure, and there are corresponding parasitic resistances between its source, gate and drain.

[0051] Furthermore, in order to prevent the second thin-film transistor T2 from entering a saturated state during the charging and discharging process of the liquid crystal capacitor Clc, the aspect ratio of the third thin-film transistor T3 is greater than that of the second thin-film transistor T2.

[0052] The beneficial effects of the present invention embodiment compared with the prior art are as follows: The above-mentioned display panel 100 includes multiple scan lines, multiple data lines, multiple enable signal lines EN, and pixel units 10 arranged in an array. The pixel unit 10 includes a first thin film transistor T1, a storage capacitor Cst, an impedance circuit 11, a liquid crystal capacitor Clc, and an adjustable impedance circuit 12 connected in sequence. When the row scan signal is input, the polarity of the initial gray level voltage input to two adjacent pixel units 10 in each row is opposite, and the absolute value of the initial gray level voltage input to each pixel unit 10 or the initial gray level voltage input to each two adjacent pixel units 10 in each row is equal. Therefore, the coupling effect of the gray level voltage of each pixel unit 10 in the same row to the common electrode cancels each other out, and the voltage of the common electrode remains unchanged. Then, the enable signal is input, and the voltage of the liquid crystal capacitor Clc is adjusted to the corresponding target gray level voltage through the impedance circuit 11 and the adjustable impedance circuit 12 to achieve normal screen display.

[0053] Example 3 A second aspect of this invention provides a driving method for a display panel 100, applicable to the display panel 100 described above, such as... Figure 6 As shown, the driving method for the display panel 100 includes: S11. Obtain the target grayscale voltage of each pixel unit 10 of the frame to be output, and compare and calculate the target grayscale voltage of each pixel unit 10 in each target display area with the common electrode voltage respectively. S12. The target gray level voltage with the largest voltage difference from the common electrode voltage among the target gray level voltages of the pixel unit 10 in each target display area is taken as the first initial gray level voltage of the pixel unit 10 in each target display area, and the second initial gray level voltage of the pixel unit 10 in each target display area is calculated. The second initial gray level voltage has the opposite polarity to the first initial gray level voltage and the absolute value of the voltage difference with the common electrode voltage is equal. S13. Output the grayscale voltage of the current frame, and output the line scanning signal during the first time period of scanning each line, and output the first initial grayscale voltage and the second initial grayscale voltage corresponding to each target display area to each pixel unit 10 of each line corresponding to the polarity. S14. In the second time period of scanning each row, output multiple enable signals to adjust the voltage of each pixel unit 10 in each row to its corresponding target gray level voltage. The second time period lags behind the first time period.

[0054] In this embodiment, the target grayscale voltage of each pixel unit 10 to be output in each frame is first obtained, and the required initial grayscale voltage is determined from it.

[0055] Furthermore, the multiple pixel units 10 of the display panel 100 can be divided into multiple target display areas. Each target display area may include multiple pixel units 10, and at least each row of every two adjacent pixel units 10. In an optional embodiment, the target display area is one of each pixel unit 10 of the display panel 100, the pixel units 10 of each row of the display panel 100, or each row of every two adjacent pixel units 10 in the display panel 100.

[0056] In order to reduce the number of voltage charging and discharging of pixel units 10, in the target display area, the target gray level voltage of one of the pixel units 10 with the largest voltage difference from the common electrode voltage is taken as the first initial gray level voltage, and the second initial gray level voltage of the other pixel unit 10 is calculated.

[0057] For example, if the target display area is each row of every two adjacent pixel units 10, and the target grayscale voltages of the pixel unit 10 in the first row and first column and the pixel unit 10 in the first row and second column are 12V and 5.9V respectively, and the common electrode voltage is 6.4V, then the target grayscale voltage of the pixel unit 10 in the first row and first column is taken as its first initial grayscale voltage, and the second initial grayscale voltage of the pixel unit 10 in the first row and second column is calculated based on the initial grayscale voltage of the pixel unit 10 in the first row and first column, that is, its second initial grayscale voltage is calculated to be 0.8V.

[0058] For example, if the target grayscale voltages of pixel unit 10 in the first row and first column and pixel unit 10 in the first row and second column are 6.7V and 1V respectively, and the common electrode voltage is 6.4V, then the target grayscale voltage of pixel unit 10 in the first row and second column is used as its first initial grayscale voltage, and the second initial grayscale voltage of pixel unit 10 in the first row and first column is calculated based on the initial grayscale voltage of pixel unit 10 in the first row and second column, that is, its second initial grayscale voltage is calculated to be 11.8V.

[0059] Alternatively, the target display area can be multiple pixel units 10 in each row. Each pixel unit 10 in each row is compared with a common electrode voltage, and the target grayscale voltage with the largest voltage difference from the common electrode voltage is selected as the first initial grayscale voltage. A second initial grayscale voltage is then calculated. For example, if the target grayscale voltages of multiple pixel units 10 in each row are 12.5V, 5.4V, 11.4V, 4.4V, 10V, and 0.8V respectively, and the common electrode voltage is 6.4V, then the target grayscale voltage with the largest voltage difference from the common electrode voltage is 12.5V. Therefore, the first initial grayscale voltage is 12.5V, and the corresponding second initial grayscale voltage is 0.3V. Thus, the adjusted initial grayscale voltages of the multiple pixel units 10 in the current row are 12.5V, 0.3V, 12.5V, 0.3V, 12.5V, and 0.3V respectively.

[0060] Alternatively, the target display area can be multiple pixel units 10 of the entire display panel 100. Similarly, the multiple pixel units 10 are compared with the common electrode voltage, and the target gray level voltage with the largest voltage difference with the common electrode voltage is selected as the first initial gray level voltage, and the second initial gray level voltage is calculated.

[0061] For example, display panel 100 includes 12 pixel units 10 arranged in two rows and six columns. The target grayscale voltages of each pixel unit 10 in the first row are 12.5V, 5.4V, 11.4V, 4.4V, 10V, and 0.8V, respectively. The target grayscale voltages of each pixel unit 10 in the second row are 12.7V, 5.4V, 11.4V, 4.4V, 10V, and 0.3V, respectively. Then, the target grayscale voltage with the largest voltage difference from the common electrode is 12.7V. If V, then the first initial grayscale voltage is 12.7V, and the corresponding second initial grayscale voltage is 0.1V. Therefore, the initial grayscale voltages of each pixel unit 10 in the first row after adjustment are 12.7V, 0.1V, 12.7V, 0.1V, 12.7V, and 0.1V, respectively. The initial grayscale voltages of each pixel unit 10 in the second row after adjustment are 12.7V, 0.1V, 12.7V, 0.1V, 12.7V, and 0.1V, respectively.

[0062] In the target display area, the adjusted initial grayscale voltages of positive and negative polarities are equal in number, opposite in polarity, and equal in absolute value of voltage difference compared to the common electrode voltage. The coupling ability of each initial grayscale voltage to the common electrode voltage is the same and opposite in direction, thus canceling each other out. The common electrode voltage is stabilized at its original value, without causing additional coupling deviation, and without crosstalk, ensuring the display effect of the display panel 100.

[0063] Then, after determining the initial grayscale voltage of the target display area, the initial grayscale voltage is output. Taking the target display area as each row of two adjacent pixel units 10 as an example, such as the pixel units 10 in the first row, first column and second column, during the row-by-row scanning, in the first time period, the first scan line inputs the row scan signal to the two first thin film transistors T1 of the pixel units 10 in the first row, first column and second column, and simultaneously inputs the positive polarity initial grayscale voltage to the first thin film transistor T1 of the pixel unit 10 in the first row, first column and inputs the negative polarity initial grayscale voltage to the second thin film transistor T2 of the pixel unit 10 in the first row, second column.

[0064] The positive initial grayscale voltage is stored in the storage capacitor Cst of the pixel unit 10 in the first row and first column, and the negative initial grayscale voltage is stored in the storage capacitor Cst of the pixel unit 10 in the first row and second column. Since the positive and negative initial grayscale voltages have opposite polarities and the absolute values ​​of their voltage differences relative to the common electrode voltage are equal, the two initial grayscale voltages have the same coupling ability to the common electrode voltage and are opposite in direction, thus canceling each other out. The common electrode voltage remains stable at its original value, without causing additional coupling deviation, and without crosstalk, ensuring the display effect of the display panel 100.

[0065] Then, in order to input the target grayscale voltage required by the liquid crystal capacitor Clc of the actual pixel unit 10, in the second time period, the pixel unit 10 in the first row and first column and the pixel unit 10 in the first row and second column respectively input enable signals of corresponding magnitudes. For example, their initial grayscale voltages are 12V and 0.8V respectively, the common electrode voltage is 6.4V, the target grayscale voltage of the pixel unit 10 in the first row and first column is 12V, and the target grayscale voltage of the pixel unit 10 in the first row and second column is 5.9V. Then, the 0.8V needs to be adjusted to 5.9V, and the pixel unit 10 in the first row and first column inputs the corresponding enable signal. The signal is 0.8V. In the second time period, the adjustable impedance circuit 12 of the first row and first column pixel unit 10 receives an enable signal. Its adjustable impedance circuit 12 remains on and its impedance is zero. The first initial gray level voltage is transferred to the liquid crystal capacitor Clc without voltage division. The pixel unit 10 of the first row and second column receives an enable signal of the corresponding magnitude. The impedance of its adjustable impedance circuit 12 changes accordingly. The voltage difference between the standard voltage V0 and the second initial gray level voltage is divided between the impedance circuit 11 and the adjustable impedance circuit 12. The voltage of the liquid crystal capacitor Clc gradually rises until it reaches its target gray level voltage of 5.9V.

[0066] The corresponding pixel unit 10 receives the target gray level voltage of the corresponding polarity in the second time period, and forms a driving voltage with the common electrode voltage to display the required display image. This avoids the coupling of the data line to the common electrode layer, prevents screen crosstalk, and improves the display effect.

[0067] Example 4 A fourth aspect of this invention provides a driving circuit 200 for a display panel, applicable to the display panel 100 described above, such as... Figure 7 As shown, the driving circuit 200 for the display panel includes: The gate driving circuit 220 is connected to multiple scan lines of the display panel 100 and is used to output a row scanning signal according to the first control signal; The source drive circuit 210 is connected to multiple data lines of the display panel 100 and is used to output the corresponding first initial gray level voltage and second initial gray level voltage to the corresponding pixel unit 10 according to the second control signal. The timing controller 230 is connected to the gate drive circuit 220, the source drive circuit 210 and multiple enable signal lines EN, respectively. The timing controller 230 is used to output corresponding first control signal, second control signal and enable signal based on the driving method of the display panel 100.

[0068] In this embodiment, the timing controller 230 acquires and compares the target grayscale voltages of each target display area, calculates and stores the first initial grayscale voltage and the second initial grayscale voltage corresponding to each target display area, and then controls the gate driving circuit 220 to output the row scanning signal. During the row scanning, in the first time period of scanning each row, that is, the time period when the pixel unit 10 inputs the row scanning signal, the source driving circuit 210 is synchronously controlled to output the first initial grayscale voltage and the second initial grayscale voltage corresponding to each target display area to the corresponding target display area.

[0069] In the target display area, the adjusted initial grayscale voltages of positive and negative polarities are equal in number, opposite in polarity, and equal in absolute value of voltage difference compared to the common electrode voltage. The coupling ability of each initial grayscale voltage to the common electrode voltage is the same and opposite in direction, thus canceling each other out. The common electrode voltage is stabilized at its original value, without causing additional coupling deviation, and without crosstalk, ensuring the display effect of the display panel 100.

[0070] Then, in the second time period, the timing controller 230 outputs multiple enable signals of corresponding magnitudes to the pixel unit 10 of the target display area, so that the pixel unit 10 is regulated to the corresponding target gray level voltage to achieve the desired display effect.

[0071] The standard voltage V0 can be provided by a corresponding signal source. In an optional embodiment, such as... Figure 8 As shown, the driving circuit 200 of the display panel also includes: The power management integrated circuit 240 is connected to the positive voltage terminal of each pixel unit 10. The power management integrated circuit 240 is used to output a standard voltage V0 to the positive voltage terminal of the pixel unit 10.

[0072] In this embodiment, the standard voltage V0 is the common electrode voltage. The standard voltage V0 is output by the power management integrated circuit 240. The power management integrated circuit 240 also provides the operating power required by the timing controller 230, the source drive circuit 210 and the gate drive circuit 220.

[0073] Example 5 The present invention also proposes a display device, such as Figure 7 and Figure 8 As shown, the display device includes the driving circuit 200 of the display panel and the display panel 100. The specific structures of the driving circuit 200 and the display panel 100 are as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The driving circuit 200 of the display panel is connected to the display panel 100.

[0074] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, It includes multiple scan lines, multiple data lines, multiple enable signal lines, and pixel units arranged in an array. The pixel units in the same row are connected to the same scan line, and the pixel units in the same column are connected to the same data line and the same enable signal line, respectively. The pixel unit includes: Storage capacitor; A first thin-film transistor is connected to the corresponding data line, the scan line and the storage capacitor respectively. The first thin-film transistor is used to trigger conduction according to the received row scan signal and store the initial gray level voltage input by the data line into the storage capacitor. The initial gray level voltage input by each two adjacent pixel units in each row has opposite polarities and the absolute value of the voltage difference compared with the common electrode voltage is equal. An impedance circuit, wherein the first terminal of the impedance circuit is connected to the storage capacitor, and the impedance circuit has a preset impedance; A liquid crystal capacitor, wherein the liquid crystal capacitor is connected to the second terminal of the impedance circuit; An adjustable impedance circuit is connected to the liquid crystal capacitor, the enable signal line, and the positive voltage terminal, respectively. The adjustable impedance circuit is used to adjust the target impedance of the output matching size according to the corresponding size of the enable signal input by the enable signal line, so as to reduce the voltage difference between the initial gray level voltage and the standard voltage of the positive voltage terminal to the target gray level voltage. The phase of the enable signal lags behind the row scan signal of the current row.

2. The display panel as described in claim 1, characterized in that, The impedance circuit includes a resistor, a second thin-film transistor, and a capacitor; The first end of the resistor and the first end of the second thin-film transistor are connected to form the first end of the impedance circuit. The second end of the resistor, the control terminal of the second thin-film transistor and the first end of the capacitor are connected. The second end of the second thin-film transistor and the second end of the capacitor are connected to form the second end of the impedance circuit.

3. The display panel as described in claim 2, characterized in that, The resistor is the parasitic resistance of the second thin-film transistor.

4. The display panel as described in claim 2, characterized in that, The adjustable impedance circuit includes a third thin-film transistor; The first terminal of the third thin-film transistor is connected to the second terminal of the impedance circuit and the liquid crystal capacitor, respectively. The control terminal of the third thin-film transistor is connected to the enable signal line. The second terminal of the third thin-film transistor is used to input a standard voltage. The third thin-film transistor operates in the variable resistance region.

5. The display panel as described in claim 4, characterized in that, The aspect ratio of the third thin-film transistor is greater than that of the second thin-film transistor.

6. A driving method for a display panel, applicable to the display panel as described in any one of claims 1 to 5, characterized in that, The driving method for the display panel includes: Obtain the target grayscale voltage of each pixel unit in the frame to be output, and compare and calculate the target grayscale voltage of each pixel unit in each target display area with the common electrode voltage respectively; The target gray level voltage with the largest voltage difference from the common electrode voltage among the target gray level voltages of the pixel units in each target display area is taken as the first initial gray level voltage of the pixel units in each target display area, and the second initial gray level voltage of the pixel units in each target display area is calculated. The second initial gray level voltage has the opposite polarity to the first initial gray level voltage and the absolute value of the voltage difference with the common electrode voltage is equal. Output the grayscale voltage of the current frame, and output the line scanning signal during the first time period of scanning each line, and output the first initial grayscale voltage and the second initial grayscale voltage corresponding to each target display area to each pixel unit of each line corresponding to the polarity; In the second time period of scanning each row, multiple enable signals are output to adjust the voltage of each pixel unit in each row to the corresponding target gray level voltage. The second time period lags behind the first time period.

7. The driving method for a display panel as described in claim 6, characterized in that, The target display area is one of the pixel units of the display panel, the pixel units of each row of the display panel, and one of every two adjacent pixel units in each row of the display panel.

8. A driving circuit for a display panel, applicable to the display panel as described in any one of claims 1 to 5, characterized in that, The driving circuit of the display panel includes: A gate driving circuit, connected to multiple scan lines of the display panel, is used to output a row scan signal according to a first control signal; The source driving circuit is connected to multiple data lines of the display panel and is used to output the corresponding first initial gray level voltage and second initial gray level voltage to the corresponding pixel unit according to the second control signal. A timing controller is connected to the gate driving circuit, the source driving circuit, and the plurality of enable signal lines, respectively. The timing controller is used to output the first control signal, the second control signal, and the enable signal based on the driving method of the display panel as described in any one of claims 6 or 7.

9. The driving circuit for the display panel as described in claim 8, characterized in that, The driving circuit of the display panel also includes: A power management integrated circuit is connected to the positive voltage terminal of each pixel unit, and the power management integrated circuit is used to output a standard voltage to the positive voltage terminal of the pixel unit.

10. A display device, characterized in that, It includes a driving circuit for a display panel as described in any one of claims 8 to 9 and a display panel as described in any one of claims 1 to 4, wherein the driving circuit for the display panel is connected to the display panel.

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