Memory device for adjusting jump level and method of operating same

Abstract

The invention provides a memory device for adjusting a jump level and a method of operating the same. The memory device includes: a cell string including memory cells; and a page buffer configured to be connected to the cell string through a bit line, and configured to sense data of a selected memory cell among the memory cells through a sense latch circuit, in which the sense latch circuit includes: a sense latch including a first inverter and a second inverter; and a trim transistor circuit electrically connected to a p-type metal oxide semiconductor (PMOS) transistor of the first inverter and configured to adjust a jump level of the sense latch based on a trim voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0091226, filed on July 10, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] This application relates to a storage device for adjusting switching levels and a method of operating the same. Background Technology

[0004] Memory can include volatile and non-volatile memory. For example, flash memory can be one type of non-volatile memory and can retain stored data without power. Flash memory technology can be electrically erasable programmable read-only memory (EEPROM) and data can be electrically erased and written. Flash memory can be used in a variety of electronic devices, primarily computers, smartphones, cameras, universal serial drive (USB) drives, and solid-state drives (SSDs). Page buffers can be used for data sensing in flash memory. Each bit line of flash memory can be connected to a page buffer, and the page buffer can be used to sense the data stored in each memory cell on each bit line. Summary of the Invention

[0005] The switching operation of a sense latch can be used for data sensing in memory (e.g., flash memory). The switching operation can be based on pull-up and pull-down operations of p-type metal-oxide-semiconductor (PMOS) transistors and n-type metal-oxide-semiconductor (NMOS) transistors. Variations in the process voltage-temperature (PVT) of PMOS and NMOS transistors can cause variations in the switching level of the switching operation. These variations in switching level can prevent ensuring the required sensing margin (e.g., sensing margin for low-power operation).

[0006] In some embodiments, a memory device includes: a cell string including memory cells; and a page buffer connected to the cell string via bit lines, and including a sense latch circuit. The page buffer is configured to sense data in a selected memory cell using the sense latch circuit, wherein the sense latch circuit includes: a sense latch including a first inverter and a second inverter; and a trimmer transistor circuit electrically connected to a PMOS transistor of the first inverter and configured to adjust the switching level of the sense latch based on a trimmer voltage.

[0007] In some embodiments, a storage device includes: a cell string including storage cells; and a page buffer connected to the cell string via bit lines, and including a sense latch circuit. The page buffer is configured to sense data in a selected storage cell using the sense latch circuit, wherein the sense latch circuit includes: a sense latch disposed between a latch node and an inverting latch node; a sense transistor disposed between the latch node and a ground terminal; and a trimmer transistor circuit connected in series with the sense transistor and configured to adjust the switching level of the sense latch based on a trimmer voltage.

[0008] In some embodiments, a storage device includes: a cell string including storage cells; and a page buffer connected to the cell string via bit lines, and including a sense latch circuit. The page buffer is configured to sense data in a selected storage cell using the sense latch circuit, wherein the sense latch circuit includes: a sense latch disposed between a latch node and an inverting latch node, and including a first inverter and a second inverter; a sense transistor disposed between the latch node and a ground terminal; and a trimmer transistor circuit configured to adjust the switching level of the sense latch based on a trimmer voltage, wherein the trimmer transistor circuit includes: a first trimmer transistor circuit electrically connected to a PMOS transistor of the first inverter; and a second trimmer transistor circuit electrically connected to the sense transistor.

[0009] In some implementations, the switching operation can be controlled by using a trimmer transistor circuit added to the sensing latch circuit, thereby ensuring the required sensing margin. In some implementations, a sample sensing latch circuit corresponding to the sensing latch circuit can be used to automatically determine the trimmer voltage used to control the switching operation.

[0010] Other features and aspects will become apparent from the following detailed description, drawings and claims. Attached Figure Description

[0011] Figure 1 This is a block diagram of an example configuration of a storage device.

[0012] Figure 2 This is a circuit diagram of an example configuration of storage blocks in a storage cell array.

[0013] Figure 3 This is a circuit diagram of an example configuration of the cell strings of a storage block.

[0014] Figure 4 This is a circuit diagram of an example configuration of a sense latch circuit, including a first trimmer transistor circuit and a second trimmer transistor circuit.

[0015] Figure 5This is a diagram illustrating examples of conduction margin, cutoff margin, and switching level changes.

[0016] Figure 6 and Figure 7 This is a circuit diagram of an example configuration of a sense latch circuit having one of a first trimmer transistor circuit and a second trimmer transistor circuit.

[0017] Figure 8 This is a circuit diagram of an example configuration of a sense latch circuit with parallel trimmer transistors.

[0018] Figure 9 This is a circuit diagram of an example configuration of a sense latch circuit, including a second trimmer transistor circuit located between the latch node and the sense transistor.

[0019] Figure 10 This is a circuit diagram of an example configuration of a sense latch circuit, including the first trimmer transistor circuit located inside the inverter of the sense latch.

[0020] Figure 11 This is a circuit diagram of an example configuration of a sense latch circuit including a first trimmer transistor circuit and a second trimmer transistor circuit, each of which includes at least one trimmer transistor.

[0021] Figure 12 This is a circuit diagram of an example configuration for performing calibration steps using a sample sensing latch circuit.

[0022] Figure 13 This is a circuit diagram of an example configuration of a page buffer.

[0023] Figure 14 This is a flowchart illustrating an example of a method executed by a storage device.

[0024] Throughout the accompanying drawings and detailed description, unless otherwise described or provided, the same reference numerals may refer to the same elements, features, and structures. The drawings may not be drawn to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be enlarged. Detailed Implementation

[0025] In the following description, embodiments will be described in detail with reference to the accompanying drawings. When describing embodiments with reference to the accompanying drawings, the same reference numerals denote the same elements, and repeated descriptions related to them will be omitted.

[0026] Figure 1 This is a block diagram illustrating an example configuration of a storage device according to some implementation methods. (See also...) Figure 1The storage device 100 may include a memory cell array 110 and peripheral circuitry 120. Peripheral circuitry 120 may include a voltage generator 121, an address decoder 122, control logic 123, and a page buffer circuit 124. Peripheral circuitry 120 may also include... Figure 1 Additional components not shown (e.g., column logic, pre-decoder, temperature sensor, command decoder, address decoder, and input / output interface). Although Figure 1 Not shown, but the storage device 100 may also include a controller (e.g., a memory controller) configured to control the storage device 100. For example, the controller may control programming, reading, and erasing operations for the memory cell array 110 in response to requests from a host device (e.g., a processor, such as a central processing unit (CPU)).

[0027] The memory cell array 110 can be connected to the page buffer circuit 124 via the bit line BL, and can be connected to the address decoder 122 via the serial select line SSL, the word line WL, and the ground select line GSL.

[0028] The storage cell array 110 may include storage cells. Multiple bits of data may be stored in each storage cell. For example, a storage cell may be a flash memory cell. In this case, storage device 100 may correspond to a flash memory device. In this case, storage device 100 may be a non-volatile storage device, such as a solid-state drive (SSD) and a universal serial bus (USB) drive. Examples of storage cells being NAND flash memory cells may be described below, but the examples are not limited thereto. For example, storage cells may be different types of storage cells, such as resistive random access memory (ReRAM), phase-change RAM (PRAM), ferroelectric RAM (FRAM), or magnetic RAM (MRAM).

[0029] The memory cell array 110 may include a 3D cell array. The 3D cell array may include cell strings. Each cell string may include a memory cell. The memory cells of each cell string may be connected to word lines WL vertically stacked on a substrate. The memory cell array 110 may be divided into memory blocks. Each memory block may include a 3D cell array of a predetermined size.

[0030] Control logic 123 can generate various control signals for programming, reading, and erasing operations. For example, control signals may include voltage control signals, address signals, etc. Control logic 123 typically controls various operations within the storage device 100.

[0031] Voltage generator 121, under the control of control logic 123, can generate various voltages for performing programming, reading, and erasing operations on memory cell array 110. For example, voltage generator 121 can generate word line voltage VWL. Voltage generator 121 can generate programming voltage, read voltage, pass voltage, erase verification voltage, and programming verification voltage. Furthermore, voltage generator 121, under the control of control logic 123, can generate serial select line voltage and ground select line voltage. Additionally, voltage generator 121 can generate one or more voltages to drive or control page buffer circuitry 124. For example, voltage generator 121 can generate a trimming voltage V_Trim provided to each page buffer of page buffer circuitry 124.

[0032] Address decoder 122 can perform selection operations on word line WL and string selection line SSL based on address signals (e.g., row address signals). Page buffer circuit 124 can perform selection operations on bit line BL based on address signals (e.g., column address signals). Each page buffer PB of page buffer circuit 124 can operate as a write driver or a sense amplifier depending on the operating mode.

[0033] Page buffer circuit 124 may include page buffers connected to bit lines BL. Each page buffer may be connected to a corresponding bit line in the bit lines BL. Page buffer circuit 124 may temporarily store data read from memory cell array 110 and data to be programmed into memory cell array 110.

[0034] Each page buffer may include at least one latch. Each latch may temporarily store data. For example, each latch may include a sense latch. The sense latch may be connected to a sense node. During data sensing operations, the bit lines and the sense node (e.g., the sense capacitor of the sense node) may be precharged, the voltage of the sense node may evolve (e.g., change) according to the logical state of the data stored in the memory cell, and as the voltage of the sense node evolves, data may be stored in the sense latch connected to the sense node.

[0035] Data sensing can be performed using the switching operations of a sense latch. Switching operations can be based on pull-up and pull-down operations of p-type metal-oxide-semiconductor (PMOS) transistors and n-type MOS (NMOS) transistors. Switching levels can be defined for switching operations, and data with different logic states can be stored in the sense latch based on whether the voltage of the evolving sense node is less than or greater than the switching level. Process voltage-temperature (PVT) variations in PMOS and NMOS transistors can cause variations in switching levels. These variations in switching levels can hinder ensuring the required sensing margin (e.g., sensing margin for low-power operation).

[0036] In some implementations, a trimmer transistor circuit added to the sense latch circuitry is used to adjust the switching level of the sense latch. More specifically, each page buffer of the page buffer circuitry 124 may include a sense latch circuitry, and the sense latch circuitry of the page buffer may include a sense latch and a trimmer transistor circuitry. The trimmer transistor circuitry can adjust the switching level of the sense latch based on a trimmer voltage V_Trim. Therefore, the required sensing margin can be ensured.

[0037] In some implementations, during the calibration step, a sample sense latch circuit corresponding to the sense latch circuit is used to automatically determine the trim voltage V_Trim. The sample sense latch circuit may have the same configuration and structure as the sense latch circuit. The voltage that causes the sample sense latch to switch at the target switching level can be determined as the trim voltage V_Trim, and the switching operation of the sense latch can be induced by providing the trim voltage V_Trim to the sense latch circuit. The sense latch circuit and the sample sense latch circuit may be fabricated on the same wafer. The PVT changes of the sense latch circuit and the sample sense latch circuit may have corresponding levels. Therefore, the switching operation of the sense latch circuit can be induced using the same trim voltage that causes the sample sense latch circuit to switch.

[0038] Figure 2 This is a circuit diagram illustrating an example configuration of memory blocks in a memory cell array according to some implementation methods. (Refer to...) Figure 2 A memory block BLK may include a string of cells STR formed between the bit line BL and the common source line CSL. Each string of cells may include a string select transistor SST, a memory cell MC, and a ground select transistor (GST). The memory block BLK may be an array of memory cells (e.g., Figure 1 One of the storage blocks in the storage cell array 110.

[0039] The series select transistor SST can be connected to the series select line SSL. The ground select transistor GST can be connected to the ground select line GSL. The series select transistor SST can be connected to the bit line BL, and the ground select transistor GST can be connected to the common source line CSL.

[0040] Memory cells MC can be connected to word lines WL. Word lines WL can be located above ground select lines GSL. Memory cells MC with the same or substantially similar substrate height can be connected to word lines WL. Each word line WL can be a selected word line sWL or an unselected word line uWL. Each memory cell can be a selected memory cell sMC or an unselected memory cell uMC. For example, when the z-th word line is selected from word lines WL, the z-th word line can be sWL, and the other word lines can be uWL. The z-th memory cell connected to the z-th word line can be sMC, and the memory cells connected to the other word lines can be uMC.

[0041] Bit lines BL can be connected to page buffers. Each page buffer can be connected to the corresponding bit line in the bit line BL.

[0042] Figure 3 This is a circuit diagram of an example configuration of a cell string of a storage block according to some implementation methods. Figure 3 It can correspond to in Figure 2 An example of selecting the x-th bit line BLx, the y-th unit string STRy, and the z-th word line WLz from the storage block BLK. (See also...) Figure 3 The y-th unit string STRy can be selected by the y-th string selection line SSLy and the y-th ground selection line GSLy. The z-th memory unit MCz can be selected by the z-th word line WLz. The z-th word line WLz can correspond to the selected word line, and the other word lines of the y-th unit string STRy can correspond to the unselected word lines. The z-th memory unit MCz can correspond to the selected memory unit, and the other memory units of the y-th unit string STRy can correspond to the unselected memory units.

[0043] The y-th cell string STRy may include memory cells. The x-th page buffer PBx can be connected to the y-th cell string STRy via the x-th bit line BLx. The x-th page buffer PBx may include one or more latch circuits. For example, the latch circuit may include a sensing latch circuit. The x-th page buffer PBx can use the sensing latch circuit to sense data in a selected memory cell (e.g., the z-th memory cell MCz).

[0044] Figure 4 This is a circuit diagram showing an example configuration of a sense latch circuit including a first trimmer transistor circuit and a second trimmer transistor circuit, according to some implementations. (Refer to...) Figure 4 The sensing latch circuit SL may include a sensing latch LAT, a first trimming transistor circuit TTC1, a second trimming transistor circuit TTC2, a latch setting transistor STT, and a sensing transistor ST. Although Figure 4 The sensor latch circuit SL may include other components, such as a latch reset transistor, but is not shown in the diagram.

[0045] The sense latch LAT can be located between latch node LAT_N and inverter latch node ILAT_N, and can include a first inverter INV1 and a second inverter INV2. The first inverter INV1 and the second inverter INV2 can each include a PMOS transistor and an NMOS transistor.

[0046] The latch set transistor STT receives the latch set signal SET_S via its gate. STT sets the latch node LAT_N based on the SET_S signal. The sense transistor ST is positioned between the latch node LAT_N and ground. The gate of the sense transistor ST is connected to the sense node SO_N. Both the latch set transistor STT and the sense transistor ST can be composed of NMOS transistors.

[0047] The first trimmer transistor circuit TTC1 and the second trimmer transistor circuit TTC2 can form a trimmer transistor circuit. The trimmer transistor circuit can adjust the switching level of the sense latch LAT based on a trimmer voltage. The trimmer voltage can be provided by a voltage generator 121. The trimmer voltage can include a first trimmer voltage V_Trim1 and a second trimmer voltage V_Trim2. The first trimmer transistor circuit TTC1 can be electrically connected to the PMOS transistor of the first inverter INV1. The second trimmer transistor circuit TTC2 can be electrically connected to the sense transistor ST.

[0048] The first fine-tuning transistor circuit TTC1 can be located between the power supply terminal and the PMOS transistor of the first inverter INV1, or between the PMOS transistor of the first inverter INV1 and the NMOS transistor of the first inverter INV1. Figure 4 An example is shown where the first trimmer transistor circuit TTC1 is disposed between the power supply terminal and the PMOS transistor of the first inverter INV1. Although not shown, it should be understood that the first trimmer transistor circuit TTC1 may be disposed between the PMOS transistor and the NMOS transistor of the first inverter INV1.

[0049] The first trimmer transistor circuit TTC1 may include one or more first trimmer transistors. The first trimmer transistor may receive a first trimmer voltage V_Trim1 via its gate. The first trimmer transistor may be a PMOS transistor. The first trimmer transistor circuit TTC1 may include multiple first trimmer transistors, and the multiple first trimmer transistors may be connected in series or in parallel.

[0050] The second trimmer transistor circuit TTC2 can be located between the latch node LAT_N and the ground terminal. For example, the second trimmer transistor circuit TTC2 can be located between the sensing transistor ST and the ground terminal, or between the latch node LAT_N and the sensing transistor ST. Figure 4 An example is shown where the second trimmer transistor circuit TTC2 is positioned between the sensing transistor ST and the ground terminal. Although Figure 4 Not shown, but it should be understood that the second trimmer transistor circuit TTC2 can be located between the latch node LAT_N and the sensing transistor ST.

[0051] The second trimmer transistor circuit TTC2 may include one or more second trimmer transistors. Each second trimmer transistor may receive a second trimmer voltage V_Trim2 via its gate. The second trimmer transistor may be an NMOS transistor. The second trimmer transistor circuit TTC2 may include multiple second trimmer transistors, and these multiple second trimmer transistors may be connected in series or in parallel.

[0052] The PMOS transistor of the first inverter INV1 can perform a pull-up operation, and the sensing transistor ST can perform a pull-down operation. The sense latch LAT can switch based on a P / N conflict arising from the pull-up operation of the PMOS transistor of the first inverter INV1 and the pull-down operation of the sensing transistor ST. The P / N conflict may be affected by changes in the PVT of the sensing transistor ST and the PMOS transistor, and changes in PVT may cause changes in the switching level of the sense latch LAT. Changes in the switching level may prevent ensuring the required sensing margin (e.g., sensing margin for low-power operation). In some embodiments, the required sensing margin is ensured by adjusting the P / N strength using a trimmer transistor circuit.

[0053] Figure 5 This is a graph illustrating the variations in turn-on margin, turn-off margin, and switching level according to some embodiments. (Refer to...) Figure 5 During data sensing operations, the sensing node connected to the selected bit line of the page buffer is shown (e.g., Figure 4 The voltage "Selected.vSO (also referred to as Sel.vSO in this disclosure)" of the SO_N and the voltage "Unselected.vSO (also referred to as Unsel.vSO in this disclosure)" of the sensing node connected to the unselected bit line in the page buffer. During data sensing operation, the voltage of the bit line (e.g., SO_N) can be adjusted. Figure 3 The BLx in the memory and the sensing node are precharged. The voltage of the sensing node can be developed based on the logical state of the data stored in the memory cell, and the data can be stored in the sensing latch LAT (e.g., based on the development of the sensing node voltage) connected to the sensing node. Figure 4 In the LAT shown, the voltage Sel.vSO can be different when the selected memory cell is an on cell and when the selected memory cell is an off cell. If the voltage Sel.vSO is greater than the switching level, the sense latch LAT can switch, and if the voltage Sel.vSO is less than the switching level, the sense latch LAT can not switch.

[0054] The PVT variation of the transistors involved in the switching operation of the sense latch LAT can cause a change in the switching level. This change in switching level can hinder the assurance of the required sensing margin (e.g., sensing margin for low-power operation). In some implementations, a fine-tuning voltage can be applied to the fine-tuning transistor circuits TTC1 and TTC2 of the sense latch circuit SL to switch the sense latch LAT when it is in the off state, and the switching operation of the sense latch circuit SL can be performed as the fine-tuning voltage is applied. Since the switching operation can be performed at the target switching level by applying a fine-tuning voltage, the effect of reducing switching level variation can be achieved, and sensing margin can be ensured.

[0055] Figure 6 and Figure 7 This is an example configuration of a sense latch circuit diagram according to some embodiments, having a first trimmer transistor circuit and a trimmer transistor circuit, specifically a trimmer transistor circuit of one of the second trimmer transistor circuits. See reference... Figure 4 The fine-tuning transistor circuit may include at least one of a first fine-tuning transistor circuit TTC1 and a second fine-tuning transistor circuit TTC2. Figure 4 The sensor latch circuit SL is shown, comprising both a first trimmer transistor circuit TTC1 and a second trimmer transistor circuit TTC2. Figure 4 different, Figure 6 A sense latch circuit SL is shown, including a first fine-tuning transistor circuit TTC1 but excluding a second fine-tuning transistor circuit TTC2. Figure 7 A sense latch circuit SL is shown, which includes a second trimmer transistor circuit TTC2 but does not include a first trimmer transistor circuit TTC1.

[0056] Reference Figure 6 The sense latch circuit SL may include a sense latch LAT and a first trimmer transistor circuit TTC1, wherein the sense latch LAT includes a first inverter INV1 and a second inverter INV2, and the first trimmer transistor circuit TTC1 is electrically connected to the PMOS transistor of the first inverter INV1 and is configured to adjust the switching level of the sense latch LAT based on a first trimmer voltage V_Trim1. (Refer to...) Figure 7The sensing latch circuit SL may include a sensing latch LAT disposed between latch node LAT_N and inverting latch node ILAT_N, a sensing transistor ST disposed between latch node LAT_N and ground terminal, and a second fine-tuning transistor circuit TTC2 connected in series with the sensing transistor ST and configured to adjust the switching level of the sensing latch LAT based on the second fine-tuning voltage V_Trim2.

[0057] Figure 8 This is a circuit diagram of an example configuration of a sense latch circuit using parallel trimmer transistors, based on some implementation methods. (Refer to...) Figure 8 The first trimmer transistor circuit TTC1 may include first trimmer transistors TT11, TT12, and TT13 connected in parallel. The first trimmer transistors TT11, TT12, and TT13 may be connected in parallel to the PMOS transistor of the first inverter INV1, and each trimmer transistor may receive a first trimmer voltage V_Trim1[0:2] via its gate. The first trimmer transistors TT11, TT12, and TT13 may be PMOS transistors. The second trimmer transistor circuit TTC2 may include second trimmer transistors TT21, TT22, and TT23 connected in parallel. The second trimmer transistors TT21, TT22, and TT23 may be connected in parallel to the sensing transistor ST, and each trimmer transistor may receive a second trimmer voltage V_Trim2[0:2] via its gate. The second trimmer transistors TT21, TT22, and TT23 may be NMOS transistors. The first trimmer voltage V_Trim1[0:2] and the second trimmer voltage V_Trim2[0:2] may be digital signals and may be generated by control logic (e.g., control logic 123).

[0058] The first trimmer transistor circuit TTC1 and the second trimmer transistor circuit TTC2 can use the first trimmer voltage V_Trim1[0:2] and the second trimmer voltage V_Trim2[0:2] to adjust the switching level of the sense latch LAT. The first trimmer transistors TT11, TT12, TT13 and the second trimmer transistors TT21, TT22, TT23 can be controlled on or off based on the first trimmer voltage V_Trim1[0:2] and the second trimmer voltage V_Trim2[0:2], respectively, and the switching level of the sense latch LAT can be adjusted based on the on or off states of the first trimmer transistors TT11, TT12, TT13 and the second trimmer transistors TT21, TT22, TT23. For example, when a voltage corresponding to a digital high level is applied to the first trimmer transistors TT11, TT12, and TT13 and the second trimmer transistors TT21, TT22, and TT23, the first trimmer transistors TT11, TT12, and TT13 and the second trimmer transistors TT21, TT22, and TT23 can be in the on state. When a voltage corresponding to a digital low level is applied to the first trimmer transistors TT11, TT12, and TT13 and the second trimmer transistors TT21, TT22, and TT23, the first trimmer transistors TT11, TT12, and TT13 and the second trimmer transistors TT21, TT22, and TT23 can be in the off state.

[0059] The fine-tuning transistor circuit may include at least one of the first fine-tuning transistor circuit TTC1 and the second fine-tuning transistor circuit TTC2. Figure 8 The diagram illustrates a sense latch circuit SL that includes both a first trimmer transistor circuit TTC1 and a second trimmer transistor circuit TTC2. The sense latch circuit SL may include the first trimmer transistor circuit TTC1 but may not include the second trimmer transistor circuit TTC2 (e.g., ...). Figure 6 (as shown), or may include a second trimmer transistor circuit TTC2 and may not include the first trimmer transistor circuit TTC1 (as shown). Figure 7 (As shown).

[0060] Figure 9 This is a circuit diagram of an example configuration of a sense latch circuit, including a second trimmer transistor circuit located between the latch node and the sense transistor, according to some implementations. (Refer to...) Figure 9The first trimmer transistor circuit TTC1 may include a first trimmer transistor TT1 located between the power supply terminal and the first inverter INV1, the first trimmer transistor TT1 being configured to receive a first trimmer voltage V_Trim1 via its gate. The second trimmer transistor circuit TTC2 may include a second trimmer transistor TT2 located between the latch node LAT_N and the sensing transistor ST, the second trimmer transistor TT2 being configured to receive a second trimmer voltage V_Trim2 via its gate.

[0061] Figure 9 The diagram illustrates a sense latch circuit SL that includes both a first trimmer transistor circuit TTC1 and a second trimmer transistor circuit TTC2. The sense latch circuit SL may include the first trimmer transistor circuit TTC1 but may not include the second trimmer transistor circuit TTC2 (e.g., ...). Figure 6 (as shown), or may include a second trimmer transistor circuit TTC2 and may not include the first trimmer transistor circuit TTC1 (as shown). Figure 7 (As shown).

[0062] Figure 10 This is a circuit diagram of an example configuration of a sense latch circuit, including a first trimmer transistor circuit located inside the inverter of the sense latch, according to some embodiments. (Refer to...) Figure 10 The sensing latch (LAT) may include a first inverter (INV1) and a second inverter (INV2). Each of the first inverters (INV1 and INV2) may include a PMOS transistor and an NMOS transistor. The first trimmer transistor circuit (TTC1) may include a first trimmer transistor (TT1) disposed between the PMOS transistor and the NMOS transistor of the first inverter (INV1). The first trimmer transistor (TT1) may be electrically connected to both the PMOS transistor and the NMOS transistor of the first inverter (INV1). A second trimmer transistor (TT2) may be disposed between the sensing transistor (ST) and the ground terminal.

[0063] Figure 10 The diagram illustrates a sense latch circuit SL that includes both a first trimmer transistor circuit TTC1 and a second trimmer transistor circuit TTC2. The sense latch circuit SL may include the first trimmer transistor circuit TTC1 but may not include the second trimmer transistor circuit TTC2 (e.g., ...). Figure 6 (as shown), or may include a second trimmer transistor circuit TTC2 and may not include the first trimmer transistor circuit TTC1 (as shown). Figure 7 (As shown).

[0064] Figure 11This is a circuit diagram of an example configuration of a sense latch circuit including a first trimmer transistor circuit and a second trimmer transistor circuit, according to some embodiments. Both the first and second trimmer transistor circuits include at least one trimmer transistor. (Refer to...) Figure 11 The first trimmer transistor circuit TTC1 may include first trimmer transistors TT11 and TT12 connected in series. TT11 and TT12 may be connected in series to a PMOS transistor, and each trimmer transistor may receive a first trimmer voltage V_Trim1 via its gate. The second trimmer transistor circuit TTC2 may include second trimmer transistors TT21 and TT22 connected in series. TT21 and TT22 may be connected in series to a sensing transistor ST, and each trimmer transistor may receive a second trimmer voltage V_Trim2 via its gate.

[0065] Figure 11 The diagram illustrates a sense latch circuit SL that includes both a first trimmer transistor circuit TTC1 and a second trimmer transistor circuit TTC2. The sense latch circuit SL may include the first trimmer transistor circuit TTC1 but may not include the second trimmer transistor circuit TTC2 (e.g., ...). Figure 6 (as shown), or may include a second trimmer transistor circuit TTC2 and may not include the first trimmer transistor circuit TTC1 (as shown). Figure 7 (As shown).

[0066] Figure 12 This is a circuit diagram of an example configuration for performing a calibration step using a sample sensing latch circuit according to some implementation methods. (Refer to...) Figure 12 Storage devices (e.g., Figure 1 The storage device 100 may include a sensing latch circuit SL (e.g., Figure 4 and Figures 6 to 11 The sample sensing latch circuit SASL corresponds to the sensing latch LAT. The sample sensing latch circuit SASL can have the same configuration and structure as the sensing latch circuit SL. The sample sensing latch circuit SASL may include a sample sensing latch SLAT corresponding to the sensing latch LAT and a trimmer transistor circuit TTC (e.g., Figure 4 and Figures 6 to 11 The corresponding sample fine-tuning transistor circuit STTC for TTC1 and TTC2.

[0067] In some implementations, a calibration step is performed to determine the trimming voltage V_Trim. The calibration step can be performed once, periodically, or irregularly. For example, the calibration step can be performed at a predetermined time (e.g., chip drive time, wafer production time, etc.). If calibration is performed during chip drive time, jump level variations due to temperature changes can be compensated. If calibration is performed on each wafer during wafer production time, jump level variations due to the process characteristics of each wafer can be compensated. As another example, the calibration step can be performed according to a predetermined calibration cycle. As another example, the calibration step can be performed when predetermined conditions (e.g., temperature changes, voltage changes, etc.) are met. In the calibration step, control logic 123 can use the sample sensing latch circuit SASL to determine the trimming voltage V_Trim.

[0068] During the calibration step, a voltage V_TTL of the target transition level can be applied to the sample sensing transistor SAST of the sample sensing latch circuit SASL, such as... Figure 12 As shown. Control logic 123 can provide a sample trimming voltage V_Trim_S to the sample trimming transistor circuit STTC of the sample sensing latch SLAT, and adjust the sample trimming voltage V_Trim_S while applying a target transition level voltage V_TTL to the sample sensing transistor SAST. For example, control logic 123 can sequentially increase or decrease the sample trimming voltage V_Trim_S.

[0069] Control logic 123 can use a trim code (Trim_code) to adjust the sample trim voltage V_Trim_S. Storage device 100 may include a digital-to-analog converter (DAC) 1210, a voltage generator 121, and a switch 1220. Control logic 123 can generate a trim code (Trim_code). The trim code (Trim_code) can be an n-bit digital control signal. DAC 1210 can convert the trim code (Trim_code) into the sample trim voltage V_Trim_S. Control logic 123 can adjust the sample trim voltage V_Trim_S by changing the trim code (Trim_code).

[0070] The adjusted sample trimming voltage V_Trim_S can trigger a switching operation of the sample sensing latch SLAT. When the switching operation of the sample sensing latch SLAT occurs, the control logic 123 can store the trimming code Trim_code of the sample trimming voltage V_Trim_S that caused the switching operation of the sample sensing latch SLAT as a calibration result.

[0071] In some implementations, the sample sensing latch circuit LA includes both a first sample trimming transistor circuit TTC1 and a second sample trimming transistor circuit TTC2 (e.g., corresponding to...). Figure 9The sensing latch circuit SL in the middle. The sample trimming voltage V_Trim_S may include at least one first sample trimming voltage V_Trim1_S and / or at least one second sample trimming voltage V_Trim2_S. In some embodiments, the first sample trimming transistor circuit STTC1 includes two or more sample first trimming transistors (e.g., corresponding to Figure 8 The sensing latch circuit SL in the middle, and the first sample trimming voltage V_Trim1_S that causes the switching operation can be different for different samples of the first trimming transistor.

[0072] When the calibration step is terminated, control logic 123 can provide the stored trim code Trim_code to DAC 1210. DAC 1210 can convert the trim code Trim_code into a sample trim voltage V_Trim_S. Voltage generator 121 can generate the trim voltage V_Trim by amplifying the sample trim voltage V_Trim_S.

[0073] The sense latch circuit SL and the sample sense latch circuit SASL can be fabricated on the same wafer. The PVT changes in the sense latch circuit and the PVT changes in the sample sense latch circuit SASL can have corresponding voltage levels. Therefore, a fine-tuning voltage that causes the sample sense latch circuit SASL to switch can trigger a switching operation in the sense latch circuit SL.

[0074] Switch 1220 can enable or disable the trimmer transistor circuit TTC. To enable the trimmer transistor circuit TTC, switch 1220 can provide a trimmer voltage V_Trim to the trimmer transistor circuit TTC. To disable the trimmer transistor circuit TTC, switch 1220 can provide a weak voltage (e.g., the voltage that turns off the PMOS transistor) to the trimmer transistor circuit TTC. When the trimmer transistor circuit TTC is disabled, the page buffer PB can operate as if the trimmer transistor circuit TTC is not present. Switch 1220 can be operated under the control of control logic 123.

[0075] When the calibration step is terminated, the Sample Sensing Latch (SASL) circuit can be disabled to reduce power consumption. For example, the PMOS transistor in the inverter of the SLAT can be biased to reduce the constant current generated when the SLAT flips, thereby lowering the PMOS transistor. Additionally, the system power consumption and power noise of the page buffer PB can be reduced. As another example, when the chip is in standby mode, the off-state current of the sense latch LAT can be reduced by biasing the gate of the PMOS transistor in the inverter of the SLAT. The standby power of the chip can be reduced by suppressing the gate-induced drain leakage (GIDL) current of the sense latch LAT.

[0076] For reference Figure 8 The fine-tuning voltage V_Trim can correspond to a digital signal. In this case, DAC 1210 may not be used. The fine-tuning voltage V_Trim can correspond to the sample fine-tuning voltage V_Trim_S. During the calibration step, control logic 123 can find and store the trimming code Trim_code that causes the sample sensing latch SLAT to switch at the target switching level. When the calibration step is terminated, control logic 123 can provide the stored trimming code Trim_code to the voltage generator 121 associated with the sample fine-tuning voltage V_Trim_S. The voltage generator 121 can generate the fine-tuning voltage V_Trim by amplifying the sample fine-tuning voltage V_Trim_S.

[0077] Figure 13 This is a circuit diagram of an example configuration of a page buffer according to some implementation methods. (Refer to...) Figure 13 The x-th page buffer PBx can be connected to the x-th bit line Blx. The z-th memory cell MCz (which is the selected memory cell sMC) can be connected to the x-th bit line Blx. The z-th word line WLz (which is the selected word line sWL) can be connected to the z-th memory cell MCz. The x-th bit line BLx can be connected to the common source line CSL through the z-th memory cell MCz.

[0078] The first NMOS transistor NM1 may be included between the x-th bit line BLx and the first node N1. The first NMOS transistor NM1 may be a bit line select transistor driven by the bit line select signal BLSLT. The bit line select transistor may be implemented as a high-voltage transistor. The bit line select transistor may be located in the high-voltage region.

[0079] The second NMOS transistor NM2 can be included between the first node N1 and the second node N2. The second NMOS transistor NM2 can be a bit-line turn-off transistor driven by the bit-line turn-off signal BLSHF. The third NMOS transistor NM3 can be included between the second node N2 and the third node N3. The third NMOS transistor NM3 can be a bit-line clamping transistor driven by the bit-line clamping control signal BLCLAMP. The fourth NMOS transistor NM4 can be included between the second node N2 and the readout node SO_N. The fourth NMOS transistor NM4 can be a bit-line connected transistor driven by the bit-line connection control signal CLBLK.

[0080] A first PMOS transistor PM1 may be included between the sensing node SO_N and the power supply terminal. The first PMOS transistor PM1 may be a precharged load transistor driven by the load signal LOAD. A second PMOS transistor PM2 may be included between the sensing node SO_N and the third node N3. The second PMOS transistor PM2 may be a bit line set transistor driven by the bit line set signal BLSETUP. A third PMOS transistor PM3 may be included between the third node N3 and the power supply terminal. The third PMOS transistor PM3 may be a precharged transistor driven by an inverting latch node.

[0081] The sensing latch circuit SL, the forced latch circuit FL, the high-order latch circuit ML, and the low-order latch circuit LL can be connected to the sensing node SO_N. The sensing latch circuit SL can store data stored in the selected memory cell sMC or the sensing result of the threshold voltage of the selected memory cell sMC during read or program verification operations. Furthermore, the sensing latch circuit SL can be used to apply a programming bit line voltage or a programming inhibit voltage to the x-th bit line BLx during programming operations. The forced latch circuit FL can be used to improve the threshold voltage distribution during programming operations. The high-order latch circuit ML and the low-order latch circuit LL can be used to store data input from an external source during programming operations.

[0082] Figure 14 This is a flowchart illustrating an example of a method executed by a storage device according to some embodiments. (Refer to...) Figure 14 In operation 1410, the memory device can apply a voltage of a target transition level to the sample sensing transistor of the sample sensing latch circuit corresponding to the sense latch circuit of the page buffer. In operation 1420, the memory device can provide a sample fine-tuning voltage to the sample fine-tuning transistor circuit of the sample sensing latch circuit, and adjust the sample fine-tuning voltage while applying the voltage of the target transition level to the sample sensing transistor. In operation 1430, the memory device can control the fine-tuning voltage provided to the fine-tuning transistor circuit of the sense latch circuit based on the sample fine-tuning voltage that causes the transition operation of the sample sensing latch of the sample sensing latch circuit at the target transition level.

[0083] Although this disclosure contains many specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, different features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. Furthermore, although the foregoing features may be described as functioning in certain combinations, in some cases, one or more features in a combination may be removed from the combination, and a combination may refer to a sub-combination or a variation of a sub-combination.

[0084] Although various examples have been described with reference to the accompanying drawings, the concepts described herein may be implemented in other specific forms without departing from the scope of this disclosure. Therefore, the examples described above should be considered illustrative. For example, suitable results may be achieved if the techniques disclosed in this disclosure are performed in a different order, and / or if the components in the system, architecture, device, or circuit are combined in different ways, and / or replaced or supplemented by other components or their equivalents.

Claims

1. A storage device, comprising: A string of cells, including storage units; as well as A page buffer, connected to the cell string via bit lines, includes a sense latch circuitry configured to sense data in a selected memory cell via the sense latch circuitry. The sensing latch circuit includes: The sensing latch includes a first inverter and a second inverter; and A fine-tuning transistor circuit is electrically connected to the p-type metal-oxide-semiconductor (PMOS) transistor of the first inverter and is configured to adjust the switching level of the sensing latch based on the fine-tuning voltage.

2. The storage device according to claim 1, wherein, The trimmer transistor circuit includes: A fine-tuning transistor is disposed between the power supply terminal and the PMOS transistor of the first inverter.

3. The storage device according to claim 1, wherein, The trimmer transistor circuit includes: A fine-tuning transistor is disposed between the PMOS transistor of the first inverter and the n-type metal-oxide-semiconductor NMOS transistor of the first inverter.

4. The storage device according to claim 1, wherein, The trimmer transistor circuit includes: Trimming transistors connected in parallel.

5. The storage device according to claim 1, wherein, The trimmer transistor circuit includes: Series-connected trimmer transistors.

6. The storage device according to claim 1, further comprising: The sample sensing latch circuit includes a sample sensing latch corresponding to the sensing latch and a sample fine-tuning transistor circuit corresponding to the fine-tuning transistor circuit. as well as The control logic is configured to determine the fine-tuning voltage via the sample sensing latch circuit.

7. The storage device according to claim 6, wherein, The control logic is configured to: provide a sample fine-tuning voltage to the sample fine-tuning transistor circuit, adjust the sample fine-tuning voltage while applying a voltage to the sample sensing transistor of the sample sensing latch circuit at a target transition level, and control the fine-tuning voltage based on the adjusted sample fine-tuning voltage that causes a transition operation of the sample sensing latch at the target transition level.

8. A storage device comprising: A string of cells, including storage units; as well as A page buffer, connected to the cell string via bit lines, includes a sense latch circuitry configured to sense data in a selected memory cell via the sense latch circuitry. The sensing latch circuit includes: A sensing latch is positioned between the latch node and the inverting latch node; A sensing transistor is disposed between the latch node and the ground terminal; and A fine-tuning transistor circuit is connected in series with the sensing transistor and is configured to adjust the switching level of the sensing latch based on the fine-tuning voltage.

9. The storage device according to claim 8, wherein, The trimmer transistor circuit includes: A fine-tuning transistor is disposed between the sensing transistor and the ground terminal.

10. The storage device according to claim 8, wherein, The trimmer transistor circuit includes: A fine-tuning transistor is disposed between the latch node and the sensing transistor.

11. The storage device according to claim 8, wherein, The trimmer transistor circuit includes: Trimming transistors connected in parallel.

12. The storage device according to claim 8, wherein, The trimmer transistor circuit includes: Series-connected trimmer transistors.

13. The storage device according to claim 8, further comprising: The sample sensing latch circuit includes a sample sensing latch corresponding to the sensing latch and a sample fine-tuning transistor circuit corresponding to the fine-tuning transistor circuit. as well as The control logic is configured to determine the fine-tuning voltage via the sample sensing latch circuit.

14. The storage device according to claim 13, wherein, The control logic is configured to: provide a sample fine-tuning voltage to the sample fine-tuning transistor circuit, adjust the sample fine-tuning voltage while applying a voltage to the sample sensing transistor of the sample sensing latch circuit at a target transition level, and control the fine-tuning voltage based on the adjusted sample fine-tuning voltage that causes a transition operation of the sample sensing latch at the target transition level.

15. A storage device comprising: A string of cells, including storage units; as well as A page buffer, connected to the cell string via bit lines, includes a sense latch circuitry configured to sense data in a selected memory cell via the sense latch circuitry. The sensing latch circuit includes: A sensing latch is disposed between a latch node and an inverting latch node, and includes a first inverter and a second inverter; A sensing transistor is disposed between the latch node and the ground terminal; and The fine-tuning transistor circuit is configured to adjust the switching level of the sensing latch based on the fine-tuning voltage. The fine-tuning transistor circuit includes: The first fine-tuning transistor circuit is electrically connected to the p-type metal-oxide-semiconductor (PMOS) transistor of the first inverter, and The second fine-tuning transistor circuit is electrically connected to the sensing transistor.

16. The storage device according to claim 15, wherein, The first trimmer transistor circuit includes: The first fine-tuning transistor is disposed between the power supply terminal and the PMOS transistor of the first inverter, or between the PMOS transistor of the first inverter and the n-type metal-oxide-semiconductor NMOS transistor of the first inverter.

17. The storage device according to claim 15, wherein, The second fine-tuning transistor circuit includes: The second fine-tuning transistor is disposed between the sensing transistor and the ground terminal or between the latch node and the sensing transistor.

18. The storage device according to claim 15, wherein, The first trimmer transistor circuit includes first trimmer transistors connected in parallel, or The second trimmer transistor circuit includes second trimmer transistors connected in parallel.

19. The storage device according to claim 15, wherein, The first trimmer transistor circuit includes a first trimmer transistor connected in series, or The second trimmer transistor circuit includes a second trimmer transistor connected in series.

20. The storage device of claim 15, further comprising: The sample sensing latch circuit includes a sample sensing latch corresponding to the sensing latch and a sample fine-tuning transistor circuit corresponding to the fine-tuning transistor circuit. as well as The control logic is configured to use the sample sensing latch circuit to determine the fine-tuning voltage.

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