Self-correctable digital-to-analog conversion circuit and digital-to-analog converter correction method

Abstract

The invention provides a digital-to-analog conversion circuit capable of self-correction and a correction method of a digital-to-analog converter. The circuit comprises a resistance circuit, a buffer amplifier, a fine tuning circuit and a correction switching circuit. In the normal operation mode, the resistance circuit receives the common voltage for conversion. In the correction mode, the circuit carries out self-correction in two steps: sampling time and comparison time. In sampling time, the resistance circuit receives a reference voltage and a first correction digital value, and the input end of the buffer amplifier samples the voltage. And at the comparison time, the resistance circuit receives the common voltage and the second correction digital value, the fine tuning circuit adjusts the correction data until the output voltage of the buffer amplifier is overturned, and the correction value is recorded to correspond to the second correction digital value. By means of the self-correction mechanism, the circuit can output theoretically correct digital-analog conversion results under the reference voltage and the common voltage.

Description

Technical Field

[0001] This application relates to a technology for a digital-to-analog converter, and more particularly to a self-calibrating digital-to-analog converter circuit and a calibration method for the digital-to-analog converter. Background Technology

[0002] In the design of digital and analog systems, digital-to-analog converters (DACs) play a crucial role in converting digital information into analog voltage or analog current. However, due to factors such as process variations and component aging, the output value of a DAC often deviates from the ideal value, leading to a decrease in conversion accuracy. To ensure the performance of the DAC, calibration becomes an indispensable step.

[0003] Traditionally, there are two main methods for calibrating digital-to-analog converters (D / A converters). The first method involves directly measuring the D / A converter's output voltage and then correcting the resistor array. This correction includes using an electronic fuse to blow specific resistors or removing resistors using laser cutting to adjust their values. While this method effectively improves conversion linearity, it requires specialized processes to embed the electronic fuse or laser cutting equipment, significantly increasing manufacturing complexity and cost.

[0004] The second calibration method involves using an additional calibration DAC connected in parallel with the original DAC to compensate for the output deviation of the original DAC. This approach does not require special manufacturing processes, but it does require additional silicon area to house the calibration DAC. Furthermore, the calibration DAC continuously consumes power during operation, increasing the system's power consumption.

[0005] Regardless of the calibration method used, a full code scan of the digital-to-analog converter is required in a controlled measurement environment to accurately measure the output voltage or current corresponding to each digital input. These measurement processes are not only time-consuming and labor-intensive, but also require high-precision testing equipment, such as high-precision digital voltmeters, which keeps calibration costs high.

[0006] Although existing digital-to-analog converter calibration techniques can improve conversion accuracy to some extent, they all suffer from drawbacks such as complex manufacturing processes, large indirect costs (such as area and power consumption), and high testing costs. Therefore, a new low-cost and high-efficiency calibration scheme is needed. Summary of the Invention

[0007] Embodiments of this application provide a self-correcting digital-to-analog converter circuit and a correction method for the digital-to-analog converter, used to correct output inaccuracies caused by impedance drift within the digital-to-analog converter circuit.

[0008] Embodiments of this application provide a self-calibrating digital-to-analog converter circuit, which includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a calibration switching circuit. The resistor circuit includes multiple bit input terminals, a reference voltage input terminal, an output terminal, and a common calibration terminal, wherein the reference voltage input terminal of the resistor circuit receives a reference voltage. The first input terminal of the fine-tuning circuit is coupled to the output terminal of the resistor circuit, the output terminal of the fine-tuning circuit is coupled to the first input terminal of the buffer amplifier, and the second input terminal of the fine-tuning circuit is coupled to the output terminal of the buffer amplifier. The first terminal of the calibration switching circuit is coupled to the second input terminal of the buffer amplifier, and the second terminal of the calibration switching circuit is coupled to the output terminal of the buffer amplifier.

[0009] In normal operation, the aforementioned self-calibrating digital-to-analog converter circuit has a common voltage input to the common calibration terminal of the resistor circuit, and the first and second terminals of the calibration switching circuit are short-circuited. In calibration mode, the self-calibrating digital-to-analog converter circuit includes a sampling time and a comparison time. During the sampling time, the first and second terminals of the calibration switching circuit are short-circuited, the common calibration terminal of the resistor circuit is input with the reference voltage, and a first calibration digital value is input to multiple bit input terminals of the resistor circuit. The first terminal of the calibration switching circuit samples and temporarily stores the voltage at the second input terminal of the buffer amplifier. During the comparison time, the common calibration terminal of the resistor circuit is input with a common voltage, and a second calibration digital value is input to multiple bit input terminals of the resistor circuit. The first and second terminals of the calibration switching circuit are open-circuited, and the voltage sampled by the first terminal of the calibration switching circuit is output to the second input terminal of the buffer amplifier. During the comparison time, the fine-tuning circuit adjusts a calibration data and adjusts the voltage at the output terminal of the fine-tuning circuit according to the calibration data until the voltage at the output terminal of the buffer amplifier switches from a first saturation voltage to a second saturation voltage.

[0010] The fine-tuning circuit records the correction data when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage, and uses this data as the correction value corresponding to the second correction digital value. When the common correction terminal of the resistor circuit is input with a reference voltage and the resistor circuit is input with the first correction digital value, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage. When the common correction terminal of the resistor circuit is input with a common voltage and the resistor circuit is input with the second correction digital value, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage. The first theoretical voltage is equal to the second theoretical voltage.

[0011] Another embodiment of this application provides a calibration method for a digital-to-analog converter. This calibration method includes: providing a buffer amplifier and a resistor circuit; dividing a calibration time into a sampling time and a comparison time; during the sampling time: controlling the second input terminal of the buffer amplifier to be short-circuited with the output terminal of the buffer amplifier; inputting a first calibration digital value through the resistor circuit and inputting a reference voltage to the common calibration terminal of the resistor circuit, causing the resistor circuit to generate a first voltage, which is output to the first input terminal of the buffer amplifier; sampling the first voltage through the second input terminal of the buffer amplifier; during the comparison time: controlling the second input terminal of the buffer amplifier to be open-circuited with the output terminal of the buffer amplifier; inputting a common voltage to the common calibration terminal of the resistor circuit and inputting a second calibration digital value to the resistor circuit, causing the resistor circuit to generate a second voltage, which is output to the buffer amplifier. The first input terminal of the device; outputting the sampled voltage to the second input terminal of the buffer amplifier; adjusting a correction data, and adjusting the voltage according to the correction data until the voltage at the output terminal of the buffer amplifier switches from a first saturation voltage to a second saturation voltage; and recording the correction data at the time when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage as the correction value corresponding to the second correction digital value, wherein, when the common correction terminal of the resistor circuit is input with the reference voltage, and the resistor circuit is input with the first correction digital value, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage, wherein, when the common correction terminal of the resistor circuit is input with the common voltage, and the resistor circuit is input with the second correction digital value, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage, wherein, the first theoretical voltage is equal to the second theoretical voltage.

[0012] As can be seen from the above embodiments, the self-correcting digital-to-analog converter circuit of this application can automatically correct the conversion accuracy during operation by designing the sampling time and comparison time, and eliminate circuit offset caused by factors such as process changes, component aging or mixing of different digital-to-analog converters.

[0013] To further understand the techniques, methods, and effects of this application, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of this application. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the invention. Attached Figure Description

[0014] The accompanying drawings are provided to enable those skilled in the art to further understand this application and are incorporated in and constitute a part of the specification of this application. The drawings illustrate exemplary embodiments of this application and are used together with the specification of this application to explain the principles of this application.

[0015] Figure 1 The diagram illustrates a circuit block diagram of a self-correcting digital-to-analog converter circuit according to a preferred embodiment of this application.

[0016] Figure 2 The flowchart illustrates a calibration method for a digital-to-analog converter according to a preferred embodiment of this application.

[0017] Explanation of reference numerals in the attached figures:

[0018] 101…Resistor circuit; 102…Buffer amplifier; 103…Fine-tuning circuit; 104…Correction switching circuit; R…Second resistor; 2R…First resistor; X2R…Correction resistor; Scal…Correction switch; Vcom…Common voltage; Vref…Reference voltage; b0~b7…Least significant bit; T1~T15…Most significant bit of thermometer encoding; S1…First switch; S2…Second switch; S3…Third switch; CSP…Sampling capacitor; CTRL…Control circuit; 131…Offset voltage adjustment circuit; 132…Data adjustment circuit; Vout…Voltage at the output of the resistor circuit; Dcal…Correction data; Voffset…Offset voltage; S201~S219…Flow steps of the correction method for a digital-to-analog converter according to a preferred embodiment of the present invention. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of this application, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and description to refer to the same or similar parts. Furthermore, the practices of these exemplary embodiments are merely one way of implementing the design concept of this application, and the following examples are not intended to limit this application.

[0020] Figure 1 The diagram illustrates a self-correcting digital-to-analog converter circuit according to a preferred embodiment of this application. Please refer to... Figure 1This self-calibrating digital-to-analog converter circuit includes a resistor circuit 101, a buffer amplifier 102, a fine-tuning circuit 103, and a calibration switching circuit 104. In this embodiment, the resistor circuit 101 itself is a digital-to-analog converter. In this embodiment, the resistor circuit 101 is implemented with an 8-bit Least Significant Bit (LSB) portion using an R-2R resistor ladder circuit, that is, each second resistor R is coupled between first resistors 2R. In this embodiment, the first resistor is used as a calibration resistor X2R. Under normal operation, the calibration resistor X2R is coupled to the common voltage Vcom through the calibration switch Scal. In calibration mode, the calibration resistor X2R is coupled to the reference voltage Vref through the calibration switch Scal. In other embodiments, in calibration mode, the calibration resistor X2R can be coupled to the common voltage Vcom.

[0021] The 4 Most Significant Bits (MSB) portion is implemented using a thermometer code circuit. Therefore, a preferred embodiment of this application is a 12-bit digital-to-analog converter. Since the thermometer code circuit outputs a sequence of "logic 1s" based on the magnitude of the digit, in this embodiment, the least significant bits b0-b7 represent the thermometer code T0, while T1-T15 vary according to the 4 most significant bits. For example, assuming the most significant bit is 0110, it means T1-T6 are connected to the reference voltage Vref, and the corresponding resistors are input with a logic high voltage; the remaining T7-T15 are connected to a logic low voltage, i.e., a common voltage Vcom. The thermometer code circuit includes an input terminal and an output terminal, wherein the input terminal of the thermometer code circuit is coupled to the last first resistor (i.e.,... Figure 1 The second terminal of the right resistor R connected to switch b7 is connected to the output terminal of the thermometer encoding digital-to-analog converter circuit, which is coupled to the first input terminal of the fine-tuning circuit 103.

[0022] In this embodiment, the correction switching circuit 104 includes a first switch S1, a second switch S2, a third switch S3, a sampling capacitor CSP, and a control circuit CTRL. The control circuit CTRL in this embodiment controls the conduction states of the first switch S1, the second switch S2, and the third switch S3. In this embodiment, the fine-tuning circuit 103 includes an offset voltage adjustment circuit 131 and a data adjustment circuit 132. The first input terminal of the offset voltage adjustment circuit 131 receives the voltage Vout from the output terminal of the resistor circuit. The output terminal of the offset voltage adjustment circuit 131 is coupled to the first input terminal of the buffer amplifier 102, and the second input terminal of the offset voltage adjustment circuit 131 receives data from the data adjustment circuit 132 to adjust the offset voltage.

[0023] As can be seen from the resistor circuit 101 in the above embodiment, this circuit is a segment digital-to-analog converter. The worst case of a segment digital-to-analog converter usually occurs during the transition between the two, which in this embodiment is when 255 (b0 to b7 are all equal to logic 1) is converted to 256 (b0 to b7 are all equal to logic 0, and T1 is logic 1). To correct for the worst case, this embodiment enters a correction mode. At this time, the input digital data is 255. However, the correction resistor X2R is coupled to the reference voltage Vref. Therefore, the output voltage Vout of node N1, under ideal conditions (all components are error-free), will be equal to the output voltage Vout where T1 is logic 1 and the remaining least significant bits b0 to b7 are all logic 0.

[0024] In this embodiment, the correction mode is divided into two time periods: a sampling time and a comparison time. During the sampling time, the control circuit CTRL controls the control switches S1, S2, and S3 to be turned on. At this time, the buffer amplifier 102 acts as a buffer; in other words, the voltage at the output of the buffer amplifier 102 is equal to the voltage at the positive input of the buffer amplifier 102. Additionally, during the sampling time, the correction resistor X2R is coupled to the reference voltage Vref, and a first correction digital value is input to the R-2R resistor ladder circuit, for example, 255, which is the case where b0 to b7 are all equal to logic 1. At this time, the output voltage Vout of the resistor circuit 101 is equivalent to the input 256. At this time, the fine-tuning circuit 103 is not activated, so this voltage Vout is equal to the voltage at the positive input of the buffer amplifier 102. Furthermore, since the positive input and negative input of the buffer amplifier 102 are virtually short-circuited, the voltage at the negative input of the buffer amplifier 102 is also equal to Vout. Therefore, the sampling capacitor CSP can sample the voltage Vout at the positive input terminal of the buffer amplifier 102. In order to distinguish the time of the voltage, the voltage sampled by the sampling capacitor CSP will be represented by the literal Vout[0].

[0025] Next, the calibration mode will enter the comparison time. During the comparison time, the control circuit CTRL controls the first switch S1 to open, and then the terminal of the calibration resistor X2R of the resistor circuit 101 will be input with the common voltage Vcom. At this time, the second calibration digital value is input to multiple bit input terminals of the resistor circuit 101, for example, 256, which means that b0 to b7 are all equal to logic 0, and T1 is logic high voltage, which is the reference voltage Vref. In addition, at this time, the first switch S1 of the calibration switching circuit 104 is controlled to open, and the second switch S2 and the third switch S3 are turned on. The voltage Vout[0] sampled by the sampling capacitor CSP last time will be output to the negative input terminal of the buffer amplifier 102. However, the positive input terminal of the buffer amplifier 102 receives the voltage Vout[1] with T1 being logic 1 (to distinguish the time of the output voltage of the resistor circuit 101, it is represented by the word Vout[1]).

[0026] At this point, those skilled in the art can see that, since the first switch S1 is open, the buffer amplifier 102 is equivalent to a voltage comparator. When the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is greater than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, the output terminal of the buffer amplifier 102 will output a positive saturation voltage; when the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is less than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, the output terminal of the buffer amplifier 102 will output a negative saturation voltage. For ease of explanation, let's assume that the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is greater than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102. At this point, the fine-tuning circuit 103 starts to operate. When the data adjustment circuit 132 of the fine-tuning circuit 103 receives a positive saturation voltage, it will adjust the correction data Dcal output by the data adjustment circuit 132 to a negative direction. At this time, the offset voltage adjustment circuit 131 receives a negative correction data Dcal and will adjust the offset voltage Voffset to a negative voltage. Then, it will continue to receive the voltage at the output terminal of the buffer amplifier 102 and continue to adjust the correction data Dcal and the offset voltage Voffset until the positive saturation voltage turns into a negative saturation voltage. At this time, it means that the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 minus the offset voltage Voffset is very close to the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, which is the voltage sampled last time. Thus, this correction is completed. Afterwards, in normal mode, as long as the data input is 256, the data adjustment circuit 132 of the fine-tuning circuit 103 will directly output the correction data Dcal after the last adjustment, and the offset voltage adjustment circuit 131 will output the corresponding offset voltage Voffset to output correction for this data 256.

[0027] Similarly, suppose the voltage Vout[1] at the positive input terminal of buffer amplifier 102 is less than the voltage Vout[0] at the negative input terminal of buffer amplifier 102. At this time, the fine-tuning circuit 103 starts to operate. When the data adjustment circuit 132 of the fine-tuning circuit 103 receives the negative saturation voltage, it will adjust the correction data Dcal output by the data adjustment circuit 132 in the positive direction. At this time, when the offset voltage adjustment circuit 131 receives the positive correction data Dcal, it will adjust the offset voltage Voffset to a positive voltage. Then, it continues to receive the voltage at the output terminal of buffer amplifier 102 and continues to adjust the correction data Dcal and the offset voltage Voffset until the negative saturation voltage turns into a positive saturation voltage. At this time, it means that the voltage Vout[1] at the positive input terminal of buffer amplifier 102 plus the offset voltage Voffset is very close to the voltage Vout[0] at the negative input terminal of buffer amplifier 102, which is the voltage sampled last time. In this way, the correction is completed. Subsequently, in normal mode, as long as the data input is 256, the data adjustment circuit 132 of the fine-tuning circuit 103 will directly output the correction data Dcal after the last adjustment, and the offset voltage adjustment circuit 131 will output the corresponding offset voltage Voffset to correct the output of this data 256.

[0028] As can be seen from the above embodiments, this self-correcting digital-to-analog converter circuit, through the design of sampling and comparison times, can automatically correct the conversion accuracy during operation, eliminating circuit offsets caused by factors such as process changes, component aging, or the mixing of different digital-to-analog converters. Furthermore, although the above embodiments use 255 as an example of the first correction digital value and 256 as an example of the second correction digital value, those skilled in the art should understand that the main spirit of this invention is that when the common correction terminal of resistor circuit 101 (i.e., the endpoint of correction resistor X2R) is input with a reference voltage Vref, and the first correction digital value is input to resistor circuit 101, the theoretical value of the output voltage Vout of resistor circuit 101 will be equal to the theoretical value of the output voltage Vout of resistor circuit 101 when the common correction terminal of resistor circuit 101 (i.e., the endpoint of correction resistor X2R) is input with a common voltage Vcom, and the second correction digital value is input to resistor circuit 101. Taking the R-2R resistor ladder circuit of this embodiment as an example, if the first correction digital value is 1 (that is, b0 equals logic 1, and b1 to b7 are all equal to logic 0), and the second correction digital value is 2 (that is, b1 equals logic 1, and b0, b2 to b7 are all equal to logic 0), when a reference voltage Vref is input to the terminal of the former correction resistor X2R, the theoretical value of the output voltage Vout of the resistor circuit 101 will be equal to the common voltage Vcom input to the terminal of the latter correction resistor X2R, and the output voltage Vout of the resistor circuit 101. In other words, if the embodiment is changed to have the first correction digital value as 1 and the second correction digital value as 2, the circuit will still operate normally. Therefore, this application is not limited to this.

[0029] Similarly, while the above embodiments appear to use a segmented digital-to-analog converter that combines an R-2R resistor ladder circuit and a thermometer-encoded digital-to-analog converter circuit, those skilled in the art should understand that numerical correction can be performed using either a simple R-2R resistor ladder circuit or a simple thermometer-encoded digital-to-analog converter circuit. This invention is not limited thereto. In other words, how the resistor circuit 101 changes is not the focus of this application, as long as it conforms to the above spirit; this application is not limited to the above-described circuit.

[0030] The above embodiments can be summarized into a correction method for a digital-to-analog converter. Figure 2 The diagram illustrates a calibration method for a digital-to-analog converter according to a preferred embodiment of this application. Please refer to... Figure 2 The calibration method for this digital-to-analog converter includes the following steps:

[0031] Step S201: Begin.

[0032] Step S202: Provide a buffer amplifier and a resistor circuit.

[0033] Step S203: Divide a calibration time into a sampling time and a comparison time.

[0034] Step S204: Enter sampling time.

[0035] Step S205: Short-circuit the second input terminal of the control buffer amplifier with the output terminal of the control buffer amplifier.

[0036] Step S206: A first correction digital value is input from the resistor circuit, and a reference voltage is input to the common correction terminal of the resistor circuit, so that the resistor circuit generates a first voltage and outputs it to the first input terminal of the buffer amplifier.

[0037] Step S207: Sample the first voltage from the second input terminal of the buffer amplifier.

[0038] Step S208: Enter the comparison time.

[0039] Step S209: Open the second input terminal of the buffer amplifier from the output terminal of the buffer amplifier. At this time, the buffer amplifier acts as a comparator.

[0040] Step S210: Input a common voltage to the common correction terminal of the resistor circuit, and input a second correction digital value to the resistor circuit, so that the resistor circuit generates a second voltage and outputs it to the first input terminal of the buffer amplifier.

[0041] Step S211: Output the sampled voltage to the second input terminal of the buffer amplifier.

[0042] Step S212: Determine whether the output voltage of the buffer amplifier is the first saturation voltage or the second saturation voltage. If it is determined to be the first saturation voltage, proceed to step S213. If it is determined to be the second saturation voltage, proceed to step S216.

[0043] Step S213: Adjust the correction data using the first direction, and adjust the voltage accordingly. For example, if the voltage is a positive saturation voltage as described above, adjust the correction data using the negative direction.

[0044] Step S214: Determine whether the voltage at the output of the buffer amplifier has switched from the first saturation voltage to the second saturation voltage. If the determination is negative, return to step S213. If the determination is positive, proceed to step S215.

[0045] Step S215: Record the calibration data. Record the calibration data at the moment when the voltage at the output of the buffer amplifier switches from the first saturation voltage to the second saturation voltage, and use this data as the calibration value corresponding to the second calibration digital value.

[0046] Step S216: Adjust the correction data using the second direction, and adjust the voltage accordingly. For example, if the voltage is a negative saturation voltage as described above, adjust the correction data using the positive direction.

[0047] Step S217: Determine whether the voltage at the output of the buffer amplifier has switched from the second saturation voltage to the first saturation voltage. If the determination is negative, return to step S216. If the determination is positive, proceed to step S218.

[0048] Step S218: Record the calibration data. Record the calibration data at the moment when the voltage at the output of the buffer amplifier switches from the second saturation voltage to the first saturation voltage, and use this data as the calibration value corresponding to the second calibration digital value.

[0049] Step S219: End.

[0050] In summary, the self-calibrating digital-to-analog converter circuit proposed in a preferred embodiment of this application, through the design of sampling and comparison times, can automatically correct conversion accuracy during operation, eliminating circuit deviations caused by factors such as process variations, component aging, or the mixing of different digital-to-analog converters, ensuring long-term stable and reliable conversion accuracy. Furthermore, the calibration process requires no external instruments; it can be completed simply by switching the internal circuit connections, making it convenient and cost-effective. Simultaneously, this circuit retains the structural advantages of traditional resistor-parallel digital-to-analog converters, featuring small size, low power consumption, and good process compatibility. Therefore, the self-calibrating digital-to-analog converter circuit of the preferred embodiment of this application has practical value and can be widely applied in analog / digital systems requiring high precision and high reliability, improving overall system performance and product lifespan.

[0051] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A self-correcting digital-to-analog converter circuit, characterized in that, include: A resistor circuit includes multiple bit input terminals, a reference voltage input terminal, an output terminal, and a common correction terminal, wherein the reference voltage input terminal of the resistor circuit receives a reference voltage. A buffer amplifier includes a first input terminal, a second input terminal, and an output terminal; A fine-tuning circuit includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fine-tuning circuit is coupled to the output terminal of the resistor circuit, the output terminal of the fine-tuning circuit is coupled to the first input terminal of the buffer amplifier, and the second input terminal of the fine-tuning circuit is coupled to the output terminal of the buffer amplifier; and A correction switching circuit includes a first terminal and a second terminal, wherein the first terminal of the correction switching circuit is coupled to the second input terminal of the buffer amplifier, and the second terminal of the correction switching circuit is coupled to the output terminal of the buffer amplifier. In the case of the self-correcting digital-to-analog converter circuit, during normal operation, the common correction terminal of the resistor circuit is input with a common voltage, and the first and second terminals of the correction switching circuit are short-circuited. The self-correcting digital-to-analog converter circuit, in a correction mode, includes: Sampling time: The first and second terminals of the correction switching circuit are short-circuited, wherein the common correction terminal of the resistor circuit is input with the reference voltage, and the plurality of bit input terminals of the resistor circuit are input with a first correction digital value; the first terminal of the correction switching circuit samples and temporarily stores the voltage at the second input terminal of the buffer amplifier; and Comparison time: A common voltage is input to the common correction terminal of the resistor circuit, and a second correction digital value is input to the plurality of bit input terminals of the resistor circuit. The first and second terminals of the correction switching circuit are disconnected, and the voltage sampled by the first terminal of the correction switching circuit is output to the second input terminal of the buffer amplifier. During the comparison time, the fine-tuning circuit adjusts a correction data and adjusts the voltage at its output terminal according to the correction data until the voltage at the output terminal of the buffer amplifier switches from a first saturation voltage to a second saturation voltage. The fine-tuning circuit records the correction data at which the voltage at the output of the buffer amplifier switches from the first saturation voltage to the second saturation voltage, and uses this data as the correction value corresponding to the second correction digital value. Specifically, when the reference voltage is input to the common correction terminal of the resistor circuit, and the resistor circuit receives the first correction digital value, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage. Wherein, the common correction terminal of the resistor circuit is input with the common voltage, and when the resistor circuit is input with the second correction digital value, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage. Wherein, the first theoretical voltage is equal to the second theoretical voltage.

2. The self-correcting digital-to-analog converter circuit as described in claim 1, characterized in that, The resistor circuit includes: A 1R-2R resistor ladder circuit includes: A plurality of switching circuits, wherein each of the plurality of switching circuits includes a control terminal, a first terminal and a second terminal, wherein the first terminal of each of the plurality of switches is coupled to the reference voltage terminal of the resistor circuit to receive the reference voltage, and the control terminals of the plurality of switches are respectively coupled to the plurality of bit input terminals. A plurality of first resistors, wherein each of the plurality of first resistors includes a first terminal and a second terminal, wherein the first terminal of the plurality of first resistors is respectively coupled to the second terminal of the plurality of switching circuits; A plurality of second resistors, wherein each of the plurality of second resistors includes a first terminal and a second terminal, wherein the first terminal of the Kth second resistor is coupled to the second terminal of the Kth first resistor, and the second terminal of the Kth second resistor is coupled to the second terminal of the (K+1)th first resistor; and A calibration resistor includes a first terminal and a second terminal, wherein the first terminal of the calibration resistor is coupled to the common calibration terminal, and the second terminal of the calibration resistor is coupled to the second terminal of a first resistor and the first terminal of a second resistor. Where K is a natural number, and K is greater than 0 and less than the total number of the first resistors.

3. The self-correcting digital-to-analog converter circuit as described in claim 2, characterized in that, The resistor circuit also includes: A thermometer encoding digital-to-analog converter circuit includes an input terminal and an output terminal, wherein the input terminal of the thermometer encoding digital-to-analog converter circuit is coupled to the second terminal of the last first resistor, and the output terminal of the thermometer encoding digital-to-analog converter circuit is coupled to the first input terminal of the fine-tuning circuit.

4. The self-correcting digital-to-analog converter circuit as described in claim 1, characterized in that, The correction switching circuit also includes: A first switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to the second input terminal of the buffer amplifier, and the second terminal of the first switch is coupled to the output terminal of the buffer amplifier. A second switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second input terminal of the buffer amplifier; A sampling capacitor includes a first terminal and a second terminal, wherein the first terminal of the sampling capacitor is coupled to the second terminal of the second switch; A third switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the second terminal of the sampling capacitor, and the second terminal of the third switch is coupled to the common voltage; and A control circuit is coupled to the control terminals of the first switch, the second switch, and the third switch. During normal operation, the control circuit controls the first switch to be turned on, while the second and third switches are turned off. During the sampling time, the control circuit controls the first switch, the second switch, and the third switch to be turned on. During the comparison time, the control circuit controls the first switch to turn off, and the second and third switches to turn on.

5. The self-correcting digital-to-analog converter circuit as described in claim 1, characterized in that, The fine-tuning circuit includes: An offset voltage adjustment circuit includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the offset voltage adjustment circuit is coupled to the output terminal of the resistor circuit, and the output terminal of the offset voltage adjustment circuit is coupled to the first input terminal of the buffer amplifier; and A data adjustment circuit includes an input terminal and an output terminal, wherein the input terminal of the data adjustment circuit is coupled to the output terminal of the buffer amplifier, and the output terminal of the data adjustment circuit outputs the correction data to the second input terminal of the offset voltage adjustment circuit. The data adjustment circuit determines the adjustment direction of the correction data based on the first saturation voltage at the output of the buffer amplifier until the voltage at the output of the buffer amplifier switches to the second saturation voltage.

6. A calibration method for a digital-to-analog converter, characterized in that: Provide a buffer amplifier and a resistor circuit; A calibration time is divided into a sampling time and a comparison time; At the sampling time: The second input terminal of the buffer amplifier is short-circuited to the output terminal of the buffer amplifier. A first correction digital value is input to the resistor circuit, and a reference voltage is input to the common correction terminal of the resistor circuit, so that the resistor circuit generates a first voltage, which is output to the first input terminal of the buffer amplifier. The first voltage is sampled from the second input terminal of the buffer amplifier; At the time of comparison: The second input terminal of the buffer amplifier is controlled to be open-circuited with the output terminal of the buffer amplifier; A common voltage is input to the common correction terminal of the resistor circuit, and a second correction digital value is input to the resistor circuit, so that the resistor circuit generates a second voltage, which is output to the first input terminal of the buffer amplifier. The sampled voltage is output to the second input terminal of the buffer amplifier; Adjust a calibration data, and adjust the voltage according to the calibration data until the voltage at the output of the buffer amplifier switches from a first saturation voltage to a second saturation voltage; and The correction data recorded when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage is used as the correction value corresponding to the second correction digital value. Specifically, when the reference voltage is input to the common correction terminal of the resistor circuit, and the resistor circuit receives the first correction digital value, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage. Wherein, the common correction terminal of the resistor circuit is input with the common voltage, and when the resistor circuit is input with the second correction digital value, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage. Wherein, the first theoretical voltage is equal to the second theoretical voltage.

7. The calibration method for a digital-to-analog converter as described in claim 6, characterized in that, The resistor circuit includes: A 1R-2R resistor ladder circuit includes: Multiple switching circuits, wherein each of the multiple switching circuits includes a control terminal, a first terminal and a second terminal, wherein the first terminal of each of the multiple switches receives the reference voltage, and the control terminals of the multiple switches are respectively used to receive the first correction digital value and the second correction digital value. A plurality of first resistors, wherein each of the plurality of first resistors includes a first terminal and a second terminal, wherein the first terminal of the plurality of first resistors is respectively coupled to the second terminal of the plurality of switching circuits; A plurality of second resistors, wherein each of the plurality of second resistors includes a first terminal and a second terminal, wherein the first terminal of the Kth second resistor is coupled to the second terminal of the Kth first resistor, and the second terminal of the Kth second resistor is coupled to the second terminal of the (K+1)th first resistor; and A calibration resistor, comprising a first terminal and a second terminal, wherein the first terminal of the calibration resistor is coupled to the common calibration terminal, and the second terminal of the calibration resistor is coupled to the second terminal of a first resistor and the first terminal of a second resistor. Where K is a natural number, and K is greater than 0 and less than the total number of the first resistors.

8. The calibration method for a digital-to-analog converter as described in claim 7, characterized in that, The resistor circuit also includes: A thermometer encoding digital-to-analog converter circuit, wherein the thermometer encoding digital-to-analog converter circuit includes an input terminal and an output terminal, wherein the input terminal of the thermometer encoding digital-to-analog converter circuit is coupled to the second terminal of the last first resistor, and the output terminal of the thermometer encoding digital-to-analog converter circuit is coupled to the first input terminal of the fine-tuning circuit.

9. The calibration method for a digital-to-analog converter as described in claim 6, characterized in that: The first correction bit value is 2 N -1, and the second correction digit value is 2. N , Where N is a natural number.

10. The calibration method for a digital-to-analog converter as described in claim 6, characterized in that, Also includes: The direction of adjustment of the correction data is determined according to the polarity of the first saturation voltage.

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