Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a manufacturing method thereof, which comprises the following steps: providing a substrate, wherein a gate dielectric layer is formed on the substrate; sequentially forming a high-resistance component and a first mask layer on the gate dielectric layer, the first mask layer covers the high-resistance component and the gate dielectric layer, and a first opening exposing part of the high-resistance component is formed in the first mask layer; etching the high-resistance component and part of the gate dielectric layer based on the first mask layer to form a groove penetrating through the high-resistance component and extending into the gate dielectric layer; performing an epitaxial growth process, so that the epitaxially grown high-resistance component fills part of the groove higher than the gate dielectric layer and forms an air gap in the part of the groove located in the gate dielectric layer; forming a protective layer covering at least the high-resistance component, and performing an ion implantation process to form a high-resistance structure, wherein the high-resistance structure comprises the air gap and the high-resistance component subjected to the ion implantation; and removing the protective layer. The application reduces the probability of parasitic PN junction or capacitance between the high-resistance component and the substrate, and improves the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] High-resistivity polycrystalline silicon is a type of polycrystalline silicon material with high resistivity, commonly used in the semiconductor and microelectronics fields. Generally, the desired resistivity can be obtained by adjusting the doping concentration of the high-resistivity polycrystalline silicon (e.g., undoped polycrystalline silicon has a naturally higher resistivity) or by adjusting the doping level through ion implantation. Simultaneously, the structure of the polycrystalline silicon (grain size, interface state) also affects the resistivity.

[0003] However, in practical applications, polysilicon with high resistive loads acts like a resistor in the circuit and does not form a complete CMOS structure. Furthermore, when high-resistivity polysilicon is deposited on field oxide (FOX), unnecessary parasitic PN junctions or capacitances will form between the high-resistivity polysilicon and the substrate, which may even affect the performance and stability of semiconductor devices in severe cases. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor device and a method for manufacturing the same, so as to reduce the probability of generating unwanted parasitic PN junctions or capacitances between high-resistivity components and substrates.

[0005] This application provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate is provided on which a gate dielectric layer is formed;

[0007] A high-resistivity component and a first mask layer are sequentially formed on the gate dielectric layer. The first mask layer covers the high-resistivity component and the gate dielectric layer, and a first opening is formed in the first mask layer to expose a portion of the high-resistivity component.

[0008] Based on the first mask layer, the high-resistivity component and part of the gate dielectric layer are etched to form a groove that penetrates the high-resistivity component and extends into the gate dielectric layer;

[0009] An epitaxial growth process is performed so that the epitaxially grown high-resistivity component fills the portion of the groove above the gate dielectric layer, and an air gap is formed in the portion of the groove located within the gate dielectric layer.

[0010] A protective layer is formed to at least cover the high-resistivity component, and an ion implantation process is performed based on the protective layer to form a high-resistivity structure, the high-resistivity structure including the gas gap and the high-resistivity component after ion implantation;

[0011] Remove the protective layer.

[0012] In one embodiment, after forming the air gap and before forming the protective layer, the method for manufacturing the semiconductor device further includes:

[0013] A filling dielectric layer is formed on the first mask layer and the high-resistivity component, and the surface of the filling dielectric layer is higher than the surface of the first mask layer and the high-resistivity component;

[0014] A planarization process is performed to remove the first mask layer on the high-resistivity component and to make the high-resistivity component flush with the remaining first mask layer and the remaining filling dielectric layer.

[0015] A second mask layer with a second opening is formed on the high-resistivity component, the first mask layer, and the filling dielectric layer, the second opening exposing the high-resistivity component.

[0016] In one embodiment, the process of forming the first mask layer having the first opening includes:

[0017] The first mask layer is formed on the high-resistivity component and the gate dielectric layer;

[0018] The first mask layer is subjected to a first patterning process to form the first opening within the first mask layer that exposes a portion of the high-resistivity component.

[0019] In one embodiment, the process of forming the second mask layer having the second opening includes:

[0020] The second mask layer is formed on the high-resistivity component and the first mask layer;

[0021] The second mask layer is subjected to a second patterning process to form a third opening in the second mask layer that exposes a portion of the high-resistivity component. The second patterning process corresponds to the same mask plate as the first patterning process.

[0022] The second mask layer is etched using a wet etching process to remove the portion of the second mask layer located on the surface of the high-resistivity component, thereby forming the second opening that exposes the high-resistivity component.

[0023] In one embodiment, the process of forming the second mask layer having the second opening includes:

[0024] The second mask layer is formed on the high-resistivity component and the first mask layer;

[0025] The second mask layer is subjected to a third patterning process to form a fourth opening within the second mask layer that exposes the high-resistivity component. The third patterning process corresponds to a different mask plate than the first patterning process.

[0026] In one embodiment, the process of forming the high-resistivity component on the substrate includes:

[0027] A high-resistivity material layer is formed on the gate dielectric layer;

[0028] The high-resistivity material layer is patterned to form the high-resistivity component;

[0029] During the patterning process of the high-resistivity material layer, a gate is also formed on the gate dielectric layer on one side of the high-resistivity component.

[0030] In one embodiment, at least two of the first openings are formed within the first mask layer, and the number of air gaps formed is the same as the number of the first openings.

[0031] Accordingly, this application also provides a semiconductor device, comprising:

[0032] Substrate;

[0033] A gate dielectric layer is located on the substrate;

[0034] A high-resistivity structure includes a high-resistivity component and an air gap, wherein the high-resistivity component is located on the gate dielectric layer and the air gap is located within the gate dielectric layer below the high-resistivity component;

[0035] A first mask layer is located on the gate dielectric layer on both sides of the high-resistivity structure, and the first mask layer covers the sidewall of the high-resistivity structure.

[0036] In one embodiment, the thickness of the portion of the gate dielectric layer located between the air gap and the substrate ranges from 5 Å to 10 Å.

[0037] In one embodiment, the semiconductor device is manufactured using the semiconductor device manufacturing method described above.

[0038] An unexpected effect of this application is that by forming an air gap in the gate dielectric layer below the high-resistivity component, and utilizing the characteristic that the dielectric constant of air is lower than that of the gate dielectric layer material, the probability of generating unnecessary parasitic PN junctions or capacitances between the high-resistivity component and the substrate is reduced, thereby helping to improve the resistance stability of the high-resistivity component; by first growing and forming a protective layer covering the high-resistivity component, and then performing the ion implantation process, the impact of the previous layer process on the high-resistivity component is reduced, thereby helping to further improve the resistance stability of the high-resistivity component. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application.

[0041] Figure 2 This is a schematic diagram of the structure corresponding to the step of providing a substrate and forming a gate dielectric layer on the substrate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0042] Figure 3 This is a schematic diagram of the structure corresponding to the step of forming a high-resistivity component and a gate in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0043] Figure 4 This is a schematic diagram of the structure corresponding to the step of forming a first mask layer and a second photoresist layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0044] Figure 5 This is a schematic diagram of the structure corresponding to the step of forming a first opening in the first mask layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0045] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming a groove in a high-resistivity component and a portion of the gate dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0046] Figure 7 This is a schematic diagram of the structure corresponding to the step of epitaxial process and forming air gap in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0047] Figure 8 This is a schematic diagram of the structure corresponding to the step of forming a filling dielectric layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0048] Figure 9 This is a schematic diagram of the structure corresponding to the planarization step in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0049] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming a second mask layer and a third photoresist layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0050] Figure 11 This is a schematic diagram of the structure corresponding to the step of etching the second mask layer using the third photoresist layer as a mask in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0051] Figure 12 This is a schematic diagram of the structure corresponding to the step of forming a second opening in a second mask layer in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0052] Figure 13 This is a schematic diagram of the structure corresponding to the step of forming a protective layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0053] Figure 14 This is a schematic diagram of the structure corresponding to the step of removing the protective layer in the manufacturing method of a semiconductor device provided in one embodiment of this application.

[0054] Figure 15 This is a schematic diagram of the structure corresponding to the step of forming an interlayer dielectric layer and an electrical connector in a method for manufacturing a semiconductor device according to one embodiment of this application.

[0055] The reference numerals in the figures include: 100-substrate; 101-source region; 102-drain region; 110-gate dielectric layer; 111-air gap; 120-high resistivity material layer; 121-high resistivity component; 122-gate; 130-first photoresist layer; 140-first mask layer; 141-first opening; 150-second photoresist layer; 160-filling dielectric layer; 170-second mask layer; 171-second opening; 172-third photoresist layer; 173-third opening; 180-protective layer; 190-interlayer dielectric layer; 191-electrical connector; 192-silicide layer; T-groove; H-high resistivity structure. Detailed Implementation

[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0058] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0059] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0060] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0061] High-resistivity polycrystalline silicon (HR Poly) is a polycrystalline silicon material with high resistivity, commonly used in the semiconductor and microelectronics fields. In CMOS processes, HR Poly serves several purposes: as a high-value resistor in analog circuits (e.g., feedback networks in operational amplifiers), as a load resistor in digital circuits, as a high-precision resistor with temperature stability and low parasitic capacitance in mixed-signal circuits, and as part of an electrostatic discharge (ESD) protection structure (using its high resistance to limit current). Generally, during the fabrication of HR Polycrystalline silicon, the desired resistivity can be obtained by adjusting the doping concentration (e.g., undoped polycrystalline silicon has a higher natural resistance) or by adjusting the doping level through ion implantation. Simultaneously, the structure of the polycrystalline silicon (grain size, interface state) also affects the resistivity.

[0062] However, polysilicon with high resistive loads functions similarly to a resistor in a circuit and does not form a complete CMOS structure. When high-resistivity polysilicon is deposited on field oxide (FOX), unwanted parasitic PN junctions or capacitances can form between the high-resistivity polysilicon and the substrate. Therefore, it is necessary to further improve the device performance of semiconductor devices by reducing the parasitic capacitance between the high-resistivity polysilicon and the substrate.

[0063] Generally, in the manufacturing process of high-resistivity polysilicon, processes such as photoresist rework (RWK) and photoresist rework (PR RMV) often use wet etching (WET) processes, which can easily lead to large variations in the thickness of the oxide layer on the polysilicon surface, thereby affecting the resistance value of the high-resistivity polysilicon and ultimately affecting the product yield.

[0064] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to reduce the probability of unnecessary parasitic PN junctions or capacitances between high-resistivity components and substrates, while improving the performance and stability of the semiconductor device.

[0065] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this application. See also... Figure 1 One embodiment of this application provides a method for manufacturing a semiconductor device, which includes the following steps S01 to S06.

[0066] Step S01: Provide a substrate on which a gate dielectric layer is formed.

[0067] Step S02: A high-resistivity component and a first mask layer are sequentially formed on the gate dielectric layer. The first mask layer covers the high-resistivity component and the gate dielectric layer, and a first opening is formed in the first mask layer to expose a portion of the high-resistivity component.

[0068] It should be noted that the number of first openings in the first mask layer can be one, two or more. The number of first openings is positively correlated with the number of air gaps formed in subsequent steps, and the number of first openings can be adjusted according to the performance requirements of the semiconductor device. This application does not impose any restrictions on this.

[0069] Step S03: Etch the high-resistivity component and part of the gate dielectric layer based on the first mask layer to form a groove that penetrates the high-resistivity component and extends into the gate dielectric layer.

[0070] Step S04: Perform an epitaxial growth process to fill the portion of the groove above the gate dielectric layer with the epitaxially grown high-resistivity component, and form an air gap in the portion of the groove located within the gate dielectric layer.

[0071] It should be noted that by forming an air gap within the gate dielectric layer, the lower dielectric constant of air compared to the gate dielectric layer material can be utilized to reduce the probability of unnecessary parasitic PN junctions or capacitances between high-resistivity components and the substrate.

[0072] Step S05: Form a protective layer that at least covers the high-resistivity component, and perform an ion implantation process based on the protective layer to form a high-resistivity structure, the high-resistivity structure including the gas gap and the high-resistivity component after ion implantation.

[0073] It should be noted that by first growing a protective layer covering the high-resistivity component and then performing the ion implantation process, the protective layer can be used to protect the high-resistivity component from damage during the ion implantation process. This reduces the impact of the preceding process on the high-resistivity component while achieving resistance adjustment.

[0074] Step S06: Remove the protective layer.

[0075] The semiconductor device manufacturing method described above, by forming an air gap in the gate dielectric layer below the high-resistivity component, utilizes the characteristic that the dielectric constant of air is lower than that of the gate dielectric layer material, reducing the probability of unnecessary parasitic PN junctions or capacitances between the high-resistivity component and the substrate, thereby helping to improve the resistance stability of the high-resistivity component; by first growing and forming a protective layer covering the high-resistivity component and then performing the ion implantation process, the influence of the previous layer process on the high-resistivity component is reduced, thereby helping to further improve the resistance stability of the high-resistivity component.

[0076] Figures 2 to 15This is a schematic diagram of the structure corresponding to some steps in the manufacturing method of a semiconductor device provided in one embodiment of this application. The following is in conjunction with... Figures 2 to 15 This application provides a detailed description of a method for manufacturing a semiconductor device according to one embodiment.

[0077] First, refer to Figure 2 Step S01 includes providing a substrate 100, on which a gate dielectric layer 110 is formed. In one embodiment, a high-resistivity material layer 120 and a first photoresist layer 130 are also formed on the gate dielectric layer 110 to facilitate the subsequent formation of a high-resistivity component. Optionally, the material of the substrate 100 includes silicon, the material of the gate dielectric layer 110 includes silicon oxide, and the material of the high-resistivity material layer 120 includes polysilicon. In other embodiments of this application, the materials of the various films can be adjusted according to actual needs, and this application does not impose any limitations on this.

[0078] Next, refer to Figures 3 to 5 The process of step S02 includes: sequentially forming a high-resistivity component 121 and a first mask layer 140 on the gate dielectric layer 110, wherein the first mask layer 140 covers the high-resistivity component 121 and the gate dielectric layer 110, and a first opening 141 is formed in the first mask layer 140 to expose a portion of the high-resistivity component 121. Optionally, at least two first openings 141 are formed in the first mask layer 140.

[0079] It should be noted that the number of first openings in the first mask layer can be one, two or more. The number of first openings is positively correlated with the number of air gaps formed in subsequent steps. The number of first openings can be adjusted according to the performance requirements of the semiconductor device and the process requirements in the actual production process. This application does not impose any restrictions on this.

[0080] In one embodiment, the process of forming a high-resistivity component on a substrate includes: first, referring to... Figure 2 and Figure 3 Using the first photoresist layer 130 as a mask, the high-resistivity material layer 120 is etched to form a high-resistivity component 121 on the gate dielectric layer 110; then, the first photoresist layer 130 is removed; subsequently, refer to... Figure 4 and Figure 5A first mask layer 140 is formed on the high-resistivity component 121 and the gate dielectric layer 110. The first mask layer 140 is then patterned to form a first opening 141 within the first mask layer 140 that exposes a portion of the high-resistivity component 121. Optionally, the first patterning process of the first mask layer 140 includes: forming a patterned second photoresist layer 150 on the first mask layer 140; etching the first mask layer 140 using the second photoresist layer 150 as a mask to form the first opening 141 within the first mask layer 140; subsequently, removing the second photoresist layer 150. Optionally, the first mask layer 140 is formed using a furnace tube deposition process.

[0081] Continue reading Figure 3 In one embodiment, after forming a high-resistivity material layer 120 on the gate dielectric layer 110, during the process of patterning the high-resistivity material layer 120 to form a high-resistivity component 121, a gate 122 is also formed on the gate dielectric layer 110 on one side of the high-resistivity component 121. In other embodiments of this application, the methods for forming the high-resistivity component and the first mask layer can also be adjusted according to actual needs, and this application does not limit them.

[0082] See Figure 6 Step S03 includes etching the high-resistivity component 121 and a portion of the gate dielectric layer 110 based on the first mask layer 140 to form a groove T that penetrates the high-resistivity component 121 and extends into the gate dielectric layer 110. In one embodiment, a dry etching process is used to etch the high-resistivity component 121 and a portion of the gate dielectric layer 110 to form the groove, and the thickness of the remaining gate dielectric layer 110 after etching ranges from 5 Å to 10 Å.

[0083] See Figure 6 and Figure 7 Step S04 includes performing an epitaxial growth process to fill the portion of the groove T above the gate dielectric layer 110 with the epitaxially grown high-resistivity component 121, and forming an air gap 111 in the portion of the groove T located within the gate dielectric layer 110. It should be noted that during the epitaxial growth process, the epitaxial growth (or epitaxial deposition) rate needs to be controlled to ensure that the epitaxially grown portion can be sealed above the gate dielectric layer and form an air gap. This is common knowledge well-known to those skilled in the art, and this application does not impose any limitations on it.

[0084] In one embodiment, the number of air gaps formed is the same as the number of first openings within the first mask layer. It should be noted that by forming air gaps within the gate dielectric layer, the lower dielectric constant of air compared to the gate dielectric material can be utilized to reduce the probability of unwanted parasitic PN junctions or capacitances between the high-resistivity component and the substrate.

[0085] In one embodiment, after forming the air gap and before forming the protective layer, the method for manufacturing the semiconductor device further includes: (See below) Figure 8 A filling dielectric layer 160 is formed on the first mask layer 140 and the high-resistivity component 121, and the surface of the filling dielectric layer 160 is higher than the surface of the first mask layer 140 and the high-resistivity component 121; see reference. Figure 9 A planarization process is performed, removing the first mask layer 140 on the high-resistivity component 121, and making the high-resistivity component 121 flush with the remaining first mask layer 140 and the remaining filling dielectric layer 160; see reference Figures 10 to 12 A second mask layer 170 with a second opening 171 is formed on the high-resistivity component 121, the first mask layer 140, and the filling dielectric layer 160, the second opening 171 exposing the high-resistivity component 121. Optionally, the filling dielectric layer 160 is made of silicon oxide, and the second mask layer 170 is made of silicon nitride. Optionally, planarization is performed using a chemical mechanical polishing (CMP) process.

[0086] Continue reading Figures 10 to 12 In one embodiment, the process of forming a second mask layer 170 having a second opening 171 includes: first, referring to... Figure 10 A second mask layer 170 is formed on the high-resistivity component 121 and the first mask layer 140; then, refer to Figure 10 and Figure 11 A patterned third photoresist layer 172 is formed on the second mask layer 170, and a second patterning process is performed on the second mask layer 170 based on the third photoresist layer 172 to form a third opening 173 within the second mask layer 170 to expose a portion of the high-resistivity component 121. The second patterning process corresponds to the same mask as the first patterning process (i.e., Figure 10 The third photoresist layer 172 in Figure 4 (The second photoresist layer 150 corresponds to the same mask); then, the third photoresist layer 172 is removed; next, refer to... Figure 12 The second mask layer 170 is etched using a wet etching process to remove the portion of the second mask layer 170 located on the surface of the high-resistivity component 121, thereby forming a second opening 171 that exposes the high-resistivity component 121.

[0087] It should be noted that, in the manufacturing process of the second opening as described above, the photomask used for the third photoresist layer is the same as the photomask used for the second photoresist layer, thereby saving the number of photomasks required in the process and reducing production costs. In other embodiments of this application, other methods can also be used to manufacture the second photomask layer with the second opening, and this application does not limit this.

[0088] For example, in other embodiments of this application, the process of forming a second mask layer with a second opening may also include: forming a second mask layer on a high-resistivity component and a first mask layer; performing a third patterning process on the second mask layer to form a fourth opening in the second mask layer that exposes the high-resistivity component, wherein the third patterning process corresponds to a different mask plate than the first patterning process.

[0089] It should be noted that, in the manufacturing process of directly forming the fourth opening of the exposed high-resistivity component in the second mask layer as described above, although the third patterning process corresponds to different mask plates as the first patterning process, increasing the number of mask plates required in the process, after the fourth opening is formed, no additional wet etching process is required to further process the fourth opening. Therefore, the preparation method of directly forming the fourth opening in the second mask layer optimizes the process steps, helps to shorten the process time, and improves production efficiency.

[0090] Then refer to Figure 13 Step S05 includes: forming a protective layer 180 that at least covers the high-resistivity component 121, and performing an ion implantation process based on the protective layer 180 to form a high-resistivity structure H, the high-resistivity structure H including an air gap 111 and the ion-implanted high-resistivity component 121. In one embodiment, the material of the protective layer 180 includes silicon dioxide. Optionally, the protective layer 180 is formed using a chemical vapor deposition (CVD) process.

[0091] It should be noted that by first growing a protective layer covering the high-resistivity component and then performing the ion implantation process, the protective layer can be used to protect the high-resistivity component from damage during the ion implantation process. This reduces the impact of the preceding process on the high-resistivity component while achieving resistance adjustment.

[0092] Next, refer to Figure 13 and Figure 14 Step S06 includes removing the protective layer 180. In one embodiment, during the removal of the protective layer 180, the second mask layer 170 and the filling dielectric layer 160 are also removed to facilitate subsequent process steps. Optionally, a wet etching process is used to remove the protective layer 180, the second mask layer 170, and the filling dielectric layer 160.

[0093] Then refer to Figure 15In one embodiment of this application, after removing the protective layer 180, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer 190 covering the high-resistivity structure H and the first mask layer 140, and forming an electrical connector 191 that penetrates the interlayer dielectric layer 190 and connects to the high-resistivity component 121 within the interlayer dielectric layer 190. Optionally, the material of the interlayer dielectric layer 190 includes silicon oxide, and the material of the electrical connector 191 includes one of copper, tungsten, and aluminum. In other embodiments of this application, the materials of the interlayer dielectric layer 190 and the electrical connector 191 can also be adjusted according to actual needs, and this application does not impose any limitations on this.

[0094] Continue reading Figure 15 When a gate 122 is formed on one side of the high-resistivity component 121, the interlayer dielectric layer 190 also includes electrical connectors 191 for respectively leading out the gate 122, the source region 101, and the drain region 102. Optionally, a silicide layer 192 is formed on the top of the gate 122, the source region 101, and the drain region 102. It should be noted that the specific methods for forming the source region 101, the drain region 102, and the silicide layer 192 are common knowledge well known to those skilled in the art, and will not be described in detail here.

[0095] Accordingly, please continue to refer to Figure 15 One embodiment of this application also provides a semiconductor device, including a substrate 100, a gate dielectric layer 110, a high-resistivity structure H, and a first mask layer 140; wherein, the gate dielectric layer 110 is located on the substrate 100; the high-resistivity structure H includes a high-resistivity component 121 and an air gap 111, the high-resistivity component 121 is located on the gate dielectric layer 110, and the air gap 111 is located within the gate dielectric layer 110 below the high-resistivity component 121; the first mask layer 140 is located on the gate dielectric layers 110 on both sides of the high-resistivity structure H, and the first mask layer 140 covers the sidewalls of the high-resistivity structure H.

[0096] As described above, the semiconductor device, by providing an air gap in the gate dielectric layer below the high-resistivity component, utilizes the characteristic that the dielectric constant of air is lower than that of the gate dielectric layer material, thereby reducing the probability of unnecessary parasitic PN junctions or capacitances between the high-resistivity component and the substrate, which helps to improve the resistance stability of the high-resistivity component.

[0097] See Figure 15 In one embodiment, the thickness of the portion of the gate dielectric layer 110 located between the air gap 111 and the substrate 100 ranges from 5 Å to 10 Å. Optionally, the gate dielectric layer 110 is made of silicon oxide, the substrate 100 is made of silicon, the high-resistivity component 121 is made of polysilicon, and the first mask layer 140 is made of silicon nitride.

[0098] Continue reading Figure 15In one embodiment, a gate 122 is further disposed on the gate dielectric layer 110 on one side of the high-resistivity component 121, and a source region 101 and a drain region 102 are respectively disposed in the substrate 100 on both sides of the gate 122. At this time, a silicide layer 192 is disposed on the surface of the high-resistivity component 121, the gate 122, the source region 101, and the drain region 102. Correspondingly, an interlayer dielectric layer 190 is also disposed on the high-resistivity structure H and the gate dielectric layer 110, and an electrical connector 191 is disposed in the interlayer dielectric layer 190, penetrating the interlayer dielectric layer 190 and respectively connected to the high-resistivity component 121, the gate 122, the source region 101, and the drain region 102.

[0099] In one embodiment, the interlayer dielectric layer is made of silicon dioxide, the gate is made of polysilicon, and the electrical connector is made of one of copper, tungsten, and aluminum. In other embodiments of this application, the materials and arrangement of the various film layers in the semiconductor device can be adjusted according to actual needs, and this application does not impose any limitations on this.

[0100] In one embodiment, the semiconductor device is manufactured using the semiconductor device manufacturing method described above. In other embodiments of this application, other semiconductor structures with the same or similar structures can be manufactured using the semiconductor device manufacturing method described above. By providing an air gap in the gate dielectric layer below the high-resistivity component, the probability of unnecessary parasitic PN junctions or capacitances between the high-resistivity component and the substrate can be reduced, thereby helping to improve the resistance stability of the high-resistivity component.

[0101] An unexpected effect of this application is that by forming an air gap in the gate dielectric layer below the high-resistivity component, and utilizing the characteristic that the dielectric constant of air is lower than that of the gate dielectric layer material, the probability of generating unnecessary parasitic PN junctions or capacitances between the high-resistivity component and the substrate is reduced, thereby helping to improve the resistance stability of the high-resistivity component; by first growing and forming a protective layer covering the high-resistivity component, and then performing the ion implantation process, the impact of the previous layer process on the high-resistivity component is reduced, thereby helping to further improve the resistance stability of the high-resistivity component.

[0102] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, wherein a gate dielectric layer is formed on the substrate; forming a high-resistance component and a first mask layer on the gate dielectric layer in sequence, wherein the first mask layer covers the high-resistance component and the gate dielectric layer, and the first mask layer has a first opening exposing part of the high-resistance component; etching the high-resistance component and part of the gate dielectric layer based on the first mask layer to form a groove extending through the high-resistance component and into the gate dielectric layer; performing an epitaxial growth process, so that the high-resistance component after epitaxial growth fills the part of the groove higher than the gate dielectric layer, and forms an air gap in the part of the groove located in the gate dielectric layer; forming a protective layer covering at least the high-resistance component, and performing an ion implantation process based on the protective layer to form a high-resistance structure, wherein the high-resistance structure comprises the air gap and the high-resistance component after ion implantation; removing the protective layer.

2. The method of manufacturing a semiconductor device according to claim 1, wherein After forming the air gap and before forming the protective layer, the method further comprises the following steps: forming a filling dielectric layer on the first mask layer and the high-resistance component, and the surface of the filling dielectric layer is higher than the surface of the first mask layer and the high-resistance component; performing a planarization process to remove the first mask layer on the high-resistance component, and making the high-resistance component flush with the remaining first mask layer and the remaining filling dielectric layer; forming a second mask layer with a second opening on the high-resistance component, the first mask layer and the filling dielectric layer, wherein the second opening exposes the high-resistance component.

3. The method of manufacturing a semiconductor device according to claim 2, wherein The process of forming the first mask layer with the first opening comprises the following steps: forming the first mask layer on the high-resistance component and the gate dielectric layer; performing a first patterning process on the first mask layer to form the first opening exposing part of the high-resistance component in the first mask layer.

4. The method of manufacturing a semiconductor device according to claim 3, wherein The process of forming the second mask layer with the second opening comprises the following steps: forming the second mask layer on the high-resistance component and the first mask layer; performing a second patterning process on the second mask layer to form a third opening exposing part of the high-resistance component in the second mask layer, wherein the second patterning process corresponds to the same mask plate as the first patterning process; performing etching on the second mask layer by using a wet etching process to remove part of the second mask layer located on the surface of the high-resistance component, so as to form the second opening exposing the high-resistance component.

5. The method of manufacturing a semiconductor device according to Claim 3, wherein The process of forming the second mask layer with the second opening comprises the following steps: forming the second mask layer on the high-resistance component and the first mask layer; performing a third patterning process on the second mask layer to form a fourth opening exposing the high-resistance component in the second mask layer, wherein the third patterning process corresponds to a different mask plate from the first patterning process.

6. The method of manufacturing a semiconductor device according to Claim 1, wherein The process of forming the high-resistance component on the substrate comprises the following steps: forming a high-resistance material layer on the gate dielectric layer; performing a patterning process on the high-resistance material layer to form the high-resistance component; In the process of patterning the high-resistance material layer, a gate is formed on the gate dielectric layer on the side of the high-resistance component.

7. The method of manufacturing a semiconductor device according to Claim 1, wherein The first mask layer has at least two first openings formed therein, and the number of the air gaps formed is the same as the number of the first openings.

8. A semiconductor device, characterized by, It comprises: a substrate; a gate dielectric layer on the substrate; a high-resistance structure comprising a high-resistance component on the gate dielectric layer and an air gap in the gate dielectric layer below the high-resistance component; a first mask layer on the gate dielectric layer on both sides of the high-resistance structure, and the first mask layer covering the sidewall of the high-resistance structure.

9. The semiconductor device of claim 8, wherein, The thickness of the part of the gate dielectric layer between the air gap and the substrate ranges from 5 Å to 10 Å.

10. The semiconductor device of claim 8, wherein, It is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1 to 7. It is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

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