ESD protection circuit and method thereof

Abstract

The invention relates to an ESD protection circuit and a method thereof. An electrostatic discharge (ESD) protection circuit is provided herein. The ESD protection circuit includes a clamping circuit coupled between a first voltage supply node and a second voltage supply node. The clamp circuit includes a first transistor coupled in series with a second transistor. The first transistor includes a control electrode coupled to the second voltage supply node through a first resistor. The second transistor includes a first current electrode coupled at the first voltage supply node. A trigger circuit is coupled with the clamping circuit. The trigger circuit includes a first output coupled at the control electrode of the first transistor and a second output coupled at the control electrode of the second transistor.

Description

Technical Field

[0001] This disclosure generally relates to electronic circuits, and more specifically, to semiconductor devices having electrostatic discharge (ESD) protection circuitry. Background Technology

[0002] Today, most sophisticated semiconductor devices incorporate circuitry with ESD protection. For example, ESD protection circuits are widely used in a wide variety of applications and electronic products—from sewing machines to washing machines, from automobiles to cell phones, and more. With advancements in process technology, these semiconductor devices are expected to see improved reliability alongside increased performance. However, challenges remain in balancing size, cost, performance, and long-term reliability. Summary of the Invention

[0003] Generally, an ESD protection circuit is provided, including a clamping circuit coupled between a first voltage supply node and a second voltage supply node, and a triggering circuit coupled to the clamping circuit. The clamping circuit includes: a first transistor having a first current electrode, a second current electrode coupled to the second voltage supply node, and a control electrode coupled to the second voltage supply node through a first resistor; a second transistor coupled in series with the first transistor, the second transistor having a first current electrode, a second current electrode, and a control electrode coupled to the first voltage supply node; a first bias generator circuit coupled to the control electrode of the second transistor, the first bias generator circuit being configured to make the gate-to-source voltage of the second transistor substantially equal to the gate-to-source voltage of the first transistor during normal operating mode; and a triggering circuit having a first output coupled to the control electrode of the first transistor and a second output coupled to the control electrode of the second transistor. The first bias generator circuit may include a second resistor having a first terminal coupled to the control electrode of the second transistor and a second terminal coupled to the second current electrode of the second transistor. The clamping circuit may further include a third transistor series coupled between the first transistor and the second transistor, the third transistor having a first current electrode coupled to a second current electrode of the second transistor, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode. The clamping circuit may further include a second bias generator circuit coupled to the control electrode of the third transistor, the second bias generator circuit being configured to make the gate-to-source voltage of the third transistor substantially equal to the gate-to-source voltage of the first transistor during normal operating mode. The triggering circuit may include a first inverter stage and a second inverter stage, the first inverter stage including: a first trigger transistor having a first current electrode, a second current electrode coupled to a third voltage supply node, and a control electrode coupled to a first trigger node; a second trigger transistor having a first current electrode coupled to a first output of the triggering circuit, a second current electrode coupled to the first current electrode of the first trigger transistor, and a control electrode coupled to a second trigger node; the second inverter stage including: a third trigger transistor having a first current electrode coupled to a second output of the triggering circuit, a second current electrode coupled to a third voltage supply node, and a control electrode coupled to the first trigger node. The trigger circuit may further include: an RC stage coupled between the second and third voltage supply nodes; and a third inverter stage having an input coupled to the output of the RC stage and an output coupled to the inputs of the first and second inverter stages. The ESD protection circuit may further include a voltage divider circuit coupled to the trigger circuit, the voltage divider circuit having a first tap and configured to generate a first reference voltage at the first tap. The first reference voltage at the first tap may be characterized as a voltage value substantially equal to half the voltage value across the voltage divider circuit.The voltage divider circuit may include a second tap coupled to the control electrode of the second transistor, the second tap being configured as a first bias generator circuit.

[0004] In another embodiment, an ESD protection circuit is provided, including a clamping circuit coupled between a first voltage supply node and a second voltage supply node, and a triggering circuit coupled to the clamping circuit. The clamping circuit includes: a first transistor having a first current electrode, a second current electrode coupled to the second voltage supply node, and a control electrode coupled to the second voltage supply node through a first resistor; a second transistor coupled in series with the first transistor, the second transistor having a first current electrode, a second current electrode coupled to the first voltage supply node, and a control electrode coupled to the second current electrode of the second transistor through a second resistor; a first bias generator circuit coupled to the control electrode of the second transistor, the first bias generator circuit being configured to make the gate-to-source voltage of the second transistor substantially equal to the gate-to-source voltage of the first transistor during normal operating mode; and a triggering circuit having a first output coupled to the control electrode of the first transistor and a second output coupled to the control electrode of the second transistor, the triggering circuit being configured to turn on the first transistor and the second transistor of the clamping circuit during an ESD event. The clamping circuit may further include a third transistor series coupled between the first transistor and the second transistor, the third transistor having a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode. The clamping circuit may further include a third resistor coupled between the control electrode and the second current electrode of the third transistor. The triggering circuit may include a first inverter stage and a second inverter stage, the first inverter stage including: a first trigger transistor having a first current electrode, a second current electrode coupled to a third voltage supply node, and a control electrode coupled to a first trigger node; a second trigger transistor having a first current electrode coupled to a first output of the triggering circuit, a second current electrode coupled to the first current electrode of the first trigger transistor, and a control electrode coupled to a second trigger node; the second inverter stage including: a third trigger transistor having a first current electrode coupled to a second output of the triggering circuit, a second current electrode coupled to the third voltage supply node, and a control electrode coupled to the first trigger node. The trigger circuit may further include: an RC stage coupled between the second and third voltage supply nodes; and a third inverter stage having an input coupled to the output of the RC stage and an output coupled to the inputs of the first and second inverter stages. The ESD protection circuit may further include a voltage divider circuit coupled to the trigger circuit, the voltage divider circuit having a first tap and configured to generate a first reference voltage at the first tap.

[0005] In another embodiment, an ESD protection circuit is provided, including a clamping circuit coupled between a first voltage supply node and a second voltage supply node, and a triggering circuit coupled to the clamping circuit. The clamping circuit includes: a first transistor having a first current electrode, a second current electrode coupled to the second voltage supply node, a control electrode coupled to the second voltage supply node through a first resistor, and a body electrode coupled to the second voltage supply node; a second transistor having a first current electrode, a second current electrode coupled to the first current electrode of the first transistor at the first clamping node, a control electrode, and a body electrode coupled to the second current electrode; a third transistor having a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the first current electrode of the second transistor at the second clamping node, a control electrode, and a body electrode coupled to the second current electrode; a first bias generator circuit coupled to the control electrode of the second transistor; a second bias generator circuit coupled to the control electrode of the third transistor; and a triggering circuit having a first output coupled to the control electrode of the first transistor, a second output coupled to the control electrode of the second transistor, and a third output coupled to the control electrode of the third transistor. The ESD protection circuit may additionally include a voltage divider circuit coupled to a trigger circuit, the voltage divider circuit having a first tap and configured to generate a first reference voltage at the first tap. The trigger circuit may be coupled to receive the first reference voltage during normal operation. A first bias generator circuit may include a second resistor having a first end coupled to a control electrode of a second transistor and a second end coupled to a second current electrode of the second transistor, and wherein the second bias generator circuit may include a third resistor having a first end coupled to a control electrode of a third transistor and a second end coupled to a second current electrode of the third transistor. The first bias generator circuit may be configured such that the voltage at the first clamping node is substantially equal to 1 / 3 of the voltage at the first voltage supply node, and wherein the second bias generator circuit may be configured such that the voltage at the second clamping node is substantially equal to 2 / 3 of the voltage at the first voltage supply node. Attached Figure Description

[0006] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0007] Figure 1 An example ESD protection circuit according to an embodiment is shown in simplified schematic form.

[0008] Figure 2 An example embodiment for bias generation for a clamping device according to an embodiment is shown in simplified schematic form.

[0009] Figure 3 An alternative example implementation for bias generation of a clamping device according to an embodiment is shown in simplified schematic form.

[0010] Figure 4 An alternative example ESD protection circuit according to an embodiment is shown in simplified schematic form.

[0011] Figure 5 Example simulation results of the ESD protection circuit according to the embodiment are shown in simplified graph form. Detailed Implementation

[0012] Generally, a low-leakage ESD protection circuit is provided. The ESD protection circuit for a semiconductor device includes a trigger circuit and a clamping circuit. The trigger circuit includes an RC transient circuit configured to detect electrostatic discharge (i.e., an ESD event) and an inverter stage configured to drive transistors in the clamping circuit during an ESD event. The clamping circuit includes a stack of ESD transistors (e.g., multiple ESD transistors connected in series) between a power rail and a ground supply rail. The ESD transistors are configured to form a shunt between the power rail and the ground supply rail during an ESD event and to absorb the current associated with the ESD event. After the RC transient circuit detects the ESD event, the inverter stage drives the gate terminals of the ESD transistors, thereby turning on the ESD transistors. The stacked ESD transistors then absorb the current associated with the ESD event. In normal operating modes (e.g., non-ESD events), the ESD transistors are configured to be in a low-leakage mode. For example, the clamping circuit may include a resistor connected between the gate and source terminals of the respective ESD transistor in the ESD transistor stack. The output of the inverter stage is configured to a high-impedance state during normal operation, allowing each resistor to self-bias its corresponding transistor to the Vgs = 0 volt off state. By self-biasing the ESD transistors in the ESD transistor stack in this way, leakage current associated with the ESD transistors can be minimized during normal operation.

[0013] Figure 1An example ESD protection circuit 100 according to an embodiment is shown in simplified schematic form. In this embodiment, the ESD protection circuit 100 includes a voltage divider circuit 102, a reference current generator circuit 104, a resistor-capacitor (RC) filter stage circuit 106, inverter stage circuits 108-114, and a clamping circuit 116. The reference current generator circuit 104, the RC stage circuit 106, and the inverter stage circuits 108-114 together form an RC-based transient triggering circuit of the ESD protection circuit 100. In this embodiment, the triggering circuit is coupled between an ESD rail node labeled VESD and a first supply node labeled VSS, and the clamping circuit 116 is coupled between a second supply node labeled VDD and the VSS supply node. In this embodiment, the VDD supply node is configured to supply a positive operating voltage (e.g., ~3.3 volts at a 16nm technology node), and the VSS supply node is configured to supply ground (e.g., zero volts). In some embodiments, the VDD supply node is configured to supply a positive operating voltage consistent with other technology nodes. In this embodiment, the VESD rail may be coupled to multiple input / output (I / O) pads and the VDD supply node. In some embodiments, the VDD supply node and the VESD rail may enable triggering circuitry to overdrive or "boost" the clamping circuitry to a voltage exceeding the VDD supply voltage during an ESD event. In some embodiments, the VESD rail and the VDD supply node may be combined into a single VDD supply rail. For illustrative purposes, the VESD rail node voltage may be characterized as being substantially equal to the VDD supply node voltage during normal operating modes (e.g., non-ESD events) and at or above the VDD supply node voltage during ESD events.

[0014] In this embodiment, the voltage divider circuit 102 is configured to connect in series between the VESD rail node and the VSS supply node, comprising a plurality of P-channel transistors. Each of the series-connected transistors includes a first current electrode (e.g., drain) connected to its control electrode and a second current electrode (e.g., source) connected to the first current electrode of the preceding transistor in the series. In this embodiment, the transistors of the voltage divider circuit 102 are formed to have substantially similar physical parameters (e.g., width, length) and electrical characteristics (e.g., IV characteristics). The voltage divider circuit 102 is configured to generate a first reference voltage VDIV1 at a first tap node labeled VDIV1. In this embodiment, the VDIV1 node is configured to provide a voltage substantially equal to half the voltage of the VESD rail node. Therefore, the same number of transistors connected in series between the VDIV1 node and the VSS supply node are connected in series between the VDIV1 node and the VESD rail node.

[0015] exist Figure 1 In the embodiment depicted, the reference current generator circuit 104 includes P-channel transistors 120, 122, and 126, and N-channel transistors 124, 128, and 130 coupled between the VESD rail node and the VSS supply node. The reference current generator circuit 104 is coupled to the voltage divider circuit 102 via a P-channel pass transistor 118. Transistor 118 includes a first current electrode connected at the VDIV1 node, a second current electrode connected at the input of the reference current generator circuit 104 at a node labeled N21H, and a control electrode connected at a node labeled T. In this embodiment, transistors 120, 124, and 128 are connected in series in a first branch, and transistors 122, 126, and 128 are connected in series in a second branch. A first current mirror is formed by transistors 120 and 122. Transistor 120 includes a first current electrode connected at the VESD rail node, and a control electrode and a second current electrode connected at the first current electrode of transistor 124. Transistor 124 includes a control electrode connected at node N21H and a second current electrode connected at node N11. Transistor 128 includes a first current electrode connected at node N11, a second current electrode connected at the VSS supply node, and a control electrode connected at node T. In this embodiment, transistor 128 can be characterized as a switchable current source based on the logic level at node T.

[0016] Transistor 122 includes a first current electrode connected to the VESD rail node, a control electrode connected to the control electrode of transistor 120, and a second current electrode connected to the first current electrode of transistor 126. Transistor 126 includes a control electrode connected to the N21H node and a second current electrode connected to a bias reference node labeled VBR. The second current mirror is formed by transistors 130 and 132 of the RC filter stage circuit 106. Transistor 130 includes a first current electrode and a control electrode connected to node VBR, and a second current electrode connected to the VSS supply node. In this embodiment, the reference current generator circuit 104 is configured to generate a bias reference voltage VBR at the VBR node, and consequently generate a minimal mirror current through transistor 132 of the RC filter stage circuit 106. It may be necessary to size the transistors of the reference current generator circuit 104 such that the branch current of the second branch is attenuated to reduce the bias reference voltage VBR. For example, the reference current generator circuit 104 can be configured such that the branch current of the second branch is approximately one-tenth of the branch current of the first branch.

[0017] The RC filter stage circuit 106 includes capacitors 164 and 166, resistor 168, and N-channel transistors 132 and 134 coupled between the VESD rail node and the VSS supply node. The RC filter stage circuit 106 is coupled to the output of the reference current generator circuit 104 at the VBR node. The RC filter stage circuit 106 is configured to receive a bias reference voltage VBR generated at the output of the reference current generator circuit 104. In this embodiment, capacitors 164 and 166 are characterized as P-channel transistors configured as capacitors. Capacitor 164 includes a first terminal connected to the VESD rail node and a second terminal connected to the N21H node. Capacitor 166 includes a first terminal connected to the N21H node and a second terminal connected to a node labeled N21L. The first terminal of resistor 168 is connected to the N21L node, and the second terminal of resistor 168 is connected to the first current electrode of transistors 132 and 134. Transistor 132 further includes a control electrode connected at the VBR node and a second current electrode connected at the VSS supply node. In this embodiment, the current mirror formed by transistors 130 and 132 is configured to generate a very small “percolation” current through transistor 132 during an ESD event to slowly charge capacitors 164 and 166. Transistor 134 further includes a control electrode connected at a node labeled TB and a second current electrode connected at the VSS supply node.

[0018] The inverter stage circuits 108-114 of the ESD protection circuit 100 are coupled between the VESD rail node and the VSS supply node. The first inverter stage circuit 108 is coupled to the N21H and N21L output nodes of the RC filter stage circuit 106. In this embodiment, the first inverter stage circuit 108 includes a pull-up resistor 170 and N-channel transistors 136 and 138 connected in series between the VESD rail node and the VSS supply node. A first end of the resistor 170 is connected at the VESD rail node, and a second end of the resistor 170 is connected at the node labeled N31H to the first current electrode of transistor 136. The control electrode of transistor 136 is connected at the N21H node, and the second current electrode of transistor 136 is connected at the node labeled N31L to the first current electrode of transistor 138. The control electrode of transistor 138 is connected at the N21L node, and the second current electrode of transistor 138 is connected at the VSS supply node to the first current electrode of transistor 138.

[0019] Multiple second inverter stage circuits 110, 112, and 114 are coupled to the N31H and N31L output nodes of the first inverter stage circuit 108. In this embodiment, inverter stage circuits 110, 112, and 114 have corresponding trigger outputs labeled TL, TM, and TH, coupled to the corresponding clamping devices of clamping circuit 116. The TL inverter stage circuit 110 includes P-channel transistors 140 and 142 connected in series. The first current electrode of transistor 140 is connected at the VESD rail node, the control electrode of transistor 140 is connected at the N31H node, and the second current electrode of transistor 140 is connected to the first current electrode of transistor 142. The control electrode of transistor 142 is connected at the N31L node, and the second current electrode of transistor 142 is connected at the TL node. The TM inverter stage circuit 112 includes P-channel transistors 144 and 146 connected in series. The first current electrode of transistor 144 is connected to the VESD rail node, the control electrode of transistor 144 is connected to the N31H node, and the second current electrode of transistor 144 is connected to the first current electrode of transistor 146. The control electrode of transistor 146 is connected to the N31L node, and the second current electrode of transistor 146 is connected to the TM node. The TH inverter stage circuit 114 includes a P-channel transistor 148. The first current electrode of transistor 148 is connected to the VESD rail node, the control electrode of transistor 148 is connected to the N31H node, and the second current electrode of transistor 148 is connected to the TH node.

[0020] In this embodiment, the clamping circuit 116 includes N-channel clamping transistors 150, 152, and 154 connected in series between the VDD supply node and the VSS supply node. Each of the clamping transistors 150, 152, and 154 includes a body electrode connected to its source electrode, such as... Figure 1 As depicted in the diagram. The first current electrode (e.g., drain) of clamped transistor 150 is connected to the VDD supply node, the control electrode (e.g., gate) of transistor 150 is connected to the TH node, and the second current electrode (e.g., source) of transistor 150 is connected to the first current electrode (e.g., drain) of transistor 152 at a node labeled N41H. The control electrode (e.g., gate) of transistor 152 is connected to the TM node, and the second current electrode (e.g., source) of transistor 152 is connected to the first current electrode (e.g., drain) of transistor 154 at a node labeled N41L. The control electrode (e.g., gate) of transistor 154 is connected to the TL node, and the second current electrode (e.g., source) of transistor 154 is connected to the VSS supply node.

[0021] In this embodiment, a first bias generator circuit 156 is coupled to the control electrode of clamping transistor 150, and a second bias generator circuit 158 ​​is coupled to the control electrode of clamping transistor 152. A pull-down resistor 172 includes a first terminal connected to the control electrode of clamping transistor 154 and a second terminal at the VSS supply node. In this embodiment, clamping transistors 150, 152, and 154 of clamping circuit 116 are formed with substantially similar physical layouts, including substantially similar physical parameters (e.g., width, length) and electrical characteristics (e.g., IV characteristics). Clamping circuit 116 is configured to form a shunt between the VDD supply node and the VSS supply node during an ESD event and to absorb the current associated with the ESD event.

[0022] In this embodiment, during normal operation, a first bias generator circuit 156 is configured to provide a first gate bias voltage at the control electrode of clamping transistor 150, and a second bias generator circuit 158 ​​is configured to provide a second gate bias voltage at the control electrode of clamping transistor 152. The first bias generator circuit 156 is configured to generate a first gate bias voltage substantially equal to two-thirds of the VDD voltage (i.e., 2 / 3 * VDD). Similarly, the second bias generator circuit 158 ​​is configured to generate a second gate bias voltage substantially equal to one-third of the VDD voltage (i.e., 1 / 3 * VDD). Additionally, resistor 172 is configured to provide a voltage substantially equal to the voltage at the VSS supply node (e.g., 0 volts) at the control electrode of clamping transistor 154 during normal operation. Because each of the clamping transistors 150, 152, and 154 is configured to have substantially the same electrical characteristics, the gate-to-source voltage (Vgs) of each of the clamping transistors 150 and 152 is substantially equal to the Vgs of the clamping transistor 154 (e.g., 0 volts) during normal operating mode. Therefore, during normal operating mode, the voltage at node N41L is substantially equal to one-third of the VDD voltage (i.e., 1 / 3 * VDD), and the voltage at node N41H is substantially equal to two-thirds of the VDD voltage (i.e., 2 / 3 * VDD). In this embodiment, it is desirable that the drain voltage (Vds) of each of the clamping transistors 150, 152, and 154 is substantially equal to one-third of the VDD voltage to minimize gate-induced drain leakage (GIDL) during normal operating mode.

[0023] In this embodiment, the trigger output node TL is coupled to the input of inverter 160. The output of inverter 160 is connected at node TB to the input of inverter 162 and the control electrode of transistor 134. The output of inverter 162 is connected at node T to the control electrodes of transistor 118 and transistor 128.

[0024] In normal operating mode (e.g., non-ESD event), transistors 140 and 142 of inverter stage 110 are in an "off" state (e.g., off, not conducting), allowing resistor 172 to pull the TL node down to logic low. Therefore, the TB node at the output of inverter 160 is at logic high, and consequently, transistor 134 of RC filter stage circuit 106 is in an "on" state (e.g., closed, conducting), and transistor 138 of inverter stage circuit 108 is off. When the TB node is at logic high, the T node at the output of inverter 162 is at logic low. Therefore, transistor 128 of reference current generator circuit 104 is off and pass transistor 118 is on, allowing the voltage at node N21H to be substantially equal to the VDIV1 voltage of voltage divider circuit 102. When transistor 138 is off, pull-up resistor 170 pulls node N31H up to the voltage at the VESD rail node, and node N31L is driven to the VDIV1 node voltage by transistor 136. Therefore, transistors 140-148 in inverter stage circuits 110-112 are off. Thus, a feedback loop is formed from the TL output of inverter stage circuit 110 to the input of inverter stage circuit 108.

[0025] During an ESD event, a voltage spike on the VESD rail node causes a voltage increase at node N21L (due to capacitive coupling via capacitors 164 and 166) to a level sufficient to turn on transistor 138 of inverter stage circuit 108. When transistor 138 is on, nodes N31H and N31L are pulled to the voltage at the VSS supply node, thereby driving the trigger output nodes TL, TM, and TH of the corresponding inverter stage circuits 110, 112, and 114 to the VESD rail node voltage. Accordingly, when trigger output nodes TH, TM, and TL are driven to the VESD rail node voltage, the corresponding clamping transistors 150, 152, and 154 turn on and draw ESD current from the VDD supply node to the VSS supply node. In this embodiment, the drive strength of transistors 140-148 is sufficient to overcome the relatively weak bias strength of resistor 172 and bias generator circuits 156 and 158 during an ESD event.

[0026] Figure 2 An example embodiment 200 for bias generation of a corresponding clamping device according to an embodiment is shown in simplified schematic form. In this embodiment, example embodiment 200 includes a clamping circuit 116 (in... Figure 1 The circuit system (described in the image), and the circuits corresponding to bias generator circuits 156 and 158 respectively (in the image). Figure 1The bias generator circuits 202 and 204 are depicted in the diagram. In this embodiment, bias generator circuit 202 is implemented as a resistor 206 coupled between the control electrode of clamping transistor 150 and node N41H. Resistor 206 includes a first terminal connected to the control electrode of clamping transistor 150 and a second terminal connected to node N41H. Similarly, bias generator circuit 204 is implemented as a resistor 208 coupled between the control electrode of clamping transistor 152 and node N41L. Resistor 208 includes a first terminal connected to the control electrode of clamping transistor 152 and a second terminal connected to node N41L. Therefore, when the trigger output nodes TH, TM, and TL are not driven to a logic high level (e.g., normal operating mode), the corresponding resistors 206, 208, and 172 couple the corresponding voltages to the control electrodes in a self-biased (off state) manner, such that the Vgs of each of the clamping transistors 150, 152, and 154 is essentially equal to 0 volts.

[0027] Figure 3 An alternative example embodiment 300 for bias generation of a corresponding clamping device according to an embodiment is shown in simplified schematic form. In this embodiment, example embodiment 300 includes a voltage divider circuit 102 (in... Figure 1 The voltage divider circuit 302 (described in the image) corresponds to the clamping circuit 116 (in the image). Figure 1 The clamping circuit 304 (described in the image), and the bias generator circuits 156 and 158 (described in the image) respectively. Figure 1The bias generator circuits 310 and 312 are depicted in the diagram. In this embodiment, the bias generator circuit 310 is implemented as a P-channel pass-through transistor 306 coupled between the control electrode of the clamping transistor 150 and a second voltage tap node labeled VDIV2 of the voltage divider circuit 302. Transistor 306 includes a first current electrode connected at the VDIV2 node, a second current electrode connected at the control electrode of the clamping transistor 150, and a control electrode connected at the T node. Similarly, the bias generator circuit 312 is implemented as a P-channel pass-through transistor 308 coupled between the control electrode of the clamping transistor 152 and a third voltage tap node labeled VDIV3 of the voltage divider circuit 302. Transistor 308 includes a first current electrode connected at the VDIV3 node, a second current electrode connected at the control electrode of the clamping transistor 150, and a control electrode connected at the T node. In this embodiment, the voltage divider circuit 302 is configured to provide a voltage at the VDIV2 node that is substantially equal to two-thirds of the VESD rail node voltage (e.g., 2 / 3 * VDD), and is configured to provide a voltage at the VDIV3 node that is substantially equal to one-third of the VESD rail node voltage (e.g., 1 / 3 * VDD). Therefore, when the control electrodes of transistors 306 and 308 are at logic low during normal operation (and the trigger output nodes TH, TM, and TL are not driven to logic high), the VDIV2 and VDIV3 voltages are coupled to the corresponding control electrodes of clamping transistors 150 and 152, such that the voltage at the N41L node is substantially equal to one-third of the VDD voltage (i.e., 1 / 3 * VDD) and the voltage at the N41H node is substantially equal to two-thirds of the VDD voltage (i.e., 2 / 3 * VDD), because the Vgs of each of the clamping transistors 150, 152, and 154 is substantially equal to 0 volts.

[0028] Figure 4An alternative example of an ESD protection circuit 400 according to an embodiment is shown in simplified schematic form. In this embodiment, the ESD protection circuit 400 includes a voltage divider circuit 402, a reference current generator circuit 404, a resistor-capacitor (RC) filter stage circuit 406, inverter stage circuits 408-412, and a clamping circuit 414. The reference current generator circuit 404, the RC stage circuit 406, and the inverter stage circuits 408-412 together form an RC-based transient triggering circuit of the ESD protection circuit 400. In this embodiment, the triggering circuit is coupled between an ESD rail node labeled VESD and a first supply node labeled VSS, and the clamping circuit 414 is coupled between a second supply node labeled VDD and the VSS supply node. In this embodiment, the VDD supply node is configured to supply a positive operating voltage (e.g., ~3.3 volts at a 16nm technology node), and the VSS supply node is configured to supply ground (e.g., zero volts). The VESD rail node acts as a separate supply rail for the triggering circuit. In this embodiment, the VESD rail may be coupled to multiple input / output (I / O) pads and a VDD supply node. In some embodiments, separate supply rails (VDD and VESD) allow triggering circuitry to overdrive or "boost" the clamping circuitry to a voltage exceeding the VDD rail voltage during an ESD event. In some embodiments, the VESD and VDD rails may be combined into a single VDD supply rail. For illustrative purposes, the VESD rail node voltage may be characterized as being substantially equal to the VDD supply node voltage during normal operating modes (e.g., non-ESD events) and at or above the VDD supply node voltage during an ESD event.

[0029] In this embodiment, the voltage divider circuit 402 is configured to be connected in series between the VESD rail node and the VSS supply node. In this embodiment, the voltage divider circuit 402 is configured to generate a first reference voltage VDIV1 at a first tap node labeled VDIV1. In this embodiment, the VDIV1 node is configured to provide a voltage substantially equal to half the voltage of the VESD rail node. Therefore, the same number of transistors connected in series between the VDIV1 node and the VSS supply node are connected in series between the VDIV1 node and the VESD rail node.

[0030] exist Figure 4In the embodiment depicted, the reference current generator circuit 404 includes P-channel transistors 420, 422, and 426, and N-channel transistors 424, 428, and 430 coupled between the VESD rail node and the VSS supply node. The reference current generator circuit 404 is coupled to the voltage divider circuit 402 via a P-channel pass transistor 418. Transistor 418 includes a first current electrode connected at the VDIV1 node, a second current electrode connected at the input of the reference current generator circuit 404 at a node labeled N24H, and a control electrode connected at a node labeled T. In this embodiment, transistors 420, 424, and 428 are connected in series in a first branch, and transistors 422, 426, and 428 are connected in series in a second branch. Transistor 420 includes a first current electrode and a control electrode connected at the VESD rail node, and a second current electrode connected at the first current electrode of transistor 424. Transistor 424 includes a control electrode connected at node N24H and a second current electrode connected at node N14. Transistor 428 includes a first current electrode connected at node N14, a second current electrode connected at the VSS supply node, and a control electrode connected at node T.

[0031] Transistor 422 includes a first current electrode connected to the VESD rail node, a control electrode connected to the control electrode of transistor 420, and a second current electrode connected to the first current electrode of transistor 426. Transistor 426 includes a control electrode connected to the N24H node and a second current electrode connected to a bias reference node labeled VBR. Transistor 430 includes a first current electrode and a control electrode connected to node VBR, and a second current electrode connected to the VSS supply node. In this embodiment, the reference current generator circuit 404 is configured to generate a bias reference voltage VBR at the VBR node.

[0032] The RC filter stage circuit 406 includes capacitors 454 and 456, a resistor 458, and N-channel transistors 432 and 434 coupled between the VESD rail node and the VSS supply node. The RC filter stage circuit 406 is coupled to the output of the reference current generator circuit 404 at the VBR node. The RC filter stage circuit 406 is configured to receive a bias reference voltage VBR generated at the output of the reference current generator circuit 404. In this embodiment, capacitors 454 and 456 are characterized as P-channel transistors configured as capacitors. Capacitor 454 includes a first terminal connected to the VESD rail node and a second terminal connected to the N24H node. Capacitor 456 includes a first terminal connected to the N24H node and a second terminal connected to a node labeled N21L. The first terminal of resistor 458 is connected to the N24L node, and the second terminal of resistor 458 is connected to the first current electrode of transistors 432 and 434. Transistor 432 further includes a control electrode connected at the VBR node and a second current electrode connected at the VSS supply node. Transistor 434 further includes a control electrode connected at the node labeled TB and a second current electrode connected at the VSS supply node.

[0033] The inverter stage circuits 408-412 of the ESD protection circuit 400 are coupled between the VESD rail node and the VSS supply node. The first inverter stage circuit 408 is coupled to the N24H and N24L output nodes of the RC filter stage circuit 406. In this embodiment, the first inverter stage circuit 408 includes a pull-up resistor 460 and N-channel transistors 436 and 438 connected in series between the VESD rail node and the VSS supply node. A first end of the resistor 460 is connected at the VESD rail node, and a second end of the resistor 460 is connected at the node labeled N34H to the first current electrode of transistor 436. The control electrode of transistor 436 is connected at the N24H node, and the second current electrode of transistor 436 is connected at the node labeled N34L to the first current electrode of transistor 438. The control electrode of transistor 438 is connected at the N24L node, and the second current electrode of transistor 438 is connected at the VSS supply node to the first current electrode of transistor 438.

[0034] Multiple second inverter stage circuits 410 and 412 are coupled to the N34H and N34L output nodes of the first inverter stage circuit 408. In this embodiment, inverter stage circuits 410 and 412 have corresponding trigger outputs, labeled TL and TH, coupled to the corresponding clamping devices of clamping circuit 414. The TL inverter stage circuit 410 includes P-channel transistors 440 and 442 connected in series. The first current electrode of transistor 440 is connected at the VESD rail node, the control electrode of transistor 440 is connected at the N34H node, and the second current electrode of transistor 440 is connected to the first current electrode of transistor 442. The control electrode of transistor 442 is connected at the N34L node, and the second current electrode of transistor 442 is connected at the TL node. The TH inverter stage circuit 412 includes a P-channel transistor 444. The first current electrode of transistor 444 is connected to the VESD rail node, the control electrode of transistor 444 is connected to the N34H node, and the second current electrode of transistor 444 is connected to the TH node.

[0035] In this embodiment, the clamping circuit 414 includes N-channel clamping transistors 446 and 448 connected in series between the VDD supply node and the VSS supply node. Each of the clamping transistors 446 and 448 includes a body electrode connected to its source electrode, such as... Figure 4 As depicted in the diagram. The first current electrode (e.g., drain) of clamping transistor 446 is connected to the VDD supply node, the control electrode (e.g., gate) of transistor 446 is connected to the TH node, and the second current electrode (e.g., source) of transistor 446 is connected to the first current electrode (e.g., drain) of transistor 448 at a node labeled N44. The control electrode (e.g., gate) of transistor 448 is connected to the TL node, and the second current electrode (e.g., source) of transistor 448 is connected to the VSS supply node. In this embodiment, during normal operation, the voltage at node N44 is substantially equal to half the VDD voltage (i.e., 1 / 2 * VDD). In this embodiment, the clamping transistors 446 and 448 of clamping circuit 414 are formed with substantially similar physical layouts, including substantially similar physical parameters (e.g., width, length) and electrical characteristics (e.g., IV characteristics).

[0036] In this embodiment, bias generator circuit 416 is coupled to the control electrode of clamp transistor 446, and pull-down resistor 172 is coupled to the control electrode of clamp transistor 448. In this embodiment, bias generator circuit 416 is implemented as resistor 462 coupled between the control electrode of clamp transistor 446 and node N44. Resistor 462 includes a first terminal connected to the control electrode of clamp transistor 446 and a second terminal connected to node N44. Similarly, resistor 464 includes a first terminal connected to the control electrode of clamp transistor 448 and a second terminal connected to the VSS supply node. In this embodiment, during normal operation, resistor 462 is configured to provide a voltage at the control electrode of clamp transistor 446 that is substantially equal to half the VDD voltage (i.e., 1 / 2 * VDD), and resistor 464 is configured to provide a voltage at the control electrode of clamp transistor 448 that is substantially equal to the voltage at the VSS supply node. Because each of clamping transistors 446 and 448 is configured to have substantially the same electrical characteristics, the Vgs of clamping transistor 446 is substantially equal to the Vgs of clamping transistor 448 (e.g., 0 volts) during normal operating mode. Therefore, the voltage at node N44 is substantially equal to half the VDD voltage (i.e., 1 / 2 * VDD). Clamping circuit 414 is configured to create a shunt between the VDD supply node and the VSS supply node during an ESD event and to absorb the current associated with the ESD event.

[0037] In this embodiment, the trigger output node TL is coupled to the input of inverter 450. The output of inverter 450 is connected at node TB to the input of inverter 452 and the control electrode of transistor 434. The output of inverter 452 is connected at node T to the control electrodes of transistor 418 and transistor 428.

[0038] In normal operating mode (e.g., non-ESD events), transistors 440 and 442 of inverter stage 410 are off, allowing resistor 464 to pull the TL node down to logic low. Therefore, the TB node at the output of inverter 450 is logic high, and consequently, transistor 434 of RC filter stage circuit 406 is on, while transistor 438 of inverter stage circuit 408 is off. When the TB node is logic high, the T node at the output of inverter 452 is logic low. Therefore, transistor 428 of reference current generator circuit 404 is off and pass transistor 418 is on, allowing the voltage at node N24H to be substantially equal to the VDIV1 voltage of voltage divider circuit 402. When transistor 438 is off, pull-up resistor 460 pulls node N34H up to the voltage at the VESD rail node, and node N34L is driven by transistor 436 to the VDIV1 node voltage. Therefore, transistors 440-444 in inverter stage circuits 410 and 412 are in the off state. Thus, a feedback loop is formed from the TL output of inverter stage circuit 410 to the input of inverter stage circuit 408.

[0039] During an ESD event, a voltage spike on the VESD rail node causes a voltage increase at node N24L (due to capacitive coupling via capacitors 454 and 456) to a level sufficient to turn on transistor 438 of inverter stage circuit 408. When transistor 438 is on, nodes N34H and N34L are pulled to the voltage at the VSS supply node (e.g., 0 volts), thereby driving the trigger output nodes TL and TH of the corresponding inverter stage circuits 410 and 412 to the VESD rail node voltage. Accordingly, when trigger output nodes TH and TL are driven to the VESD rail node voltage, the corresponding clamping transistors 446 and 448 turn on and draw ESD current from the VDD supply node to the VSS supply node.

[0040] Figure 5 An example analog current-voltage graph 500 of an ESD protection circuit according to an embodiment is shown in simplified graph form. The current-voltage graph 500 includes curves corresponding to… Figure 1 and 2The simulation results of the clamping circuit system depicted are shown in Figure 502 and Figure 504. Voltage values ​​in millivolts (mV) are indicated on the X-axis, labeled voltage, and the corresponding current values ​​in amperes (A) are indicated on the Y-axis, labeled current. Waveform 502 is an example waveform representing the change in leakage current caused by the difference between the gate voltage (at the TH node) and two-thirds of the VDD voltage (i.e., 2 / 3 * VDD), and waveform 504 is an example waveform representing the leakage current caused by the difference between the gate voltage (at the TM node) and one-third of the VDD voltage (i.e., 1 / 3 * VDD).

[0041] In graph 500, waveform 502 shows the increase in leakage current when the voltage at the gate of clamping transistor 150 deviates from two-thirds of the VDD voltage (i.e., 2 / 3 * VDD). Similarly, waveform 504 shows the increase in leakage current when the voltage at the gate of clamping transistor 152 deviates from one-third of the VDD voltage (i.e., 1 / 3 * VDD). When the VDD supply node voltage is equally divided across the clamping device, the voltage deviation at the gate of the clamping transistor may lead to an overall increase in leakage current, such as... Figure 5 As shown in the diagram. Therefore, when the voltages at the gate and source terminals are substantially the same (i.e., Vgs = 0 volts), the leakage current of each clamped transistor is minimized. Therefore, for low-power devices, minimizing the leakage current of the clamped transistors is desirable.

[0042] Therefore, it should be understood that a low-leakage ESD protection circuit has been provided. The ESD protection circuit for a semiconductor device includes a trigger circuit and a clamping circuit. The trigger circuit includes an RC transient circuit configured to detect an ESD event and an inverter stage configured to drive the transistors of the clamping circuit during an ESD event. The clamping circuit includes a stack of ESD transistors (e.g., multiple ESD transistors connected in series) between a power rail and a ground supply rail. The ESD transistors are configured to form a shunt between the power rail and the ground supply rail during an ESD event and to absorb the current associated with the ESD event. After the RC transient circuit detects the ESD event, the inverter stage drives the gate of the ESD transistor, thereby turning on the ESD transistor. The stacked ESD transistors then absorb the current associated with the ESD event. In normal operating modes (e.g., non-ESD event conditions), the ESD transistors are configured to be in a low-leakage mode. For example, the clamping circuit may include a resistor connected between the gate and source terminals of the respective ESD transistor of each transistor in the ESD transistor stack. The output of the inverter stage is configured to a high-impedance state during normal operation, allowing each resistor to self-bias its corresponding transistor to the Vgs = 0 volt off state. By self-biasing the ESD transistors in the ESD transistor stack in this way, leakage current associated with the ESD transistors can be minimized during normal operation.

[0043] Since the devices implementing this invention are mostly composed of electronic components and circuits known to those skilled in the art, the circuit details will not be described to any greater extent than those deemed necessary above in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or departing from its teachings.

[0044] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with reference to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0045] Furthermore, as used herein, the term “a” or “an” is defined as one or more. Moreover, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed as implying that another claim element introduced by the indefinite article “a” or “an” limits any particular claim containing such introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrase “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same applies to the use of definite articles.

[0046] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority of such elements.

Claims

1. An electrostatic discharge (ESD) protection circuit, characterized in that, include: A clamping circuit, coupled between a first voltage supply node and a second voltage supply node, the clamping circuit comprising: The first transistor has a first current electrode, a second current electrode coupled to the second voltage supply node, and a control electrode coupled to the second voltage supply node through a first resistor; The second transistor is coupled in series with the first transistor, and the second transistor has a first current electrode, a second current electrode, and a control electrode coupled at the first voltage supply node. A first bias generator circuit, coupled to the control electrode of the second transistor, is configured to make the gate-to-source voltage of the second transistor substantially equal to the gate-to-source voltage of the first transistor during normal operation. A trigger circuit coupled to the clamping circuit, the trigger circuit having a first output coupled to the control electrode of the first transistor and a second output coupled to the control electrode of the second transistor.

2. The ESD protection circuit according to claim 1, characterized in that, The clamping circuit further includes a third transistor series coupled between the first transistor and the second transistor, the third transistor having a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode.

3. The ESD protection circuit according to claim 2, characterized in that, The clamping circuit further includes a second bias generator circuit coupled to the control electrode of the third transistor, the second bias generator circuit being configured to make the gate-to-source voltage of the third transistor substantially equal to the gate-to-source voltage of the first transistor during the normal operating mode.

4. The ESD protection circuit according to claim 1, characterized in that, The trigger circuit includes: The first inverter stage includes: The first trigger transistor has a first current electrode, a second current electrode coupled to a third voltage supply node, and a control electrode coupled to the first trigger node. The second trigger transistor has a first current electrode coupled to the first output of the trigger circuit, a second current electrode coupled to the first current electrode of the first trigger transistor, and a control electrode coupled to the second trigger node; and The second inverter stage includes: The third trigger transistor has a first current electrode coupled to the second output of the trigger circuit, a second current electrode coupled to the third voltage supply node, and a control electrode coupled to the first trigger node.

5. An electrostatic discharge (ESD) protection circuit, characterized in that, include: A clamping circuit, coupled between a first voltage supply node and a second voltage supply node, the clamping circuit comprising: The first transistor has a first current electrode, a second current electrode coupled to the second voltage supply node, and a control electrode coupled to the second voltage supply node through a first resistor; A second transistor is coupled in series with the first transistor, and the second transistor has a first current electrode, a second current electrode coupled at the first voltage supply node, and a control electrode coupled to the second current electrode of the second transistor through a second resistor. A first bias generator circuit, coupled to the control electrode of the second transistor, is configured to make the gate-to-source voltage of the second transistor substantially equal to the gate-to-source voltage of the first transistor during normal operation. A trigger circuit coupled to the clamping circuit, the trigger circuit having a first output coupled to the control electrode of the first transistor and a second output coupled to the control electrode of the second transistor, the trigger circuit being configured to turn on the first transistor and the second transistor of the clamping circuit during an ESD event.

6. The ESD protection circuit according to claim 5, characterized in that, The clamping circuit further includes a third transistor series coupled between the first transistor and the second transistor, the third transistor having a first current electrode coupled to the second current electrode of the second transistor, a second current electrode coupled to the first current electrode of the first transistor, and a control electrode.

7. The ESD protection circuit according to claim 5, characterized in that, The trigger circuit includes: The first inverter stage includes: The first trigger transistor has a first current electrode, a second current electrode coupled to a third voltage supply node, and a control electrode coupled to the first trigger node. The second trigger transistor has a first current electrode coupled to the first output of the trigger circuit, a second current electrode coupled to the first current electrode of the first trigger transistor, and a control electrode coupled to the second trigger node; and The second inverter stage includes: The third trigger transistor has a first current electrode coupled to the second output of the trigger circuit, a second current electrode coupled to the third voltage supply node, and a control electrode coupled to the first trigger node.

8. An electrostatic discharge (ESD) protection circuit, characterized in that, include: A clamping circuit, coupled between a first voltage supply node and a second voltage supply node, the clamping circuit comprising: The first transistor has a first current electrode, a second current electrode coupled to the second voltage supply node, a control electrode coupled to the second voltage supply node through a first resistor, and a body electrode coupled to the second voltage supply node; The second transistor has a first current electrode, a second current electrode coupled to the first current electrode of the first transistor at a first clamping node, a control electrode, and a body electrode coupled to the second current electrode. The third transistor has a first current electrode coupled to the first voltage supply node, a second current electrode coupled to the first current electrode of the second transistor at the second clamping node, a control electrode, and a body electrode coupled to the second current electrode. A first bias generator circuit is coupled to the control electrode of the second transistor; A second bias generator circuit is coupled to the control electrode of the third transistor; and A trigger circuit coupled to the clamping circuit, the trigger circuit having a first output coupled to the control electrode of the first transistor, a second output coupled to the control electrode of the second transistor, and a third output coupled to the control electrode of the third transistor.

9. The ESD protection circuit according to claim 8, characterized in that, Additionally, a voltage divider circuit coupled to the trigger circuit is included, the voltage divider circuit having a first tap and being configured to generate a first reference voltage at the first tap.

10. The ESD protection circuit according to claim 8, characterized in that, The first bias generator circuit includes a second resistor having a first end coupled to the control electrode of the second transistor and a second end coupled to the second current electrode of the second transistor, and wherein the second bias generator circuit includes a third resistor having a first end coupled to the control electrode of the third transistor and a second end coupled to the second current electrode of the third transistor.

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