Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device includes: a first semiconductor structure including a memory array; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bond pad electrically connected to the memory array, the first bond pad being in the first insulating layer; and a second bonding pad electrically connected to the first transistor, the second bonding pad being in the second insulating layer. The first bonding pad and the second bonding pad are in contact with each other. At least one of the plurality of sidewalls of the first bonding pad and the second bonding pad includes a curved portion.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202011013407.X (application date: September 24, 2020, invention title: semiconductor device and method of manufacturing thereof). Technical Field

[0002] This disclosure generally relates to electronic devices, and more specifically, to a semiconductor device and a method of manufacturing the same. Background Technology

[0003] Semiconductor devices include integrated circuits configured with metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design specifications of semiconductor devices continue to shrink, the miniaturization of MOSFETs is accelerating.

[0004] Miniaturization of MOSFETs can lead to short-channel effects, which may degrade the operating characteristics of semiconductor devices. Therefore, various methods have been investigated to overcome the limitations caused by the high integration of semiconductor devices while forming semiconductor devices with improved performance.

[0005] Furthermore, these integrated circuits prioritize operational reliability and low power consumption. Therefore, methods have been investigated to form devices with higher reliability and lower power consumption using smaller form factors. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a semiconductor device includes: a first semiconductor structure including a memory array; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bonding pad electrically connected to the memory array, the first bonding pad being located in the first insulating layer; and a second bonding pad electrically connected to the first transistor, the second bonding pad being located in the second insulating layer, wherein the first bonding pad and the second bonding pad are in contact with each other, and wherein at least one of a plurality of sidewalls of the first bonding pad and the second bonding pad includes a curved portion.

[0007] According to another embodiment of this disclosure, a semiconductor device includes: a first semiconductor structure including a stacked structure, a channel structure penetrating the stacked structure, and a bit line electrically connected to the channel structure; a second semiconductor structure spaced apart from the first semiconductor structure, the second semiconductor structure including a first transistor; a first insulating layer between the first semiconductor structure and the second semiconductor structure; a second insulating layer between the second semiconductor structure and the first insulating layer; a first bonding pad located in the first insulating layer, the first bonding pad being electrically connected to the channel structure; and a second bonding pad located in the second insulating layer, the second bonding pad being electrically connected to the first transistor, the second bonding pad contacting the first bonding pad, wherein the first bonding pad includes: a first portion contacting the second bonding pad; a second portion contacting the bit line; and a third portion between the first portion and the second portion, wherein the sidewalls of the third portion are curved.

[0008] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes the following steps: forming an insulating layer; forming a hard mask layer including a first opening on the insulating layer; etching the insulating layer using the hard mask layer as an etch barrier to form a second opening in the insulating layer; enlarging the first opening of the hard mask layer; after the first opening is enlarged, etching the insulating layer using the hard mask layer as an etch barrier to form a third opening and a fourth opening in the insulating layer; and forming bonding pads in the third opening and the fourth opening, wherein the width of the fourth opening is greater than the width of the third opening, wherein the third opening and the fourth opening overlap each other, and wherein the corner between the third opening and the fourth opening of the insulating layer is curved.

[0009] According to another embodiment of this disclosure, a method of manufacturing a semiconductor device includes the following steps: forming an insulating layer; forming a hard mask layer including a first opening on the insulating layer; etching the insulating layer using the hard mask layer as an etch barrier to form a second opening; exposing the top surface of the insulating layer by enlarging the first opening of the hard mask layer; after enlarging the first opening, etching the insulating layer using the hard mask layer as an etch barrier to form a third opening and a fourth opening in the insulating layer; and forming bonding pads in the third opening and the fourth opening, wherein the width of the fourth opening is greater than the width of the third opening, and wherein the third opening and the fourth opening overlap each other. Attached Figure Description

[0010] Example embodiments are described below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure possible for those skilled in the art.

[0011] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0012] Figure 1A This is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' is shown.

[0014] Figures 2A to 2F It is shown Figure 1A and Figure 1B A cross-sectional view of the manufacturing method of the semiconductor device shown.

[0015] Figure 3 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 5A This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 5B It is along Figure 5A The plan view of the second joint structure in the first region as shown by line B-B'.

[0019] Figure 5C It is along Figure 5A The plan view of the second joint structure in the second region as seen by line B-B'.

[0020] Figure 6 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0021] Figures 7A to 7H It is shown Figures 5A to 5C A cross-sectional view of the manufacturing method of the semiconductor device shown.

[0022] Figure 8 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0023] Figure 9 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0024] The specific structural and functional descriptions disclosed herein are merely illustrative in order to describe implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the implementations set forth herein.

[0025] Some implementations relate to a semiconductor device capable of improving operational reliability and a method of manufacturing the semiconductor device.

[0026] Figure 1A This is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The cross-sectional view taken by line A-A' is shown.

[0027] Reference Figure 1A and Figure 1B The semiconductor device may include a first insulating layer 110, a second insulating layer 120, a conductor CB, and a bonding pad BP.

[0028] The first insulating layer 110 may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be different intersecting directions. In an example, the first direction D1 and the second direction D2 may be orthogonal to each other. The first insulating layer 110 may include an insulating material. In an example, the first insulating layer 110 may include an oxide or a nitride.

[0029] Conductor CB may be disposed in the first insulating layer 110. Conductor CB may extend in the second direction D2. The top surface of conductor CB may lie in the same plane as the top surface of the first insulating layer 110. Conductor CB may comprise a conductive material. In an example, conductor CB may comprise copper, aluminum, or tungsten.

[0030] A second insulating layer 120 may be disposed on the first insulating layer 110. The second insulating layer 120 may have a plate shape extending along a plane defined by a first direction D1 and a second direction D2. The second insulating layer 120 may include an insulating material. In an example, the second insulating layer 120 may include SiCN.

[0031] Bonding pad BP may be disposed within the second insulating layer 120. Bonding pad PB may penetrate the second insulating layer 120 in a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. In the example, the third direction D3 may be orthogonal to the first direction D1 and the second direction D2.

[0032] The bonding pad BP may include a conductive portion BP_C and a barrier portion BP_B. The barrier portion BP_B may be disposed on the surface of the second insulating layer 120. The conductive portion BP_C may be disposed on the surface of the barrier portion BP_B. The barrier portion BP_B may be disposed between the conductive portion BP_C and the second insulating layer 120. The conductive portion BP_C and the second insulating layer 120 may be spaced apart from each other by the barrier portion BP_B.

[0033] The conductive portion BP_C may include a conductive material. In the example, the conductive portion BP_C may include copper, aluminum, or tungsten. In the example, the barrier portion BP_B may include titanium, titanium nitride, tantalum, or tantalum nitride.

[0034] The bonding pad BP may include a first sidewall SW1 facing each other in a first direction D1 and a second sidewall SW2 facing each other in a second direction D2. The first sidewall SW1 and the second sidewall SW2 may be connected to each other. The second sidewall SW2 may connect the first sidewall SW1 to each other. The first sidewall SW1 may connect the second sidewall SW2 to each other. The first sidewall SW1 and the second sidewall SW2 of the bonding pad BP may be defined by the surface of the barrier portion BP_B.

[0035] Each first sidewall SW1 of the bonding pad BP may include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2. The first flat portion F1 may be connected to the first curved portion C1. The first curved portion C1 may be connected to the second curved portion C2. The second flat portion F2 may be connected to the second curved portion C2. The first flat portion F1, the first curved portion C1, the second curved portion C2, and the second flat portion F2 are connected to form the first sidewall SW1 of the bonding pad BP.

[0036] The first flat portion F1 can be connected to the bottom surface BS of the bonding pad BP. The second flat portion F2 can be connected to the top surface TS of the bonding pad BP. From Figure 1B The cross-sectional angles shown, the first flat portion F1 and the second flat portion F2 can be represented as straight lines. In the example, from... Figure 1B The cross-sectional angle shown indicates that the first curvature center C1_C of the first curved portion C1 can be located outside the bonding pad BP. In the example, from Figure 1B As shown by the cross-sectional angle, the second curvature center C2_C of the second curved portion C2 can be located inside the bonding pad BP.

[0037] The first curved portion C1 and the second curved portion C2 can be bent in different directions. In the example, the first curved portion C1 can be bent such that the central portion of the first curved portion C1 protrudes toward the interior of the bonding pad BP (in a convex shape), and the second curved portion C2 can be bent such that the central portion of the second curved portion C2 protrudes toward the exterior of the bonding pad BP (in a convex shape).

[0038] The distance between the first flat portions F1 in the first direction D1 can be defined as a first distance L1. The first distance L1 can decrease as the first flat portions F1 get closer to the conductor CB. The distance between the second flat portions F2 in the first direction D1 can be defined as a second distance L2. The second distance L2 can decrease as the second flat portions F2 get closer to the conductor CB. Alternatively, the second distance L2 can be constant at all levels. The second distance L2 can be greater than the first distance L1.

[0039] The distance between the first curved portions C1 in the first direction D1 and the distance between the second curved portions C2 in the first direction D1 can be defined as a third distance L3. The third distance L3 decreases as the first curved portions C1 and the second curved portions C2 get closer to the conductor CB. The maximum value of the third distance L3 can be equal to the minimum value of the second distance L2. The minimum value of the third distance L3 can be equal to the maximum value of the first distance L1.

[0040] The bonding pad BP may include a first part PA1, a second part PA2, and a third part PA3. The first part PA1 may be the portion connected to the conductor CB. The second part PA2 may be the portion connected to the first part PA1. The third part PA3 may be the portion connected to the second part PA2. The second part PA2 may be located between the first part PA1 and the third part PA3.

[0041] The sidewall of the first part PA1 may be defined by a first flat portion F1. The sidewall of the first part PA1 may be flat. The sidewall of the second part PA2 may be defined by a first curved portion C1 and a second curved portion C2. The sidewall of the second part PA2 may be curved. The first curved portion C1 may be formed at the portion of the sidewall of the second part PA2 that connects to the first part PA1. The second curved portion C2 may be formed at the portion of the sidewall of the second part PA2 that connects to the third part PA3. The sidewall of the third part PA3 may be defined by a second flat portion F2. The sidewall of the third part PA3 may be flat.

[0042] As the first portion PA1 gets closer to the conductor CB, the width of the first portion PA1 can decrease. In the example, the width of the first portion PA1 in the first direction D1 can decrease as the first portion PA1 gets closer to the conductor CB. The width of the first portion PA1 in the first direction D1 can be equal to the first distance L1.

[0043] As the second portion PA2 gets closer to the conductor CB, its width can decrease. In the example, the width of the second portion PA2 in the first direction D1 can decrease as the second portion PA2 gets closer to the conductor CB. The width of the second portion PA2 in the first direction D1 can be equal to the third distance L3.

[0044] As the third portion PA3 gets closer to the conductor CB, its width can decrease. In the example, the width of the third portion PA3 in the first direction D1 can decrease as the third portion PA3 gets closer to the conductor CB. The width of the third portion PA3 in the first direction D1 can be equal to the second distance L2.

[0045] Similar to the first sidewall SW1, each of the second sidewalls SW2 of the bonding pad BP may include curved portions and flat portions.

[0046] In the semiconductor device according to this embodiment, the sidewall of the bonding pad BP includes a curved portion, and the width of the third portion PA3, which is the upper part of the bonding pad BP, is relatively large. Therefore, the bonding pad BP can have improved gap-filling characteristics, and the bonding pad BP can be formed without any gaps. Furthermore, since the width of the first portion PA1, which is the lower part of the bonding pad BP, is relatively small, the overlap allowance between the conductor CB and the bonding pad BP can be ensured.

[0047] Figures 2A to 2F It is shown Figure 1A and Figure 1B A cross-sectional view of a semiconductor device manufacturing method is shown. For simplicity, references to other methods are omitted. Figure 1A and Figure 1B Redundant descriptions of the components being described.

[0048] The following manufacturing method is only Figure 1A and Figure 1B An embodiment of the manufacturing method of the semiconductor memory device shown. Figure 1A and Figure 1B The manufacturing method of the semiconductor memory device shown is not limited to the manufacturing method described below.

[0049] Reference Figure 2A A conductor CB can be formed in the first insulating layer 110. A trench can be formed by etching the first insulating layer 110, and the conductor CB can be formed in the trench. The conductor CB can be an interconnect structure. In the example, the conductor CB can be a bit line, a contact plug, or a wire.

[0050] The first insulating layer 110 may include an insulating material. In an example, the first insulating layer 110 may include an oxide or a nitride. The conductor CB may include a conductive material. In an example, the conductor CB may include copper, aluminum, or tungsten.

[0051] A second insulating layer 120 may be formed on the first insulating layer 110. The second insulating layer 120 may include an insulating material. In an example, the second insulating layer 120 may include SiCN. In an example, the second insulating layer 120 may be a single layer.

[0052] A first hard mask layer MA1 may be formed on the second insulating layer 120. The thickness of the first hard mask layer MA1 may be greater than the thickness of the second insulating layer 120. The length of the first hard mask layer MA1 in the third direction D3 may be greater than the length of the second insulating layer 120 in the third direction D3. In an example, the first hard mask layer MA1 may comprise amorphous carbon.

[0053] A second hard mask layer MA2 may be formed on the first hard mask layer MA1. The second hard mask layer MA2 may include an insulating material. In an example, the second hard mask layer MA2 may include SiON.

[0054] Reference Figure 2B A photoresist pattern PR can be formed on the second hard mask layer MA2. After the photoresist layer is formed on the second hard mask layer MA2, the photoresist pattern PR can be formed by patterning the photoresist layer through exposure and development processes.

[0055] Subsequently, a photoresist pattern PR can be used as an etching barrier to etch the second hard mask layer MA2 and the first hard mask layer MA1. Therefore, the first hard mask layer MA1 and the second hard mask layer MA2 can be patterned, and a first opening OP1 can be formed in the first hard mask layer MA1.

[0056] Subsequently, the first hard mask layer MA1 can be used as an etching barrier to etch the second insulating layer 120. Therefore, the second insulating layer 120 can be patterned, and a second opening OP2 can be formed in the second insulating layer 120.

[0057] A second opening OP2 can be formed, so that the conductor CB is not exposed. The second opening OP2 can penetrate a portion of the second insulating layer 120. The second opening OP2 can not completely penetrate the second insulating layer 120.

[0058] The bottom surface OP2_B of the second opening OP2 may be defined by the second insulating layer 120. The level of the bottom surface OP2_B of the second opening OP2 may be higher than the level of the bottom surface of the second insulating layer 120. The bottom surface OP2_B of the second opening OP2 may be spaced apart from the conductor CB in the third direction D3. A portion of the second insulating layer 120 may be disposed between the bottom surface OP2_B of the second opening OP2 and the conductor CB.

[0059] The width of the second opening OP2 in the first direction D1 can be defined as a first width W1. The first width W1 can be substantially equal to the width of the conductor CB in the first direction D1. The width of the first opening OP1 can be substantially equal to the width of the second opening OP2. The width of the first opening OP1 in the first direction D1 can be equal to the first width W1.

[0060] In one embodiment, as shown in the figure, the photoresist pattern PR and the second hard mask layer MA2 retained after forming the first opening OP1 and the second opening OP2 can be removed. In another embodiment, unlike the one shown in the figure, the second opening OP2 can be formed after forming the first opening OP1 and removing the photoresist pattern PR and the second hard mask layer MA2. When the photoresist pattern PR is removed, the second hard mask layer MA2 can protect the first hard mask layer MA1. When the photoresist pattern PR and the second hard mask layer MA2 are removed after forming the first opening OP1, the top surface of the first hard mask layer MA1 can be exposed in the process of forming the second opening OP2, and a portion of the top surface of the first hard mask layer MA1 can be etched.

[0061] Reference Figure 2C The first opening OP1 of the first hard mask layer MA1 can be enlarged. By etching the first hard mask layer MA1, the first hard mask layer MA1 can be reduced in size, and the first opening OP1 can be enlarged. In this example, an isotropic etching process can be used to etch the first hard mask layer MA1. Depending on the etching process, the length (height) of the first hard mask layer MA1 in the third direction D3 can be reduced, and the width of the first opening OP1 can be increased. In this example, the width of the first opening OP1 in the first direction D1 can be increased to a second width W2. The second width W2 can be greater than the first width W1. When the first opening OP1 is enlarged, the top surface of the second insulating layer 120 can be exposed. When the first opening OP1 is enlarged, the first corner CO1 between the top surface of the second insulating layer 120 and the sidewall of the second opening OP2 can be exposed. When the first opening OP1 is enlarged, a first contact point PC can be defined between the top surface of the second insulating layer 120 and the sidewall of the first hard mask layer MA1. The first contact point PC can be the contact point between the top surface of the second insulating layer 120 and the sidewall of the enlarged first opening OP1.

[0062] Reference Figure 2D The first hard mask layer MA1 can be used as an etching barrier to etch the second insulating layer 120. The second insulating layer 120 can be etched through the first opening OP1.

[0063] The second insulating layer 120 can be etched simultaneously with the downward transfer of the first opening OP1 and the second opening OP2. During the transfer of the second opening OP2, a third opening OP3 can be formed in the second insulating layer 120. The third opening OP3 can be formed to expose the conductor CB. During the transfer of the first opening OP1, a fourth opening OP4 can be formed in the second insulating layer 120. The third opening OP3 and the fourth opening OP4 can overlap each other. In this example, the third opening OP3 and the fourth opening OP4 can overlap perpendicularly to each other.

[0064] The width of the third opening OP3 in the first direction D1 can be defined as the third width W3. The width of the fourth opening OP4 in the first direction D1 can be defined as the fourth width W4. The fourth width W4 can be greater than the third width W3. When the third opening OP3 and the fourth opening OP4 are formed, a T-shaped opening can be formed in the second insulating layer 120. The sidewall OP3_S of the third opening OP3 can be flat. The sidewall OP4_S of the fourth opening OP4 can be flat.

[0065] When the second insulating layer 120 is etched, a second corner CO2 and a third corner CO3 can be formed in the second insulating layer 120. The second corner CO2 and the third corner CO3 can be defined by a third opening OP3 and a fourth opening OP4. The second corner CO2 can be formed at the portion where the third opening OP3 and the fourth opening OP4 are connected to each other, and the third corner CO3 can be formed at the portion where the bottom surface OP4_B and the sidewall OP4_S of the fourth opening OP4 are connected to each other.

[0066] CO2 can be released at the second corner of the second insulating layer 120 at the first corner ( Figure 2C The CO1 shown is formed when it transfers downwards, and at the first corner ( Figure 2C The CO1 shown is correspondingly set. CO3 at the third corner of the second insulating layer 120 can be located at the first contact point ( Figure 2C The PC shown is formed as it moves downwards, and forms contact with the first contact point ( Figure 2C The PC settings shown correspond to the settings shown.

[0067] In the etching process, due to the first corner ( Figure 2C The CO1 shown is relatively prominent, so the first corner ( Figure 2C The CO1 shown can be relatively highly exposed to the etching environment, and the first corner ( Figure 2C The etching amount of CO1 shown can be relatively large. Therefore, the first corner ( Figure 2C The CO1 shown can be transferred downwards while rounding, and can form a curved second corner CO2.

[0068] In the etching process, the first contact point ( Figure 2CThe PC shown can be exposed to the etching environment with relatively low exposure, and the first contact point ( Figure 2C The etching amount of the PC shown can be relatively small. Therefore, the first contact point ( Figure 2C The PC shown can be transferred downwards while rounding, and can form a curved third corner CO3.

[0069] The bottom surface OP4_B of the fourth opening OP4 can be connected between the second corner CO2 and the third corner CO3 of the second insulating layer 120. The bottom surface OP4_B of the fourth opening OP4 can be flat or curved. The second corner CO2 can be formed between the bottom surface OP4_B of the fourth opening OP4 and the sidewall OP3_S of the third opening OP3. The third corner CO3 can be formed between the bottom surface OP4_B of the fourth opening OP4 and the sidewall OP4_S of the fourth opening OP4.

[0070] The center of curvature of the second corner CO2 can be located in the second insulating layer 120. The center of curvature of the third corner CO3 can be located in the fourth opening OP4.

[0071] Reference Figure 2E The first hard mask layer MA1 can be removed. In the example, the first hard mask layer MA1 can be removed by a cleaning process.

[0072] Reference Figure 2F A bonding pad BP can be formed in the second insulating layer 120. A first portion PA1 of the bonding pad BP can be formed in the third opening OP3. A second portion PA2 and a third portion PA3 of the bonding pad BP can be formed in the fourth opening OP4.

[0073] The bonding pad BP may include a conductive portion BP_C and a barrier portion BP_B.

[0074] The first sidewall SW1 of the bonding pad BP may include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2. The sidewall of the first portion PA1 of the bonding pad BP may be flat and simultaneously contact the sidewall OP3_S of the third opening OP3 of the second insulating layer 120. The sidewall of the second portion PA2 of the bonding pad BP may be curved and simultaneously contact the second corner CO2 and the third corner CO3 of the second insulating layer 120, as well as the bottom surface OP4_B of the fourth opening OP4. The sidewall of the third portion PA3 of the bonding pad BP may be flat and simultaneously contact the sidewall OP4_S of the fourth opening OP4 of the second insulating layer 120.

[0075] When the bonding pad BP is formed in the second insulating layer 120, the width of the third portion PA3, which is the upper part of the bonding pad BP, in the first direction D1 may be greater than the width of the first portion PA1, which is the lower part of the bonding pad BP.

[0076] Because the width of the fourth opening OP4 of the second insulating layer 120 is relatively large, the bonding pad BP can be formed without any gaps. Because the width of the third opening OP3 of the second insulating layer 120 is relatively small, the overlap allowance between the bonding pad BP and the conductor CB can be ensured.

[0077] In the semiconductor device manufacturing method according to this embodiment, after forming the second opening OP2 in the second insulating layer 120 and the first opening OP1 in the first hard mask layer MA1, the first opening OP1 is enlarged. Subsequently, the second insulating layer 120 is etched through the enlarged first opening OP1. Therefore, a third opening OP3 and a fourth opening OP4 with different widths are formed as a single layer in the second insulating layer 120.

[0078] The third opening OP3 and the fourth opening OP4 are formed through a single etching process, thereby reducing the cost and time of the etching process. Bent second corner CO2 and third corner CO3 can also be formed in the second insulating layer 120. Bonding pads BP are formed in the second insulating layer 120 with the bent second corner CO2 and third corner CO3, thereby improving the gap-filling characteristics of the bonding pads BP and allowing the bonding pads BP to be formed without any voids.

[0079] Figure 3 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0080] Apart from the following, the semiconductor device according to this embodiment may be similar to Figure 1A and Figure 1B The semiconductor device shown.

[0081] Reference Figure 3 The semiconductor device according to this embodiment may include a first insulating layer 110, a second insulating layer 120, a third insulating layer 130, and a fourth insulating layer 140.

[0082] The first conductor CB1 may be disposed in the first insulating layer 110, the first bonding pad BP1 may be disposed in the second insulating layer 120, the second bonding pad BP2 may be disposed in the third insulating layer 130, and the second conductor CB2 may be disposed in the fourth insulating layer 140.

[0083] The first conductor CB1 can be connected to the first bonding pad BP1, the first bonding pad BP1 can be connected to the second bonding pad BP2, and the second bonding pad BP2 can be connected to the second conductor CB2. The first conductor CB1 and the second conductor CB2 can be electrically connected to each other through the first bonding pad BP1 and the second bonding pad BP2.

[0084] The first bonding pad BP1 may include a conductive portion BP1_C and a barrier portion BP1_B. The second bonding pad BP2 may include a conductive portion BP2_C and a barrier portion BP2_B. The sidewall of each of the first bonding pad BP1 and the second bonding pad BP2 may include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2.

[0085] The first flat portion F1 of each of the first bonding pad BP1 and the second bonding pad BP2 may be connected to the first conductor CB1 or the second conductor CB2. The second flat portion F2 of the first bonding pad BP1 may be connected to the third insulating layer 130. The second flat portion F2 of the second bonding pad BP2 may be connected to the first bonding pad BP1.

[0086] A portion of the top surface of the first bonding pad BP1 may contact the bottom surface of the second bonding pad BP2. Another portion of the top surface of the first bonding pad BP1 may contact a portion of the bottom surface of the third insulating layer 130. The width of the top surface of the first bonding pad BP1 in the first direction D1 may be greater than the width of the bottom surface of the second bonding pad BP2 in the first direction D1.

[0087] Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0088] Apart from the following, the semiconductor device according to this embodiment may be similar to Figure 3 The semiconductor device shown.

[0089] Reference Figure 4 The semiconductor device according to this embodiment may include a first insulating layer 110, a second insulating layer 120, a fifth insulating layer 150, a sixth insulating layer 160, and a seventh insulating layer 170.

[0090] The first conductor CB1 may be disposed in the first insulating layer 110, the first bonding pad BP1 may be disposed in the second insulating layer 120, the third bonding pad BP3 may be disposed in the fifth insulating layer 150, the contact CT may be disposed in the sixth insulating layer 160, and the second conductor CB2 may be disposed in the seventh insulating layer 170.

[0091] The first conductor CB1 can be connected to the first bonding pad BP1, the first bonding pad BP1 can be connected to the third bonding pad BP3, the third bonding pad BP3 can be connected to the contact CT, and the contact CT can be connected to the second conductor CB2. The first conductor CB1 and the second conductor CB2 can be electrically connected to each other through the contact CT, the third bonding pad BP3, and the first bonding pad BP1.

[0092] The first bonding pad BP1 may include a conductive portion BP1_C and a barrier portion BP1_B. The third bonding pad BP3 may include a conductive portion BP3_C and a barrier portion BP3_B. The contact CT may include a conductive portion CT_C and a barrier portion CT_B.

[0093] The sidewall SW of the first bonding pad BP1 may include a first flat portion F1, a second flat portion F2, a first curved portion C1, and a second curved portion C2. The sidewall of the third bonding pad BP3 may be flat. The sidewall of the contact CT may be flat.

[0094] Figure 5A This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 5B It is along Figure 5A The plan view of the second joint structure in the first region as shown by line B-B'. Figure 5C It is along Figure 5A The plan view of the second joint structure in the second region as seen by line B-B'.

[0095] Reference Figure 5A The semiconductor device according to this embodiment may include a first semiconductor structure SEM1, a second semiconductor structure SEM2, a first bonding structure BDS1, and a second bonding structure BDS2.

[0096] The first semiconductor structure SEM1 and the second semiconductor structure SEM2 may be spaced apart from each other. The first semiconductor structure SEM1 and the first bonding structure BDS1 may be connected to each other, the first bonding structure BDS1 and the second bonding structure BDS2 may be connected to each other, and the second bonding structure BDS2 and the second semiconductor structure SEM2 may be connected to each other. The first semiconductor structure SEM1 and the second semiconductor structure SEM2 may be electrically connected to each other through the first bonding structure BDS1 and the second bonding structure BDS2.

[0097] The semiconductor device may include a first region RG1 and a second region RG2. Each of the first semiconductor structure SEM1, the second semiconductor structure SEM2, the first bonding structure BDS1, and the second bonding structure BDS2 may be divided into a first region RG1 and a second region RG2.

[0098] The first semiconductor structure SEM1 may include a substrate 100, a first transistor TR1 and a second transistor TR2 in the substrate 100, and a first connection structure CNS1.

[0099] A first transistor TR1 may be disposed in the substrate 100 of the first region RG1. In an example, the first transistor TR1 may be a transistor constituting a page buffer. In an example, the substrate 100 may be a semiconductor substrate.

[0100] Each first transistor TR1 may include a first impurity region IR1 and a first gate structure. In an example, the first impurity region IR1 may be formed by doping the substrate 100 with impurities. In an example, the first gate structure may include a gate electrode GE and a gate insulating layer GI between the gate electrode GE and the substrate 100.

[0101] An isolation layer 101 may be disposed in the substrate 100 of the first region RG1. The isolation layer 101 may electrically isolate the first transistors TR1 from each other. The isolation layer 101 may include an insulating material.

[0102] The first connection structure CNS1 may include a first insulating layer 111, a first contact CT1, and a first conductor CB1'. The first insulating layer 111 may be formed on the substrate 100. The first contact CT1 and the first conductor CB1' may be disposed in the first insulating layer 111 of the first region RG1.

[0103] The first insulating layer 111 may include an insulating material. The first contact CT1 and the first conductor CB1' may include a conductive material.

[0104] The first contact CT1 and the first conductor CB1' can be electrically connected to the first transistor TR1 in the substrate 100.

[0105] The first bonding structure BDS1 may include a second insulating layer 121, a third insulating layer 131, a second contact CT2, and a first bonding pad BP1'. The second insulating layer 121 may be formed on the first insulating layer 111, and the third insulating layer 131 may be formed on the second insulating layer 121.

[0106] The second contact CT2 may be disposed in the second insulating layer 121 of the first region RG1. The first bonding pad BP1' may be disposed in the third insulating layer 131 of the first region RG1. Each of the second contact CT2 and the first bonding pad BP1' may include a conductive portion and a barrier portion. The sidewalls of each of the second contact CT2 and the first bonding pad BP1' may be flat.

[0107] The second insulating layer 121 and the third insulating layer 131 may include insulating materials. The second contact CT2 and the first bonding pad BP1' may include conductive materials. The second contact CT2 may be connected to the first conductor CB1', and the first bonding pad BP1' may be connected to the second contact CT2.

[0108] The second bonding structure BDS2 may include a fourth insulating layer 141 and a second bonding pad BP2'. The fourth insulating layer 141 may be formed on the third insulating layer 131.

[0109] The second bonding pad BP2' may be disposed in the fourth insulating layer 141 of the first region RG1. Each second bonding pad BP2' may include a conductive portion and a barrier portion. The sidewall of the second bonding pad BP2' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The first curved portion C1' and the second curved portion C2' may be disposed between the first flat portion F1' and the second flat portion F2'.

[0110] The fourth insulating layer 141 may include an insulating material. In this example, the fourth insulating layer 141 may include SiCN. The second bonding pad BP2' may include a conductive material. The second bonding pad BP2' may be connected to the first bonding pad BP1'.

[0111] The second semiconductor structure SEM2 may include a memory array AR and a second interconnect structure CNS2.

[0112] The second connection structure CNS2 may include a fifth insulating layer 151, a sixth insulating layer 161, a seventh insulating layer 171, a bit line BL, a third contact CT3, and a fourth contact CT4.

[0113] The fifth insulating layer 151 may be formed on the fourth insulating layer 141, the sixth insulating layer 161 may be formed on the fifth insulating layer 151, and the seventh insulating layer 171 may be formed on the sixth insulating layer 161.

[0114] The bit line BL can be disposed in the fifth insulating layer 151 and the sixth insulating layer 161 of the first region RG1. The third contact CT3 can be disposed in the sixth insulating layer 161 and the seventh insulating layer 171 of the first region RG1. The fourth contact CT4 can be disposed in the seventh insulating layer 171 of the first region RG1.

[0115] The fifth through seventh insulating layers 151, 161, and 171 may comprise insulating material. In this example, the fifth insulating layer 151 and the seventh insulating layer 171 may comprise oxide. In this example, the sixth insulating layer 161 may comprise nitride. The third contact CT3 and the fourth contact CT4 may comprise conductive material. The bit line BL may comprise conductive material.

[0116] Bit line BL can be connected to the second bonding pad BP2', the third contact CT3 can be connected to bit line BL, and the fourth contact CT4 can be connected to the third contact CT3.

[0117] The width of bit line BL can be equal to the width of the bottom surface of the second bonding pad BP2'. In the example, the width of bit line BL in the first direction D1 can be equal to the width of the bottom surface of the second bonding pad BP2' in the first direction D1.

[0118] Reference Figure 5BBit lines BL can extend in the second direction D2. Bit lines BL can be spaced apart from each other in the first direction D1. The second bonding pad BP2' can overlap with multiple bit lines BL.

[0119] Return to reference Figure 5A The memory array AR can be disposed on the second connection structure CNS2. The memory array AR may include a stacked structure STA, a channel structure CS, and a memory layer ML.

[0120] A stacked structure STS may be disposed on a seventh insulating layer 171. The stacked structure STS may include alternately stacked conductive patterns CP and insulating patterns IP. The conductive pattern CP may include a conductive material. In an example, the conductive pattern CP may include at least one selected from doped silicon, a metal silicide layer, tungsten, nickel, and cobalt. The insulating pattern IP may include an insulating material. In an example, the insulating pattern IP may include an oxide.

[0121] The channel structure CS and memory layer ML can penetrate the stacked structure STS. The channel structure CS may include a fill layer FI and a channel layer CL surrounding the fill layer FI. The memory layer ML may include a tunnel insulating layer TL surrounding the channel structure CS, a data storage layer DL surrounding the tunnel insulating layer TL, and a barrier layer BKL surrounding the data storage layer DL.

[0122] The fill layer FI may include an insulating material. In an example, the fill layer FI may include an oxide. The channel layer CL may include a semiconductor material. In an example, the channel layer CL may include polysilicon. The tunnel insulating layer TL may include a charge tunneling material. In an example, the tunnel insulating layer TL may include an oxide. In an example, the data storage layer DL may include a nitride capable of trapping charge. However, the material included in the data storage layer DL is not limited to nitrides and may vary depending on the data storage method. In an example, the data storage layer DL may include silicon, a phase change material, or nanodots. The barrier layer BKL may include a material capable of blocking the movement of charge. In an example, the barrier layer BKL may include an oxide.

[0123] The channel structure CS can be connected to the fourth contact CT4. The channel structure CS can be electrically connected to the first transistor TR in the substrate 100 through the fourth contact CT4, the third contact CT3, the bit line BL, the second bonding pad BP2', the first bonding pad BP1', the second contact CT2, the first conductor CB1', and the first contact CT1.

[0124] The memory array AR can be electrically connected to the fourth contact CT4, the third contact CT3, the bit line BL, the second bonding pad BP2', the first bonding pad BP1', the second contact CT2, the first conductor CB1', and the first contact CT1 to be electrically connected to the first transistor TR1 in the substrate 100.

[0125] The second transistor TR2 may be disposed in the substrate 100 of the second region RG2. In the example, the second transistor TR2 may be a pass transistor connected to the X decoder.

[0126] Each second transistor TR2 may include a second impurity region IR2 and a second gate structure. In the example, the second impurity region IR2 may be formed by doping the substrate 100 with impurities. In the example, similar to the first gate structure, the second gate structure may include a gate electrode and a gate insulating layer between the gate electrode and the substrate 100.

[0127] An isolation layer 101 may be disposed in the substrate 100 of the second region RG2. The isolation layer 101 can electrically isolate the second transistors TR2 from each other.

[0128] The fifth contact CT5 and the second conductor CB2' can be disposed in the first insulating layer 111 of the second region RG2. The fifth contact CT5 can be connected to the second transistor TR2. The second conductor CB2' can be connected to the fifth contact CT5.

[0129] The sixth contact CT6 may be disposed in the second insulating layer 121 of the second region RG2. The third bonding pad BP3' may be disposed in the third insulating layer 131 of the second region RG2. Each of the sixth contact CT6 and the third bonding pad BP3' may include a conductive portion and a barrier portion. The sixth contact CT6 and the third bonding pad BP3' may include a conductive material.

[0130] The sixth contact CT6 can be connected to the second conductor CB2'. The third bonding pad BP3' can be connected to the sixth contact CT6. The sidewalls of each of the sixth contact CT6 and the third bonding pad BP3' can be flat.

[0131] A fourth bonding pad BP4' may be disposed in the fourth insulating layer 141 of the second region RG2. The fourth bonding pad BP4' may include a conductive portion and a barrier portion. The sidewall of the fourth bonding pad BP4' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The first curved portion C1' and the second curved portion C2' may be disposed between the first flat portion F1' and the second flat portion F2'.

[0132] The fourth bonding pad BP4' may include conductive material. The fourth bonding pad BP4' may be connected to the third bonding pad BP3'.

[0133] The third conductor CB3' can be disposed in the fifth insulating layer 151 and the sixth insulating layer 161 of the second region RG2. The seventh contact CT7 can be disposed in the sixth insulating layer 161 and the seventh insulating layer 171 of the second region RG2. The eighth contact CT8 can be disposed in the seventh insulating layer 171 of the second region RG2.

[0134] Reference Figure 5C The third conductor CB3' may include first to third portions CB3'_a, CB3'_b, and CB3'_c. The first portion CB3'_a and the third portion CB3'_c may extend in the second direction D2. The second portion CB3'_b may extend in the first direction D1 and connect the first portion CB3'_a and the third portion CB3'_c. The first portion CB3'_a may be connected to the fourth bonding pad BP4'. The fourth bonding pad BP4' may overlap with the first portion CB3'_a of the third conductor CB3'.

[0135] Return to reference Figure 5A The third conductor CB3', the seventh contact CT7, and the eighth contact CT8 may include conductive material. The third conductor CB3' may be connected to the fourth bonding pad BP4', the seventh contact CT7 may be connected to the third conductor CB3', and the eighth contact CT8 may be connected to the seventh contact CT7.

[0136] The eighth insulating layer 181 may be disposed on the seventh insulating layer 171 of the second region RG2. The stacked structure STS may be disposed on the eighth insulating layer 181. The eighth insulating layer 181 may include insulating material.

[0137] The stacked structure STS of the second region RG2 can have a stepped structure. The insulating pattern IP and the conductive pattern CP of the stacked structure STS of the second region RG2 are formed into a stepped shape, thereby forming a stepped structure.

[0138] The ninth contact CT9 may be disposed in the seventh insulating layer 171 and the eighth insulating layer 181. The ninth contact CT9 may be connected to the eighth contact CT8. The ninth contact CT9 may be connected to the conductive pattern CP of the stacked structure STS. The ninth contact CT9 may include conductive material.

[0139] The conductive pattern CP can be electrically connected to the second transistor TR2 through the ninth contact CT9, the eighth contact CT8, the seventh contact CT7, the third conductor CB3', the fourth bonding pad BP4', the third bonding pad BP3', the sixth contact CT6, the second conductor CB2', and the fifth contact CT5.

[0140] In the semiconductor device according to this embodiment, since the width of the portion of the second bonding pad BP2' connected to the bit line BL is relatively small, the overlap margin between the bit line BL and the second bonding pad BP2' can be ensured.

[0141] In the semiconductor device according to this embodiment, since the width of the portion of the fourth bonding pad BP4' connected to the third conductor CB3' is relatively small, the overlap margin between the third conductor CB3' and the fourth bonding pad BP4' can be ensured.

[0142] Figure 6 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0143] Apart from the following, the semiconductor device according to this embodiment may be similar to Figures 5A to 5C The semiconductor device shown.

[0144] Reference Figure 6 In the semiconductor device according to this embodiment, the first bonding structure BDS1 may include a ninth insulating layer 191. The ninth insulating layer 191 may be disposed between the first insulating layer 111 and the fourth insulating layer 141.

[0145] The fifth bonding pad BP5' may be disposed in the ninth insulating layer 191 of the first region RG1. The sidewall of the fifth bonding pad BP5' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The fifth bonding pad BP5' may be connected to the second bonding pad BP2' of the second bonding structure BDS2.

[0146] The sidewall of the second bonding pad BP2' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'.

[0147] The sixth bonding pad BP6' may be disposed in the ninth insulating layer 191 of the second region RG2. The sidewall of the sixth bonding pad BP6' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The sixth bonding pad BP6' may be connected to the fourth bonding pad BP4' of the second bonding structure BDS2.

[0148] The sidewall of the fourth bonding pad BP4' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'.

[0149] The fifth bonding pad BP5' can be connected to the first transistor TR1 via the first conductor CB1' and the first contact CT1 of the first connection structure CNS1. In this example, the first transistor TR1 may be a transistor constituting a page buffer.

[0150] The sixth bonding pad BP6' can be connected to the second transistor TR2 via the second conductor CB2' and the fifth contact CT5 of the first connection structure CNS1. In this example, the second transistor TR2 can be a through transistor connected to the X decoder.

[0151] Figures 7A to 7H It is shown Figures 5A to 5C A cross-sectional view of the manufacturing method of the semiconductor device shown.

[0152] For the sake of brevity, references will be omitted. Figures 5A to 5C Redundant descriptions of the components being described.

[0153] The following manufacturing method is only Figures 5A to 5C An embodiment of the manufacturing method of the semiconductor memory device shown. Figures 5A to 5C The manufacturing method of the semiconductor memory device shown is not limited to the manufacturing method described below.

[0154] Reference Figure 7A This can form a second semiconductor structure SEM2. The second semiconductor structure SEM2 may include a memory array AR and a second interconnect structure CNS2.

[0155] A fourth insulating layer 141 may be formed on the second connection structure CNS2, a first hard mask layer MA1' may be formed on the fourth insulating layer 141, and a second hard mask layer MA2' may be formed on the first hard mask layer MA1'. In the example, the fourth insulating layer 141 may be a single layer.

[0156] Reference Figure 7B A photoresist pattern PR' can be formed on the second hard mask layer MA2'.

[0157] Subsequently, a photoresist pattern PR' can be used as an etching barrier to etch the second hard mask layer MA2' and the first hard mask layer MA1'. Therefore, the first hard mask layer MA1' and the second hard mask layer MA2' can be patterned, and a first opening OP1' can be formed in the first hard mask layer MA1'.

[0158] Subsequently, the first hard mask layer MA1' can be used as an etching barrier to etch the fourth insulating layer 141. Therefore, the fourth insulating layer 141 can be patterned, and a second opening OP2' can be formed in the fourth insulating layer 141.

[0159] In one embodiment, as shown in the figure, the photoresist pattern PR' and the second hard mask layer MA2' retained after the formation of the first opening OP1' and the second opening OP2' can be removed. In another embodiment, unlike the one shown in the figure, the second opening OP2' can be formed after the formation of the first opening OP1' and the removal of the photoresist pattern PR' and the second hard mask layer MA2'.

[0160] Reference Figure 7C The first opening OP1' of the first hard mask layer MA1' can be enlarged. By etching the first hard mask layer MA1', the first hard mask layer MA1' can be reduced, and the first opening OP1' can be enlarged. When the first opening OP1' is enlarged, the top surface of the fourth insulating layer 141 can be exposed.

[0161] Reference Figure 7D The first hard mask layer MA1' can be used as an etching barrier to etch the fourth insulating layer 141. The fourth insulating layer 141 can be etched through the first opening (…). Figure 7C The fourth insulating layer 141 is etched as shown in OP1'.

[0162] When the fourth insulating layer 141 is etched, the first opening ( Figure 7C OP1' shown) and the second opening ( Figure 7C OP2' (as shown) can be transferred in the fourth insulating layer 141. When the second opening ( Figure 7C When the first opening (OP2') is transferred, a third opening OP3' can be formed in the fourth insulating layer 141. Figure 7C When OP1' is transferred, a fourth opening OP4' can be formed in the fourth insulating layer 141.

[0163] A third opening OP3' may be formed in the first region RG1 to expose the bit line BL. A third opening OP3' may be formed in the second region RG2 to expose the third conductor CB3' electrically connected to the conductive pattern CP of the stacked structure STS.

[0164] The sidewalls of the third opening OP3' and the fourth opening OP4' may be flat. The surface of the fourth insulating layer 141 that connects the third opening OP3' and the fourth opening OP4' may be flexible. When the fourth insulating layer 141 is etched, flexible sidewalls may be formed in the fourth insulating layer 141.

[0165] Reference Figure 7E The first hard mask layer MA1' can be removed.

[0166] Reference Figure 7F A second bonding pad BP2' may be formed in the fourth insulating layer 141 of the first region RG1. The second bonding pad BP2' may include a first flat portion F1', a second flat portion F2', a first curved portion C1', and a second curved portion C2'. The second bonding pad BP2' may be connected to the bit line BL.

[0167] A fourth bonding pad BP4' may be formed in the fourth insulating layer 141 of the second region RG2. The fourth bonding pad BP4' may include a first flat portion F1', a second flat portion F2', a first bent portion C1', and a second bent portion C2'. The fourth bonding pad BP4' may be connected to a third conductor CB3' electrically connected to the conductive pattern CP of the stacked structure STS. When the second bonding pad BP2' and the fourth bonding pad BP4' are formed, a second bonding structure BDS2 may be formed.

[0168] Reference Figure 7G A first semiconductor structure SEM1 and a first bonding structure BDS1 can be formed. The first semiconductor structure SEM1 may include a substrate 100, a first transistor TR1 and a second transistor TR2 in the substrate 100, and a first connection structure CNS1.

[0169] The first bonding structure BDS1 may include a second insulating layer 121 and a third insulating layer 131. A first bonding pad BP1' may be disposed in the third insulating layer 131 of the first region RG1. A third bonding pad BP3' may be disposed in the third insulating layer 131 of the second region RG2. The sidewalls of the first bonding pad BP1' and the third bonding pad BP3' may be flat.

[0170] Reference Figure 7H The first bonding structure BDS1 and the second bonding structure BDS2 can be bonded to each other. After the second semiconductor structure SEM2 and the second bonding structure BDS2 are rotated, the first bonding structure BDS1 and the second bonding structure BDS2 can be bonded to each other. In the example, the second semiconductor structure SEM2 and the second bonding structure BDS2 can be rotated 180 degrees.

[0171] When the first bonding structure BDS1 and the second bonding structure BDS2 are bonded to each other, the first semiconductor structure SEM1 and the second semiconductor structure SEM2 can be electrically connected to each other.

[0172] The first bonding pad BP1' of the first bonding structure BDS1 and the second bonding pad BP2' of the second bonding structure BDS2 can be bonded to each other. When the first bonding pad BP1' of the first bonding structure BDS1 and the second bonding pad BP2' of the second bonding structure BDS2 are bonded to each other, the channel structure CS can be electrically connected to the first transistor TR1. In the example, the channel structure CS can be connected to the transistor constituting the page buffer. When the first bonding pad BP1' of the first bonding structure BDS1 and the second bonding pad BP2' of the second bonding structure BDS2 are bonded to each other, the memory array AR can be electrically connected to the first transistor TR1.

[0173] The third bonding pad BP3' of the first bonding structure BDS1 and the fourth bonding pad BP4' of the second bonding structure BDS2 can be bonded to each other. When the third bonding pad BP3' of the first bonding structure BDS1 and the fourth bonding pad BP4' of the second bonding structure BDS2 are bonded to each other, the conductive pattern CP of the stacked structure STS can be electrically connected to the second transistor TR2. In the example, the conductive pattern CP of the stacked structure STS can be connected to the through transistor connected to the X decoder.

[0174] Figure 8 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0175] Reference Figure 8 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0176] Memory device 1120 may include reference Figure 1A and Figure 1B , Figure 3 , Figure 4 , Figures 5A to 5C or Figure 6 The described structure. The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0177] The storage controller 1110 is configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory of the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the memory system 1100. The ECC circuit 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 interfaces with the memory device 1120. Additionally, the storage controller 1110 may also include ROM for storing code data, etc., used for interfacing with the host.

[0178] The memory system 1100 configured as described above can be a memory card or a solid-state drive (SSD), wherein the memory device 1120 is combined with the controller 1110. For example, when the memory system 1100 is an SSD, the storage controller 1110 can communicate with an external source (e.g., a host) via one of various interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0179] Figure 9 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0180] Reference Figure 9 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210, which are electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor, mobile D-RAM, etc.

[0181] The memory system 1210 can be referred to as follows Figure 8 The configuration utilizes memory device 1212 and memory controller 1211.

[0182] In the semiconductor device according to this disclosure, the sidewalls of the bonding pads include curved portions. Therefore, the bonding pads can be formed without any gaps, and overlap allowance between the bonding pads and the conductors can be ensured.

[0183] Although this disclosure has been shown and described with reference to specific embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0184] In the above embodiments, all steps may be performed selectively, or some steps may be omitted. In various embodiments, the steps may not be performed in the described order, but may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0185] Furthermore, embodiments of this disclosure have been shown and described in the accompanying drawings and specification. Although specific terminology has been used herein, those terms are for illustrative purposes only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0186] Cross-references to related applications

[0187] This application claims priority to Korean Patent Application No. 10-2020-0044168, filed with the Korean Intellectual Property Office on April 10, 2020, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A first bonding pad, the first bonding pad having a surface facing a first direction; as well as The second bonding pad is in contact with the surface of the first bonding pad; Wherein, at least one of the first bonding pad and the second bonding pad includes a first portion, a second portion, and a third portion. The second part is positioned between the first part and the third part. The third portion is adjacent to the surface of the first bonding pad. The width of the third part is greater than the width of the first part, and The first part and the second part are located in a single insulating layer.

2. The semiconductor device according to claim 1, wherein, The surface of the first bonding pad includes a portion that contacts the second bonding pad and a portion that does not contact the second bonding pad.

3. The semiconductor device according to claim 1, in, The first bonding pad includes a first conductive portion and a first barrier portion extending along the sidewall of the first conductive portion, and The second bonding pad includes a second conductive portion and a second barrier portion extending along the sidewall of the second conductive portion.

4. The semiconductor device according to claim 3, wherein, The first conductive portion includes a portion that contacts the second conductive portion and a portion that contacts the second barrier portion.

5. The semiconductor device according to claim 3, wherein, The first barrier portion is offset from the second barrier portion.

6. The semiconductor device according to claim 3, wherein, The first barrier portion and the second barrier portion comprise titanium, titanium nitride, tantalum, or tantalum nitride.

7. The semiconductor device according to claim 1, wherein, The curved sidewall of the second part includes a first curved portion and a second curved portion.

8. The semiconductor device according to claim 7, wherein, The center of curvature of the first curved portion is located inside the corresponding bonding pad in the first bonding pad and the second bonding pad, and The curvature center of the second curved portion is located outside the corresponding bonding pad in the first bonding pad and the second bonding pad.

9. The semiconductor device of claim 1, further comprising a bit line electrically connected to the second bonding pad.

10. The semiconductor device of claim 1, further comprising a transistor electrically connected to a page buffer of the first conductor.

11. The semiconductor device of claim 1, further comprising: A transistor, the transistor being electrically connected to the first bonding pad; as well as A memory array electrically connected to the second bonding pad.

12. The semiconductor device according to claim 11, wherein, The memory array includes: A stacked structure comprising alternating insulating and conductive patterns stacked in the first direction; A channel structure that penetrates the stacked structure; and A memory layer that surrounds the channel structure and penetrates the stacked structure.

13. The semiconductor device of claim 12, further comprising: A contact point located between the second bonding pad and the channel structure and connected to the channel structure; as well as Bit lines that electrically connect the second bonding pad to the contact.

14. The semiconductor device of claim 12, further comprising: A contact point located between the second bonding pad and a corresponding conductive pattern in the conductive pattern; as well as A conductor that electrically connects the second bonding pad to the corresponding conductive pattern.

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