Chip testing method

Abstract

The invention discloses a chip testing method, which comprises the following steps of: executing a first wafer test which comprises a wakeup step; executing first environment screening; executing a second wafer test, wherein the second wafer test comprises a depolarization step; executing second environment screening; executing a third wafer test; wherein each wafer test at least comprises a direct current parameter test and a function test. The chip testing method provided by the invention comprises at least three times of wafer testing, environment screening is executed between two adjacent times of wafer testing, and an awakening step is executed in the first wafer testing, so that the read-write function of the chip is recovered, the chip is prevented from being misjudged to be invalid, the misjudgment rate of the first wafer testing is reduced, and the testing efficiency of the chip is improved. By executing the depolarization step in the second wafer test, the detection rate of the faulty chips in the second wafer test can be improved, and the newly increased rate of the faulty chips in the third wafer test can be reduced, so that the faulty chips can be detected as soon as possible, and the manufacturing cost of the chips is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a chip testing method. Background Technology

[0002] Chip testing is a crucial part of the chip manufacturing process. If defective chips are not detected in time during chip testing, subsequent manufacturing processes will waste a lot of resources and greatly increase the cost of the chips. Therefore, chip testing needs to detect faulty chips as early as possible.

[0003] Chip testing is divided into two stages. The first stage is wafer testing, also known as CP (Chip Probing) testing. The second stage is FT (Final Test) testing, which is performed after the chip is packaged. CP testing occurs between wafer fabrication and packaging in the entire chip manufacturing process. After the wafer is fabricated, thousands of bare dies (unpackaged chips) are regularly distributed across the entire wafer. Since they have not yet been diced and packaged, these exposed chip pins need to be connected to a tester via probes to perform chip testing, which is CP testing.

[0004] Therefore, it is necessary to propose a chip testing method to detect faulty chips in a timely manner during the CP testing phase, so as to reduce chip manufacturing costs. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] This invention provides a chip testing method comprising:

[0007] Perform a first wafer test, which includes a wake-up step;

[0008] Perform the first environment screening;

[0009] Perform a second wafer test, which includes a depolarization step;

[0010] Perform a second environment screening;

[0011] Perform third wafer testing;

[0012] Each wafer test includes at least DC parameter testing and functional testing.

[0013] For example, the wake-up step includes performing multiple data reads and writes to activate the chip.

[0014] For example, the number of times the data is read and written ranges from 1E3 to 1E7.

[0015] For example, the depolarization step includes baking, the depolarization temperature range includes 85°C to 125°C, and the depolarization time range includes 45 min to 75 min.

[0016] For example, the functional test includes at least data write and read and data verification, wherein the data write and read includes a first type of data write and read, a first type of data write and read and / or full-graphics data write and read, and the data verification includes a first type of data verification and / or a second type of data verification.

[0017] For example, the wake-up step is set before the full graphics data write / read.

[0018] Exemplarily, the first wafer test includes:

[0019] Perform DC parameter testing;

[0020] Perform first-type data validation;

[0021] Perform the wake-up procedure;

[0022] Perform full-scale graphical data writing and reading;

[0023] Perform first-type data write and read operations.

[0024] For example, the depolarization step is set between data writing / reading and data verification of the same data.

[0025] For example, the second wafer test includes:

[0026] Perform DC parameter testing;

[0027] Perform first-type data validation;

[0028] Perform second-type data write and read operations;

[0029] Perform the depolarization step;

[0030] Perform second type of data validation;

[0031] Perform first-type data write and read operations.

[0032] For example, the first environmental screening and the second environmental screening include baking, the first environmental screening temperature range includes 140℃~200℃, the first environmental screening time range includes 45min~75min; the second environmental screening temperature range includes 140℃~200℃, and the second environmental screening time is greater than 18 hours.

[0033] The chip testing method provided by the present invention includes at least three wafer tests, and performs environmental screening between two adjacent wafer tests. By performing a wake-up step in the first wafer test, the chip is restored to read and write functions, avoiding the chip being falsely judged as faulty, thereby reducing the false judgment rate of the first wafer test. By performing a depolarization step in the second wafer test, the detection rate of faulty chips in the second wafer test can be improved, and the new rate of faulty chips in the third wafer test can be reduced, thereby achieving early detection of faulty chips and reducing chip manufacturing costs. Attached Figure Description

[0034] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0035] In the attached image:

[0036] Figure 1 This is a flowchart of a chip testing method according to an embodiment of the present invention;

[0037] Figure 2 This is a flowchart of the first wafer test according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the ferromagnetic hysteresis curve according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the residual polarization intensity according to an embodiment of the present invention;

[0040] Figure 5A The result of the first wafer test according to an embodiment of the present invention when the first wafer test does not include a wake-up step;

[0041] Figure 5B The result of the first wafer test according to an embodiment of the present invention when the first wafer test includes a wake-up step;

[0042] Figure 6 This is a flowchart of the second wafer testing according to an embodiment of the present invention;

[0043] Figure 7A The results of the second wafer test according to an embodiment of the present invention are as follows: when the second wafer test does not include a depolarization step;

[0044] Figure 7B The results of the second wafer test according to an embodiment of the present invention are as follows: when the second wafer test includes a depolarization step;

[0045] Figure 8 This is a flowchart of the third wafer testing according to an embodiment of the present invention;

[0046] Figure 9A The result of the third wafer test according to an embodiment of the present invention is when the second wafer test does not include a depolarization step;

[0047] Figure 9B The result of the third wafer test is given when the second wafer test includes a depolarization step, according to an embodiment of the present invention. Detailed Implementation

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0049] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0052] Ferroelectric RAM (FRAM) is a new type of memory that combines the easy-to-write characteristics of dynamic random access memory (DRAM) and static random access memory (SRAM) with the non-volatile characteristics of flash memory and electrically erasable programmable read-only memory (EEPROM). It can store data without refresh circuits and has the advantages of high-speed read and write, low power consumption and high reliability.

[0053] The core of the novel ferroelectric memory is a MIM (metal-insulator-metal) ferroelectric capacitor. The ferroelectric capacitor structure typically consists of two metal layers as capacitor electrodes, with a layer of HZO ferroelectric thin film material in between. The HZO ferroelectric thin film can spontaneously polarize under the influence of an external electric field applied to the metal electrodes. Simultaneously, the dielectric capacitance and the current within the dielectric also change with the polarization state. When the applied electric field is removed, a certain polarization intensity, i.e., ±Pr state, remains in the dielectric. The direction of this remaining polarization intensity can be used to represent "1" and "0" in a binary digital system, thus achieving data storage capability with non-volatile characteristics.

[0054] However, in memory integrated circuits, erroneous readings and writings of the stored state may occur due to factors such as the HZO ferroelectric capacitor's storage window not reaching the operating threshold or significant leakage current. This necessitates chip probing (CP) testing before packaging to effectively and systematically evaluate the functionality of the HZO ferroelectric memory circuitry on the wafer, while also reducing packaging costs.

[0055] To address the aforementioned problems, this invention provides a chip testing method for ferroelectric memory, comprising performing at least three wafer tests on the chip and performing environmental screening between two adjacent wafer tests. Each wafer test includes at least a DC parameter test and a functional test. Furthermore, the first wafer test includes a wake-up step, and the second wafer test includes a depolarization step.

[0056] In one embodiment, refer to Figure 1 The chip testing method includes the following steps:

[0057] Step S110: Perform a first wafer test, which includes a wake-up step;

[0058] Step S120: Perform the first environment screening;

[0059] Step S130: Perform a second wafer test, which includes a depolarization step;

[0060] Step S140: Perform the second environment screening;

[0061] Step S150: Perform the third wafer test;

[0062] Each wafer test includes at least DC parameter testing and functional testing.

[0063] In step S110, as Figure 2 As shown, it further includes the following steps:

[0064] Step S111: Perform DC parameter testing;

[0065] Step S112: Perform the first type of data validation;

[0066] Step S113: Perform the wake-up procedure;

[0067] Step S114: Perform full graphics data write and read;

[0068] Step S115: Perform first type of data write / read.

[0069] In step S111, the DC parameter test (i.e., DC test) in chip testing refers to the process of verifying whether the electrical performance of the chip meets the design requirements by measuring the DC characteristic parameters of the chip. These DC characteristic parameters include, but are not limited to, current, voltage, and resistance. In one embodiment, the DC test includes power supply voltage testing, ground pin testing, IV testing, and resistance testing. Power supply voltage testing primarily measures the current change of the chip under different voltages, aiming to determine the minimum and maximum power supply voltage range of the chip. Ground pin testing primarily measures the ground voltage of the chip to determine whether the ground voltage meets the design specifications. IV testing is used to measure the relationship between current and voltage in the chip, i.e., measuring the current change in the chip under a constant voltage or the voltage change in the chip under a constant current. Resistance testing is used to measure the resistance between different components in the chip and ensure that it is within a reasonable range required by the design.

[0070] For example, the functional test includes at least data write and read and data verification, wherein the data write and read includes a first type of data write and read, a first type of data write and read and / or full-graphics data write and read, and the data verification includes a first type of data verification and / or a second type of data verification.

[0071] In one embodiment, the first type of data and the second type of data are two types of data with opposite states in a binary digital system. That is, when the first type of data is "0" in the nth bit, the second type of data is "1" in the nth bit.

[0072] In one embodiment, for either the first type of data or the second type of data, functional testing includes first performing write-read operations on a set of data, followed by performing verification operations on that set of data. In the chip testing provided by this invention, functional tests on the first type of data and the second type of data are typically performed alternately.

[0073] Step S112: Since the first wafer test is the first CP test in the chip testing method, a data verification step is performed before data writing and reading. In one embodiment, a first type of data verification can be performed.

[0074] Next, step S113, the wake-up step, is executed. Specifically, the wake-up step includes performing multiple data read / write operations to activate the chip.

[0075] HZO ferroelectric memories exhibit unstable memory window behavior with wake-up and fatigue effects due to their known metastable ferroelectric phase and complex interface effects. The wake-up effect is mainly attributed to the increase in residual polarization after several device cycles, referring to... Figure 3 and Figure 4 As shown, the hysteresis curve observed in its original state is under compression, gradually opening up during cycling, with the remanent polarization (Pr) gradually increasing until it reaches a maximum value. Subsequently, it begins to be affected by fatigue effects, and Pr gradually decreases with the number of cycles. This inherent characteristic of ferroelectric materials—the increase in Pr during cycling—may lead to misreading of stored information during initial use in memory circuits. However, after a certain number of read / write cycles, as the memory window increases, the device can perform correct read / write operations. This results in some potentially recoverable devices being initially classified as failed in typical CP tests, leading to waste.

[0076] In one embodiment, the number of data read / write operations (also referred to as "wake-up count") in the wake-up step ranges from 1E3 to 1E7. When the wake-up count reaches approximately 1E6, the HZO ferroelectric capacitor can achieve its maximum remanent polarization intensity, i.e., its maximum storage window. By executing the wake-up step, the ferroelectric domain inversion ratio is increased, thereby improving the HZO ferroelectric storage window within a certain range.

[0077] In one embodiment, refer to Figure 5A and 5B , Figure 5A The results of the first wafer test are shown when the wake-up step is not included in the first wafer test. Among them, the number of dies that failed the functional test was 9, accounting for 3.4% of the total number of dies. Figure 5BThe results of the first wafer test are shown when a wake-up step is included. Four dies failed the functional test, representing 1.5% of the total dies. This means that the functionality of five of these dies could be restored through the wake-up step. When the first wafer test does not include a wake-up step, these five dies are mistakenly identified as faulty, resulting in wasted resources. Therefore, by including a wafer wake-up step in the first wafer test, the false positive rate of chip testing can be reduced.

[0078] For example, the wake-up step is set before the full graphics data write / read.

[0079] In one embodiment, the full pattern data is the formal data used for the first wafer test. Therefore, the above wake-up step must be performed before writing and reading the full pattern data to ensure that the die can be read and written correctly. Then, steps S114 and S115 are performed to sequentially write and read the full pattern data and the first type of data.

[0080] Next, proceed to step S120 to perform the first environment screening.

[0081] An environmental screening step must be performed between two adjacent wafer tests. This environmental screening is used to simulate the failure of ferroelectric memory in its operating environment. Typically, environmental screening is performed using high-temperature baking. In the embodiments of this application, the temperature range of the first environmental screening between the first wafer test and the second wafer test includes 140°C to 200°C, and the time range includes 45 min to 75 min. When the first environmental screening is 175°C for 1 hour, it can achieve the same simulation effect as low-temperature baking, such as 125°C for 100 hours, which can simulate the die failure of ferroelectric memory after approximately 3 months of use in a room temperature environment.

[0082] In step S130, as Figure 6 As shown, it further includes the following steps:

[0083] Step S131: Perform DC parameter testing;

[0084] Step S132: Perform first type of data validation;

[0085] Step S133: Perform the second type of data write / read;

[0086] Step S134: Perform the depolarization step;

[0087] Step S135: Perform the second type of data validation;

[0088] Step S136: Perform first type of data write / read.

[0089] The execution of step S131 is the same as that of step S111, and will not be repeated here.

[0090] In response to the first type of data write / read in step S115, the first type of data verification in step S132 is performed. Here, if step S115 is a second type of data write / read, then step S132 is a second type of data verification.

[0091] Since the functional testing of the first type of data and the functional testing of the second type of data are usually performed alternately, after the functional testing of the first type of data is completed in steps S115 and S132, the functional testing of the second type of data is performed, including the write and read operations of the second type of data in step S133 and the verification operation of the second type of data in step S135. However, in the embodiments of this application, the second wafer test also includes a depolarization step.

[0092] For example, the depolarization step is set between the data writing / reading and data verification of the same data. In an embodiment of this application, the depolarization step S134 is set between the writing / reading of the second type of data (step S133) and the verification of the second type of data (step S135).

[0093] In one embodiment, the depolarization step includes baking, the depolarization temperature range is 85°C to 125°C, and the depolarization time range is 45 min to 75 min. Specifically, depolarization is performed at 85°C for 1 hour or at 125°C for 1 hour. It should be noted that the temperature of the depolarization step is lower than the temperature of the wafer screening step.

[0094] In one embodiment, refer to Figure 7A and 7B , Figure 7A The results of the second wafer test are shown when the depolarization step is not included in the second wafer test. Among them, the number of dies that failed the functional test was 39, accounting for 14.9% of the total number of dies. Figure 7B The results of the second wafer test are shown when a depolarization step is included in the second wafer test. The number of dies that failed the functional test was 51, accounting for 19.5% of the total number of dies. In other words, by adding the depolarization step, 12 faulty dies were detected earlier, improving the detection efficiency of the second wafer test by 4.6% and reducing chip manufacturing costs.

[0095] In response to the second type of data write / read in step S133, after depolarization (step S134), the second type of data verification in step S135 is performed. Here, if step S133 is a first type of data write / read, then step S135 is a first type of data verification. After step S135, step S136, the first type of data write / read, continues to be performed.

[0096] Next, proceed to step S140 to perform the second environment screening.

[0097] An environmental screening step must be performed between each two adjacent wafer tests. This environmental screening is used to simulate the failure of ferroelectric memory in its operating environment. Typically, environmental screening is performed by high-temperature baking. In the embodiments of this application, the temperature range of the second environmental screening between the second and third wafer tests includes 140°C to 200°C, and the time is greater than 18 hours. When the second environmental screening is 175°C for 20 hours, it can simulate the die failure of ferroelectric memory after approximately 5 years of use in a room temperature environment.

[0098] In step S150, as Figure 8 As shown, it further includes the following steps:

[0099] Step S151: Perform DC parameter testing;

[0100] Step S152: Perform first type of data validation;

[0101] Step S153: Perform the second type of data write / read;

[0102] Step S154: Perform the second type of data validation;

[0103] Step S155: Perform first type of data write / read.

[0104] The execution of step S131 is the same as that of step S111, and will not be repeated here.

[0105] In response to the first type of data write / read operation in step S136, the first type of data verification in step S152 is performed. Since the functional testing of the first type of data and the functional testing of the second type of data are usually performed alternately, after the functional testing of the first type of data is completed in steps S136 and S152, the functional testing of the second type of data is performed, including the second type of data write / read operation in step S153 and the second type of data verification operation in step S154. Then, the functional testing of the first type of data is performed, including the first type of data write / read operation in step S155.

[0106] In one embodiment, refer to Figure 9A and 9B , Figure 9A The results of the third wafer test are shown when the depolarization step is not included in the second wafer test. The number of dies that failed the functional test was 47, compared to the results of the second wafer test. Figure 7A Compared to the previous version, there are 9 new fault dies; Figure 9BThe results of the third wafer test are shown when the second wafer test includes a depolarization step, in which the number of dies that failed the functional test was 55, compared with the results of the second wafer test. Figure 7B Compared to the four newly added faulty dies, the addition of a depolarization step reduces the number of newly added faulty dies from the second wafer test to the third wafer test, indicating that more faulty dies are detected earlier, thereby reducing chip manufacturing costs.

[0107] Next, chip testing may also include repeating the steps of the second environment screening (step S140) and the third wafer testing (step S150), which will not be described in detail here.

[0108] The chip testing method provided by the present invention includes at least three wafer tests, and performs environmental screening between two adjacent wafer tests. By performing a wake-up step in the first wafer test, the chip is restored to read and write functions, avoiding the chip being falsely judged as faulty, thereby reducing the false judgment rate of the first wafer test. By performing a depolarization step in the second wafer test, the detection rate of faulty chips in the second wafer test can be improved, and the new rate of faulty chips in the third wafer test can be reduced, thereby achieving early detection of faulty chips and reducing chip manufacturing costs.

[0109] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method of testing a chip, characterized by, The method comprises: performing a first wafer test, the first wafer test comprising a wake-up step; performing a first environmental screening; performing a second wafer test, the second wafer test comprising a depolarization step; performing a second environmental screening; performing a third wafer test; wherein each of the wafer tests comprises at least a direct current parameter test and a function test.

2. The chip testing method according to claim 1, wherein The wake-up step comprises performing a plurality of data read-write to activate the chip.

3. The chip testing method according to claim 2, wherein The number of data read-write ranges from 1E3 to 1E7.

4. The chip testing method according to Claim 1, wherein The depolarization step comprises baking, the depolarization temperature ranges from 85℃ to 125℃, and the depolarization time ranges from 45min to 75min.

5. The method of claim 1, wherein The function test comprises at least data write-read and data verification, wherein the data write-read comprises a first type data write-read, a first type data write-read and / or a full-pattern data write-read, and the data verification comprises a first type data verification and / or a second type data verification.

6. The chip testing method according to Claim 5, wherein The wake-up step is arranged before the full-pattern data write-read.

7. The chip testing method according to Claim 6, wherein The first wafer test comprises: performing a direct current parameter test; performing a first type data verification; performing a wake-up step; performing a full-pattern data write-read; performing a first type data write-read.

8. The method of claim 5, wherein the test chip is a wafer. The depolarization step is arranged between data write-read and data verification of the same data.

9. The chip testing method according to Claim 8, wherein The second wafer test comprises: performing a direct current parameter test; performing a first type data verification; performing a second type data write-read; performing a depolarization step; performing a second type data verification; performing a first type data write-read.

10. The method of claim 1, wherein The first environmental screening and the second environmental screening comprise baking, the first environmental screening temperature ranges from 140℃ to 200℃, and the first environmental screening time ranges from 45min to 75min; the second environmental screening temperature ranges from 140℃ to 200℃, and the second environmental screening time is greater than 18 hours.

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