Photoelectric co-packaging structure and manufacturing method thereof, controller and medium

Abstract

The invention discloses a photoelectric co-packaging structure, a manufacturing method thereof, a controller and a medium, and relates to the technical field of packaging substrates. The structure includes: a frame substrate; the electric chip is arranged in the frame substrate; the optical chip is arranged in the frame substrate, and one side of the optical chip is provided with an optical interface; the dielectric material layer covers the two surfaces of the frame substrate and packages the electric chip and the optical chip in the frame substrate, and the optical interface is exposed out of the side face of the dielectric material layer; a first blind hole communicated with the upper surface of the electric chip, a second blind hole communicated with the lower surface of the electric chip, a third blind hole communicated with the upper surface of the optical chip and a fourth blind hole communicated with the lower surface of the optical chip are formed in the dielectric material layer; the first circuit is arranged on the two surfaces of the dielectric material layer, and the first circuit is communicated with the first blind hole, the second blind hole, the third blind hole and the fourth blind hole. According to the structure of the embodiment of the invention, the integration density of products can be improved, and the transmission path of photoelectric signals is shortened.

Description

Technical Field

[0001] This invention relates to the field of packaging substrate technology, and in particular to an optoelectronic co-packaging structure, its fabrication method, controller, and medium. Background Technology

[0002] With the rapid development of cutting-edge technologies such as artificial intelligence and high-performance computing, higher demands are being placed on optical communication systems: they need to achieve ultra-high speed, ultra-large bandwidth, and ultra-low power consumption transmission capabilities, while also meeting the requirements of miniaturization and high-density integration. Against this backdrop, traditional pluggable optical modules, limited by their architectural design, are gradually showing bottlenecks in transmission bandwidth, signal delay, and energy efficiency. To address this, co-packaged optoelectronic (CPO) technology has emerged. By integrating the optical engine with the electrical chip into a single design, it not only significantly shortens the optoelectronic signal conversion path but also achieves a significant improvement in transmission rate and energy efficiency, providing a breakthrough interconnect solution for next-generation high-performance computing systems.

[0003] However, in existing optoelectronic co-packaging methods, optical devices are usually fabricated as surface-mount components. Although the process is relatively mature, there are still significant limitations, including: limited integration density, making it difficult to further improve; high heat dissipation pressure due to thermal coupling between the electrical chip and the optical device, which easily leads to local hot spots; high edge coupling loss, with insertion loss reaching 3-5dB, and strict alignment accuracy requirements; and reliance on silicon interposers in the manufacturing process, resulting in persistently high costs, making it difficult to meet the future development needs of high integration and high reliability. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes an optoelectronic co-packaging structure, its fabrication method, controller, and dielectric, which can improve the integration density of products and shorten the transmission path of optoelectronic signals.

[0005] In a first aspect, the optoelectronic co-packaging structure according to embodiments of the present invention includes: Frame substrate; An electrical chip is disposed within the frame substrate; An optical chip is disposed within the frame substrate, and an optical interface is provided on one side of the optical chip; A dielectric material layer covers both surfaces of the frame substrate and encapsulates the electrical chip and the optical chip within the frame substrate. The optical interface is exposed on the side of the dielectric material layer. The dielectric material layer is provided with a first blind via communicating with the upper surface of the electrical chip, a second blind via communicating with the lower surface of the electrical chip, a third blind via communicating with the upper surface of the optical chip, and a fourth blind via communicating with the lower surface of the optical chip. The first circuit is disposed on two surfaces of the dielectric material layer, and the first circuit is interconnected with the first blind via, the second blind via, the third blind via, and the fourth blind via. According to some embodiments of the present invention, a conductive copper pillar is disposed inside the frame substrate, and a second circuit is disposed on two surfaces of the frame substrate, which is interconnected by the conductive copper pillar. A fifth blind via is also disposed in the dielectric material layer, which is interconnected with the second circuit, and the fifth blind via is also interconnected with the first circuit.

[0006] According to some embodiments of the present invention, the frame substrate has a first cavity and a second cavity penetrating the frame substrate, the electrical chip is located in the first cavity, the optical chip is located in the second cavity, and both the first cavity and the second cavity are filled by the dielectric material layer.

[0007] According to some embodiments of the present invention, a first connection terminal is provided on one surface of the electrical chip, and a second connection terminal is provided on one surface of the optical chip. The first connection terminal is connected to the second blind hole, and the second connection terminal is connected to the fourth blind hole.

[0008] Secondly, the method for fabricating an optoelectronic co-packaging structure according to an embodiment of the present invention includes the following steps: Prepare a frame substrate; the frame substrate has a first cavity and a second cavity penetrating the frame substrate. An electrical chip is placed in the first cavity, and an optical chip is placed in the second cavity; an optical interface is provided on one side of the optical chip. The electrical chip and the optical chip are encapsulated by a dielectric material layer; the dielectric material layer covers both surfaces of the frame substrate and fills the first cavity and the second cavity; A window is made in the dielectric material layer to form a first opening communicating with the upper surface of the electrical chip, a second opening communicating with the lower surface of the electrical chip, a third opening communicating with the upper surface of the optical chip, and a fourth opening communicating with the lower surface of the optical chip, and to form a cutting cavity communicating with the optical interface. The frame substrate is subjected to hole-filling electroplating to form a first blind hole in the first opening, a second blind hole in the second opening, a third blind hole in the third opening, and a fourth blind hole in the fourth opening. A first line is formed on both surfaces of the frame substrate to be connected to the first blind hole, the second blind hole, the third blind hole, and the fourth blind hole. The frame substrate is longitudinally cut according to the cutting cavity to expose the optical interface.

[0009] According to some embodiments of the present invention, placing an electrical chip in the first cavity and an optical chip in the second cavity includes: An adhesive element is provided at the bottom of the frame substrate; The electrical chip is placed in the first cavity, the optical chip is placed in the second cavity, and the electrical chip and the optical chip are fixed by the adhesive element.

[0010] According to some embodiments of the present invention, the encapsulation of the electrical chip and the optical chip using a dielectric material to form a dielectric material layer includes: A first dielectric material is pressed from the top of the frame substrate, so that the first dielectric material covers the upper surface of the frame substrate and fills the first cavity and the second cavity; Remove the adhesive element and press a second dielectric material from the bottom of the frame substrate so that the second dielectric material covers the lower surface of the frame substrate; the first dielectric material and the second dielectric material form the dielectric material layer.

[0011] According to some embodiments of the present invention, the side of the second cavity near the optical interface extends beyond the cutting position of the cutting cavity.

[0012] Thirdly, according to an embodiment of the present invention, a controller includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, the instructions being executed by the at least one control processor to enable the at least one control processor to perform the method for fabricating an optoelectronic co-packaging structure as described in the second aspect embodiment.

[0013] Fourthly, according to an embodiment of the present invention, a computer-readable storage medium stores computer-executable instructions for causing a computer to perform a method for manufacturing an optoelectronic co-packaging structure as described in the second aspect embodiment.

[0014] The optoelectronic co-packaging structure, its fabrication method, controller, and dielectric according to embodiments of the present invention have at least the following beneficial effects: By placing both the electrical chip and the optical chip inside the frame substrate, without surface-mounting the optical chip to the surface of the frame substrate, the integration density of the product is increased, and the surface-mount solder joints of external devices are protected from mechanical stress under temperature cycling conditions, which could lead to reliability issues such as solder joint cracking. Simultaneously, this architecture can shorten the optoelectronic signal conversion path between the electrical chip and the optical chip, avoiding significant signal attenuation, thereby reducing overall system power consumption and improving product performance. Furthermore, this method exposes the optical interface of the optical chip inside the frame substrate, facilitating optoelectronic signal conversion and transmission.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart illustrating the steps of a method for fabricating an optoelectronic co-packaging structure according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the frame substrate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after attaching the elements to the bottom of the frame substrate according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after placing the electrical chip and the optical chip in the first cavity and the second cavity according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after the first dielectric material is pressed from the top of the frame substrate according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after the second dielectric material is pressed from the bottom of the frame substrate according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the dielectric material layer after metal sputtering according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the dielectric material layer after hole-filling electroplating according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after removing the photosensitive dry film and the metal seed layer in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the frame substrate after longitudinal cutting according to an embodiment of the present invention; Figure 11 This is a top view of the frame substrate according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the controller according to an embodiment of the present invention. Detailed Implementation

[0017] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0018] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0019] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0020] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] In existing optoelectronic co-packaging methods, optical devices are typically fabricated as surface-mount components. This approach has significant limitations: First, the independent packaging structure and temperature control module significantly increase the number of system components, directly limiting the product's integration density and making it difficult to meet the increasingly urgent demands for thinner and miniaturized modern electronic devices. Second, the surface-mount solder joints of external devices are highly susceptible to mechanical stress under temperature cycling conditions, posing reliability risks such as solder joint cracking. More importantly, this architecture results in excessively long optoelectronic signal conversion paths, with external pins and traces introducing significant signal attenuation, leading to an increase in overall system power consumption. These factors collectively restrict further improvements in product performance.

[0022] To address this, this invention proposes a photoelectric co-packaging structure, its fabrication method, controller, and dielectric. By placing both the electrical chip and the optical chip inside a frame substrate, eliminating the need to surface-mount the optical chip on the substrate, the integration density of the product is increased. Furthermore, this avoids the mechanical stress that can affect surface-mount solder joints of external devices under temperature cycling conditions, preventing reliability issues such as solder joint cracking. Simultaneously, this architecture shortens the photoelectric signal conversion path between the electrical and optical chips, avoiding significant signal attenuation and thus reducing overall system power consumption and improving product performance. Additionally, this approach exposes the optical interface of the optical chip inside the frame substrate, facilitating photoelectric signal conversion and transmission.

[0023] The following is in conjunction with the appendix Figure 1-12 The present invention describes in detail the optoelectronic co-packaging structure, its fabrication method, controller, and medium of the embodiments thereof.

[0024] Firstly, such as Figure 1 As shown, the method for fabricating an optoelectronic co-packaging structure according to an embodiment of the present invention includes, but is not limited to, steps S100-S600: Step S100: Prepare a frame substrate 100; the frame substrate 100 has a first cavity 140 and a second cavity 150 penetrating through the frame substrate 100. Specifically, such as Figure 2As shown, in this example, in order to subsequently encapsulate both the electrical chip 300 and the optical chip 400 inside the substrate, the frame substrate 100 used has a first cavity 140 and a second cavity 150. The dimensions of the first cavity 140 and the second cavity 150 need to be larger than the dimensions of the electrical chip 300 and the optical chip 400. In some embodiments of this application, in order to subsequently realize the interconnection of the inner and outer layer circuits of the optoelectronic co-packaging structure, second circuits 130 are provided on both the upper and lower surfaces of the frame substrate 100, and the second circuits 130 on the upper and lower surfaces are interconnected. In this example, in order to realize the interconnection of the second circuits 130 on the upper and lower surfaces, conductive copper pillars 120 are also provided inside the frame substrate 100, and the two ends of the conductive copper pillars 120 are used to connect the second circuits 130 on the upper and lower surfaces of the frame substrate 100. Therefore, the frame substrate 100 includes a core layer 110, conductive copper pillars 120, a second circuit 130, a first cavity 140, and a second cavity 150. The core layer 110 serves as the main body of the frame substrate 100, providing support and load-bearing capacity. The conductive copper pillars 120 are disposed within and penetrate the core layer 110. The second circuit 130 is disposed on the upper and lower surfaces of the core layer 110 and is interconnected via the conductive copper pillars 120. The first cavity 140 and the second cavity 150 penetrate the core layer 110. The first cavity 140 and the second cavity 150 can be manufactured using laser cutting or CNC (Computer Numerical Control) cutting, or they can be obtained by etching a sacrificial copper block pre-placed within the core layer 110.

[0025] Step S200: An electrical chip 300 is placed in the first cavity 140, and an optical chip 400 is placed in the second cavity 150; an optical interface 420 is provided on one side of the optical chip 400. Specifically, such as Figure 4 As shown, by placing an electrical chip 300 in the first cavity 140 and an optical chip 400 in the second cavity 150, both the electrical chip 300 and the optical chip 400 are disposed inside the frame substrate 100, eliminating the need to surface mount the optical chip 400 on the surface of the frame substrate 100. This increases the product's integration density and avoids the vulnerability of surface-mount solder joints of external devices to mechanical stress under temperature cycling conditions, which could lead to solder joint cracking and other reliability issues. Simultaneously, this architecture shortens the photoelectric signal conversion path between the electrical chip 300 and the optical chip 400, preventing significant signal attenuation and thus reducing overall system power consumption and improving product performance. The optical interface 420 of the optical chip 400 is primarily responsible for the conversion and transmission of photoelectric signals. It converts the input electrical signal into an optical signal of a specific wavelength, which is then transmitted through an optical fiber. It also converts the optical signal in the optical fiber back into an electrical signal.

[0026] like Figure 3 and Figure 4 As shown, in this example, in order to place the electrical chip 300 in the first cavity 140 and the optical chip 400 in the second cavity 150, step S200 specifically includes the following two sub-steps: Step S210: Place the adhesive element 200 at the bottom of the frame substrate 100; Step S220: Place an electrical chip 300 in the first cavity 140, place an optical chip 400 in the second cavity 150, and fix the electrical chip 300 and the optical chip 400 by means of adhesive element 200.

[0027] By providing an adhesive element 200 at the bottom of the frame substrate 100, when the electrical chip 300 and the optical chip 400 are placed in the first cavity 140 and the second cavity 150 respectively, the adhesive element 200 can fix the electrical chip 300 and the optical chip 400 in place. The adhesive element 200 serves to support and fix the electrical chip 300 and the optical chip 400, preventing their positions from shifting. It should be noted that the adhesive element 200 can be made of pressure-sensitive adhesive tape or other adhesive tapes, mainly serving to support and fix the electrical chip 300 and the optical chip 400, and needs to be removed in subsequent processes.

[0028] Step S300: The electrical chip 300 and the optical chip 400 are encapsulated by the dielectric material layer 500; the dielectric material layer 500 covers the two surfaces of the frame substrate 100 and fills the first cavity 140 and the second cavity 150. Specifically, such as Figure 5 and Figure 6 As shown, in order to encapsulate the electrical chip 300 and the optical chip 400, a dielectric material layer 500 needs to be laminated onto the upper and lower surfaces of the frame substrate 100; simultaneously, the dielectric material layer 500 needs to completely fill both the first cavity 140 and the second cavity 150. After the electrical chip 300 and the optical chip 400 are placed in the first cavity 140 and the second cavity 150, there will be certain gaps in the first cavity 140 and the second cavity 150, which facilitates the dielectric material layer 500 to enter the first cavity 140 and the second cavity 150 to encapsulate the electrical chip 300 and the optical chip 400.

[0029] like Figure 5 and Figure 6 As shown, in this example, in order to encapsulate the electrical chip 300 and the optical chip 400 through the dielectric material layer 500, step S300 specifically includes the following two sub-steps: Step S310: Press the first dielectric material 510 from the top of the frame substrate 100 so that the first dielectric material 510 covers the upper surface of the frame substrate 100 and fills the first cavity 140 and the second cavity 150. Step S320: Remove the adhesive element 200 and press the second dielectric material 520 from the bottom of the frame substrate 100 so that the second dielectric material 520 covers the lower surface of the frame substrate 100; the first dielectric material 510 and the second dielectric material 520 form a dielectric material layer 500.

[0030] To ensure that the electrical chip 300 and optical chip 400 remain fixed and do not shift during the lamination of the dielectric material layer 500, the adhesive element 200 is not removed initially. First, the first dielectric material 510 is laminated from the top of the frame substrate 100, covering the upper surface of the frame substrate 100 and filling the first cavity 140 and the second cavity 150. At this point, the electrical chip 300 and optical chip 400 are encapsulated by the first dielectric material 510 and remain fixed. Then, the adhesive element 200 can be removed. Next, the second dielectric material 520 is laminated from the bottom of the frame substrate 100, covering the lower surface of the frame substrate 100. Finally, the first dielectric material 510 and the second dielectric material 520 constitute the complete dielectric material layer 500. At this point, both the electrical chip 300 and the optical chip 400 are fully encapsulated.

[0031] Step S400: Window the dielectric material layer 500 to form a first opening 540 communicating with the upper surface of the electrical chip 300, a second opening 570 communicating with the lower surface of the electrical chip 300, a third opening 550 communicating with the upper surface of the optical chip 400, and a fourth opening 580 communicating with the lower surface of the optical chip 400, and form a cutting cavity 560 communicating with the optical interface 420. Specifically, in order to achieve the interconnection between the electrical chip 300 and the optical chip 400, and the conduction between the electrical chip 300 and the optical chip 400 and the circuit, it is necessary to create windows in the dielectric material layer 500, such as... Figure 6As shown, after opening a window in the dielectric material layer 500, a first opening 540 communicating with the upper surface of the electrical chip 300, a second opening 570 communicating with the lower surface of the electrical chip 300, a third opening 550 communicating with the upper surface of the optical chip 400, and a fourth opening 580 communicating with the lower surface of the optical chip 400 are obtained, forming a cutting cavity 560 communicating with the optical interface 420. It should be noted that a first connection terminal 310 is provided on the lower surface of the electrical chip 300, and a second connection terminal 410 is provided on the lower surface of the optical chip 400. The second opening 570 communicates with the first connection terminal 310 on the lower surface of the electrical chip 300, and the fourth opening 580 communicates with the second connection terminal 410 on the lower surface of the optical chip 400. Furthermore, since the upper and lower surfaces of the frame substrate 100 are also provided with second lines 130, when opening a window in the dielectric material layer 500, a fifth opening 530 communicating with the second lines 130 also needs to be formed. In this example, the dielectric material layer 500 is a photosensitive dielectric material. When creating windows in the dielectric material layer 500, it undergoes exposure, development, and curing to form various openings and cavities 560. By setting the cavities 560, the optical interface 420 is exposed, enabling it to transmit optical signals and preventing residual adhesive at the optical interface 420 from obstructing this transmission. It should be noted that besides using exposure and development to create windows in the dielectric material layer 500, laser cutting or other cutting methods can also be used. However, compared to cutting, exposure and development avoids damaging the chip during the cutting process. Before laminating the dielectric material layer 500, the surface of the frame substrate 100 can be roughened to improve the bonding strength between the dielectric material layer 500 and the frame substrate 100.

[0032] Step S500: The frame substrate 100 is filled by electroplating to form a first blind hole 720 in the first opening 540, a second blind hole 740 in the second opening 570, a third blind hole 730 in the third opening 550, and a fourth blind hole 750 in the fourth opening 580. A first line 800 communicating with the first blind hole 720, the second blind hole 740, the third blind hole 730, and the fourth blind hole 750 is formed by electroplating on both surfaces of the frame substrate 100. Specifically, such as Figure 8As shown, by performing a hole-filling electroplating process on the frame substrate 100, a first blind via 720 can be formed in the first opening 540, a second blind via 740 can be formed in the second opening 570, a third blind via 730 can be formed in the third opening 550, and a fourth blind via 750 can be formed in the fourth opening 580. The first blind via 720 is electrically connected to the upper surface of the electrical chip 300, the second blind via 740 is electrically connected to the first connection terminal 310 of the electrical chip 300, the third blind via 730 is electrically connected to the upper surface of the optical chip 400, and the fourth blind via 750 is electrically connected to the second connection terminal 410 of the optical chip 400. Furthermore, a fifth blind via 750 is formed in the fifth opening 530 and is connected to the second line 130. Simultaneously, first lines 800, which are conductive to each blind via, are electroplated on both surfaces of the frame substrate 100. Thus, through the blind vias, the first line 800, the second line 130, the electrical chip 300, and the optical chip 400 can be interconnected, achieving interconnection of the various structures. It should be noted that, as... Figure 7 As shown, before hole-filling electroplating, a metal seed layer 600 can be formed on the surface of the dielectric material layer 500, the inner walls of each opening, and the inner wall of the cutting cavity 560 by metal sputtering, serving as the basis for hole-filling electroplating. Figure 8 As shown, during the hole-filling electroplating process, a photosensitive dry film 900 is deposited on the surface of the dielectric material layer 500 to protect the areas that do not require electroplating. Then, through exposure and development, a window is created in the photosensitive dry film 900 to expose the areas that need electroplating. For example... Figure 9 As shown, after completing the fabrication of the blind via and the first line 800, the photosensitive dry film 900 is removed, and the excess metal seed layer 600 is etched away.

[0033] Step S600: According to the cutting cavity 560, the frame substrate 100 is longitudinally cut to expose the optical interface 420.

[0034] Specifically, such as Figure 10 As shown, the frame substrate 100 is longitudinally cut along the location of the cutting cavity 560 to remove the excess portion on the right side of the optical interface 420, exposing the optical interface 420 to facilitate optical signal transmission. Figure 11 As shown, the edge of the second cavity 150 near the optical interface 420 needs to extend beyond the cutting line 561 of the cutting cavity 560 to avoid damage to the optical interface 420 when the frame substrate 100 is longitudinally cut, and to ensure that the side of the optical interface 420 of the cut optical chip 400 is unobstructed, which is conducive to the transmission of optical signals.

[0035] According to the method for fabricating the optoelectronic co-packaging structure in this application, by placing both the electrical chip 300 and the optical chip 400 inside the frame substrate 100, without surface-mounting the optical chip 400 to the surface of the frame substrate 100, the integration density of the product is improved. Furthermore, this avoids the vulnerability of surface-mount solder joints of external devices to mechanical stress under temperature cycling conditions, which could lead to solder joint cracking and other reliability issues. Simultaneously, this architecture shortens the optoelectronic signal conversion path between the electrical chip 300 and the optical chip 400, avoiding significant signal attenuation and thus reducing overall system power consumption and improving product performance. Additionally, this method exposes the optical interface 420 of the optical chip 400 inside the frame substrate 100, facilitating optoelectronic signal conversion and transmission.

[0036] Secondly, embodiments of the present invention also propose an optoelectronic co-packaging structure, which is fabricated using the optoelectronic co-packaging structure fabrication method described in the above embodiments, such as... Figure 10 As shown, the optoelectronic co-packaging junction includes: Frame substrate 100; The electrical chip 300 is disposed within the frame substrate 100; An optical chip 400 is disposed within a frame substrate 100, and an optical interface 420 is provided on one side of the optical chip 400. A dielectric material layer 500 covers two surfaces of the frame substrate 100 and encapsulates the electrical chip 300 and optical chip 400 within the frame substrate 100. The side of the dielectric material layer 500 exposes the optical interface 420. The dielectric material layer 500 is provided with a first blind hole 720 communicating with the upper surface of the electrical chip 300, a second blind hole 740 communicating with the lower surface of the electrical chip 300, a third blind hole 730 communicating with the upper surface of the optical chip 400, and a fourth blind hole 750 communicating with the lower surface of the optical chip 400. The first line 800 is disposed on two surfaces of the dielectric material layer 500, and the first line 800 is interconnected with the first blind via 720, the second blind via 740, the third blind via 730 and the fourth blind via 750.

[0037] According to the optoelectronic co-packaging structure of this application embodiment, by placing both the electrical chip 300 and the optical chip 400 inside the frame substrate 100, without surface-mounting the optical chip 400 to the surface of the frame substrate 100, the integration density of the product is improved. This also avoids the surface-mount solder joints of external devices being susceptible to mechanical stress under temperature cycling conditions, which could lead to reliability issues such as solder joint cracking. Simultaneously, this architecture shortens the optoelectronic signal conversion path between the electrical chip 300 and the optical chip 400, avoiding significant signal attenuation, thereby reducing overall system power consumption and improving product performance. Furthermore, this method exposes the optical interface 420 of the optical chip 400 inside the frame substrate 100, facilitating optoelectronic signal conversion and transmission. The first line 800 achieves mutual conduction with the electrical chip 300 and the optical chip 400 through the first blind via 720, the second blind via 740, the third blind via 730, and the fourth blind via 750, thereby realizing the connection between the various chips and lines.

[0038] Furthermore, such as Figure 2As shown, a conductive copper pillar 120 is disposed inside the frame substrate 100, and second lines 130 interconnected by the conductive copper pillar 120 are disposed on the two surfaces of the frame substrate 100. A fifth blind via 710 interconnected with the second line 130 is also disposed within the dielectric material layer 500, and the fifth blind via 710 is also interconnected with the first line 800. In order to realize the interconnection of the inner and outer layer lines of the optoelectronic co-packaging structure, second lines 130 are disposed on both the upper and lower surfaces of the frame substrate 100, and the second lines 130 on the upper and lower surfaces are interconnected. In this example, in order to realize the interconnection of the second lines 130 on the upper and lower surfaces, a conductive copper pillar 120 is also disposed inside the frame substrate 100, and the two ends of the conductive copper pillar 120 are used to connect the second lines 130 on the upper and lower surfaces of the frame substrate 100. Therefore, the frame substrate 100 includes a core layer 110, conductive copper pillars 120, a second circuit 130, a first cavity 140, and a second cavity 150. The core layer 110 serves as the main body of the frame substrate 100, providing support and load-bearing capacity. The conductive copper pillars 120 are disposed within and penetrate the core layer 110. The second circuit 130 is disposed on the upper and lower surfaces of the core layer 110 and is interconnected via the conductive copper pillars 120. The first cavity 140 and the second cavity 150 penetrate the core layer 110. The first cavity 140 and the second cavity 150 can be manufactured using laser cutting or CNC (Computer Numerical Control) cutting, or they can be obtained by etching a sacrificial copper block pre-placed within the core layer 110. After placing the electrical chip 300 in the first cavity 140 and the optical chip 400 in the second cavity 150, both the first cavity 140 and the second cavity 150 are filled with the dielectric material layer 500, thereby achieving the filling of the electrical chip 300 and the optical chip 400.

[0039] In some embodiments of this application, a first connection terminal 310 is provided on the lower surface of the electrical chip 300, and a second connection terminal 410 is provided on the lower surface of the optical chip 400. The first connection terminal 310 is connected to a second blind via 740, and the second connection terminal 410 is connected to a fourth blind via 750. Thus, the first connection terminal 310 of the electrical chip 300 can be connected to the first line 800 through the second blind via 740, and the second connection terminal 410 of the optical chip 400 can be connected to the first line 800 through the fourth blind via 750.

[0040] Thirdly, embodiments of the present invention also provide a controller, such as... Figure 12 As shown, it includes: The processor 101 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 102 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 502 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called and executed by the processor 501 using the method for fabricating the optoelectronic co-packaging structure of the embodiments of this application. Input / output interface 103 is used to implement information input and output; The communication interface 104 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 105 transmits information between various components of the device (e.g., processor 101, memory 102, input / output interface 103, and communication interface 104); The processor 101, memory 102, input / output interface 103 and communication interface 104 are connected to each other within the device via bus 105.

[0041] On the other hand, embodiments of the present invention also provide a storage medium, which is a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the above-described method for manufacturing an optoelectronic co-packaging structure.

[0042] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0043] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0044] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0045] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0046] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0047] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0048] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0049] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An opto-electronic co-packaged structure, characterized in that, include: Frame substrate; An electrical chip is disposed within the frame substrate; An optical chip is disposed within the frame substrate, and an optical interface is provided on one side of the optical chip; A dielectric material layer covers both surfaces of the frame substrate and encapsulates the electrical chip and the optical chip within the frame substrate. The optical interface is exposed on the side of the dielectric material layer. The dielectric material layer is provided with a first blind via communicating with the upper surface of the electrical chip, a second blind via communicating with the lower surface of the electrical chip, a third blind via communicating with the upper surface of the optical chip, and a fourth blind via communicating with the lower surface of the optical chip. The first circuit is disposed on two surfaces of the dielectric material layer, and the first circuit is interconnected with the first blind via, the second blind via, the third blind via, and the fourth blind via.

2. The optoelectronic co-packaged structure of claim 1, wherein, The frame substrate has a conductive copper pillar inside, and two surfaces of the frame substrate have a second line that is interconnected through the conductive copper pillar. The dielectric material layer also has a fifth blind via that is interconnected with the second line, and the fifth blind via is also interconnected with the first line.

3. The optoelectronic co-packaged structure of claim 1, wherein, The frame substrate has a first cavity and a second cavity penetrating the frame substrate. The electrical chip is located in the first cavity, and the optical chip is located in the second cavity. Both the first cavity and the second cavity are filled with the dielectric material layer.

4. The optoelectronic co-packaged structure of claim 1, wherein, One surface of the electrical chip is provided with a first connection terminal, and one surface of the optical chip is provided with a second connection terminal. The first connection terminal is connected to the second blind hole, and the second connection terminal is connected to the fourth blind hole.

5. A method for fabricating an optoelectronic co-packaging structure, characterized in that, Includes the following steps: Prepare a frame substrate; the frame substrate has a first cavity and a second cavity penetrating the frame substrate. An electrical chip is placed in the first cavity, and an optical chip is placed in the second cavity; an optical interface is provided on one side of the optical chip. The electrical chip and the optical chip are encapsulated using a dielectric material layer; The dielectric material layer covers both surfaces of the frame substrate and fills the first cavity and the second cavity; A window is made in the dielectric material layer to form a first opening communicating with the upper surface of the electrical chip, a second opening communicating with the lower surface of the electrical chip, a third opening communicating with the upper surface of the optical chip, and a fourth opening communicating with the lower surface of the optical chip, and to form a cutting cavity communicating with the optical interface. The frame substrate is subjected to hole-filling electroplating to form a first blind hole in the first opening, a second blind hole in the second opening, a third blind hole in the third opening, and a fourth blind hole in the fourth opening. A first line is formed on both surfaces of the frame substrate to be connected to the first blind hole, the second blind hole, the third blind hole, and the fourth blind hole. The frame substrate is longitudinally cut according to the cutting cavity to expose the optical interface.

6. The method of claim 5, wherein the method further comprises: The step of placing an electrical chip in the first cavity and an optical chip in the second cavity includes: An adhesive element is provided at the bottom of the frame substrate; The electric chip is placed in the first cavity, the optical chip is placed in the second cavity, and the electric chip and the optical chip are fixed by the adhesive element.

7. The method of claim 6, wherein the method further comprises: The electric chip and the optical chip are encapsulated by the medium material to form a medium material layer, including: A first medium material is laminated from the top of the frame substrate to cover the upper surface of the frame substrate and fill the first cavity and the second cavity; The adhesive element is removed, and a second medium material is laminated from the bottom of the frame substrate to cover the lower surface of the frame substrate; the first medium material and the second medium material form the medium material layer.

8. The method of claim 5, wherein: The second cavity exceeds the cutting position of the cutting cavity on the side close to the optical interface.

9. A controller characterized by comprising: The computer readable storage medium stores computer executable instructions for causing a computer to execute the method for manufacturing the optoelectronic co-encapsulation structure according to any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for causing a computer to execute the method for manufacturing the optoelectronic co-encapsulation structure according to any one of claims 5 to 8.

Images