Method, device and storage medium for obtaining correction coefficient of instruction execution efficiency

Abstract

This invention relates to the field of chip design technology, and in particular to a method, device, and storage medium for obtaining correction coefficients for instruction execution efficiency. The invention obtains test cases used to test the efficiency of various instructions in the pre-silicon stage. Before silicon, the test cases are tested in a verification environment based on a simulator. After the test cases are executed, the estimated and actual execution efficiency values ​​of each instruction are obtained. The estimated value is obtained by reading the values ​​of an instruction counter used to record the instruction execution cycle and a state counter used to record the clock cycle in which the processor core is in operation. The actual value is obtained based on the instruction execution cycle and the actual data in the waveform information generated by the simulator. Based on the estimated and actual values ​​of each instruction, a correction coefficient for each instruction is obtained, solving the problem of the inability to accurately obtain the execution efficiency of instructions during post-silicon testing.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method, device and storage medium for obtaining a correction coefficient for instruction execution efficiency. Background Technology

[0002] In the performance evaluation of graphics processing unit (GPU) architecture, the instruction execution efficiency of the core computing unit is one of the key indicators for measuring its computing resource utilization efficiency. This instruction execution efficiency reflects the activity level of a functional unit when executing a specific instruction type, and is usually quantified as the proportion of effective execution cycles to total available cycles. For a specific instruction type A, its execution efficiency can be defined as: the number of effective execution cycles of instruction A divided by the sum of the number of execution cycles and the number of idle waiting cycles of instruction A. This instruction execution efficiency can effectively reveal the fill level of the instruction pipeline and the utilization rate of functional units, providing data support for architecture optimization. To accurately calculate this instruction execution efficiency, two types of timing parameters must be precisely obtained: one is the number of hardware cycles actually consumed by instruction A in the functional unit, and the other is the idle cycles. However, in the operating environment of a real physical chip, existing monitoring mechanisms have significant limitations; GPU architecture provides a limited number of hardware performance counters (PMUs) for counting instruction execution cycles, but it is difficult to accurately obtain the execution efficiency of instructions during post-silicon testing. Therefore, a method that can accurately obtain the execution efficiency of instructions during post-silicon testing is urgently needed. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention employs the following technical solution: a method for obtaining the correction coefficient for instruction execution efficiency, the method comprising the following steps:

[0004] S100: Obtain test cases used in the pre-silicon phase to test the efficiency of various instructions.

[0005] S200, before silicon, the test cases are tested in a verification environment based on a simulator. After the test cases are executed, the estimated and actual execution efficiency of each instruction is obtained.

[0006] The steps for obtaining the estimated execution efficiency of each instruction include:

[0007] S210, read the instruction counter used to record the instruction execution cycle to obtain the execution cycle ins_Ecyc of all instructions, where the execution cycle of the i-th instruction in ins_Ecyc is ins_Ecyc. i The value of i ranges from 1 to N, where N is the total number of instructions.

[0008] S220: Read the state counter used to record the clock cycles in which the processor core is in operation, and obtain the total execution cycle Tot_Ecyc.

[0009] S230, based on ins_Ecyc and Tot_Ecyc, obtain an estimated value of the execution efficiency of each instruction to get Eff_est, where the estimated value of the execution efficiency of the i-th instruction in Eff_est is Eff_est. 。

[0010] The steps for obtaining the actual execution efficiency of each instruction include:

[0011] S240, extract the actual data from the waveform information generated by the simulator to obtain the actual execution cycle of the processor core in working state, and calculate the true value of the execution efficiency of each instruction based on the actual execution cycle to obtain Eff_tru, where the true value of the execution efficiency of the i-th instruction in Eff_tru is Eff_tru. i .

[0012] S300, based on the estimated and actual execution efficiency of each instruction, obtain the correction coefficient for each instruction; where the correction coefficient for the i-th instruction is Eff_tru i With Eff_est i The ratio of .

[0013] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0014] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0015] The present invention has at least the following beneficial effects:

[0016] This invention provides a method, device, and storage medium for obtaining correction coefficients for instruction execution efficiency. It acquires test cases used in the pre-silicon testing phase to test the efficiency of various instructions. After the test cases are executed, it obtains the estimated and actual values ​​for each instruction. The estimated value is calculated using a counter, and the actual value is calculated by reading waveform information generated by a simulator. Based on the estimated and actual values ​​for each instruction, a corresponding correction coefficient is obtained. This correction coefficient corrects for efficiency losses caused by initialization and shutdown cycles, calibrating the estimated instruction execution efficiency obtained after post-silicon testing to approximate the actual value. This solves the current problem of not being able to accurately obtain the instruction execution efficiency during post-silicon testing. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for obtaining a correction coefficient for instruction execution efficiency, provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0021] Please see Figure 1 It illustrates a method for obtaining a correction coefficient for instruction execution efficiency, the method comprising the following steps:

[0022] S100: Obtain test cases used in the pre-silicon phase to test the efficiency of various instructions.

[0023] The pre-silicon phase refers to the period after a GPU chip design is completed but before it has been fabricated. During this phase, engineers use simulation, FPGA prototyping, and other methods to verify the design and ensure that its functionality and performance meet expectations.

[0024] The test case is a micro-benchmark program for performance evaluation, executable in an RTL simulation environment. Its purpose is to accurately measure the execution efficiency of various instructions in the processor by controlling the instruction flow, acquiring performance counters and waveform data. Each test case includes one or more instructions.

[0025] S200, before silicon, the test cases are tested in a verification environment based on a simulator. After the test cases are executed, the estimated and actual execution efficiency of each instruction is obtained.

[0026] Furthermore, the steps for obtaining an estimate of the execution efficiency of each instruction include:

[0027] S210, read the instruction counter used to record the instruction execution cycle to obtain the execution cycle ins_Ecyc of all instructions, where the execution cycle of the i-th instruction in ins_Ecyc is ins_Ecyc. i The value of i ranges from 1 to N, where N is the total number of instructions.

[0028] In one implementation, each instruction is configured with an instruction counter.

[0029] It should be noted that other methods of configuring instruction counters for instructions also fall within the protection scope of this invention.

[0030] In one implementation, the instruction counter is a hardware functional module independent of the test cases, integrated within the processor, but it needs to be triggered, configured, and read by the test cases. That is, the counter itself is part of the RTL design, independent of the test cases, and belongs to the processor's performance monitoring unit. The configuration and reading of the counter are accomplished by software code within the test cases, such as writing to registers to initiate the process and reading registers to obtain results.

[0031] S220: Read the state counter used to record the clock cycles in which the processor core is in operation, and obtain the total execution cycle Tot_Ecyc.

[0032] The status counter counts throughout the entire runtime of the processor core while it is in an active state. The total execution cycle Tot_Ecyc includes all clock cycles from the start of execution of the first instruction to the end of execution of the last instruction.

[0033] S230, based on ins_Ecyc and Tot_Ecyc, obtain an estimated value of the execution efficiency of each instruction to get Eff_est, where the estimated value of the execution efficiency of the i-th instruction in Eff_est is Eff_est. i .

[0034] In one implementation, Eff_est in S230 i for ins_Ecyc i The ratio of Eff_est to Tot_Ecyc. i =ins_Ecyc i / Tot_Ecyc.

[0035] It's important to note that Eff_est is referred to as an estimate of the execution efficiency of each instruction because the instruction counter's measurement window covers the entire execution process from the initiation of the first instruction under test to the completion of the last. Since the counter remains enabled throughout this process, the recorded execution cycles include the overhead of the initialization and shutdown phases. This results in the measured cycle count including not only the total clock cycles of all instruction execution but also the time spent on environment preparation and result processing, leading to inaccurate measurement results. In other words, Eff_est is an estimate, not an exact value.

[0036] Furthermore, the step of obtaining the true value of the execution efficiency of each instruction includes: S240, extracting actual data from the waveform information generated by the simulator to obtain the actual execution cycle of the processor core in the working state, and calculating the true value of the execution efficiency of each instruction based on the actual execution cycle to obtain Eff_tru, where the true value of the execution efficiency of the i-th instruction in Eff_tru is Eff_tru. i .

[0037] In one implementation, in S240, the actual data extracted from the waveform information of the simulator includes the actual cycle, initialization cycle (Warm_up), and shutdown cycle (End_up) of the processor core in the working state. The actual execution cycle is the actual cycle minus the initialization cycle and the shutdown cycle. That is, the actual execution cycle = actual cycle - initialization cycle - shutdown cycle.

[0038] The initialization cycle (Warm_up) is the number of clock cycles consumed to establish the test environment, prepare data, and configure resources after the test case program begins execution and before entering the core performance measurement phase. This phase includes operations such as register setup, memory initialization, and peripheral configuration.

[0039] The shutdown period (End_up) is the number of clock cycles consumed to read performance counter results, save data, release resources, or enter a low-power state after the core performance test ends and before the test program completely exits.

[0040] In one implementation, in S240, Eff_tru i for ins_Ecyc_tru i The ratio to the actual execution cycle, wherein ins_Ecyc_tru i for ins_Ecyc i Alternatively, it can be obtained by extracting the waveform information generated by the simulator to determine the actual execution cycle of the i-th instruction. That is, Eff_tru i =ins_Ecyc_tru i / Actual execution cycle=ins_Ecyc_tru i / (Actual cycle - Initialization cycle - Shutdown cycle). It should be noted that, theoretically, the clock cycle of the instruction counted by the instruction counter is equal to the actual execution cycle recorded by the waveform information.

[0041] In one implementation, in S240, the runtime event records in the simulation log are automatically parsed by a script to obtain the execution cycle of each instruction, the actual cycle of the processor core in the working state, the initialization cycle (Warm_up), and the shutdown cycle (End_up).

[0042] S300, based on the estimated and actual execution efficiency of each instruction, obtain the correction coefficient for each instruction; where the correction coefficient for the i-th instruction is Eff_tru i With Eff_est i The ratio of .

[0043] The total execution cycle Tot_Ecyc includes an initialization cycle and a shutdown cycle. However, since the instruction counter cannot distinguish between the initialization cycle and the shutdown cycle, the estimated value can be further corrected by using a correction factor.

[0044] It should be noted that the correction factor reflects the systematic deviation between the estimation model and the real system. It can correct the efficiency loss caused by the initialization cycle and shutdown cycle, and is used to calibrate the estimated value of instruction execution efficiency obtained by post-silicon testing, so that it is closer to the real value.

[0045] In one implementation, when the test cases in S100 change, steps S200 and S300 are executed again to obtain a list of correction coefficients for all instructions in the changed test cases. It should be noted that the test cases in S100 are the same as those used in post-silicon testing. When the test cases for post-silicon testing change, the method provided by this invention needs to be executed again with the changed test cases to obtain a new list of correction coefficients for the instructions. For test cases of different instructions, the initialization cycle and shutdown cycle will be different. Correction coefficients applicable to each test case scenario can be provided for different test case scenarios.

[0046] In one embodiment, the method further includes: S400, when the test cases are tested via post-silicon testing, obtaining a post-silicon estimated value of the execution efficiency of each instruction; and correcting the post-silicon estimated value according to the correction coefficient for each instruction to obtain the true post-silicon value. It should be noted that post-silicon testing is performed on a real chip and cannot be simulated using a simulator. Post-silicon performance observation mainly relies on the performance counters integrated within the chip. The method provided by this embodiment uses the same test cases for pre-silicon testing and post-silicon testing, and by correcting the values ​​obtained from pre-silicon testing with the correction coefficients, the estimated values ​​obtained from post-silicon testing can be corrected to the true values, improving the accuracy of instruction execution efficiency.

[0047] In one implementation, the corrected post-silicon true value of the i-th instruction is equal to the correction factor of the i-th instruction multiplied by the estimated post-silicon value of the i-th instruction.

[0048] In summary, this invention provides a method for obtaining a correction coefficient for instruction execution efficiency. It involves acquiring test cases used in the pre-silicon testing phase to assess the efficiency of various instructions. After the test cases are executed, the estimated and actual values ​​for each instruction are obtained. The estimated value is calculated using a counter, and the actual value is calculated by reading waveform information generated by the simulator. A corresponding correction coefficient is then obtained based on the estimated and actual values ​​for each instruction. This correction coefficient can correct for efficiency losses caused by initialization and shutdown cycles, calibrating the estimated instruction execution efficiency obtained after post-silicon testing to approximate the actual value. This solves the current problem of not being able to accurately obtain the instruction execution efficiency during post-silicon testing.

[0049] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0050] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0051] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0052] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0053] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A method for obtaining the correction coefficient for instruction execution efficiency, characterized in that, The method includes the following steps: S100: Obtain test cases used in the pre-silicon stage to test the efficiency of various instructions; S200, before silicon, the test cases are tested in a verification environment based on a simulator. After the test cases are executed, the estimated and actual execution efficiency of each instruction is obtained respectively. The steps for obtaining the estimated execution efficiency of each instruction include: S210, read the instruction counter used to record the instruction execution cycle to obtain the execution cycle ins_Ecyc of all instructions, where the execution cycle of the i-th instruction in ins_Ecyc is ins_Ecyc. i The value of i ranges from 1 to N, where N is the total number of instructions; S220: Read the state counter used to record the clock cycles in which the processor core is in operation, and obtain the total execution cycle Tot_Ecyc; S230, based on ins_Ecyc and Tot_Ecyc, obtain an estimated value of the execution efficiency of each instruction to get Eff_est, where the estimated value of the execution efficiency of the i-th instruction in Eff_est is Eff_est. i ; The steps for obtaining the actual execution efficiency of each instruction include: S240, extract the actual data from the waveform information generated by the simulator to obtain the actual execution cycle of the processor core in working state, and calculate the true value of the execution efficiency of each instruction based on the actual execution cycle to obtain Eff_tru, where the true value of the execution efficiency of the i-th instruction in Eff_tru is Eff_tru. i ; S300, based on the estimated and actual execution efficiency of each instruction, obtain the correction coefficient for each instruction; where the correction coefficient for the i-th instruction is Eff_tru i With Eff_est i The ratio of .

2. The method according to claim 1, characterized in that, Eff_est in S230 i for ins_Ecyc i The ratio to Tot_Ecyc.

3. The method according to claim 1, characterized in that, In S240, the actual data extracted from the waveform information of the simulator includes the actual cycle, initialization cycle and shutdown cycle of the processor core in the working state, and the actual execution cycle is the actual cycle minus the initialization cycle and shutdown cycle.

4. The method according to claim 3, characterized in that, In S240, Eff_tru i for ins_Ecyc_tru i The ratio to the actual execution cycle, wherein ins_Ecyc_tru i for ins_Ecyc i Alternatively, it can be the actual execution cycle of the i-th instruction obtained by extracting the waveform information of the simulator.

5. The method according to claim 1, characterized in that, In S240, the actual data in the waveform information generated by the simulator is automatically extracted through a script.

6. The method according to claim 1, characterized in that, The method further includes: S400, when the test case is tested by post-silicon testing, obtain the post-silicon estimated value of the execution efficiency of each instruction; and correct the post-silicon estimated value according to the correction coefficient of each instruction.

7. The method according to claim 1, characterized in that, In S210, each instruction is configured with an instruction counter.

8. The method according to claim 1, characterized in that, When the test case in S100 is changed, the steps in S200 and S300 are executed again to obtain a list of correction coefficients for all instructions in the changed test case.

9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.

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