A method, apparatus, and electronic device for generating scanning patterns.

Abstract

This disclosure provides a method, apparatus, and electronic device for generating scan patterns, belonging to the field of electronic design automation (EDA) technology. The method includes: acquiring chip project information, which includes attribute information and the number of available input / output (I / O) units for multiple chip modules; the attribute information for the multiple chip modules includes the total number of registers in each chip module; determining a target partitioning combination to divide the multiple chip modules into multiple scan blocks based on the attribute information and block allocation constraints; and determining the target scan chain length and target compression ratio for each scan block that satisfies the scan parameter constraints under the target partitioning combination, based on the number of available I / O units and the total number of registers in each chip module. This allows for the allocation of each chip module to its respective scan block.

Description

Technical Field

[0001] This disclosure relates to the field of electronic design automation technology, and in particular to a method, apparatus and electronic device for generating scan patterns. Background Technology

[0002] With the continuous advancement of integrated circuit (IC) manufacturing processes, the design complexity of system-on-chips (SoCs) has increased exponentially. Embedding Design for Testability (DFT) structures during the chip design phase has become a crucial step in ensuring efficient and accurate detection of hardware defects after chip manufacturing. Scan testing, as one of the core technologies in DFT, works by replacing sequential logic units (such as D flip-flops) in the chip with scan registers and connecting these registers into a serial shift chain. In this way, test equipment can input test vectors through external pins of the chip and observe the output response, thus solving the challenge of observing and controlling the complex logic inside the chip.

[0003] In the SoC scanning test process, a key step is defining the scan blocks, also known as scan modes. This requires dividing all functional modules of the chip into several independent groups based on the chip's overall design architecture. In actual testing, only one scan mode (i.e., one group) can be activated at a time to scan and test the modules within that group, while other groups remain inactive.

[0004] In related technologies, the process of dividing scan blocks relies on manual work by experienced DFT engineers. Engineers need to manually analyze the chip's hierarchical architecture, estimate the number of registers for all modules, and weigh available input / output (I / O) resources based on their professional experience, ultimately "manually" formulating a scan plan. This manual approach, entirely dependent on human experience, has at least the following drawbacks: In complex SoCs containing hundreds or thousands of modules, manually performing such multi-objective trade-offs is extremely time-consuming and labor-intensive, significantly extending the chip's development cycle; the quality of the plan depends entirely on the engineer's personal experience, potentially leading to unreasonable or suboptimal plans, resulting in insufficient test coverage, excessively long testing times, or wasted resources; and the manual process cannot guarantee 100% satisfaction of all hierarchical constraints, and errors can cause DFT implementation failure. Summary of the Invention

[0005] This disclosure provides a method, apparatus, and electronic device for generating scan patterns, which can divide each chip module into scan blocks and satisfy block allocation constraints and scan parameter constraints.

[0006] The technical solution disclosed herein is implemented as follows:

[0007] Firstly, this disclosure provides a method for generating a scan pattern. The method includes: acquiring chip project information, which includes attribute information and the number of available input / output I / Os for multiple chip modules; the attribute information for the multiple chip modules includes the total number of registers in each chip module; determining a target partitioning combination to divide the multiple chip modules into multiple scan blocks based on the attribute information and block allocation constraints; and determining the target scan chain length and target compression ratio of each scan block that satisfies the scan parameter constraints under the target partitioning combination, based on the number of available I / Os and the total number of registers in each chip module. This automatically allocates each chip module to its respective scan block.

[0008] In some embodiments, based on attribute information and block allocation constraints, a target partitioning combination for dividing multiple chip modules into multiple scan blocks is determined, including: determining multiple candidate partitioning combinations based on attribute information and block allocation constraints; determining a balance metric for each candidate partitioning combination; and determining the candidate partitioning combination corresponding to the minimum balance metric as the target partitioning combination. By balancing the total number of registers in each scan mode, the scan chain length can be indirectly balanced, and the load-balanced grouping can be directly converted into approximately equal test times for each scan mode, thereby making the test plan more uniform and predictable.

[0009] In some embodiments, based on the number of available I / Os and the total number of registers included in each chip module, the target scan chain length and target compression ratio for each scan block that satisfies the scan parameter constraints under the target partitioning combination are determined. This includes: determining multiple candidate combinations of scan chain lengths and compression ratios, where each candidate combination includes a different scan chain length or compression ratio, and the compression ratio in each candidate combination is less than or equal to a compression ratio threshold; determining the total number of channels for all chip modules corresponding to each candidate combination under the target partitioning combination based on the total number of registers in each chip module included in each scan block; and determining the scan chain length and compression ratio included in candidate combinations where the total number of channels is less than or equal to the number of available I / Os as the target scan chain length and target compression ratio. This allows for the determination of candidate combinations that satisfy the scan parameter constraints from a variety of candidate combinations.

[0010] In some embodiments, determining the scan chain length and compression ratio of candidate combinations whose total number of channels is less than or equal to the number of available I / Os as the target scan chain length and target compression ratio includes: determining the scan chain length and target compression ratio of candidate combinations whose total number of channels is less than or equal to the number of available I / Os, and whose difference between the total number of channels and the number of available I / Os is the smallest. For multiple candidate combinations whose total number of channels is less than or equal to the number of available I / Os, determining the scan chain length and target compression ratio of the candidate combination whose total number of channels is closest to the number of available I / Os as the target scan chain length and target compression ratio allows for the use of as many available I / O pins as possible as possible as well, enabling more scan chain data to be shifted in / out in parallel at the same time, thereby significantly reducing the time required to load each test vector.

[0011] In some embodiments, the attribute information of multiple chip modules includes: module hierarchy information between the multiple chip modules; block allocation constraints include: the top-level module included in the chip module is allocated to a single scan block. This constraint follows industry best practices, where top-level logic needs to be isolated and tested in layered testing to verify the correctness of cross-core connections and interactions.

[0012] In some embodiments, the block allocation constraint also includes that there is no parent-child relationship between chip modules allocated to the same scan block. This constraint is crucial for ensuring the effectiveness of testing, because simultaneous testing of parent and child modules may introduce signal races, timing conflicts, or unpredictable logic states, leading to unreliable test results. Automating this check can avoid a common type of design error.

[0013] In some embodiments, the attribute information of the multiple chip modules further includes: the domain in which each chip module resides, the domain including at least one of a power domain and a clock domain; the block allocation constraint further includes: chip modules assigned to the same scan block belong to the same domain. By introducing "domain constraints," the automated grouping becomes "power-aware" and "clock-aware," thereby automatically avoiding the mixing of chip modules from different power domains or clock domains in the same scan block. This prevents cross-clock domain (CDC) timing issues or cross-power domain level transition issues that may occur during DFT testing, greatly improving the robustness and automation of DFT design.

[0014] In some embodiments, the attribute information of multiple chip modules further includes: the physical location of each chip module; the block allocation constraint also includes: the distance between the physical locations of any two chip modules assigned to the same scan block is less than a distance threshold. This ensures that the chip modules in the same scan block are close to each other, thereby minimizing the routing overhead of the scan chain. By introducing "physical location constraints," automated grouping gains "physical awareness" capabilities. In DFT implementation, scan chains within the same scan block require physical routing connections. Grouping physically adjacent modules into the same group can significantly shorten the bus length of DFT routing, reduce routing congestion, and improve the timing issues of the scan chain.

[0015] Secondly, this disclosure provides an apparatus for generating a scan pattern, comprising: an acquisition section configured to acquire chip project information, the chip project information including attribute information and the number of available input / output I / Os of multiple chip modules, the attribute information of the multiple chip modules including the number of registers of each chip module; a determination section configured to determine a target partitioning combination for dividing the multiple chip modules into multiple scan blocks based on the attribute information and block allocation constraints; and, based on the number of available I / Os and the total number of registers included in each chip module, to determine the target scan chain length and target compression ratio of each scan block that satisfies the scan parameter constraints under the target partitioning combination.

[0016] Thirdly, this disclosure provides an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method for generating a scan pattern as described in the first aspect.

[0017] Fourthly, this disclosure provides a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method for generating a scan pattern as described in the first aspect.

[0018] Fifthly, this disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, which, when run on a processor, cause the processor to execute the computer program or instructions to implement the steps of the method for generating a scan pattern as described in the first aspect.

[0019] In a sixth aspect, this disclosure provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the method for generating scan patterns as described in the first aspect.

[0020] This disclosure provides a method for generating scan patterns. First, based on preset block allocation constraints, multiple chip modules are divided into multiple scan blocks, achieving automated partitioning of scan blocks that meets engineering practice requirements. Second, for each scan block, scan parameter constraints ensure that the compression ratio of each scan block meets design requirements, and the total number of channels is less than the number of available I / Os of the chip (meeting physical constraints), meaning it is physically feasible. In summary, the embodiments of this disclosure can simultaneously solve the balance problem between logical constraints (block allocation constraints) and physical constraints (scan parameter constraints), thereby automatically, quickly, and accurately generating a logically valid and physically feasible scan block partitioning scheme. Compared to relying on the personal experience of DFT engineers, this greatly reduces the technical threshold of DFT design, improves design efficiency, and significantly shortens the chip development cycle. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating a method for generating a scanning pattern provided in this disclosure.

[0022] Figure 2 This is a schematic diagram of the tree structure of the various chip modules provided in this disclosure.

[0023] Figure 3 This is a schematic diagram showing the positional relationship of the various chip modules provided in this disclosure.

[0024] Figure 4 This is a flowchart illustrating another method for generating a scan pattern provided in this disclosure.

[0025] Figure 5 This is a flowchart illustrating another method for generating a scan pattern provided in this disclosure.

[0026] Figure 6 This is a flowchart illustrating yet another method for generating a scan pattern provided in this disclosure.

[0027] Figure 7 This is a structural block diagram of an apparatus for generating scanning patterns provided in this disclosure.

[0028] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in this disclosure. Detailed Implementation

[0029] The technical solutions in the embodiments of this disclosure will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure are within the scope of protection of this disclosure.

[0030] To facilitate understanding of the following embodiments, the core terms involved in this disclosure are described in detail herein:

[0031] DFT refers to a specialized design structure and method that embeds specific logic (such as scan chains) during the chip design phase to improve the testability of the chip after manufacturing.

[0032] EDA refers to the tools or field that use computer software to assist in the process of integrated circuit (IC) design, simulation, verification, and testing. This disclosure belongs to an automation tool in the EDA field.

[0033] In the context of this disclosure, the terms scan mode / scan block are synonymous, referring to dividing all chip modules (blocks) of a chip into several groups, each group corresponding to a test mode, and performing tests in groups. The goal of this disclosure is to automatically generate these "groups".

[0034] Total number of registers refers to the total number of scan registers included in a chip module.

[0035] Scan chain length refers to the average number of scan registers connected in series on each scan chain within a scan block (before compression).

[0036] Compression ratio refers to the ratio of the number of internal scan chains (before compression) to the number of pins connected to external channels (after compression) in scan compression technology.

[0037] The number of scan chains refers to the total number of scan chains within a chip module (before compression), which is equal to the ratio of the total number of registers to the corresponding scan chain length.

[0038] The total number of channels refers to the total number of I / O pins required when performing a scan mode test. It is the sum of the number of input channels and output channels of all chip modules included in the scan mode. The number of input channels and output channels of each chip module refers to the actual number of external I / O pins that a chip module (after compression) needs to connect to. The number of input channels is equal to the ratio of the number of scan chains to the compression ratio. The number of output channels is usually one-half to one-fifth of the number of input channels. The specific number can be adjusted according to the number of available I / Os. In this embodiment, it is set to one-half.

[0039] The method for generating scan patterns provided in this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] like Figure 1 As shown, this disclosure provides a method for generating a scan pattern. The following description uses an electronic device as an example to illustrate the method for generating a scan pattern provided by this disclosure. The method may include the following steps S101 to S103.

[0041] In step S101, chip project information is obtained.

[0042] Chip design information refers to the files necessary for generating the scan mode obtained from the chip design file. Chip project information includes the attribute information and available I / O of multiple chip modules. The attribute information of multiple chip modules includes the total number of registers of each chip module.

[0043] In step S102, based on attribute information and block allocation constraints, a target partitioning combination is determined to divide multiple chip modules into multiple scan blocks.

[0044] The partitioning process divides N (an integer greater than 1) chip modules into M (an integer greater than 1) scan blocks. M can be user-defined or adaptively determined based on constraints during the partitioning process.

[0045] Block allocation constraints refer to the constraints that must be followed when allocating various chip modules to scan blocks, as summarized in engineering practice. A backtracking algorithm can be used to find target partition combinations that satisfy these constraints. The target partition combination indicates the scan block to which each chip module is allocated. The backtracking algorithm is a depth-first search-based algorithm that recursively attempts to build a solution. When it finds that the current path violates the block allocation constraints, it "backtracks" (undoes the previous step) and tries the next possible path. The backtracking algorithm is merely an illustrative example of an embodiment of this disclosure and is not intended to limit the scope of this disclosure.

[0046] In some embodiments, the attribute information of the multiple chip modules includes: module hierarchy information between the multiple chip modules; block allocation constraints include: the top-level module included in the chip module is allocated to a single scan block.

[0047] The module hierarchy defines the parent-child relationships and overall structure between various chip modules. When determining the scan block for chip module iteration, if the chip module is the top-level module, an empty scan block is found and allocated to the top-level module.

[0048] The top-level module (also known as the parent node or root node), which is the top layer of the chip design, must be assigned to an independent scan block and cannot be grouped with any other sub-chip modules. In layered testing, the top-level logic needs to be isolated for testing to verify whether the cross-core connections and interactions are correct.

[0049] In some embodiments, the block allocation constraint further includes: there is no parent-child relationship between chip modules allocated to the same scan block.

[0050] This means that no chip module (other than the top-level module mentioned above) and its direct parent module should be placed in the same scan block. This constraint is crucial to ensuring the effectiveness of testing, because simultaneous testing of parent and child modules may introduce signal races, timing conflicts, or unpredictable logic states, leading to unreliable test results. Automating this check can avoid a common type of design error.

[0051] In some embodiments, the attribute information of the multiple chip modules further includes: the domain in which each chip module is located, the domain including at least one of a power domain and a clock domain; the block allocation constraint further includes: chip modules assigned to the same scan block belong to the same domain.

[0052] Chip modules assigned to the same scan block belong to the same power domain. Chip modules from different power domains are prohibited from being assigned to the same scan block to avoid power consumption issues during testing. Assigning chip modules from different power domains to the same scan block will result in a significant increase in power consumption.

[0053] Chip modules assigned to the same scan block belong to the same clock domain. Grouping them based on the clock domain of the chip modules can simplify the implementation of high-speed testing and avoid level conversion across power domains.

[0054] This embodiment introduces "domain constraints," enabling automated grouping to possess "power consumption awareness" and "clock awareness" capabilities. This allows for the automatic avoidance of mixing chip modules from different power domains or clock domains within the same scan block, thereby preventing cross-clock domain (CDC) timing issues or cross-power domain level transition issues that may occur during DFT testing. This significantly improves the robustness and automation of DFT design.

[0055] In some embodiments, the attribute information of the multiple chip modules further includes: the physical location of each chip module; the block allocation constraint further includes: the distance between the physical locations of any two chip modules assigned to the same scan block is less than a distance threshold.

[0056] The constraint based on the physical location of chip modules on the chip layout aims to ensure that chip modules within the same scan block are close together, thereby minimizing the routing overhead of the scan chain. By introducing "physical location constraints," automated grouping gains "physical awareness" capabilities. In DFT implementation, scan chains within the same scan block require physical routing connections. Grouping physically adjacent modules into the same group can significantly shorten the bus length of DFT routing, reduce routing congestion, and improve timing issues in the scan chain.

[0057] For example, the chip project information includes the contents shown in Table 1.

[0058] Table 1 Chip Project Information

[0059]

[0060] like Figure 2 As shown in the figure, which corresponds to Table 1, the tree structure diagram of each chip module is shown. It can be clearly seen from the tree structure diagram that the parent modules of chip module 1, chip module 3, chip module 4, and chip module 6 are the top-level modules, and any one of them has a parent-child relationship with the top-level module. The parent module of chip module 2 is chip module 1, and there is a parent-child relationship between the two. The parent module of chip module 5 is chip module 4, and there is a parent-child relationship between the two. The parent module of chip module 7 is chip module 6, and there is a parent-child relationship between the two.

[0061] like Figure 3 The diagram shows the positional relationship between the top-level module and chip modules 1 to 7. The inclusion between rectangles indicates a parent-child relationship, such as chip module 1 being the parent module of chip module 2. The position of the rectangles on the top-level module also represents the positional relationship between the various chip modules.

[0062] It should be noted that the content included in the above block allocation constraints is not intended to be limiting. In practical applications, users can modify the content of the block allocation constraints according to their actual needs, or select some or all of the constraints in the above embodiments. This disclosure does not limit this.

[0063] In step S103, based on the number of available I / Os and the total number of registers included in each chip module, the target scan chain length and target compression ratio of each scan block that meets the scan parameter constraints under the target partitioning combination are determined.

[0064] Available I / O count refers to the number of I / O pins available for use on the chip. Scan parameter constraints mean that the total number of channels required for scanning a block must be less than or equal to the available I / O count, and the compression ratio must be less than or equal to the compression ratio threshold.

[0065] Since the total number of channels equals the sum of the number of input channels and the number of output channels, and the number of input channels equals the ratio of the number of scan chains to the compression ratio, while the number of output channels is half the number of input channels, and the number of scan chains equals the ratio of the total number of registers to the scan chain length, and since the total number of registers in each chip module within a scan block remains constant, changing the total number of channels requires modifying the compression ratio and the scan chain length. Therefore, determining the target scan chain length and target compression ratio for each scan block under the target partitioning combination, based on the available I / O quantity and the total number of registers in each chip module, can be understood as a parameter optimization process—that is, changing the scan chain length and compression ratio to ensure that each scan block satisfies the scan parameter constraints.

[0066] For any given scan block, determine the total number of registers in each chip module within that scan block. Randomly generate a scan chain length and compression ratio, and determine whether this scan chain length and compression ratio meet the scan parameter constraints. If they do, then determine this scan chain length and compression ratio as the target scan chain length and target compression ratio; otherwise, update the scan chain length and compression ratio until the scan parameter constraints are met, at which point the target scan chain length and target compression ratio are obtained.

[0067] In some feasible ways, the results of the scanned block partitioning can be output. For example, Table 2 shows the scanned block partitioning results.

[0068] Table 2 Scan Block Division Results

[0069]

[0070] With 50 available I / Os and a compression ratio threshold of 200, Table 2 shows that the division of the scan blocks satisfies both the block division constraint and the scan parameter constraint.

[0071] In this embodiment, firstly, based on preset block allocation constraints, multiple chip modules are divided into multiple scan blocks, achieving automated partitioning of scan blocks that meets engineering practice requirements. Secondly, for each scan block, scan parameter constraints ensure that the compression ratio of each scan block meets design requirements, and the total number of channels is less than the number of available I / Os of the chip (meeting physical constraints), thus making it physically feasible. In summary, this embodiment can simultaneously solve the balance problem between logical constraints (block allocation constraints) and physical constraints (scan parameter constraints), thereby automatically, quickly, and accurately generating a logically valid and physically feasible scan block partitioning scheme. Compared to relying on the personal experience of DFT engineers, this greatly reduces the technical threshold of DFT design, improves design efficiency, and significantly shortens the chip development cycle.

[0072] To ensure that the target partitioning combination is optimal while satisfying block allocation constraints, in some embodiments, such as... Figure 4 As shown, the method for generating a scan pattern includes the following steps S401 to S405.

[0073] In step S401, chip project information is obtained.

[0074] In step S402, multiple candidate partitioning combinations are determined based on attribute information and block allocation constraints.

[0075] In step S403, a balance metric is determined for each candidate partition combination.

[0076] In step S404, the candidate partitioning combination corresponding to the minimum balance metric is determined as the target partitioning combination.

[0077] Specifically, N chip modules are assigned to M scan blocks. The chip modules are sequentially divided into scan blocks that satisfy the block allocation constraints. During this process, there may be more than one scan block that satisfies the block allocation constraints. For example, if chip module 1 is assigned to scan block 1 and also to scan block 2, then any one of the scan blocks can be selected. This process continues until all chip modules are assigned, resulting in a candidate partitioning combination. Each candidate partitioning combination represents a partitioning method of the scan modules that satisfies the block allocation constraints. By traversing all partitioning methods of the scan modules that satisfy the block allocation constraints, multiple candidate partitioning combinations are obtained.

[0078] The balance metric is used to indicate whether the load on each scanning module is balanced. In some implementations, the balance metric can be calculated for each candidate partition combination as follows:

[0079] First, determine an ideal average value, which is equal to the average number of registers in all chip modules. For example, if the number of scan modules under a certain candidate partitioning combination is p, and the number of registers included in all chip modules in the chip is q, then the ideal average value is q / p.

[0080] Then, the sum of differences for the candidate partition combination is calculated. This sum of differences is equal to the sum of the absolute values ​​of the differences between the total number of registers in each scan module and the ideal average value. For example, if the total number of registers in scan module 1 is S1, the total number of registers in scan module 2 is S2, and so on, and the total number of registers in scan module p is Sp, then the sum of differences is: The sum of these differences can be used as a balance measure for candidate partitioning combinations; the smaller the value, the more balanced the grouping scheme.

[0081] The scan test time is primarily determined by the length of the longest scan chain in each scan mode. By balancing the total number of registers in each scan mode, the scan chain length can be indirectly balanced. Furthermore, load balancing grouping can be directly translated into approximately equal test times for each scan mode, thus making the test plan more uniform and predictable.

[0082] In step S405, based on the number of available I / Os and the total number of registers included in each chip module, the target scan chain length and target compression ratio of each scan block that meets the scan parameter constraints under the target partitioning combination are determined.

[0083] It should be noted that the descriptions of steps S401 and S405 can be found in steps S101 and S103 above, and will not be repeated here.

[0084] In some embodiments, to ensure that the target partitioning combination is optimal while satisfying block allocation constraints, in some embodiments, such as Figure 5 As shown, the method for generating a scan pattern includes the following steps S501 to S505.

[0085] In step S501, chip project information is obtained.

[0086] In step S502, based on attribute information and block allocation constraints, a target partitioning combination is determined to divide multiple chip modules into multiple scan blocks.

[0087] In step S503, candidate combinations of various scan chain lengths and compression ratios are determined.

[0088] Among them, the various candidate combinations include different scan chain lengths or compression ratios, and the compression ratio is less than the compression ratio threshold. That is, the compression ratios in the candidate combinations all satisfy the compression ratio constraints in the scan parameter constraints.

[0089] In step S504, based on the total number of registers of each chip module included in each scan block, the total number of channels of all chip modules corresponding to each candidate combination under the target partitioning combination is determined.

[0090] In step S505, the scan chain length and compression ratio of candidate combinations whose total number of channels is less than or equal to the number of available I / O are determined as the target scan chain length and target compression ratio.

[0091] One possible approach is to randomly generate a variety of candidate combinations of scan chain length and compression ratio, such as 1000, and then search for candidate combinations that satisfy the scan parameter constraints from the 1000 candidate combinations. When any candidate combination satisfies the scan parameter constraints, there is no need to verify subsequent candidate combinations. The scan chain length and compression ratio in that candidate combination are determined as the final target scan chain length and target compression ratio.

[0092] However, the above implementation lacks verification patterns, and finding candidate combinations that satisfy the scan parameter constraints may be time-consuming. In other feasible methods, a baseline value for the scan chain length and a baseline value for the compression ratio are determined. The baseline value for the scan chain length is a smaller value summarized from engineering experience, such as 50, and the baseline value for the compression ratio is also a smaller value, such as 10. Candidate combinations that satisfy the scan parameter constraints are determined through two nested loops. In the outer loop, the scan chain length increases by the first step length based on the baseline value for the scan chain length. In the inner loop, the compression ratio increases by the second step length based on the baseline value for the compression ratio. For example, if the baseline value for the scan chain length is 50, the first step length is 50, the baseline value for the compression ratio is 10, the second step length is 5, and the compression ratio threshold is 200. In the first loop, the scan chain length in the candidate group combination is 50, and the compression rate is 10. Under the target partition combination, the input and output channels corresponding to each chip module included in each scan block are determined. Then, the sum of all input and output channels included in each scan block is calculated, which is the total number of channels. It is determined whether the total number of channels is less than or equal to the number of available I / Os. If yes, the loop is exited, and the target scan chain length is determined to be 50, and the target compression rate is 10. Otherwise, the inner loop is updated, that is, the compression rate is updated to 10 + 5 = 15. In the second loop, the scan chain length in the candidate group combination is 50, and the compression rate is 15. It is determined whether the total number of channels is less than or equal to the number of available I / Os. If yes, the loop is exited, and the target scan chain length is determined to be 50, and the target compression rate is 15. Otherwise, the inner loop continues. If the compression ratio has been increased to 200, meaning that the scan chain length in the candidate combination is 50, and the total number of channels is still greater than the number of available I / Os when the compression ratio is 200, then the next outer loop is executed, updating the scan chain length to 50+50=100. At this point, the inner loop continues to be executed, with the compression ratio successively set to 10, 15, 20, and so on. This outer and inner loops are performed in this way to find candidate combinations that make the total number of channels less than or equal to the number of available I / Os.

[0093] Furthermore, the parameters of the outer and inner loops can be interchanged; that is, the inner loop increments the scan chain length sequentially, while the outer loop increments the compression ratio sequentially. The specific implementation process is similar and will not be elaborated here. This directional parameter lookup process can effectively shorten the time required to determine the target scan chain length and target compression ratio.

[0094] It should be noted that the descriptions of steps S501 and S502 can be found in steps S101 and S102 above, and will not be repeated here.

[0095] To maximize the utilization of available I / O, in some embodiments, such as Figure 6 As shown, the method for generating a scan pattern includes the following steps S601 to S605.

[0096] In step S601, chip project information is obtained.

[0097] In step S602, based on attribute information and block allocation constraints, a target partitioning combination is determined to divide multiple chip modules into multiple scan blocks.

[0098] In step S603, candidate combinations of scan chain length and compression ratio are determined.

[0099] Among them, the various candidate combinations include different scan chain lengths or compression ratios, and the compression ratio is less than the compression ratio threshold. That is, the compression ratios in the candidate combinations all satisfy the compression ratio constraints in the scan parameter constraints.

[0100] In step S604, based on the total number of registers of each chip module included in each scan block, the total number of channels of all chip modules corresponding to each candidate combination under the target partitioning combination is determined.

[0101] In step S605, the scan chain length and compression ratio of the candidate combinations whose total number of channels is less than or equal to the number of available I / Os and whose difference between the total number of channels and the number of available I / Os is the smallest are determined as the target scan chain length and target compression ratio.

[0102] For multiple candidate combinations where the total number of channels is less than or equal to the number of available I / Os, the scan chain length and compression ratio of the candidate combination whose total number of channels is closest to the number of available I / Os are determined as the target scan chain length and target compression ratio. This allows as many available I / O pins as possible to be used as scan channels, enabling more scan chain data to be moved in / out in parallel at the same time, thereby significantly reducing the time required to load each test vector.

[0103] Figure 7 This is a structural block diagram of an apparatus for generating a scanning pattern disclosed herein, such as... Figure 7 As shown, it includes:

[0104] The acquisition section 701 is configured to acquire chip project information, which includes attribute information and available I / O counts for multiple chip modules. The attribute information for multiple chip modules includes the number of registers in each chip module. The determination section 702 is configured to determine a target partitioning combination that divides multiple chip modules into multiple scan blocks based on the attribute information and block allocation constraints. It is also configured to determine the target scan chain length and target compression ratio of each scan block that satisfies the scan parameter constraints under the target partitioning combination, based on the available I / O counts and the total number of registers included in each chip module.

[0105] In some embodiments, the determining part 702 is configured to determine multiple candidate partitioning combinations based on attribute information and block allocation constraints; determine a balance metric for each candidate partitioning combination; and determine the candidate partitioning combination corresponding to the minimum balance metric as the target partitioning combination.

[0106] In some embodiments, the determining part 702 is configured to determine a variety of candidate combinations of scan chain lengths and compression ratios, wherein the scan chain lengths or compression ratios included in the various candidate combinations are different, and the compression ratio in each candidate combination is less than or equal to a compression ratio threshold; based on the total number of registers of each chip module included in each scan block, determine the total number of channels of all chip modules corresponding to each candidate combination under the target partitioning combination; and determine the scan chain lengths and compression ratios included in the candidate combinations whose total number of channels is less than or equal to the number of available I / Os as the target scan chain length and target compression ratio.

[0107] In some embodiments, the determining portion 702 is configured to determine the scan chain length and the compression ratio of the candidate combinations whose total number of channels is less than or equal to the number of available I / Os and whose difference between the total number of channels and the number of available I / Os is minimal, as the target scan chain length and the target compression ratio.

[0108] In some embodiments, the attribute information of the multiple chip modules includes: module hierarchy information between the multiple chip modules; block allocation constraints include: the top-level module included in the chip module is allocated to a single scan block.

[0109] In some embodiments, the block allocation constraint further includes: there is no parent-child relationship between chip modules allocated to the same scan block.

[0110] In some embodiments, the attribute information of the multiple chip modules further includes: the domain in which each chip module is located, the domain including at least one of a power domain and a clock domain; the block allocation constraint further includes: chip modules assigned to the same scan block belong to the same domain.

[0111] In some embodiments, the attribute information of the multiple chip modules further includes: the physical location of each chip module; the block allocation constraint further includes: the distance between the physical locations of any two chip modules assigned to the same scan block is less than a distance threshold.

[0112] In this embodiment, each part can implement the method for generating scanning patterns provided in the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0113] Please refer to Figure 8This illustration shows a schematic diagram of the hardware structure of an electronic device provided in an exemplary embodiment of the present disclosure. The electronic device may be a specific instance of an EDA workstation, and is a hardware entity that performs the method for generating scan patterns described above in this disclosure.

[0114] like Figure 8 As shown, this electronic device typically includes one or more processors 810, a memory 820, an input unit 830, and an output unit 840, which are interconnected via one or more communication buses 850. Those skilled in the art will understand that... Figure 8 The structure shown is for illustrative purposes only. Electronic devices may include more or fewer components than those shown, such as network interfaces, various sensors, etc.

[0115] The processor 810 may be at least one of the following hardware forms: a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a digital signal processing unit (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA).

[0116] In this embodiment, the processor 810 serves as the core of the EDA workstation, and its functions can be highly complex. The CPU can be used to handle the operation of the operating system (e.g., Linux, Windows), the interactive logic of the user interface, and the overall scheduling of the algorithms disclosed herein. The GPU can be used to render complex chip layout views or the graphical user interface of EDA tools, enabling users to intuitively view and modify scan blocks and block allocation constraints. The NPU can be used to perform more advanced EDA tasks based on machine learning, such as predictive placement and routing or power analysis.

[0117] The processor 810 connects various parts within the electronic device using various interfaces and lines, and performs the steps of the method for generating scan patterns as described in this disclosure by running or executing programs or instructions stored in the memory 820 and calling data stored in the memory 820.

[0118] Memory 820 may be used to store programs or instructions. Memory 820 may include volatile memory, such as random access memory (RAM), or non-volatile memory (non-transitory computer-readable storage medium), such as read-only memory (ROM), hard disk drive (HDD), or solid-state drive (SSD).

[0119] The memory 820 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system and instructions for at least one function. The data storage area may store data created based on the use of the electronic device.

[0120] In this embodiment, the application program is the software implementation of the method and corresponding tool for generating scan patterns provided in this disclosure. It includes a series of computer programs or instructions, and the chip design file corresponding to the chip project data.

[0121] When the electronic device is powered on, the program or instructions in the application are loaded into the processor 810. The processor 810 reads chip item data, such as obtaining chip item information, and executes the instructions in the application to implement the various steps of the method for generating the scan pattern described above.

[0122] The input unit may include a keyboard, mouse, touchpad, etc., for DFT engineers to input commands or load design files. The output unit may include a monitor, printer, etc., for displaying the scan block division results generated by this disclosure to the DFT engineer.

[0123] This disclosure also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program or instructions that, when executed by a processor (e.g., processor 810), implement the steps of the method for generating a scan pattern as described above.

[0124] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the method for generating scan patterns as described in the above embodiments.

[0125] This disclosure also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described method embodiments for generating scanning patterns, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0126] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0127] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, servers, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0128] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0130] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0131] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0132] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0133] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for generating a scanning pattern, characterized in that, The method for generating the scanning pattern includes: Obtain chip project information, which includes attribute information and the number of available input / output I / Os for multiple chip modules. The attribute information of the multiple chip modules includes the total number of registers for each chip module, the module hierarchy information between the multiple chip modules, and the domain in which each chip module is located, including at least one of the power domain and the clock domain. Based on the attribute information and block allocation constraints, a target partitioning combination is determined to divide the multiple chip modules into multiple scanning blocks. The block allocation constraints include: the top-level module included in the chip module is allocated to a single scanning block, there is no parent-child relationship between chip modules allocated to the same scanning block, and chip modules allocated to the same scanning block belong to the same domain. Based on the number of available I / Os and the total number of registers included in each chip module, the target scan chain length and target compression ratio of each scan block that meets the scan parameter constraints under the target partitioning combination are determined.

2. The method for generating a scanning pattern according to claim 1, characterized in that, The step of determining the target partitioning combination for dividing the multiple chip modules into multiple scan blocks based on the attribute information and block allocation constraints includes: Based on the attribute information and block allocation constraints, multiple candidate partitioning combinations are determined; Determine the balance metric for each candidate partition combination; The candidate partition combination corresponding to the minimum balance metric is determined as the target partition combination.

3. The method for generating a scanning pattern according to claim 1, characterized in that, The step of determining the target scan chain length and target compression ratio of each scan block satisfying the scan parameter constraints under the target partitioning combination, based on the number of available I / Os and the total number of registers included in each chip module, includes: Determine multiple candidate combinations of scan chain length and compression ratio. Each candidate combination includes different scan chain lengths or compression ratios, and the compression ratio in each candidate combination is less than or equal to a compression ratio threshold. Based on the total number of registers of each chip module included in each scan block, determine the total number of channels of all chip modules corresponding to each candidate combination under the target partitioning combination; The scan chain length and compression ratio of candidate combinations whose total number of channels is less than or equal to the number of available I / Os are determined as the target scan chain length and target compression ratio.

4. The method for generating a scanning pattern according to claim 3, characterized in that, The step of determining the target scan chain length and target compression ratio as the scan chain length and compression ratio of candidate combinations whose total number of channels is less than or equal to the number of available I / Os includes: The candidate combinations whose total number of channels is less than or equal to the number of available I / Os, and whose difference between the total number of channels and the number of available I / Os is the smallest, are determined as the target scan chain length and target compression ratio.

5. The method for generating a scanning pattern according to claim 1, characterized in that, The attribute information of the multiple chip modules also includes: the physical location of each chip module; The block allocation constraint also includes: the physical distance between any two chip modules assigned to the same scan block is less than a distance threshold.

6. An apparatus for generating a scanning pattern, characterized in that, The apparatus for generating the scan pattern includes: The acquisition section is configured to acquire chip project information, which includes attribute information and the number of available input / output I / Os for multiple chip modules. The attribute information of the multiple chip modules includes the total number of registers for each chip module, the module hierarchy information between the multiple chip modules, and the domain in which each chip module is located, including at least one of a power domain and a clock domain. The determination part is configured to determine a target partitioning combination to divide the multiple chip modules into multiple scan blocks based on the attribute information and block allocation constraints. The block allocation constraints include: the top-level module included in the chip module is allocated to a scan block alone; there is no parent-child relationship between chip modules allocated to the same scan block; and chip modules allocated to the same scan block belong to the same domain. Furthermore, based on the number of available I / Os and the total number of registers included in each chip module, the target scan chain length and target compression ratio of each scan block satisfying the scan parameter constraints under the target partitioning combination are determined.

7. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method for generating a scan pattern as described in any one of claims 1 to 5.

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