High trench density igbt

Abstract

The application provides an IGBT with high trench density. In the IGBT, a plurality of gate trenches are arranged in a substrate and extend in parallel on the top surface of the substrate, a gate electrode fills in the gate trenches and extends along the extending direction of the gate trenches, a plurality of emitter contact holes are arranged on the substrate, each of the emitter contact holes crosses the plurality of gate trenches and is partially embedded in the gate trenches, the partial bottom surface of the emitter contact hole is located on the substrate surface between two adjacent gate trenches, the gate electrode comprises a lower concave part and an upper convex part connected with each other, the lower concave part overlaps with the emitter contact hole, an emitter metal fills in the plurality of emitter contact holes and is electrically connected with the substrate between the gate trenches, and an isolation dielectric layer is located between the emitter metal and the gate electrode and covers the top surface of the gate electrode. The design that the emitter contact hole intersects with the gate trench can reduce the alignment accuracy requirement of the emitter contact hole, is favorable for reducing the process difficulty of the IGBT and improving the product yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an IGBT with high trench density. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) combines the voltage control of MOS and the conductance modulation current of BJT, featuring high input impedance, low switching losses, high speed, and low voltage drive power. It is widely used in power transmission and transformation, high-speed train traction, industrial drives, clean energy, and many other fields. Due to its inherent high voltage and high current characteristics, IGBTs have undergone continuous power dissipation reduction with each generation to improve energy conversion efficiency. This involves decreasing cell pitch, reducing channel length, and increasing channel density to reduce chip area and power consumption. However, this also significantly increases the difficulty of fabrication.

[0003] Figure 1 This is a planar layout diagram of an existing IGBT. (For example...) Figure 1 As shown, in this IGBT, the gate trench 101 and the emitter contact hole 102 are arranged in parallel, with the emitter contact hole 102 disposed between the gate trench 101. If the emitter contact hole 102 is offset perpendicular to the gate trench during photolithography ( Figure 1 This manifests as a slight offset of the emitter contact hole 102 (left or right). Uneven current distribution occurs on both sides of the emitter contact hole 102. If the offset is significant, the emitter metal will short-circuit with the gate electrode 201, causing the device to malfunction. In IGBTs with larger cell pitches, current equipment alignment accuracy can meet the device performance consistency requirements, and this offset is acceptable. However, as the density of the gate trench on the front side of the IGBT gradually increases, especially when the cell pitch is less than 2.0μm, the mesa area narrows, the emitter contact hole becomes smaller, and as the wafer size gradually increases, warpage caused by wafer stress becomes commonplace. Existing equipment alignment capabilities and wafer warpage control capabilities are insufficient to solve the contact hole alignment problem, resulting in high process difficulty and making it difficult to meet the high yield requirements of high-density trench IGBTs. Summary of the Invention

[0004] One of the objectives of this invention is to solve the contact hole alignment problem of IGBTs with high trench density, reduce the manufacturing difficulty of IGBTs, and improve product yield.

[0005] To achieve the above objectives, the present invention provides a high trench density IGBT. The high trench density IGBT includes: a substrate; a plurality of gate trenches disposed in the substrate and extending parallel to the top surface of the substrate; a plurality of gate electrodes, one gate electrode filling one of the gate trenches and extending along the direction of the gate trench extension; a plurality of emitter contact holes disposed on the substrate, each emitter contact hole spanning the plurality of gate trenches and partially embedded within the gate trenches, a portion of the bottom surface of the emitter contact hole located on the substrate surface between two adjacent gate trenches; the gate electrode includes a connected recess and a raised portion, the top surface of the recess being lower than the top surface of the raised portion, and the recess overlapping with the emitter contact holes; an emitter metal covering the top surface of the substrate and filling the plurality of emitter contact holes, the emitter metal being electrically connected to the substrate between the gate trenches; and an isolation dielectric layer located between the emitter metal and the gate electrode and covering the top surface of the gate electrode.

[0006] Optionally, a body doped region of a second conductivity type is formed in the substrate between two adjacent gate trenches, the body doped region extending along the direction of the gate trench extension; a first doped region of a first conductivity type is formed on the top of the substrate between two adjacent emitter contact holes, the first conductivity type being opposite to the second conductivity type, the first doped region being located above the body doped region and being in contact with the body doped region, the first doped region at least partially overlapping the upper protrusion of the gate electrode in the vertical direction of the gate electrode extension; the emitter metal is electrically connected to the first doped region.

[0007] Optionally, the emitter metal is in contact with the sidewall of the first doped region; or, the emitter metal is in contact with the top surface of the first doped region; or, the emitter metal is in contact with both the top surface and the sidewall of the first doped region.

[0008] Optionally, the first doped region covers the top surface of the substrate between two adjacent emitter contact holes; or, the top surface of the substrate between two adjacent emitter contact holes has two first doped regions, the bulk doped region separates the two first doped regions, and the two first doped regions are respectively located close to the two adjacent emitter contact holes.

[0009] Optionally, a second doped region of a second conductivity type is formed in the substrate of the overlapping region between the bulk doped region and the emitter contact hole. The second doped region is located above the bulk doped region and its bottom surface is in contact with the bulk doped region. The doping concentration of the second doped region is higher than that of the bulk doped region. The second doped region is electrically connected to the emitter metal.

[0010] Optionally, the isolation dielectric layer further covers at least a portion of the top surface of the first doped region, and the emitter metal covers the isolation dielectric layer above the first doped region.

[0011] Optionally, a carrier storage layer is further formed in the substrate, the carrier storage layer being located below the bulk doped region and the top surface of the carrier storage layer being in contact with the bulk doped region.

[0012] Optionally, the emitter contact hole has a first portion that overlaps with the gate trench and a second portion located on the side of the gate trench, wherein the bottom surface of the first portion is higher than the bottom surface of the second portion, or the bottom surfaces of the first portion and the second portion are flush.

[0013] Optionally, the high trench density IGBT further includes: a dummy gate trench disposed in the substrate and arranged on the side of the gate trench, wherein the extension direction of the dummy gate trench on the top surface of the substrate is the same as the extension direction of the gate trench; a dummy gate filling the dummy gate trench and extending along the extension direction of the dummy gate trench; wherein the emitter contact hole also spans the dummy gate trench, and the emitter metal is electrically connected to the dummy gate.

[0014] Optionally, a plurality of pseudo-gate trenches are formed in the substrate, and a pseudo-gate is disposed in each pseudo-gate trench; a plurality of pseudo-gate trenches are grouped together, and a plurality of gate trenches are grouped together, with the pseudo-gate trench groups and gate trench groups arranged alternately on the substrate.

[0015] Optionally, the substrate has a collector region of a second conductivity type, a buffer layer of a first conductivity type, and a drift region of a first conductivity type stacked from bottom to top, wherein the doping concentration of the buffer layer is greater than the doping concentration of the drift region, and the gate trench is formed above the drift region.

[0016] Optionally, the width of the recess is greater than the width of the emitter contact hole.

[0017] Optionally, the width of the emitter contact hole is greater than the spacing between two adjacent gate trenches.

[0018] Optionally, the spacing between the center lines of two adjacent gate trenches is less than 2 μm.

[0019] In the high trench density IGBT provided by the present invention, multiple gate trenches extend parallel to each other on the top surface of the substrate. Each emitter contact hole spans multiple gate trenches and is partially embedded in the gate trenches. Part of the bottom surface of the emitter contact hole is located on the substrate surface between two adjacent gate trenches. The gate electrode in the gate trench includes a concave portion and a convex portion connected to each other. The top surface of the concave portion is lower than the top surface of the convex portion. The concave portion overlaps with the emitter contact hole. The emitter metal covers the top surface of the substrate and fills multiple emitter contact holes. The emitter metal is electrically connected to the substrate. This design, where the emitter contact hole intersects with the gate trench, ensures that even if the emitter contact hole shifts, the emitter metal within the contact hole can easily connect electrically to the substrate between the gate trench and the emitter metal. This reduces the alignment accuracy requirements of the emitter contact hole, thus lowering the difficulty of the contact hole alignment process and the overall IGBT manufacturing process. Furthermore, the shift in the emitter contact hole does not affect the uniformity of the current distribution of the emitter metal, which is beneficial for improving IGBT consistency and product yield. In addition, the gate electrode includes a recessed portion that overlaps with the emitter contact hole. This recessed portion provides vertical space for the isolation dielectric layer, facilitating the placement of an isolation dielectric layer between the emitter metal within the contact hole and the gate electrode. This prevents short circuits between the gate electrode and the emitter metal, ensuring normal IGBT operation and improving yield. Attached Figure Description

[0020] Figure 1 This is a planar layout diagram of an existing IGBT.

[0021] Figure 2 This is a planar layout diagram of a high trench density IGBT provided in an embodiment of the present invention.

[0022] Figure 3 This is a three-dimensional cross-sectional view of a high trench density IGBT provided in an embodiment of the present invention.

[0023] Figure 4 A high trench density IGBT edge provided in an embodiment of the present invention Figure 3 A cross-sectional view of the location indicated by the AA'A”A”' line.

[0024] Figure 5 A high trench density IGBT edge provided in an embodiment of the present invention Figure 3 A cross-sectional view of the location indicated by the BB'B”B”' line.

[0025] Figure 6 A high trench density IGBT edge provided in an embodiment of the present invention Figure 3 A cross-sectional view of the location indicated by the CC'C"C"' line.

[0026] Figure 7Another embodiment of the present invention provides a high trench density IGBT edge Figure 3 A cross-sectional view of the location indicated by the AA'A”A”' line.

[0027] Figure 8 Another embodiment of the present invention provides a high trench density IGBT edge Figure 3 A cross-sectional view of the location indicated by the BB'B”B”' line.

[0028] Figure 9 Another embodiment of the present invention provides a high trench density IGBT edge Figure 3 A cross-sectional view of the location indicated by the CC'C"C"' line.

[0029] Figure 10 A perspective cross-sectional view of a high trench density IGBT provided for another embodiment of the present invention.

[0030] Figure 11 This is a perspective cross-sectional view of an IGBT with a high trench density having a carrier storage layer, provided in an embodiment of the present invention.

[0031] Figure 12 This is a planar layout diagram of a high trench density IGBT provided for another embodiment of the present invention.

[0032] Explanation of reference numerals in the attached figures: 100-substrate; 101-gate trench; 102-emitter contact hole; 103-body doped region; 104-first doped region; 105-second doped region; 106-collector region; 107-buffer layer; 108-drift region; 109-carrier storage layer; 201-gate electrode; 201a-recess; 201b-protrusion; 202-emitter metal; 203-isolation dielectric layer; 204-gate oxide layer; 205-collector metal; 300a-gate trench group; 300b-dummy gate trench group; 301-dummy gate trench; 302-dummy gate. Detailed Implementation

[0033] The high trench density IGBT proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0034] Figure 2 This is a planar layout diagram of a high trench density IGBT provided in an embodiment of the present invention. Figure 3 This is a perspective cross-sectional view of a high trench density IGBT provided according to an embodiment of the present invention. Figure 2 and Figure 3As shown, the high trench density IGBT provided in this embodiment includes a substrate 100, a plurality of gate trenches 101, a plurality of gate electrodes 201, a plurality of emitter contact holes 102, an emitter metal 202, and an isolation dielectric layer 203. The plurality of gate trenches 101 are disposed in the substrate 100 and extend parallel to each other on the top surface of the substrate 100. One gate electrode 201 fills one gate trench 101, and the gate electrode 201 extends along the direction of the gate trench 101. The plurality of emitter contact holes 102 are disposed on the substrate 100, each emitter contact hole 102 spanning the plurality of gate trenches 101 and partially embedded within the gate trenches 101, with a portion of the bottom surface of the emitter contact hole 102 located on the substrate surface between two adjacent gate trenches 101. The gate electrode 201 includes a recessed portion 201a and an upper protrusion 201b connected to each other. The top surface of the recessed portion 201a is lower than the top surface of the upper protrusion 201b, and the recessed portion 201a overlaps with the emitter contact hole 102. The emitter metal 202 covers the top surface of the substrate 200 and fills the plurality of emitter contact holes 102. The emitter metal 202 is electrically connected to the substrate between the gate trench 101 and the substrate. An isolation dielectric layer 203 is located between the emitter metal 202 and the gate electrode 201 and covers the top surface of the gate electrode 201.

[0035] Specifically, the substrate 100 can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc., and certain doping particles can be injected into the semiconductor substrate to change the electrical parameters according to design requirements.

[0036] A plurality of gate trenches 101 are spaced apart on the top of the substrate 100, and the plurality of gate trenches 101 extend parallel to each other on the top surface of the substrate 100. For example, the plurality of gate trenches 101 all extend along the Y direction.

[0037] In this embodiment, the density of gate trenches 101 on the substrate 100 is high, and the spacing between the center lines of two adjacent gate trenches 101 is less than 2μm, that is, the cell pitch of the IGBT is less than 2μm, but it is not limited to this.

[0038] Emitter contact holes 102 are disposed on substrate 100. Each emitter contact hole 102 extends along the X direction and spans multiple gate trenches 101. A portion of the emitter contact hole 102 is embedded in the gate trench 101, and a portion of the bottom surface of the emitter contact hole 102 is located on the substrate surface between two adjacent gate trenches 101.

[0039] It should be noted that the reference Figure 1As shown, in the prior art, the emitter contact hole 102 is disposed between adjacent gate trenches 101. The width design of the emitter contact hole 102 is limited by the spacing between the gate trenches 101. The width of the emitter contact hole 102 must be smaller than the spacing between the gate trenches 101, making the alignment of the small-width emitter contact hole 102 difficult. In this application, reference... Figure 2 As shown, the emitter contact hole 102 is designed to intersect with the gate trench 101. The width of the emitter contact hole 102 is not limited by the spacing between the gate trenches 101. The width W1 of the emitter contact hole 102 can be greater than the spacing W2 between two adjacent gate trenches 101. That is, the width W1 of the emitter contact hole 102 can be greater than the width of the mesa, thereby improving the alignment accuracy of the emitter contact hole 102 and reducing the difficulty of IGBT process.

[0040] The gate electrode 201 fills the gate trench 101 and extends along the direction of extension of the gate trench 101 (i.e., the Y direction). The gate electrode 201 includes a concave portion 201a and a convex portion 201b connected to each other. The top surface of the concave portion 201a is lower than the top surface of the convex portion 201b, that is, the concave portion 201a is recessed relative to the convex portion 201b. The concave portion 201a overlaps with the emitter contact hole 102. Exemplarily, the material of the gate electrode 201 includes, but is not limited to, polysilicon.

[0041] A gate oxide layer 204 is disposed between the gate trench 101 and the gate electrode 201, and the gate oxide layer 204 covers the inner surface of the gate trench 101. The material of the gate oxide layer 204 includes, but is not limited to, silicon oxide.

[0042] An isolation dielectric layer 203 is formed on the substrate 100, covering the top surface of the gate electrode 201 and filling the recess of the gate electrode recess 201. The thickness of the isolation dielectric layer 203 above the recess 201a is greater than the thickness of the isolation dielectric layer 203 above the protrusion 201b. The portion of the gate electrode 201 overlapping with the emitter contact hole 102 is recessed, providing longitudinal (i.e., Z-direction) space for the isolation dielectric layer 203, which helps to prevent short circuits between the emitter metal 202 and the gate electrode 201. The isolation dielectric layer 203 also covers a portion of the top surface of the substrate 100. Exemplarily, the material of the isolation dielectric layer 203 includes, but is not limited to, silicon oxide.

[0043] refer to Figure 2 and Figure 3 As shown, the width W3 of the recessed portion 201a of the gate electrode is greater than the width W1 of the emitter contact hole 102, thereby providing an isolation space for the gate electrode 201 and the emitter metal 202 in the Y direction. That is, an isolation medium can be provided between the sidewall of the emitter contact hole 102 and the sidewall of the protrusion 201b of the gate electrode to achieve isolation between the emitter metal 202 and the gate electrode 201.

[0044] Emitter metal 202 (i.e., Metal in the figure) covers the top surface of substrate 100 and fills multiple emitter contact holes 102. Emitter metal 202 is electrically connected to the substrate between the gate trench 101 and the emitter metal 202. The material of emitter metal 202 includes, but is not limited to, metals such as Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, or Al.

[0045] Figure 4 A high trench density IGBT edge provided in an embodiment of the present invention Figure 3 A cross-sectional view of the location indicated by the AA'A”A”' line. Figure 5 A high trench density IGBT edge provided in an embodiment of the present invention Figure 3 A cross-sectional view of the location indicated by the BB'B”B”' line. Figure 6 A high trench density IGBT edge provided in an embodiment of the present invention Figure 3 A cross-sectional view of the location indicated by the CC'C"C"' line.

[0046] refer to Figures 3 to 6 As shown, a body-doped region 103 of a second conductivity type is formed in the substrate between two adjacent gate trenches 101. The body-doped region 103 extends along the direction of the gate trench 101, for example, it extends along the Y direction. In this embodiment, the second conductivity type is P-type, and the body-doped region 103 is a P-type body region (Pbody). In other embodiments, the second conductivity type can be N-type.

[0047] refer to Figures 3 to 6 As shown, a first doped region 104 of a first conductivity type is formed on the top of the substrate between two adjacent emitter contact holes 102. The first conductivity type is opposite to the second conductivity type. For example, the first conductivity type is N-type, and the first doped region 104 is an N+ doped region, but it is not limited thereto. The first doped region 104 is located above the bulk doped region 103 and is in contact with the bulk doped region 103. The first doped region 104 at least partially overlaps with the upper protrusion 201b of the gate electrode 201 in the vertical direction of the extension direction of the gate electrode 201, that is, the first doped region 104 at least partially overlaps with the upper protrusion 201b of the gate electrode 201 in the X direction. The emitter metal 202 is in contact with and electrically connected to the first doped region 104.

[0048] In one embodiment of this application, reference is made to... Figures 4 to 6 The first doped region 104 covers the top surface of the substrate between two adjacent emitter contact holes 102, that is, the top of the substrate between two adjacent emitter contact holes 102 is entirely the first doped region 104, the top surface of the first doped region 104 is the top surface of the substrate 100, and the bottom surface of the first doped region 104 is connected to the top surface of the bulk doped region 103.

[0049] Figure 7 Another embodiment of the present invention provides a high trench density IGBT edge Figure 3 A cross-sectional view of the location indicated by the AA'A”A”' line. Figure 8 Another embodiment of the present invention provides a high trench density IGBT edge Figure 3 A cross-sectional view of the location indicated by the BB'B”B”' line. Figure 9 Another embodiment of the present invention provides a high trench density IGBT edge Figure 3 A cross-sectional view of the location indicated by the CC'C"C"' line.

[0050] In another embodiment of this application, reference is made to... Figures 7 to 9 The substrate top between two adjacent emitter contact holes 102 has two first doped regions 104, and a body doped region 103 separates the two first doped regions 104. The two first doped regions 104 are respectively located close to the two adjacent emitter contact holes 102 and electrically connected to the emitter metal 202, so that the bottom surface and one side surface of the first doped region 104 are in contact with the body doped region 103. Each first doped region 104 overlaps at least partially with the upper protrusion 201b of the gate electrode in the X direction. That is, the first doped region 104 can be segmented. This design enhances the latch-up resistance by shortening the width of the first doped region 104, improves the device's RBSOA (reverse bias safe operating area), and thus improves the device's performance.

[0051] It should be noted that existing technologies include designs that recess the entire gate electrode. However, considering the connection between the device channel and the N+ doped region, the upper surface of the gate electrode needs to be controlled within the N+ doped region in the vertical direction to ensure that the channel current can flow through the N+ doped region to the emitter. However, this introduces a new alignment problem, and this technology has extremely high requirements for etching processes, making the process difficult. In this embodiment, the gate electrode 201 adopts a partially recessed design, which can ensure that at least part of the channel is connected to the first doped region 104, and the channel corresponding to the recessed portion 201a can flow to the first doped region 104 along the contour direction of the recessed portion, reducing the difficulty of process implementation.

[0052] The isolation dielectric layer 203 also covers at least a portion of the top surface of the first doped region 104, and the emitter metal 202 covers the isolation dielectric layer 203 above the first doped region 104.

[0053] In some embodiments of this application, reference is made to Figures 4 to 9As shown, the emitter metal 202 contacts the sidewall of the first doped region 104. That is, when etching the isolation dielectric layer 203 and the substrate 100 to form the emitter contact hole 102, the first doped region 104 can be etched through, and at least one sidewall of the first doped region 104 is retained as the sidewall of the emitter contact hole 102. The isolation dielectric layer 203 covers the top surface of the first doped region 104. In other embodiments of this application, the emitter metal 202 may also contact the top surface of the first doped region 104, or the emitter metal 202 may also contact the top surface and sidewall of the first doped region 104, and the isolation dielectric layer 203 covers part of the top surface of the first doped region 104.

[0054] refer to Figures 3 to 9 As shown, a second doped region 105 of a second conductivity type is formed in the substrate where the bulk doped region 103 overlaps with the emitter contact hole 102. For example, the second doped region 105 is a P+ doped region. The second doped region 105 is located above the bulk doped region 103, and its bottom surface is in contact with the bulk doped region 103. The doping concentration of the second doped region 105 is higher than that of the bulk doped region 103. The second doped region 105 is in contact with and electrically connected to the emitter metal 202. (Reference) Figures 4 to 9 As shown, for example, the bottom surface of the emitter metal 202 in the emitter contact hole is in contact with the top surface of the second doped region 105 and is electrically connected to the second doped region 105.

[0055] refer to Figures 4 to 9 As shown, the second doped region 105 may also extend laterally below the first doped region 104, but is not limited thereto.

[0056] refer to Figure 3 As shown, in some embodiments of this application, the emitter contact hole 102 has a first portion overlapping with the gate trench 101 and a second portion located on the side of the gate trench 101. The bottom surface of the first portion of the emitter contact hole 102 is higher than the bottom surface of the second portion of the emitter contact hole 102, that is, the bottom surface of the emitter contact hole 102 is stepped. For example, the bottom surface of the first portion of the emitter contact hole 102 is the surface of the isolation dielectric layer in the gate trench 101, and the bottom surface of the second portion of the emitter contact hole 102 is the top surface of the second doped region 105.

[0057] Figure 10 A perspective cross-sectional view of a high trench density IGBT provided for another embodiment of the present invention.

[0058] refer to Figure 10As shown, the bottom surface of the first part of the emitter contact hole 102 that overlaps with the gate trench 101 is flush with the bottom surface of the second part of the gate trench 101, that is, the bottom surface of the emitter contact hole 102 is a plane, and the top surface of the isolation dielectric layer 203, the second doped region 105 and the gate oxide layer 204 on the bottom surface of the emitter contact hole 102 are flush.

[0059] refer to Figures 3 to 10 As shown, a collector region 106 of a second conductivity type, a buffer layer 107 of a first conductivity type, and a drift region 108 of a first conductivity type are stacked from bottom to top in the substrate 100. The collector region 106 is located at the bottom of the substrate 100. The doping concentration of the buffer layer 107 is greater than that of the drift region 108. A gate trench 101 is formed above the drift region 108. The buffer layer 107 is a field stop (FS) structure. A collector metal 205 is formed on the bottom surface of the substrate 100, and the collector metal 205 is electrically connected to the collector region 106.

[0060] Figure 11 This is a perspective cross-sectional view of an IGBT with a high trench density having a carrier storage layer, provided in an embodiment of the present invention.

[0061] refer to Figure 11 As shown, in some embodiments of this application, a carrier storage layer 109 is further formed in the substrate 100. The carrier storage layer 109 is located below the bulk doped region 103, and the top surface of the carrier storage layer 109 is in contact with the bulk doped region 103. Providing the carrier storage layer 109 below the bulk doped region 103 can improve carrier distribution and further improve the trade-off performance between the IGBT forward voltage drop and turn-off loss. More specifically, the carrier storage layer 109 is located between the drift region 108 and the bulk doped region 103. The top surface of the carrier storage layer 109 is in contact with the bulk doped region 103, and the bottom surface is in contact with the drift region 108. The conductivity type of the carrier storage layer 109 is N-type, opposite to that of the bulk doped region 103, and the doping concentration of the carrier storage layer 109 is greater than that of the drift region 108.

[0062] Figure 12 This is a planar layout diagram of a high trench density IGBT provided in another embodiment of the present invention. Figure 12As shown, in one embodiment of this application, the high trench density IGBT further includes a dummy gate trench 301 and a dummy gate 302. The dummy gate trench 301 is disposed in the substrate 100 and arranged on the side of the gate trench 101. The extension direction of the dummy gate trench 301 on the top surface of the substrate is the same as the extension direction of the gate trench 101; for example, both the dummy gate trench 301 and the gate trench 101 extend along the Y direction. The dummy gate 302 fills within the dummy gate trench 301 and extends along the extension direction of the dummy gate trench 301. The dummy gate 302 and the dummy gate trench 301 are isolated by a gate oxide layer. An emitter contact hole 102 also spans the dummy gate trench 301, and the emitter metal 202 within the emitter contact hole 102 is electrically connected to the dummy gate 302. The dummy gate 302 is not recessed but directly connected to the emitter metal 202.

[0063] It should be noted that setting a dummy gate 302 on the substrate 100 can reduce the current density of the device and improve the short-circuit characteristics of the IGBT. At the same time, the dummy gate changes the capacitive coupling of the chip, which can further refine the control of the waveform of the device switching process.

[0064] For example, the pseudo-gate trench 301 and the gate trench 101 can have the same depth.

[0065] refer to Figure 12 As shown, a plurality of dummy gate trenches 301 are formed in the substrate 100, and a dummy gate 302 is disposed in each dummy gate trench 301. Exemplarily, a plurality of dummy gate trenches 301 can be grouped together, and a plurality of gate trenches 101 can be grouped together. The dummy gate trench group 300b and the gate trench group 300a can be arranged alternately on the substrate. The number of dummy gate trenches 301 in the dummy gate trench group 300b and the number of gate trenches 101 in the gate trench group 300a can be the same, but are not limited thereto.

[0066] In the high trench density IGBT provided by the present invention, multiple gate trenches 101 extend parallel to each other on the top surface of the substrate 100. Each emitter contact hole 102 spans multiple gate trenches 101 and is partially embedded in the gate trenches 101. A portion of the bottom surface of the emitter contact hole 102 is located on the substrate surface between two adjacent gate trenches 101. The gate electrode 201 in the gate trench 101 includes a recessed portion 201a and an upper convex portion 201b connected to each other. The top surface of the recessed portion 201a is lower than the top surface of the upper convex portion 201b. The recessed portion 201a overlaps with the emitter contact hole 102. The emitter metal 202 covers the top surface of the substrate 100 and fills multiple emitter contact holes 102. The emitter metal 202 is electrically connected to the substrate between the gate trenches 101 and the emitter metal 202. This design, where the emitter contact hole 102 intersects with the gate trench 101, ensures that even if the emitter contact hole 102 shifts, the emitter metal 202 within it can easily connect to the substrate between the gate trench 101 and the emitter contact hole. This reduces the alignment accuracy requirements of the emitter contact hole 102, thus lowering the difficulty of the contact hole alignment process and the IGBT manufacturing process. Furthermore, the shift in the emitter contact hole does not affect the uniformity of the current distribution of the emitter metal within it, which is beneficial for improving IGBT consistency and product yield. In addition, the gate electrode 201 includes a recessed portion 201a that overlaps with the emitter contact hole 102. This recessed portion provides vertical space for the isolation dielectric layer 203, facilitating the placement of the isolation dielectric layer between the emitter metal 202 within the emitter contact hole and the gate electrode 201. This prevents short circuits between the gate electrode 201 and the emitter metal 202, ensuring normal IGBT operation and improving yield.

[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A high trench density IGBT, characterized in that, include: Base; Multiple gate trenches are disposed in the substrate and extend parallel to the top surface of the substrate; Multiple gate electrodes, one of which fills a gate trench and extends along the direction of the gate trench; Multiple emitter contact holes are disposed on the substrate, each emitter contact hole spans multiple gate trenches and is partially embedded in the gate trenches, and a portion of the bottom surface of the emitter contact hole is located on the substrate surface between two adjacent gate trenches; The gate electrode includes a concave portion and an convex portion connected to each other. The top surface of the concave portion is lower than the top surface of the convex portion, and the concave portion overlaps with the emitter contact hole. An emitter metal covers the top surface of the substrate and fills a plurality of the emitter contact holes, wherein the emitter metal is electrically connected to the substrate between the gate trench; as well as An isolation dielectric layer is located between the emitter metal and the gate electrode and covers the top surface of the gate electrode.

2. The high trench density IGBT as described in claim 1, characterized in that, A second conductivity type bulk doped region is formed in the substrate between two adjacent gate trenches, the bulk doped region extending along the direction of the gate trench extension; a first conductivity type first doped region is formed on the top of the substrate between two adjacent emitter contact holes, the first conductivity type being opposite to the second conductivity type, the first doped region being located above the bulk doped region and being in contact with the bulk doped region, the first doped region at least partially overlapping the upper protrusion of the gate electrode in the vertical direction of the gate electrode extension; the emitter metal is electrically connected to the first doped region.

3. The high trench density IGBT as described in claim 2, characterized in that, The emitter metal is in contact with the sidewall of the first doped region; or, the emitter metal is in contact with the top surface of the first doped region; or, the emitter metal is in contact with both the top surface and the sidewall of the first doped region.

4. The high trench density IGBT as described in claim 2, characterized in that, The first doped region covers the top surface of the substrate between two adjacent emitter contact holes; or, the top surface of the substrate between two adjacent emitter contact holes has two first doped regions, the bulk doped region separates the two first doped regions, and the two first doped regions are respectively located close to the two adjacent emitter contact holes.

5. The high trench density IGBT as described in claim 2, characterized in that, A second doped region of a second conductivity type is formed in the substrate of the overlapping region between the bulk doped region and the emitter contact hole. The second doped region is located above the bulk doped region and its bottom surface is in contact with the bulk doped region. The doping concentration of the second doped region is higher than that of the bulk doped region. The second doped region is electrically connected to the emitter metal.

6. The high trench density IGBT as described in claim 2, characterized in that, The isolation dielectric layer also covers at least a portion of the top surface of the first doped region, and the emitter metal covers the isolation dielectric layer above the first doped region.

7. The high trench density IGBT as described in claim 2, characterized in that, A carrier storage layer is also formed in the substrate, the carrier storage layer is located below the bulk doped region and the top surface of the carrier storage layer is in contact with the bulk doped region.

8. The high trench density IGBT as described in claim 1, characterized in that, The emitter contact hole has a first portion that overlaps with the gate trench and a second portion located on the side of the gate trench. The bottom surface of the first portion is higher than the bottom surface of the second portion, or the bottom surfaces of the first portion and the second portion are flush.

9. The high trench density IGBT as described in claim 1, characterized in that, Also includes: A dummy gate trench is disposed in the substrate and arranged on the side of the gate trench, wherein the extension direction of the dummy gate trench on the top surface of the substrate is the same as the extension direction of the gate trench. as well as A dummy gate fills the dummy gate trench and extends along the elongation direction of the dummy gate trench; The emitter contact hole also spans the dummy gate trench, and the emitter metal is electrically connected to the dummy gate.

10. The high trench density IGBT as described in claim 9, characterized in that, The substrate has a plurality of pseudo-gate trenches formed therein, and each pseudo-gate trench is provided with a pseudo-gate; a plurality of pseudo-gate trenches are grouped together, and a plurality of gate trenches are grouped together, and the pseudo-gate trench groups and gate trench groups are arranged alternately on the substrate.

11. The high trench density IGBT as described in claim 1, characterized in that, The substrate has a collector region of a second conductivity type, a buffer layer of a first conductivity type, and a drift region of a first conductivity type stacked from bottom to top. The doping concentration of the buffer layer is greater than that of the drift region, and the gate trench is formed above the drift region.

12. The high trench density IGBT as described in claim 1, characterized in that, The width of the recess is greater than the width of the emitter contact hole.

13. The high trench density IGBT as described in claim 1, characterized in that, The width of the emitter contact hole is greater than the spacing between two adjacent gate trenches.

14. The high trench density IGBT as described in claim 1, characterized in that, The spacing between the center lines of two adjacent gate trenches is less than 2 μm.

Images