Semiconductor process method and semiconductor structure
By combining a hard mask dielectric layer and a protective layer in semiconductor processes, the problems of poor sidewall morphology and low yield after semiconductor chip dicing are solved, achieving efficient chip separation and cost reduction.
Patent Information
- Application Number
- CN202410923991.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2026-01-16
AI Technical Summary
In existing technologies, semiconductor chips have poor sidewall morphology after dicing and separation, resulting in low product yield and high production costs.
A hard mask dielectric layer is used as a mask for laser cutting and plasma etching. Combined with a protective layer, etching damage is repaired, simplifying the process steps and avoiding the effects of poor photoresist coating and plasma etching.
It improved the product yield after chip dicing and separation, reduced production costs, simplified process steps, and improved production efficiency.
Smart Images
Figure CN121358201A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor process method and semiconductor structure. Background Technology
[0002] Before chip packaging, individual chips need to be cut off from the wafer and then made into different semiconductor package structures. As the size of integrated circuit chips continues to shrink, conventional blades cannot be used to cut the chips during the wafer packaging process. Generally, a combination of laser cutting and plasma etching is used to cut and separate the chips.
[0003] In existing wafer dicing methods, one approach involves first thinning the silicon layer to a certain thickness before dicing or laser separation into chips. This method carries the risk of fragmentation when dicing after thinning the silicon layer to a certain thickness. Another approach involves first removing the metal and dielectric layers from the dicing area of the silicon layer using laser dicing, then removing the silicon layer at the bottom of the dicing area using photolithography and plasma etching. Finally, the back side of the wafer is thinned to achieve chip separation. This method results in silicon trenches with depths reaching tens of micrometers after laser dicing, with a large depth-to-width ratio. However, during photolithography, it is difficult to coat the deeper trenches evenly, leading to poor development and affecting subsequent plasma etching. Ultimately, this results in poor sidewall morphology after chip dicing, and even chip separation difficulties, leading to low product yield and poor reliability.
[0004] Therefore, there is an urgent need for a method to improve the sidewall morphology and product yield of chips after dicing and separation.
[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention
[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a semiconductor process method and semiconductor structure to solve the problems of poor sidewall morphology and low product yield after chip cutting and separation in the prior art.
[0007] To achieve the above objectives, the present invention provides a semiconductor process method, the semiconductor process method comprising:
[0008] A semiconductor structure is provided, wherein the semiconductor structure comprises a substrate layer and a device layer from bottom to top, the device layer comprising two or more chips and a dicing channel region, and the dicing channel region is provided between two adjacent chips;
[0009] A hard mask dielectric layer is disposed on the upper surface of the semiconductor structure;
[0010] Laser cutting is performed on the hard mask dielectric layer and the device layer at the positions corresponding to the dicing area to expose a portion of the substrate layer, resulting in a first trench. The sidewalls of the first trench are patterned hard mask dielectric layer and patterned device layer.
[0011] Using the patterned hard mask dielectric layer as a mask, plasma etching is performed on the exposed substrate layer to etch the substrate layer to a preset depth, resulting in a second trench with sidewalls exposing the substrate layer, device layer, and hard mask dielectric layer.
[0012] The lower surface of the semiconductor structure is thinned until the second trench is completed, resulting in chip structures that are separated from each other. Each chip structure consists of a chip and a corresponding substrate layer below the chip.
[0013] Optionally, the thickness of the hard mask dielectric layer disposed on the upper surface of the semiconductor structure is greater than or equal to a preset depth etched by plasma etching of the substrate layer.
[0014] Optionally, a shielding layer is provided on the upper surface of the semiconductor structure before the hard mask dielectric layer is provided.
[0015] Optionally, the material of the shielding layer is silicon nitride.
[0016] Optionally, a laser protective liquid is coated on the surface of the hard mask dielectric layer before laser cutting.
[0017] Optionally, after plasma etching, a protective layer is applied to the exposed inner surface of the resulting second trench.
[0018] Optionally, the protective layer is made of silicon nitride.
[0019] Optionally, after covering with the protective layer, the upper surface of the semiconductor structure is polished to expose the chip on the upper surface of the semiconductor structure.
[0020] Optionally, before performing the thinning process on the lower surface of the semiconductor structure, a protective tape is applied to the upper surface of the semiconductor structure; after performing the thinning process on the lower surface of the semiconductor structure, the protective tape is removed.
[0021] The present invention also provides a semiconductor structure, wherein the semiconductor structure is cut and separated using any of the semiconductor process methods described above.
[0022] As described above, the semiconductor process method and semiconductor structure of the present invention have the following beneficial effects:
[0023] This invention uses a hard mask dielectric layer as a mask for dicing, which avoids poor development caused by poor coating of photoresist in deep trenches, avoids affecting plasma etching and resulting in poor sidewall morphology of the diced chip, improves the yield of the product obtained after dicing and separation, and reduces production costs.
[0024] This invention improves the yield of products obtained after cutting and separation by setting a protective layer in the second trench to repair the damage to the sidewalls of the second trench caused by plasma etching. Attached Figure Description
[0025] Figure 1 The diagram shown is a schematic representation of the semiconductor structure in step 1 of the semiconductor process method of the present invention.
[0026] Figure 2 The diagram shows the structure of the hard mask dielectric layer in step 2 of the semiconductor process method of the present invention.
[0027] Figure 3 The diagram shows the structure of the first trench obtained in step 3 of the semiconductor process method of the present invention.
[0028] Figure 4 The diagram shows the structure of the second trench obtained in step 4 of the semiconductor process method of the present invention.
[0029] Figure 5 The diagram shows a schematic representation of a semiconductor structure in the prior art.
[0030] Figure 6 The diagram shows a schematic representation of the structure of a semiconductor structure obtained by laser cutting in the prior art.
[0031] Figure 7 The diagram shows a structure formed by coating with photoresist in the prior art.
[0032] Figure 8 This is a schematic diagram of the plasma etching effect in the prior art.
[0033] Figure 9 The diagram shown is a schematic representation of the structure of the protective layer in step 4 of the semiconductor process method of the present invention.
[0034] Figure 10 The diagram shown is a schematic representation of the structure presented by grinding the upper surface of a semiconductor structure in step 4 of the semiconductor process method of the present invention.
[0035] Figure 11The diagram shows the structure of the thinning process performed in step 5 of the semiconductor process method of the present invention.
[0036] Figure 12 The diagram shown is a schematic representation of the structure presented in step 5 of the semiconductor process method of the present invention, which involves applying protective tape.
[0037] Figure 13 The diagram shown is a structural schematic after a thinning process is performed in an example of step 5 of the semiconductor process method of the present invention.
[0038] Component designation explanation
[0039] 11. Substrate layer; 20. Device layer; 21. Chip; 22. Cutaway region; 31. Hard mask dielectric layer; 32. Masking layer; 33. First trench; 34. Second trench; 35. Protective layer; 36. Protective tape; 41. Metal; 42. Dielectric layer; 43. Silicon layer; 44. Photoresist; 45. Trench; 50. Chip structure. Detailed Implementation
[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0041] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0042] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.
[0043] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0044] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0045] This invention provides a semiconductor process method, the semiconductor process method comprising:
[0046] Step 1: Provide a semiconductor structure, which includes a substrate layer and a device layer from bottom to top. The device layer includes two or more chips and dicing regions, and the dicing regions are provided between two adjacent chips.
[0047] Step 2: Deposit a hard mask dielectric layer on the upper surface of the semiconductor structure;
[0048] Step 3: Perform laser cutting on the hard mask dielectric layer and the device layer at the positions corresponding to the dicing area to expose part of the substrate layer, to obtain a first trench, wherein the sidewalls of the first trench are patterned hard mask dielectric layer and patterned device layer;
[0049] Step 4: Using the patterned hard mask dielectric layer as a mask, perform plasma etching on the exposed substrate layer to etch the substrate layer to a preset depth, thereby obtaining a second trench with sidewalls exposing the substrate layer, device layer and hard mask dielectric layer.
[0050] Step 5: Perform a thinning process on the lower surface of the semiconductor structure until the second trench is completed, to obtain chip structures that are separated from each other. Each chip structure consists of a chip and a corresponding substrate layer below the chip.
[0051] The semiconductor process method of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the semiconductor process method protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.
[0052] First, such as Figure 1 As shown, in step 1, a semiconductor structure is provided. The semiconductor structure includes a substrate layer 11 and a device layer 20 from bottom to top. The device layer 20 includes two or more chips 21 and dicing regions 22. The dicing regions 22 are provided between two adjacent chips 21.
[0053] In one embodiment, the substrate 11 is silicon.
[0054] Then, as Figure 2As shown, step 2 is performed, in which a hard mask dielectric layer 31 is disposed on the upper surface of the semiconductor structure.
[0055] In one embodiment, such as Figure 2 As shown, before the hard mask dielectric layer 31 is set, a shielding layer 32 is set on the upper surface of the semiconductor structure.
[0056] This invention provides a shielding layer 32 on the upper surface of a semiconductor structure to prevent scratches on the exposed metal during dicing, reduce the risk of oxidation of the exposed metal, and prevent leakage caused by the diffusion of metal ions. Specifically, the exposed metal is the metal used for WAT (Wafer Acceptance Test) and CP (Circuit Probing) within the dicing groove.
[0057] In one embodiment, the material of the shielding layer 32 is silicon nitride. Specifically, it can also be any other material capable of performing the function of the shielding layer 32.
[0058] Next, as Figure 3 As shown, in step 3, the hard mask dielectric layer 31 and the device layer 20 are laser-cut at the positions corresponding to the dicing region 22 to expose a portion of the substrate layer 11, resulting in a first trench 33. The sidewalls of the first trench 33 are patterned hard mask dielectric layer 31 and patterned device layer 20.
[0059] In one embodiment, a laser protective liquid is coated on the surface of the hard mask medium layer 31 before laser cutting.
[0060] This invention avoids scratches on the hard mask medium layer 31 during laser cutting by coating the surface of the hard mask medium layer 31 with a laser protective liquid, ensuring that the hard mask medium layer 31 can work normally and improving the yield of the final product.
[0061] In one embodiment, after laser cutting, the first groove 33 is cleaned to remove residue generated during the laser cutting process.
[0062] In one embodiment, a high-pressure water gun is used to flush away the residue in the first trench 33.
[0063] Then, as Figure 4 As shown, in step 4, the exposed substrate layer 11 is plasma etched using the patterned hard mask dielectric layer 31 as a mask to etch the substrate layer 11 to a preset depth, thereby obtaining a second trench 34 that exposes the substrate layer 11, device layer 20 and hard mask dielectric layer 31 on the sidewall.
[0064] In the prior art, when chip 21 is cut and separated, such as Figures 5-6 As shown, the metal 41 and dielectric layer 42 in the diced area on the surface of silicon layer 43 are first removed by laser cutting, and then... Figure 7 The photolithography shown, such as Figure 8 The plasma etching process shown removes the silicon layer 43 at the bottom of the dicing area, and finally, a thinning process is performed on the back side of the wafer to achieve chip separation. This method produces trenches 45 with depths reaching tens of micrometers after laser cutting, exhibiting a large depth-to-width ratio. Furthermore, due to the... Figure 7 In the photolithography process shown, the photoresist 44 is difficult to coat evenly in the deeper trenches 45, resulting in poor development. Figure 8 As shown, this affects the subsequent plasma etching effect, ultimately resulting in poor sidewall morphology of the trench 45 after chip cutting, and even problems with chip separation, leading to low product yield and poor reliability.
[0065] This invention uses a hard mask dielectric layer 31 as a mask for plasma etching, avoiding poor development caused by poor coating of photoresist in deep trenches in photolithography, thus avoiding the impact on the sidewall morphology of the chip 21 obtained by plasma etching and improving the yield of the product obtained after dicing and separation. At the same time, by eliminating the photolithography step, the process steps are simplified, production efficiency is improved, and production costs are reduced.
[0066] In one embodiment, the depth of the second trench 34 is 120 micrometers.
[0067] In one embodiment, such as Figure 9 As shown, after plasma etching, a protective layer 35 is applied to the inner surface of the second trench 34 that is exposed.
[0068] The present invention can block the diffusion of metal ions on the sidewall of the second trench 34 by covering the inner surface of the second trench 34 with a protective layer 35, and at the same time repair the sidewall damage caused by plasma etching on the inner surface of the second trench 34, thereby improving the yield of the obtained product.
[0069] In one embodiment, the protective layer 35 is made of silicon nitride. Alternatively, other materials capable of performing the function of the protective layer 35 may also be selected.
[0070] In one embodiment, the thickness of the hard mask dielectric layer 31 disposed on the upper surface of the semiconductor structure is greater than or equal to a preset depth etched by plasma etching of the substrate layer 11.
[0071] This invention ensures that the hard mask dielectric layer 31 can always serve as a mask for plasma etching by setting the thickness of the hard mask dielectric layer 31. Specifically, depending on the thickness of the hard mask dielectric layer 31, the thickness of the hard mask dielectric layer 31 remaining on the upper surface of the semiconductor structure after plasma etching will vary, and there is a possibility that no hard mask dielectric layer 31 remains on the upper surface of the semiconductor structure after plasma etching.
[0072] In one embodiment, the thickness of the hard mask dielectric layer 31 disposed on the upper surface of the semiconductor structure is 5 micrometers.
[0073] In one embodiment, such as Figure 10 As shown, after covering the protective layer 35, the upper surface of the semiconductor structure is polished to expose the chip 21 on the upper surface of the semiconductor structure.
[0074] This invention removes the protective layer 35 from the upper surface of a semiconductor structure by grinding it, while simultaneously repairing damage caused by laser cutting. Specifically, when a hard mask dielectric layer 31 remains on the upper surface of the semiconductor structure after plasma etching, grinding the upper surface removes both the remaining hard mask dielectric layer 31 and the protective layer 35.
[0075] In one embodiment, mechanical grinding is used to grind the upper surface of the semiconductor structure.
[0076] Finally, as Figure 11 As shown, in step 5, the lower surface of the semiconductor structure is thinned until the second trench 34 is completed, resulting in chip structures 50 that are separated from each other. Each chip structure 50 consists of a chip 21 and a corresponding substrate layer 11 below the chip 21.
[0077] In one embodiment, such as Figure 12 As shown, before performing the thinning process on the lower surface of the semiconductor structure, a protective tape 36 is applied to the upper surface of the semiconductor structure; as Figure 13 The diagram shown is a structural diagram after the lower surface of the semiconductor structure has been thinned. After the lower surface of the semiconductor structure has been thinned, the protective tape 36 is removed.
[0078] The present invention avoids damage to the upper surface of the semiconductor structure during the thinning process by setting a protective tape 36.
[0079] In one embodiment, solvent cleaning is used to remove surface deposits from the protective tape 36 and the semiconductor structure.
[0080] The present invention also provides a semiconductor structure, wherein the semiconductor structure is cut and separated using any of the semiconductor process methods described above.
[0081] In summary, the semiconductor process method and semiconductor structure of the present invention can be used to cut the chip by setting a hard mask dielectric layer as a mask, which avoids poor development caused by poor coating effect of photoresist in deep trenches, avoids the impact of plasma etching on the sidewall morphology of the chip obtained by cutting, improves the yield of the product obtained after cutting and separation, and reduces production costs. At the same time, by setting a protective layer in the second trench, the damage to the sidewall of the second trench caused by plasma etching is repaired, which further improves the yield of the product obtained after cutting and separation.
[0082] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method of semiconductor processing, characterized by, The semiconductor process method comprises: providing a semiconductor structure, which comprises a substrate layer and a device layer from bottom to top, and two or more chips and a cutting path region between each two adjacent chips; providing a hard mask medium layer on the upper surface of the semiconductor structure; laser cutting the hard mask medium layer and the device layer corresponding to the position of the cutting path region to expose part of the substrate layer, to obtain a first groove, and the sidewall of the first groove is the patterned hard mask medium layer and the patterned device layer; plasma etching the exposed substrate layer with the patterned hard mask medium layer as a mask to etch the substrate layer to a preset depth, to obtain a second groove with the sidewall exposing the substrate layer, the device layer and the hard mask medium layer; thinning the lower surface of the semiconductor structure until the second groove is penetrated, to obtain separated chip structures, each of which is composed of one chip and the corresponding substrate layer below the chip.
2. The semiconductor process method of claim 1, wherein, The thickness of the hard mask medium layer provided on the upper surface of the semiconductor structure is greater than or equal to the preset depth of the plasma etching of the substrate layer.
3. The semiconductor process method of claim 1, wherein, Before providing the hard mask medium layer, a shielding layer is provided on the upper surface of the semiconductor structure.
4. The semiconductor process method of claim 3, wherein, The material of the shielding layer is silicon nitride.
5. The semiconductor process method of claim 1, wherein, Before laser cutting, a laser protection liquid is coated on the surface of the hard mask medium layer.
6. The semiconductor process method of claim 1, wherein, After plasma etching, a protective layer is coated on the inner surface exposed by the obtained second groove.
7. The semiconductor process method of claim 6, wherein, The material of the protective layer is silicon nitride.
8. The semiconductor process method of claim 6, wherein, After coating the protective layer, the upper surface of the semiconductor structure is ground to expose the chips on the upper surface of the semiconductor structure.
9. The semiconductor process method of claim 1, wherein, Before thinning the lower surface of the semiconductor structure, a protective tape is attached to the upper surface of the semiconductor structure; after thinning the lower surface of the semiconductor structure, the protective tape is removed.
10. A semiconductor structure, characterized by The semiconductor structure is cut and separated by the semiconductor process method of any one of claims 1-9.