Manufacturing method of copper conductor for polymer redistribution layer

Abstract

The invention belongs to the technical field of semiconductors, and provides a manufacturing method of a copper wire for a polymer redistribution layer. The method comprises the following steps: sequentially depositing an adhesion layer and a Cu seed layer on the surface of a substrate, then completing graphical processing, filling copper in an electroplating region, etching to remove the adhesion layer and the Cu seed layer in a non-electroplating region, carrying out ALD deposition to obtain a sealing cover protection layer containing a first inorganic layer and a second inorganic layer, and then manufacturing a photosensitive dielectric layer and a through hole. And etching to remove the sealing cover protection layer in the through hole so as to ensure the electrical connection between the through hole and the copper wire below the through hole. The ALD deposition process is adopted to manufacture the sealing cover protection layer, the sealing cover protection layer can be compatible with the polymer-based RDL process, the oxygen and water vapor barrier performance is excellent, the copper wire is prevented from being oxidized, ALD conformal deposition is achieved, complete covering of the top and the side wall of the copper wire can be ensured, and the protection problem of the high-aspect-ratio through hole is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a method for fabricating copper wires for polymer redistribution layer. BACKGROUND

[0002] The growth of the semiconductor industry is driven by the demand for high performance and miniaturization of electronics, which promotes the development of advanced packaging technology and the increase of system complexity. As a key technology for chip interconnection, polymer redistribution layer (RDL) needs to reduce the number of layers through fine pitch and size miniaturization, thereby reducing costs and improving production efficiency. In the polymer redistribution layer process, copper wires are usually embedded in the polymer, but the polymer material itself cannot effectively block the diffusion of oxygen and water vapor, which will cause copper oxidation even at a temperature below 200℃, thereby causing serious reliability problems. In addition, the copper oxidation process is not self-limiting. With the continuous reduction of the critical size of copper wires, high oxidation rate has become a major reliability risk, which cannot be well inhibited even through the plastic packaging process.

[0003] Chinese patent (publication number CN1402332A) proposes a method for forming a selective protective layer on copper interconnects, which is suitable for use in damascene copper processes. First, a copper metal layer is deposited on a dielectric layer and fills the existing interconnect trenches in the dielectric layer. A polishing agent containing an organic aluminum compound is used for chemical mechanical polishing to remove excess copper metal layer. Then, the organic aluminum compound is subjected to a tempering process (about 350-420℃) to react with the underlying copper to selectively form an aluminum-copper alloy on the copper interconnects. After oxidation of the aluminum-copper alloy, an aluminum oxide protective layer is formed on the surface of the copper interconnects, so that the protective layer is selectively formed only on the surface of the copper interconnects. By forming a selective cap layer on the copper interconnects, the cap layer formed can effectively prevent copper oxidation and diffusion. However, this process flow is very complicated and the tempering process needs to be carried out at a high temperature (about 350-420℃), which is not suitable for low-temperature-sensitive polymer-based RDL processes (polymer-based RDL processes generally have a temperature of about 100-150℃), and the two processes are difficult to be compatible.

[0004] Chinese patent (publication number CN1768426A) proposes an integrated circuit die having copper contacts that form a natural oxide of copper when exposed to ambient air, and then an organic material is applied to the copper contacts that reacts with the natural oxide of copper to form an organic coating on the copper contacts to facilitate preventing further oxidation of the copper. In this way, even if subsequent process treatments are performed at high temperatures greater than 100℃, no excessive copper oxidation occurs. However, this method relies on the formation of a natural oxide layer on the copper surface as a reaction substrate, and the uniformity and adhesion of the coating may have hidden dangers, and it only focuses on wire bonding protection. The organic coating itself cannot effectively block the diffusion of oxygen and water vapor, and it fails to solve the long-term reliability problem in RDL multi-layer wiring.

[0005] From the above, a variety of schemes based on the cover layer have been developed to protect the CMOS (Complementary Metal Oxide Semiconductor) chip, but the processing temperature of these methods is high, which is incompatible with the low-temperature process of the polymer RDL, and it is difficult to be used in the semi-addition RDL process, especially difficult to handle the topology problem of multi-layer wiring (because of the topology of multi-layer wiring, on the one hand, a high-temperature cover layer needs to be deposited, and the deposition temperature of the high-temperature cover layer needs to be greater than 300℃; and in the high-temperature process, the difference in the coefficient of thermal expansion (CTE) of Cu, polymer and inorganic cover layer causes stress, and multi-layer stacking causes interface peeling or cracking. On the other hand, the topology problem of multi-layer wiring will cause the surface flatness to continue to deteriorate, thereby causing poor step coverage or causing void defects, and even causing the deformation of the lithography alignment mark, affecting the alignment of the upper and lower RDLs, etc.). In addition, if the protective layer has pinhole defects at the nanoscale, the water vapor barrier ability will decrease sharply with the thickness thinning. In addition, some protective layers prepared by organic matter are prone to degradation in a high-temperature and high-humidity environment, and cannot meet the long-term reliability requirements. The aspect ratio (AR) of the via refers to the ratio of the structure depth (H) to the opening width (W). In the deposition process, the via with a high aspect ratio (greater than or equal to 5:1) is prone to problems such as excessive thickness at the top, insufficient coverage in the hole and on the sidewall, etc., and the traditional cover layer is difficult to achieve uniform and defect-free conformal deposition in the narrow and high via structure.

[0006] Therefore, it is urgent to develop a protective layer with strong oxygen and water vapor barrier ability, high temperature and humidity resistance, which can meet the long-term reliability requirements, and can handle the topology of multi-layer wiring, and the preparation process thereof can be compatible with the low-temperature process (about 100-150℃) of the polymer RDL, and solve the problem that the cover layer is difficult to achieve uniform and defect-free conformal deposition in the via with a high aspect ratio. SUMMARY

[0007] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application proposes a method for manufacturing copper wires for polymer redistribution layers. The present application uses atomic layer deposition (ALD) to prepare a capping protective layer, which has a low process temperature (≤100℃) and can be well compatible with the low-temperature process (about 100-150℃) of the polymer RDL. The capping protective layer has excellent oxygen and water vapor barrier ability, high temperature and humidity resistance, and significant oxidation resistance effect, can meet the long-term reliability requirements, can handle the topology of multi-layer wiring, and can achieve uniform and defect-free conformal deposition in the via with a high aspect ratio (aspect ratio greater than or equal to 5:1).

[0008] The first aspect of the present application provides a method for manufacturing copper wires for polymer redistribution layers.

[0009] Specifically, a copper wire manufacturing method for a polymer redistribution layer includes the following steps: (1) taking a substrate, the substrate including a front surface and a back surface, sequentially depositing an adhesion layer and a copper seed layer on the front surface of the substrate, and performing a patterning process on the surface of the copper seed layer to obtain an electroplating area and a non-electroplating area; (2) completely filling the electroplating area with copper (Metal 1 wire); (3) etching to remove the adhesion layer and the copper seed layer of the non-electroplating area; (4) depositing on the front surface of the substrate by using an atomic layer deposition method (ALD) to obtain a capping protective layer; (5) coating a dielectric material of a redistribution layer on the surface of the capping protective layer to form a photosensitive dielectric layer; (6) opening a via hole, and then etching to remove the capping protective layer inside the via hole; In step (4), the capping protective layer includes a first inorganic layer and a second inorganic layer in order from near to far from the substrate, the first inorganic layer is at least one of a metal oxide, a nitride, a doped modified metal oxide, and a metal sulfide, and the second inorganic layer is at least one of a metal oxide, a non-metal oxide, and a transition metal; the thickness of the first inorganic layer is 8-20 nm, the thickness of the second inorganic layer is 15-30 nm, and the temperature of the atomic layer deposition method is ≤100℃.

[0010] The present application uses an atomic layer deposition method (ALD) to manufacture a thin film barrier coating (i.e., a capping protective layer), the capping protective layer has the characteristics of high compactness and high conformality, and has a low defect concentration, even if the thickness is only a few nanometers, it still exhibits excellent oxygen and water vapor barrier properties; moreover, the ALD process temperature is ≤100℃, which is relatively low, and can be well compatible with a low-temperature polymer-based RDL process (about 100-150℃), and can avoid thermal damage to the polymer substrate. In addition, the ALD is used to manufacture a capping protective layer containing a laminated inorganic material (i.e., a first inorganic layer and a second inorganic layer), which realizes lossless deposition on the polymer substrate, and covers the copper wire sidewall through this conformal deposition technology, solving the protection problem of high aspect ratio via structures in the half-addition process (especially the problem of uneven deposition and coverage of the sidewall and deep trench of the high aspect ratio via); the two inorganic thin films are selected to be stacked to obtain the capping protective layer, which completely covers the top and sidewall of the copper wire, realizing the synergistic protection effect of high compactness and barrier property; the present application isolates the copper wire from the photosensitive dielectric layer, suppresses the photoacid quenching effect, supports micro-patterned processing with a line width of <2μm, covers the full-chain protection requirements from the front-end process (seed layer deposition) to the back-end packaging (bonding pad protection), and is compatible with the photolithography process.

[0011] Preferably, in step (4), the combination of the first inorganic layer and the second inorganic layer is one of the following: (1) the first inorganic layer is a metal oxide and the second inorganic layer is a metal oxide or a non-metal oxide; (2) the first inorganic layer is a nitride and the second inorganic layer is a metal oxide; (3) the first inorganic layer is a doped modified metal oxide and the second inorganic layer is a metal oxide; (4) the first inorganic layer is a nitride or a metal sulfide and the second inorganic layer is a metal oxide, a transition metal or a transition metal containing compound.

[0012] Preferably, the metal oxide is at least one of AI2O3, ZrO2, HfO2, TiO2.

[0013] Preferably, the nitride is at least one of AIN, silicon nitride, TiN.

[0014] Preferably, the non-metal oxide is at least one of SiO2, SiN x , AIN, BN.

[0015] Preferably, the doped modified metal oxide is at least one of AI2O3:Ti, ZrO2:Y, TiO2:Ta, TiO2:N, ZnO:AI.

[0016] Preferably, the metal sulfide is at least one of MoS2, AI2S3, TaS2, ZnS.

[0017] Preferably, the transition metal is at least one of Ta, W, Mo.

[0018] Preferably, the transition metal containing compound is TiC and / or TaN.

[0019] Preferably, the first inorganic layer is AI2O3 and the second inorganic layer is ZrO2. or, the first inorganic layer is AI2O3 and the second inorganic layer is HfO2. or, the first inorganic layer is AI2O3 and the second inorganic layer is SiO2. or, the first inorganic layer is AIN and the second inorganic layer is AI2O3. or, the first inorganic layer is silicon nitride and the second inorganic layer is AI2O3. or, the first inorganic layer is AI2O3:Ti and the second inorganic layer is TiO2. or, the first inorganic layer is ZrO2:Y and the second inorganic layer is AI2O3. or, the first inorganic layer is TiN and the second inorganic layer is Ta. Alternatively, the first inorganic layer is MoS2, and the second inorganic layer is Al2O3.

[0020] Preferably, in step (1), the substrate is one of a glass substrate, a polymer substrate, a silicon wafer with a passivation layer.

[0021] Preferably, the polymer substrate includes one of a phenolic resin substrate (FR-1), an epoxy resin substrate, a bismaleimide triazine resin (BT) substrate, an ABF substrate (Ajinomoto Build-up Film), a polytetrafluoroethylene substrate.

[0022] Preferably, the passivation layer is SiO2 and / or SiN. The silicon wafer itself is a semiconductor and cannot be directly used as an interlayer, so a passivation treatment is performed on the surface of the silicon wafer, for example, an SiO2, SiN insulating film layer is coated on the surface to eliminate its conductivity; however, if the substrate is selected as glass, the material itself is an insulating material, and no passivation treatment is required, and it can be directly used as a substrate.

[0023] Preferably, in step (1), the adhesion layer is a titanium seed layer. The titanium seed layer has the dual functions of promoting adhesion and blocking copper diffusion.

[0024] Preferably, in step (1), the thickness of the adhesion layer is 20-40 nm, and / or the thickness of the copper seed layer is 140-160 nm.

[0025] Further preferably, in step (1), the thickness of the adhesion layer is 30-40 nm, and / or the thickness of the copper seed layer is 150-160 nm.

[0026] Preferably, in step (1), the patterning process includes: coating an electroplating resist on the surface of the copper seed layer, covering the areas that do not need electroplating with a mask, then performing exposure and development, removing the mask, and completing the patterning process.

[0027] The main function of the electroplating resist is to selectively block electroplating deposition, thereby achieving precise processing of the patterned structure. The electroplating resist can form a specific pattern through exposure and development, complete the patterning, expose the areas that need electroplating, and cover the non-electroplating areas, ensuring that the subsequent Cu is deposited only at the target position.

[0028] Preferably, in step (2), the complete filling of copper uses an electrochemical deposition method (ECD).

[0029] Preferably, in step (4), the temperature of the atomic layer deposition method (ALD) is 90-100°C.

[0030] Preferably, in step (4), the thickness of the first inorganic layer is 10-20 nm, and / or the thickness of the second inorganic layer is 15-25 nm.

[0031] Further preferably, in step (4), the thickness of the first inorganic layer is 15-20 nm, and / or the thickness of the second inorganic layer is 20-25 nm.

[0032] Preferably, in step (5), the dielectric material of the re-wiring layer is benzocyclobutene (BCB) and / or photosensitive polyimide (PI).

[0033] Preferably, in step (5), the thickness of the photosensitive dielectric layer is 1-10 μm.

[0034] Further preferably, in step (5), the thickness of the photosensitive dielectric layer is 7-10 μm.

[0035] Preferably, in step (5), the via is opened by a photolithography process.

[0036] Preferably, in step (5), after the via is opened, a curing process is performed.

[0037] Preferably, in step (6), the etching is soft sputter etching. The etching removes the capping layer inside the via to ensure the electrical connection between the via and the underlying copper conductor. The soft sputter etching used in the present application, compared with traditional etching techniques (such as reactive ion etching RIE or plasma etching), on the one hand, by reducing the ion energy (usually <100 eV), avoids the physical damage of high-energy plasma to the copper conductor at the bottom of the via and the surrounding polymer dielectric layer (such as PI, BCB), on the other hand, it can protect the sidewall morphology. Traditional RIE may cause sidewall roughening, while soft sputter etching can maintain the perpendicularity of the sidewall, which is more suitable for deep hole etching.

[0038] Preferably, the aspect ratio of the via is 5:1-20:1.

[0039] Preferably, after step (6) is completed, the steps (1)-(6) are repeated on the surface of the substrate to obtain at least two layers of electroplated Cu. Each electroplated Cu is identical except for the different topological structure of the bottom layer.

[0040] Further preferably, after step (6) is completed, the steps (1)-(6) are repeated on the surface of the substrate to obtain 2-14 layers of electroplated Cu.

[0041] More preferably, after step (6) is completed, the steps (1)-(6) are repeated on the surface of the substrate to obtain 4-8 layers of electroplated Cu.

[0042] Compared with the prior art, the present application has the following beneficial effects: The application first deposits an adhesion layer and a Cu seed layer on the front surface of a substrate in sequence, then completes a patterning process, fills copper in the electroplating area, removes the adhesion layer and the Cu seed layer in the non-electroplating area by etching, and then performs ALD deposition to obtain a capping protective layer containing a first inorganic layer and a second inorganic layer, and then makes a photosensitive dielectric layer and opens a via hole, and removes the capping protective layer inside the via hole by etching to ensure the electrical connection between the via hole and the copper conductor below. The application uses the ALD deposition process to make the capping protective layer, and the process temperature is ≤100℃, which can avoid the degradation of polymers, so it can be well compatible with the polymer-based RDL process (however, the traditional inorganic protective layer manufacturing process needs to be carried out at a temperature ≥200℃, which is difficult to be compatible with the polymer-based RDL process), and the capping protective layer obtained has high density and a double-layer inorganic stack structure, which is beneficial to strengthen the oxygen and water vapor barrier performance, avoid the oxidation of the copper wire, and the ALD conformal deposition can also ensure the complete coverage of the copper conductor top and sidewall, so as to solve the protection problem of high aspect ratio via holes; the copper conductor of the electrical connection structure obtained by the application has a copper oxidation inhibition rate of 100% after 85℃ / 85%RH 1000h test, which indicates that the effect of preventing the oxidation of the copper conductor is remarkable, and the mechanical strength reaches 5N without damage, the mechanical performance is excellent, and the water vapor transmission rate is only 0.01-0.02g / m 2 / day, and the barrier performance is strong. The method for making the capping protective layer provided by the application provides a promising solution for developing high-reliability polymer-based RDL. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 The operation schematic diagram for depositing the Ti seed layer, the Cu seed layer and completing the patterning in step (1) of the embodiment 1 of the application; Figure 2 The operation schematic diagram for depositing the electroplated Cu in step (2) of the embodiment 1 of the application; Figure 3 The operation schematic diagram for etching the Ti seed layer and the Cu seed layer in the non-electroplating area in step (3) of the embodiment 1 of the application; Figure 4 The operation schematic diagram for depositing the capping protective layer by ALD in step (4) of the embodiment 1 of the application; Figure 5 The operation schematic diagram for making the photosensitive dielectric layer and opening the via hole in step (5) of the embodiment 1 of the application; Figure 6 The operation schematic diagram for removing the capping protective layer inside the via hole by etching in step (6) of the embodiment 1 of the application; Figure 7 The structure schematic diagram of the finally obtained two-layer electroplated Cu in step (7) of the embodiment 1 of the application. DETAILED DESCRIPTION

[0044] In order to make the skilled in the art more clearly understand the technical solutions described in the present application, the following examples are listed for illustration. It should be noted that the following examples do not constitute a limitation on the scope of protection required by the present application.

[0045] The raw materials, reagents or devices used in the following examples, if not specifically stated, can be obtained from conventional commercial channels, or can be obtained by existing known methods.

[0046] wherein, Figures 1-7 In the figure, 100 is a polymer substrate, 200 is a Ti seed layer, 300 is a Cu seed layer, 400 is an electroplating resist, 500 is a mask, 600 is an electroplated Cu, 700 is a capping layer, and 800 is a photosensitive dielectric layer.

[0047] The aspect ratio of the through hole in all of the following examples and comparative examples is 8:1.

[0048] Example 1 A method for making a copper wire for a polymer redistribution layer, comprising the following steps: (1) Take a polymer substrate 100 (a phenolic resin substrate, FR-1), which includes a front side and a back side. On the front side of the polymer substrate 100, sequentially deposit a 30 nm adhesion layer (Ti seed layer) 200 and a 150 nm Cu seed layer 300. On the surface of the Cu seed layer 300, coat an electroplating resist 400 (a photoresist, AZ5214E) (a). Figure 1 a), then cover the area that does not need to be electroplated (b) using a mask 500, followed by exposure and development to complete the patterning, obtaining an electroplated area and a non-electroplated area (a). Figure 1 Figure 2 a); (2) Use an electrochemical deposition method (ECD) to completely fill the copper in the seed layer trench in the electroplated area, obtaining an electroplated Cu 600 (Metal 1 wire) (b). Figure 2 (3) After removing the photoresist mask, etch to remove the Ti seed layer 200 and the Cu seed layer 300 in the non-electroplated area (). Figure 3 (4) On the front side of the polymer substrate 100, use an ALD deposition method to sequentially deposit a 15 nm aluminum oxide (first inorganic layer) and a 20 nm titanium dioxide (second inorganic layer) at 100°C, obtaining a capping layer 700 (). Figure 4 (5) Spin-coat a redistribution layer dielectric material BCB on the surface of the capping layer 700 in three times to ensure uniformity and achieve the filling of the inter-wire trench, obtaining a photosensitive dielectric layer 800 (). Figure 5 ​​​​a) Due to the influence of the topography of the underlying electroplated Cu 600 (Metal 1 wire), the surface of the photosensitive dielectric layer 800 presents a non-flat topography; (6) Then cover the mask 500 ( Figure 5 b) Open the via hole by photolithography process ( Figure 6 a) and perform curing treatment; above the via hole opening, remove the capping layer 700 inside the via hole by soft sputtering etching ( Figure 6 b) to ensure the electrical connection between the via hole and the electroplated Cu (Metal 1 wire); (7) Repeat steps (1)-(6) on the surface of the substrate, and the final structure ( Figure 7 ) contains two layers of capping layer 700 and two layers of electroplated Cu 600.

[0049] Example 2-5 The difference from Example 1 is that the protective layer structure is different, as shown in Table 4.

[0050] Comparative Example 1 The difference from Example 1 is that the capping layer is replaced by 30 nm Al2O3, and the ALD deposition temperature is 250°C.

[0051] Comparative Example 2 The difference from Example 1 is that the capping layer is replaced by a 30 nm silicone coating, which is deposited by chemical vapor deposition (CVD) method.

[0052] Comparative Example 3 The difference from Example 1 is that the capping layer is replaced by 35 nm Al2O3.

[0053] Comparative Example 4 The difference from Example 1 is that the capping layer is replaced by 35 nm TiO2.

[0054] Comparative Example 5 The difference from Example 1 is that the capping layer is replaced by a commercial organic protective film (produced by HD MicroSystems Company, model PI-2611, polyimide film).

[0055] Comparative Example 6 The difference from Example 1 is that there is no capping layer, and the rest of the structure is the same.

[0056] Comparative Example 7 The difference from Example 1 is that the capping layer is replaced by 50 nm SiO2.

[0057] Comparative Example 8 The difference from Example 1 is that the capping protective layer is replaced by 5nm Al2O3 / 10nm TiO2.

[0058] Comparative Example 9 The difference from Example 1 is that the capping protective layer is replaced by 2nm Al2O3 / 5nm TiO2.

[0059] Comparative Example 10 The difference from Example 1 is that the capping protective layer is replaced by 25nm Al2O3 / 40nm TiO2.

[0060] Product performance test The structures prepared in the above examples and comparative examples are tested, wherein in Tables 1-5, when the capping protective layer is a double layer, the first inorganic protective layer / second inorganic protective layer is represented, for example, 15nm Al2O3 / 20nm TiO2 represents that the first inorganic protective layer is Al2O3 and the second inorganic protective layer is TiO2, and the rest is similar.

[0061] 1. Performance comparison of capping protective layers obtained by different deposition methods (1) Test method Substrate deformation: Referring to IPC-TM-650, which is a test method manual prepared by IPC (Institute of Electronics Industry) for detecting the reliability of electronic products. The specific test method is as follows: the structure to be detected is placed horizontally on a completely calibrated horizontal optical flat glass to avoid external force, then a laser displacement sensor is used to measure the vertical displacement LR of the maximum warping point, and the warping degree is calculated by R = LR / W, wherein W is the length of the substrate and LR is the warping amount.

[0062] Copper oxidation inhibition rate: the structure to be detected is placed in a high temperature and high humidity environment (85℃ / 85%RH, 200h) and a bias is applied, and the oxidation and electrochemical migration of the metal Cu layer are evaluated. Then, a focused ion beam (FIB) is used to prepare a cross-section sample to expose the interface between the oxidation layer and the metal layer, a scanning electron microscope (SEM) is used to observe the cross-section morphology, an X-ray spectrum (EDS) is used to analyze the element distribution of Cu and O, and an electron energy spectrum (XPS) is used to distinguish the valence state of Cu; finally, the area ratio of the oxidation area (O-containing Cu phase) in the cross-section is calculated, which is approximately the oxidation ratio. And calculate the copper oxidation inhibition rate.

[0063] (2) Test results Table 1 Performance comparison of Example 1 and Comparative Examples 1-2

[0064] From the above table, the capping protective layer of Example 1 is prepared by ALD deposition process at 100 DEG C, the process temperature is low, and the capping protective layer is compatible with the polymer RDL process, which can not only prevent the deformation of the polymer substrate, but also effectively inhibit the oxidation of copper.

[0065] The Al2O3 of Comparative Example 1 has excellent oxygen barrier performance, can effectively block the penetration of H2O and O2 in the environment, and prevent Cu oxidation, but only a single layer film may have microcracks or pinhole defects, and the long-term reliability is not as good as Example 1; the stack design of Example 1 can compensate for the defects of single Al2O3 film, form a more dense barrier, and TiO2 has high chemical stability and good interface compatibility with Cu, which can further inhibit the interface diffusion and electrochemical corrosion of Cu, so the oxidation inhibition effect of Example 1 is better than that of Comparative Example 1.

[0066] The barrier property of the silicone coating of Comparative Example 2 is weak, and it cannot effectively block the penetration of H2O and O2, resulting in local oxidation of Cu. The air permeability of silicone is high (O2 transmission rate is large), and Cu2O / CuO is easily formed on the surface of Cu, and the oxidation inhibition effect is the weakest.

[0067] 2. Comparison of barrier properties and mechanical properties of different capping protective layers (1) Test method Pinhole density: the same capping protective layer preparation process (i.e. step 4 of Example 1) is used to coat the surface of Cu-coated silicon wafer to facilitate testing, and then 10 points are randomly selected to evaluate the number of holes with a diameter of ≥5 μm in 1 cm 2 , and the average value is taken. Other examples and comparative examples use the same test method as Example 1.

[0068] Water vapor transmission rate: seal the electrolytic sensor to the same position inside the structure to be detected, and place the prepared structure in a high humidity (85% RH) environment. The water vapor transmitted through the sample structure is transmitted to the sensor, the sensor electrolyzes the water vapor into hydrogen and oxygen, and the water vapor transmission rate is calculated through the proportional relationship between the electrolysis current and the water vapor amount.

[0069] Mechanical strength of the film layer: crosshatch test is used, and the test method is referred to ASTM D3359 "Standard Test Method for Adhesion by Tape Test" (American Society for Testing and Materials).

[0070] (2) Test results Table 2 Comparison of properties of capping protective layers of Example 1 and Comparative Examples 3-4

[0071] From the above table, the pinhole density of Example 1 is reduced by about 85% compared to the Al2O3 of the same thickness of Comparative Example 3, and the water vapor barrier rate is increased by about 7 times. The pinhole density of Example 1 is reduced by about 96% compared to the single-layer TiO2 of Comparative Example 4, and the water vapor barrier rate is increased by about 21.5 times. It is shown that the double-layer structure of the sealing protective layer formed by the two different inorganic materials can effectively reduce the pinholes, block the water vapor, and has high mechanical strength.

[0072] Comparative Example 3 and Comparative Example 4 are only single-layer structure sealing protective layers, and the pinhole density of the sealing protective layer is large, the barrier property is poor, and the mechanical strength is low.

[0073] 3. Reliability comparison of structures with different sealing protective layers (1) Test method Thin film reliability test: more than 240 hours of high temperature storage, temperature cycle, temperature and humidity cycle experiment combination verification, as shown below: HTOL (High Temperature Operating Life, high temperature operating life test), test parameters: place the structure to be detected in a 150℃ high temperature environment while applying working voltage / current, and run for 2000 hours, simulate the long-term use scene of the structure in high temperature working state, evaluate the life and reliability of the thin film and the whole device, detect whether there are performance drift, failure and other problems. Specific detection method: take the structure to be detected, repeat 3 in the same group, pretreat the soldering lead of all the structures to be detected to ensure stable signal transmission, record the initial resistance performance; check the temperature measurement accuracy and power supply stability of the high temperature oven and the electric property test system; set the oven temperature to be stable at 150℃, set the voltage to be 5V, fix the sample to be tested on the high temperature carrier plate, connect the circuit to ensure good contact under high temperature, first heat the oven to 150℃ and stabilize for 30 minutes, then connect the power supply, start timing. Record the electrical performance parameters (such as leakage current, functional output) every 100 hours, if abnormal (such as failure), mark the failure time. After the test is completed, cool to room temperature, detect whether the resistance performance is still in the fluctuation range (ΔR>10% is judged as failure), and observe the sample state under microscope: whether there are damages caused by thermal aging and electromigration (such as local ablation, insulation layer breakdown).

[0074] TCT (Temperature Cycle Test): Test the sample between extremely low temperature (-55℃) and extremely high temperature (150℃) with rapid switching, each cycle includes low temperature holding, temperature rising, high temperature holding, temperature falling, etc. stages, observe the sample performance change after 1000 cycles. Thermal expansion and contraction stress caused by temperature changes, evaluate the fatigue resistance and bonding stability of the structure to be tested, detect whether cracking, delamination, peeling and other phenomena occur. Specific detection method: select the target structure, repeat 3 in the same group, record the interface state in the structure by microscope; temperature cycle box (supporting -55~150℃ range, temperature control accuracy ±2℃, liquid nitrogen cooling), with rapid temperature rising and falling capacity (temperature rising and falling rate ≥5℃ / min), set the cycle parameters: low temperature section: -55℃, hold for 30 minutes; temperature rising section: from -55℃ to 150℃ (rate 5℃ / min); high temperature section: 150℃, hold for 30 minutes; temperature falling section: from 150℃ to -55℃ (rate 5℃ / min); 1 cycle total time is about 120 minutes, repeat 1000 times. Fix the sample on the sample holder to avoid contact with the wall of the box and ensure uniform temperature transmission. Check whether the sample falls off after every 100 cycles, record the actual temperature curve in the box. After the cycle is completed, detect whether cracking, delamination, peeling occurs in the structure by optical microscope or scanning electron microscope.

[0075] THB (Temperature and Humidity Bias Test): Apply voltage bias in the environment of temperature 85℃ and relative humidity 85% for continuous test of 1000 hours, accelerate the penetration and erosion of moisture to the film in high temperature and high humidity environment, simulate the long-term effect of humid environment on the film. Evaluate the moisture resistance and anti-electrochemical corrosion ability of the structure, detect whether the structure to be tested causes insulation decline, oxidation, ion migration, and peeling from the substrate due to moisture absorption. Specific detection method: select the target structure, repeat 3 in the same group, pretreat the soldering leg leads of all samples and fix them in the constant temperature oven to avoid direct contact with condensed water, connect the circuit to ensure stable electrical signal transmission, and record the initial resistance performance; constant temperature and humidity oven (temperature control accuracy ±2℃, humidity accuracy ±5% RH), support 85℃ / 85% RH long-term stable operation, condition setting is temperature 85℃, relative humidity 85%, for 1000 hours; apply rated voltage (5V). First, raise the temperature and humidity in the box to the set value and stabilize for 1 hour, then put in the sample and start timing. Record the temperature and humidity every 200 hours to monitor whether the structure has leakage current (short circuit directly determines failure). After the test is completed, take out the sample and place it in a normal temperature and dry environment for 24 hours, test the resistance change of the structure.

[0076] (2) Test results Table 3. Performance test results of the structures finally prepared in Example 1 and Comparative Examples 5-6

[0077] Note: In the above table, 0 failure 1 That is, all the test samples must remain functional after cycling, with no electrical performance degradation or physical damage (such as cracking, delamination, etc.); 0 failure 2 After testing, the electrical performance verification (such as leakage current, functional test, etc.) is required, and there is no failure mode such as corrosion, metal migration, etc. The important certification standard (AEC-Q100 Grade 1) in the automotive electronics field is introduced, the oxidation prevention of the sealing protective layer is introduced into the chip preparation process, and the performance variation law and stability with temperature cycling are tested. Among them, ΔR is the change amount of resistance value.

[0078] From the above table, it can be seen that Example 1 of the present application meets the AEC-Q100 Grade 1 certification requirements, indicating that it has good reliability in high temperature and / or high humidity environments.

[0079] Comparative Example 5 uses a commonly used commercial organic protective film (HD MicroSystems PI-2611, PI) in the prior art, which is difficult to meet the AEC-Q100 Grade 1 certification requirements.

[0080] Comparative Example 6 lacks a sealing protective layer, and in the absence of barrier protection, the copper wire is broken or completely oxidized.

[0081] 4. Performance comparison of sealing protective layers with different stack structures (1) Test method Water vapor transmission rate: The electrolytic sensor is sealed into the same position inside the structure to be tested, and the prepared structure is placed in a high humidity (85% RH) environment. Water vapor is transmitted through the sample structure to the sensor, and the sensor electrolyzes the water vapor into hydrogen and oxygen. By the proportional relationship between electrolytic current and water vapor, the water vapor transmission rate is calculated.

[0082] Mechanical strength: The crosshatch test is used, and the test method is referred to ASTM D3359 "Standard Test Methods for Adhesion by Tape Test" (American Society for Testing and Materials).

[0083] (2) Test results Table 4. Performance test results of the structures finally prepared in each example and comparative example

[0084] From the above table, it can be seen that the water vapor transmission rate of the structure containing the sealing protective layer of Examples 1-5 of the present application is only 0.01-0.02 g / m 2 / day, excellent barrier performance, high mechanical strength.

[0085] Comparative Example 8 thinned two layers of inorganic protective layers, resulting in increased water vapor transmission rate and decreased mechanical strength.

[0086] Comparative Example 9 thinned two layers of inorganic protective layers relative to Comparative Example 8, resulting in a significant decrease in barrier performance and mechanical strength.

[0087] Comparative Example 10 thickened two layers of inorganic protective layers, although the water vapor transmission rate was 0 g / m 2 / day, the barrier property was good, but warping and peeling occurred, it could not be used, and the cost was significantly increased.

[0088] The above results show that even if the same material is used for the capping protective layer and the capping protective layer is designed as a stacked structure, when the thickness is set too thin or too thick, excellent barrier property and mechanical property cannot be obtained at the same time. For example, if the capping protective layer is too thin, the protective property is insufficient, if the capping protective layer is too thick, stress warping or even peeling occurs, and the cost is significantly increased. The material and thickness of the present application are most suitable, which can ensure barrier property and chemical protective property, and the mechanical strength is high.

[0089] 6. Water vapor protection effect of the topological structure of the multi-layer wiring (1) Test method Example 1 (15 nm Al2O3 / 20 nm TiO2 stacked layer deposited by ALD) was used as a capping protective layer and applied to a 4-layer polymer RDL structure (each completed layer was protected by a capping protective layer, and the polymer RDL structure and the capping protective layer structure of each layer were the same, and the polymer was ABF resin), while Comparative Example 1 and Comparative Example 2 used no capping protective layer and a silicone protective structure, respectively, and then the water vapor barrier property and THB (chip-level temperature and humidity bias life test) reliability were tested.

[0090] XPS analysis of Cu wire surface oxidation: the structure to be detected was placed in a high temperature and high humidity environment (85°C / 85%RH, 200 hours) and a bias was applied to evaluate the oxidation and electrochemical migration of the metal Cu layer. Then a cross-section sample was prepared using a focused ion beam (FIB) to expose the interface between the oxidation layer and the metal layer, and the element distribution of Cu and O was analyzed by X-ray spectroscopy (XPS).

[0091] Water vapor transmission rate: an electrolytic sensor was sealed to the same position inside the structure to be detected, and the prepared structure was placed in a high humidity (85%RH) environment, water vapor transmitted through the sample structure to the sensor, the sensor electrolyzed the water vapor into hydrogen and oxygen, and the water vapor transmission rate was calculated by the proportional relationship between the electrolysis current and the water vapor amount.

[0092] THB (85℃ / 85%RH / 1000h) reliability: in the environment of temperature 85℃, relative humidity 85%, while applying voltage bias for 1000 hours, in high temperature and high humidity environment, accelerate the penetration and erosion of moisture to the film, simulate the long-term effect of humid environment on the film. Evaluate the moisture resistance and anti-electrochemical corrosion ability of the structure, detect whether the structure to be detected causes insulation decline, oxidation, ion migration, and peeling from the substrate due to moisture absorption. Specific detection method: select the target structure, repeat 3 times in the same group, pretreat the soldering leg leads of all samples and fix them in the constant temperature oven to avoid direct contact with condensed water, connect the circuit to ensure stable transmission of electrical signals, and record the initial resistance performance; constant temperature and humidity chamber (temperature control accuracy ±2℃, humidity accuracy ±5% RH), supporting 85℃ / 85% RH long-term stable operation, condition setting temperature 85℃, relative humidity 85%, for 1000 hours; apply rated voltage (5V). First, the temperature and humidity in the chamber are raised to the set value and stabilized for 1 hour, then the sample is placed and timed. Record the temperature and humidity every 200 hours to monitor whether the structure has leakage current (short circuit directly determines failure). After the test, the sample is taken out and placed in a normal temperature and dry environment for 24 hours, and the resistance change of the structure is tested.

[0093] (2) Test results Table 5 Water vapor protection test results of different multi-layer wiring topologies

[0094] The above table results show that the cap protective layer of the embodiment 1 of the present application can handle the topology of multi-layer wiring, has low water vapor transmission rate, small resistance change, provides excellent oxygen and water vapor barrier ability, and is resistant to high temperature and high humidity, meeting the long-term reliability requirement.

Claims

1. A method for fabricating copper wiring for a polymer redistribution layer, characterized by, The method comprises the following steps: (1) taking a substrate, the substrate comprising a front surface and a back surface, sequentially depositing an adhesion layer and a copper seed layer on the front surface of the substrate, and performing a patterning process on the surface of the copper seed layer to obtain an electroplating area and a non-electroplating area; (2) completely filling the electroplating area with copper; (3) etching to remove the adhesion layer and the copper seed layer of the non-electroplating area; (4) depositing a capping protective layer on the front surface of the substrate by using an atomic layer deposition method; (5) coating a re-distribution layer dielectric material on the surface of the capping protective layer to form a photosensitive dielectric layer; (6) opening a via hole, and then etching to remove the capping protective layer inside the via hole. In step (4), the capping protective layer comprises a first inorganic layer and a second inorganic layer in order from near to far from the substrate, the first inorganic layer is at least one of a metal oxide, a nitride, a doped modified metal oxide, and a metal sulfide, and the second inorganic layer is at least one of a metal oxide, a non-metal oxide, a transition metal, and a transition metal-containing compound; the thickness of the first inorganic layer is 8-20 nm, and the thickness of the second inorganic layer is 15-30 nm; and the temperature of the atomic layer deposition method is ≤100℃.

2. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (4), the combination of the first inorganic layer and the second inorganic layer is one of the following: (1) the first inorganic layer is a metal oxide, and the second inorganic layer is a metal oxide or a non-metal oxide; (2) the first inorganic layer is a nitride, and the second inorganic layer is a metal oxide; (3) the first inorganic layer is a doped modified metal oxide, and the second inorganic layer is a metal oxide; (4) the first inorganic layer is a nitride or a metal sulfide, and the second inorganic layer is a metal oxide, a transition metal, or a transition metal-containing compound.

3. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (1), the adhesion layer is a titanium seed layer.

4. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (1), the patterning process comprises the following steps: coating an electroplating resist on the surface of the copper seed layer, covering the area that does not need to be electroplated with a mask, then performing exposure and development, and removing the mask to complete the patterning process.

5. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (2), the complete filling of copper is performed by using an electrochemical deposition method.

6. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (4), the temperature of the atomic layer deposition method is 90-100℃.

7. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (4), the thickness of the first inorganic layer is 10-20 nm, and / or the thickness of the second inorganic layer is 15-25 nm.

8. The method of claim 1, wherein the copper wire for a polymer redistribution layer is made by, In step (5), the re-distribution layer dielectric material is benzocyclobutene and / or photosensitive polyimide.

9. The method of claim 8, wherein the copper wire is formed by a process comprising: In step (5), the thickness of the photosensitive dielectric layer is 1-10 μm.

10. The method of claim 1, wherein, In step (5), the aspect ratio of the via hole is 5:1-20:1.

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