Airtight packaging structure and packaging method of chip

Abstract

The invention discloses an airtight packaging structure and method of a chip, the airtight packaging structure of the chip comprises a bearing substrate and a cap substrate, the middle part of the bearing substrate is provided with a groove which is recessed towards the interior of the bearing substrate, the edge of the bearing substrate is provided with a metal retaining wall in a surrounding manner, the groove is located at the inner side of the metal retaining wall, and the cap substrate is located at the inner side of the metal retaining wall. A chip is arranged in the groove; the cap substrate is provided with first bonding metal corresponding to the metal retaining wall, the cap substrate covers the metal retaining wall, and the first bonding metal is connected with the metal retaining wall through metal bonding so as to seal the chip between the bearing substrate and the cap substrate. According to the invention, the bearing substrate is provided with the groove for mounting the chip, the bearing substrate is provided with the metal retaining wall, and the cap substrate is provided with the first bonding metal, so that the bearing substrate and the cap substrate can be connected through a metal bonding process, the airtightness is good, the process is simple, and the structure is compact.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and more particularly to a hermetic packaging structure and packaging method for a chip. Background Technology

[0002] Chip packaging provides electrical connections, protection, support, heat dissipation, and assembly for chips, and is widely used in electronic products. With the trend towards thinner and lighter electronic products, chip packaging is also becoming increasingly thinner and lighter.

[0003] Existing chip packaging structures typically include a substrate, a chip mounted on the substrate, and encapsulating adhesive covering the chip. However, for applications requiring higher airtightness, such as waterproofing and dustproofing, simply sealing the chip with encapsulating adhesive is usually insufficient to meet the required sealing requirements. Furthermore, existing chip packaging structures are relatively large in size and have complex manufacturing processes. Therefore, there is an urgent need to provide a chip packaging structure that ensures good airtightness, smaller size, and simpler manufacturing process. Summary of the Invention

[0004] The purpose of this invention is to provide a hermetically sealed packaging structure and packaging method for chips, so as to solve the problems of poor hermetically sealed properties, large size, and complex process of chip packaging structures in the prior art.

[0005] To achieve the above objectives, the present invention provides a hermetically sealed chip packaging structure, comprising: a carrier substrate, wherein a groove is provided in the middle of the carrier substrate and recessed into the interior of the carrier substrate, and a metal barrier is provided around the edge of the carrier substrate, the groove being located inside the metal barrier and a chip being disposed within the groove; and a cap substrate, wherein a first bonding metal is provided on the cap substrate corresponding to the metal barrier, the cap substrate being disposed on the metal barrier, and the first bonding metal being connected to the metal barrier by metal bonding to seal the chip between the carrier substrate and the cap substrate.

[0006] Preferably, the cap substrate is further provided with a metal connection structure that penetrates it, and the chip is provided with an electrical connection structure, wherein the metal connection structure is electrically connected to the electrical connection structure.

[0007] Preferably, the chip includes a top chip, the electrical connection structure on the top chip is a plurality of first copper pillars, and the metal connection structure includes a plurality of second bonding metals disposed corresponding to the plurality of first copper pillars. The second bonding metals are metal-bonded to the first copper pillars to make the top chip electrically connected to the second bonding metals.

[0008] Preferably, the chip further includes a bottom chip, the electrical connection structure on the bottom chip being a plurality of pads, the bottom chip being disposed at the bottom of the groove, the top chip being stacked on the bottom chip and exposing the pads of the bottom chip, the carrier substrate also having electrical connection lines, the electrical connection lines being located between the metal barrier and the groove, the electrical connection lines having a plurality of second copper pillars, the pads of the bottom chip being electrically connected to the electrical connection lines; the metal connection structure further includes a plurality of third bonding metals disposed corresponding to the second copper pillars, the third bonding metals being metal-bonded to the second copper pillars to electrically connect the bottom chip to the third bonding metals.

[0009] Preferably, there are at least two bottom chips, which are stacked and staggered to expose the pads on the bottom chips. The top chip is staggered with the adjacent bottom chip to expose the pads on the bottom chip. The pads of the bottom chips are connected to the electrical connection lines via leads.

[0010] Preferably, the cap substrate is further provided with a rewiring unit on the side away from the supporting substrate, the rewiring unit is electrically connected to the metal connection structure, and the rewiring unit is provided with a docking part for electrical connection with the outside.

[0011] The present invention also provides a hermetically sealed chip packaging method, comprising the following steps: providing a carrier wafer, wherein the carrier wafer is divided into a plurality of carrier substrates, each carrier substrate having a groove recessed into the center of the center, and each carrier substrate having a metal barrier surrounding its edge; providing a chip and placing the chip in the groove; providing a capping wafer, wherein the capping wafer is divided into a plurality of cap substrates corresponding to the plurality of carrier substrates, and each cap substrate having a first bonding metal corresponding to the metal barrier; placing the capping wafer on the metal barrier, and connecting the first bonding metal to the metal barrier by metal bonding to seal the chip between the carrier substrate and the cap substrate.

[0012] Preferably, a carrier wafer is provided, the carrier wafer being divided into a plurality of carrier substrates, each carrier substrate having a groove recessed into the center of its middle portion, and each carrier substrate having a metal barrier surrounding its edge. The steps include: providing a carrier wafer, the carrier wafer being divided into a plurality of carrier substrates, each carrier substrate having a groove region in its middle portion; using a wafer-level process to form a metal barrier on the carrier wafer corresponding to each carrier substrate, the metal barrier surrounding the edge of the carrier substrate; and etching the groove region of the carrier wafer to form a groove recessed into the center of the carrier wafer.

[0013] Preferably, the cap substrate is further provided with a through-hole metal connection structure, the chip is provided with an electrical connection structure, and the metal connection structure is electrically connected to the electrical connection structure; the chip includes a top chip, the electrical connection structure on the top chip is a plurality of first copper pillars, and the metal connection structure includes a plurality of second bonding metals disposed corresponding to the plurality of first copper pillars; the capping wafer is placed on the metal barrier wall, and the first bonding metals are connected to the metal barrier wall by metal bonding, including the following steps: the capping wafer is placed on the metal barrier wall, the first bonding metals are connected to the metal barrier wall by metal bonding, and the second bonding metals are connected to the first copper pillars by metal bonding.

[0014] Preferably, the chip further includes a bottom chip, the electrical connection structure on the bottom chip being a plurality of pads, the bottom chip being disposed at the bottom of the groove, and the top chip being stacked on the bottom chip such that the pads of the bottom chip are exposed; a wafer-level process is used to set metal barriers on the carrier wafer corresponding to each carrier substrate, including the following steps: using a wafer-level process to set electrical connection lines, metal barriers, and a plurality of second copper pillars on the carrier wafer corresponding to each carrier substrate, the metal barriers surrounding the edge of the carrier substrate, the electrical connection lines being disposed between the metal barriers and the groove area, and the second copper pillars being disposed on the electrical connection lines; and The method further includes, after the step of providing a chip and placing the chip in the groove, electrically connecting the pads of the bottom chip to the electrical connection lines via leads; and the metal connection structure further includes a plurality of third bonding metals disposed corresponding to the second copper pillars. The step of covering the capping wafer on the metal barrier and connecting the first bonding metal to the metal barrier via metal bonding includes: covering the capping wafer on the metal barrier, connecting the first bonding metal to the metal barrier via metal bonding, connecting the second bonding metal to the first copper pillar via metal bonding, and connecting the third bonding metal to the second copper pillar via metal bonding.

[0015] Preferably, after the step of covering the capping wafer onto the metal barrier and connecting the first bonding metal to the metal barrier via metal bonding to seal the chip between the carrier substrate and the capping substrate, the method further includes: providing a redistribution layer on the side of the capping wafer away from the carrier wafer; the redistribution layer including a plurality of redistribution units corresponding to the capping substrate; the redistribution units being electrically connected to the second bonding metal and the third bonding metal; and the redistribution units having a docking portion for electrical connection to the outside world; and dicing the capping wafer and the carrier wafer to form a single packaged chip integrating the carrier substrate, the metal barrier, the bottom chip, the top chip, the capping substrate, the redistribution units, and the docking portion.

[0016] The present invention provides a hermetically sealed chip packaging method, comprising the following steps: providing a carrier wafer, wherein the carrier wafer is divided into a plurality of carrier substrates, each carrier substrate having a groove recessed into the center of the center, and each carrier substrate having a metal barrier surrounding its edge; providing a chip and placing the chip in the groove; providing a plurality of cap substrates, each cap substrate having a first bonding metal corresponding to the metal barrier; covering the corresponding metal barrier with the plurality of cap substrates, and connecting the first bonding metal to the metal barrier by metal bonding to seal the chip between the carrier substrate and the cap substrate.

[0017] Compared with the prior art, the present invention provides a groove for chip mounting on the carrier substrate, a metal barrier on the carrier substrate, and a first bonding metal on the cap substrate. This allows the carrier substrate and the cap substrate to be connected by a metal bonding process, resulting in good airtightness, simple process, compact structure, light weight, and low cost. Attached Figure Description

[0018] Figure 1 This is a structural diagram of the wafer carrier in an embodiment of the present invention.

[0019] Figure 2 This is a structural diagram of the wafer after a metal barrier, electrical connection lines, and a second copper pillar are installed on it, according to an embodiment of the present invention.

[0020] Figure 3 This is a structural diagram of the wafer after a groove has been formed on it, according to an embodiment of the present invention.

[0021] Figure 4 This is a structural diagram of the wafer-carrying groove after the bottom chip and the top chip are installed in the groove of the present invention.

[0022] Figure 5This is a structural diagram of the bottom chip after it is connected to the electrical connection line leads in an embodiment of the present invention.

[0023] Figure 6 This is a structural diagram of the capped wafer in an embodiment of the present invention.

[0024] Figure 7 This is a structural diagram of a capping wafer disposed on a carrier wafer in an embodiment of the present invention.

[0025] Figure 8 This is a structural diagram of the wafer after a redistribution layer is formed on the capped wafer in an embodiment of the present invention.

[0026] Figure 9 This is a structural diagram of the hermetic packaging structure of the chip according to an embodiment of the present invention.

[0027] Explanation of reference numerals in the attached diagram: 10. Carrier wafer; 1. Carrier substrate; 11. Metal barrier; 12. Electrical connection line; 13. Second copper pillar; 14. Groove; 21. Top chip; 211. First copper pillar; 212. First adhesive layer; 22. Bottom chip; 221. Pad; 222. Second adhesive layer; 3. Lead; 20. Cap wafer; 4. Cap substrate; 41. First bonding metal; 42. Third bonding metal; 43. Second bonding metal; 30. Rewiring layer; 301. Rewiring unit; 302. Solder ball. Detailed Implementation

[0028] To illustrate the technical content, structural features, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0029] Example 1 like Figure 9As shown, this embodiment of the invention provides a hermetically sealed chip packaging structure, including a carrier substrate 1 and a cap substrate 4. The carrier substrate 1 has a groove 14 recessed into the center of the carrier substrate 1, and a metal barrier 11 is provided around the edge of the carrier substrate 1. The groove 14 is located inside the metal barrier 11, and a chip is disposed in the groove 14. The cap substrate 4 is provided with a first bonding metal 41 corresponding to the metal barrier 11. The cap substrate 4 is disposed on the metal barrier 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding to seal the chip between the carrier substrate 1 and the cap substrate 4. Specifically, the carrier substrate 1 can be a silicon substrate, and the cap substrate 4 can be a ceramic substrate or a glass substrate. The metal barrier 11 can be formed on the carrier substrate 1 by electroplating. The metal barrier 11 is arranged around the perimeter of the groove 14. Correspondingly, the first bonding metal 41 is arranged around the edge of the cap substrate 4. The first bonding metal 41 can also be formed by electroplating. The first bonding metal 41 is arranged on the surface of the cap substrate 4. The metal barrier 11 and the first bonding metal 41 are connected by bonding to ensure a good connection between the metal barrier 11 and the first bonding metal 41, thereby sealing the chip between the carrier substrate 1 and the cap substrate 4, so that the packaged chip has good hermeticity. In addition, by opening the groove 14 on the carrier substrate 1 and placing the chip in the groove 14, the package size is also kept small.

[0030] The present invention provides a groove 14 for mounting the chip on the carrier substrate 1 and a metal barrier 11 on the carrier substrate 1, and a first bonding metal 41 on the cap substrate 4. The connection between the carrier substrate 1 and the cap substrate 4 can be achieved by metal bonding process, which has good airtightness, simple process, compact structure, light weight and low cost.

[0031] In embodiments of the present invention, such as Figure 9 As shown, the cap substrate 4 also has a through-hole metal connection structure, and the chip has an electrical connection structure. The metal connection structure is electrically connected to the electrical connection structure. Specifically, by setting a metal connection structure on the cap substrate 4 and using the metal connection structure to electrically connect with the chip, the chip can be electrically connected to external circuit boards and other devices.

[0032] In embodiments of the present invention, such as Figure 9 As shown, the chip includes a top chip 21, and the electrical connection structure on the top chip 21 consists of a plurality of first copper pillars 211. The metal connection structure includes a plurality of second bonding metals 43 disposed corresponding to the plurality of first copper pillars 211. The second bonding metals 43 are connected to the first copper pillars 211 by metal bonding so that the top chip 21 is electrically connected to the second bonding metals 43, resulting in a compact structure.

[0033] In embodiments of the present invention, such as Figure 9As shown, the chip also includes a bottom chip 22, on which the electrical connection structure consists of multiple pads 221. The bottom chip 22 is located at the bottom of the groove 14, and the top chip 21 is stacked on the bottom chip 22, exposing the pads 221 of the bottom chip 22. The substrate 1 also has an electrical connection line 12, which is located between the metal barrier 11 and the groove 14. The electrical connection line 12 has several second copper pillars 13, and the pads 221 of the bottom chip 22 are electrically connected to the electrical connection line 12. The metal connection structure also includes several third bonding metals 42 corresponding to the second copper pillars 13. The third bonding metals 42 are connected to the second copper pillars 13 by metal bonding, so that the bottom chip 22 is electrically connected to the third bonding metals 42.

[0034] Specifically, the second bonding metal 43 is connected to the first copper pillar 211, the third bonding metal 42, and the second copper pillar 13 through a metal bonding process. Thus, the connection between the metal barrier 11 and the first bonding metal 41, the second bonding metal 43 and the first copper pillar 211, the third bonding metal 42, and the second copper pillar 13 can be achieved through a single metal bonding process. The process is simple, the structure is compact, and the design is ingenious. Moreover, through the connection between the second bonding metal 43 and the first copper pillar 211, the third bonding metal 42, and the second copper pillar 13, the top chip 21 and the bottom chip 22 are respectively connected to the third bonding metal 42 and the second bonding metal 43, thereby enabling the top chip 21 and the bottom chip 22 to be electrically connected to the outside world.

[0035] In embodiments of the present invention, such as Figure 9 As shown, there are at least two bottom chips 22, which are stacked on top of each other and staggered to expose the pads 221 on the bottom chips 22. The top chip 21 is staggered with the adjacent bottom chip 22 to expose the pads 221 on the bottom chip 22. The pads 221 of the bottom chip 22 are connected to the electrical connection line 12 through the lead 3. Specifically, the bottom chip 22 and the top chip 21 can be the same or similar in size. The pads 221 on the bottom chip 22 can be located on one side of the bottom chip 22. By staggering them, the area where the pads 221 are located can be avoided, thus exposing the pads 221 of the bottom chip 22. Of course, in some other specific embodiments, at least two bottom chips 22 can also be successively smaller in size from bottom to top. In this way, the bottom chip 22 located on the upper layer is installed in the middle of the bottom chip 22 on the lower layer, and the pads 221 on the edge of the bottom chip 22 on the lower layer are exposed. Similarly, the size of the top chip 21 is smaller than the size of the adjacent bottom chip 22. The top chip 21 is installed in the middle of the adjacent bottom chip 22, and the pads 221 on the edge of the adjacent bottom chip 22 are exposed. Therefore, the connection method between the bottom chip 22 and the top chip 21 is not limited, as long as the pads 221 of the bottom chip 22 can be exposed.

[0036] In this embodiment of the invention, each top chip 21 has a first adhesive layer 212 on the side away from the first copper pillar 211, and each bottom chip 22 has a second adhesive layer 222 on the side away from the pad 221. The top chip 21 is connected to the adjacent bottom chip 22 through the first adhesive layer 212, and the adjacent bottom chips 22 are bonded together and the groove 14 is bonded to the adjacent bottom chip 22 through the second adhesive layer 222. The first adhesive layer 212 and the second adhesive layer 222 facilitate the connection between the bottom chips 22 and between the bottom chips 22 and the top chip 21. In addition, connecting the bottom chip 22 to the electrical connection line 12 through leads 3 such as gold wire or aluminum wire reduces manufacturing costs and does not occupy too much space.

[0037] In embodiments of the present invention, such as Figure 9 As shown, a redistribution unit 301 is also provided on the side of the cap substrate 4 away from the support substrate 1. The redistribution unit 301 is electrically connected to the metal connection structure. The redistribution unit 301 is provided with a docking part for electrical connection with the outside. Specifically, the redistribution unit 301 is electrically connected to the second bonding metal 43 and the third bonding metal 42. The docking part can be a solder ball 302, such as a solder ball. By providing the redistribution unit 301 and the docking part on the cap substrate 4, the electrical connection between the top chip 21 and the bottom chip 22 and external circuit boards and other devices can be realized.

[0038] Furthermore, the cap substrate 4 is provided with multiple first through holes and several second through holes. Second bonding metal 43 fills the first through holes to electrically connect with the redistribution unit 301 and the first copper pillar 211, respectively. Third bonding metal 42 fills the second through holes to electrically connect with the redistribution unit 301 and the second copper pillar 13, respectively. Specifically, the arrangement of the second and first through holes enables conductivity between the redistribution layer 30 on the outer side of the cap substrate 4 and the bottom chip 22 and top chip 21 on the inner side, resulting in a simple structure.

[0039] Example 2 like Figures 1 to 9 As shown, this embodiment of the invention also provides a hermetically sealed packaging method for a chip, used to fabricate the hermetically sealed packaging structure of the chip in the above embodiment. The hermetically sealed packaging method includes the following steps: S1. A carrier wafer 10 is provided, on which a plurality of carrier substrates 1 are divided. Each carrier substrate 1 has a groove 14 recessed into its center, and a metal barrier 11 surrounds the edge of each carrier substrate 1; specifically, as shown in... Figures 1 to 3 As shown, the carrier wafer 10 can be a silicon wafer, and the metal barrier 11 is arranged around the perimeter of the groove 14.

[0040] S2. Provide a chip and place the chip in the recess 14, specifically, as follows: Figures 4 to 5 As shown, by setting the groove 14 to accommodate the chip, the size of the packaged chip can be effectively reduced, resulting in a more compact structure.

[0041] S3. A capping wafer 20 is provided. The capping wafer 20 is divided into several capping substrates 4 corresponding to several carrier substrates 1. Each capping substrate 4 is provided with a first bonding metal 41 corresponding to the metal barrier 11. Specifically, the capping wafer 20 can be a ceramic wafer or a glass wafer. The first bonding metal 41 is disposed around the edge of the capping substrate 4. The first bonding metal 41 can be formed by electroplating process. The first bonding metal 41 is disposed on the surface of the capping substrate 4.

[0042] S4. The capped wafer 20 is placed on the metal barrier 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding to seal the chip between the carrier substrate 1 and the capping substrate 4. Specifically, as follows... Figure 7 As shown, the capping wafer 20 is directly placed on the metal barrier 11 of the carrier wafer, and the metal barrier 11 is connected to the first bonding metal 41 through a bonding process to ensure the connection effect between the metal barrier 11 and the first bonding metal 41, so that the packaged chip has good airtightness, compact structure, light weight and low cost.

[0043] In this embodiment of the invention, step S1, providing a carrier wafer 10, the carrier wafer 10 being divided into a plurality of carrier substrates 1, each carrier substrate 1 having a groove 14 recessed into the center of its center, and each carrier substrate 1 having a metal barrier 11 surrounding its edge, includes the following steps: S11. A carrier wafer 10 is provided, on which a plurality of carrier substrates 1 are defined, and each carrier substrate 1 has a recessed area in the middle; specifically, as shown in... Figure 1 as well as Figure 2 As shown, the division of the carrier wafer 10 into several carrier substrates 1 refers to the pre-planning of several carrier substrate 1 areas on the carrier wafer 10, specifically as follows: Figures 1 to 2 As shown by the dashed line in the image.

[0044] S12. Using wafer-level processes, metal barriers 11 are provided on the carrier wafer 10 corresponding to each carrier substrate 1. The metal barriers 11 surround the edge of the carrier substrate 1. Specifically, the metal barriers 11 can be formed on the carrier substrate 1 by electroplating.

[0045] S13. Etch the groove area of ​​the carrier wafer 10 to form a groove 14 that is recessed into the interior of the carrier wafer 10. Specifically, the processing method for the groove 14 is as follows: The carrier wafer 10 is pre-cleaned to remove surface contaminants and ensure a good initial surface condition; the carrier wafer 10 is loaded into the etching chamber, which is pre-baked to remove moisture and reduce gas contamination; a gas delivery system is set up within the etching chamber to ensure accurate supply of the required etching gases, such as CF4, CHF3, and Ar, as well as auxiliary gases, such as O2 and N2; the radio frequency power supply is activated to generate plasma. Active particles in the plasma, such as fluoride ions and fluoride radicals, contact the surface of the carrier wafer 10 and undergo a chemical reaction, etching away the silicon material in the groove area. The etching gas decomposes under the action of the plasma, generating highly reactive substances such as SiF4 and COF2. These byproducts are rapidly discharged from the chamber by the vacuum system, maintaining the continuous etching reaction. The physical bombardment of Ar ions helps enhance the etching effect, especially in cleaning the sidewalls of the etching trenches, which helps maintain the vertical etching profile; during the etching stage… Next, the process switches to a passivation gas, typically a silane gas such as SiH4 or Si2H6, sometimes with a small amount of O2 or N2. A thin and stable passivation film, such as silicon oxide or silicon nitride, is rapidly deposited on the trench sidewalls. The formation of the passivation film prevents further erosion of the sidewalls by the plasma in subsequent etching stages, thus maintaining the verticality of the etching and improving the aspect ratio. The thickness of the passivation film should be precisely controlled; it should not be too thick, which would reduce the etching rate, nor too thin, which would fail to effectively protect the sidewalls. The etching and passivation stages are alternated to form a dual-cycle loop. By precisely controlling the time, gas flow rate, and plasma parameters of each stage, a balance is maintained between the etching rate and the passivation film growth rate, gradually deepening the trench while maintaining a good sidewall morphology. When the predetermined etching depth is reached, plasma generation and gas injection are stopped, the RF power supply is turned off, and the etched silicon wafer is post-cleaned to remove residual etching byproducts and possible passivation film residues, ensuring surface cleanliness and preparing for subsequent process steps. Remove the carrier wafer 10 and complete the Bosch etching process to process the groove 14 in the groove area on the carrier wafer 10.

[0046] In this embodiment of the invention, the cap substrate 4 is further provided with a through-hole metal connection structure, and the chip is provided with an electrical connection structure. The metal connection structure is electrically connected to the electrical connection structure. Specifically, by providing a metal connection structure on the cap substrate 4 and using the metal connection structure to electrically connect with the chip, the chip can be electrically connected to external circuit boards and other devices.

[0047] In this embodiment of the invention, the chip includes a top chip 21, the electrical connection structure on the top chip 21 is a plurality of first copper pillars 211, and the metal connection structure includes a plurality of second bonding metals 43 disposed corresponding to the plurality of first copper pillars 211. In step S4, the step of covering the encapsulated wafer 20 onto the metal barrier 11 and connecting the first bonding metals 41 to the metal barrier 11 by metal bonding includes: S41. The capping wafer 20 is placed on the metal barrier 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding, and the second bonding metal 43 is connected to the first copper pillar 211 by metal bonding.

[0048] Furthermore, the chip also includes a bottom chip 22, the electrical connection structure of which consists of multiple pads 221. The bottom chip 22 is located at the bottom of the recess 14, and the top chip 21 is stacked on the bottom chip 22, exposing the pads 221 of the bottom chip 22. In step S12, a metal barrier 11 is set on the carrier wafer 10 corresponding to each carrier substrate 1 using a wafer-level process. The metal barrier 11 surrounds the edge of the carrier substrate 1. The step includes: S121. Using wafer-level technology, electrical connection lines 12, metal barriers 11, and several second copper pillars 13 are set on the carrier wafer 10 for each carrier substrate 1. The metal barriers 11 surround the edge of the carrier substrate 1, the electrical connection lines 12 are located between the metal barriers 11 and the groove 14 area, and the several second copper pillars 13 are set on the electrical connection lines 12. Specifically, the metal barriers 11, electrical connection lines 12, and second copper pillars 13 can be combined into one process to effectively save process steps and time. The fabrication method of the electrical connection line 12, the second copper pillar 13, and the metal barrier 11 is as follows: First, a circuit layer is formed on the carrier wafer 10. The circuit layer can be formed into a multi-layer structure through multiple seed layer deposition, exposure and development processes, and electroplating processes. Then, a first photoresist is spin-coated onto the circuit layer. The thickness of the first photoresist needs to be greater than the final height of the second copper pillar 13 and the metal barrier 11. The positions of the metal barrier 11 and the second copper pillar 13 are precisely defined by photolithography. Finally, the second copper pillar 13 and the metal barrier 11 are formed by electroplating. The column 13 is insulated from the metal barrier 11. The height of the second copper column 13 is tens of micrometers, for example, the height of the second copper column 13 is greater than or equal to 30 and less than or equal to 50 μm. The metal barrier 11 has the same height as the second copper column 13. The metal circuit formed by the electroplating process in the circuit layer is the electrical connection line 12. The electrical connection line 12 is connected and conductive to the second copper column 13. It should be noted that the electroplating process used in the production of the electrical connection line 12, the second copper column 13 and the metal barrier 11 is also a conventional process, which will not be described in detail here.

[0049] Step S2, providing a chip and placing the chip in the recess, further includes: S21, the pads 221 of the bottom chip 22 are electrically connected to the electrical connection line 12 via lead 3; specifically, as shown... Figure 3 as well as Figure 4As shown, lead wire 3, usually aluminum or gold wire, is used. The energy generated by the ultrasonic generator is used to rapidly expand and contract under the action of an ultra-high frequency electric field through the transducer to generate elastic vibration, causing the wedge-shaped cutter to vibrate accordingly. At the same time, a certain pressure is applied to the cutter, so the cutter drives the lead wire 3 to rub rapidly against the metallized layer surface of the soldering area, so that the lead wire 3 and the solder pad 221 or the lead wire 3 and the solder pad surface in the electrical connection line 12 make close contact to achieve interatomic bonding, thereby forming a soldered connection. In addition, the fabrication method of the top chip 21 is as follows: A first wafer is selected, specifically a 12-inch LPDDR5X wafer. The first wafer is cleaned using RCA standard cleaning to remove organic or metallic contaminants and natural oxidation. A first adhesion layer and a second seed layer are sequentially deposited on the first wafer. The material of the first adhesion layer can be Ti, Ta, or TaN. Then, a second photoresist is spin-coated onto the second seed layer. The thickness of the second photoresist must be greater than the final height of the first copper pillar 211. The position of the first copper pillar 211 is precisely defined by photolithography. The first copper pillar 211 is finally formed through electroplating. The height of the first copper pillar 211 is tens of micrometers, for example, greater than or equal to 30 μm and less than or equal to 50 μm. Then, the remaining second photoresist is removed, and the second seed layer and the first adhesion layer not covered by the first copper pillar 211 are etched away. Finally, the front side of the first wafer with circuitry is firmly bonded to a polishing tape. The back side of a wafer is ground and polished to precisely control the final thickness and thickness uniformity of the first wafer. The thickness of the thinned first wafer can be 100±5 micrometers. A polymer adhesive layer is adhered to the back side of the thinned first wafer, and then the adhesive layer is adhered to the dicing tape. A high-speed rotating ultra-thin diamond blade is used to precisely cut along the dicing path. Then, a laser of a specific wavelength, such as an ultraviolet laser, a green laser, or an infrared femtosecond laser, is used to ablate the material at the dicing path to reduce edge chipping and microcracks. During the dicing process, the adhesive layer and the first wafer are cut to form a top chip 21 with a first adhesive layer 212. However, the dicing tape is not cut or severed. The dicing tape is mechanically stretched to expand and tighten it, thereby increasing the gap between the top chips 21 to facilitate the subsequent pickup of the top chips 21. During the chip pickup process, the top chip 21 and the first adhesive layer 212 are picked up simultaneously. The fabrication method of the bottom chip 22 is basically the same as that of the top chip 21. The difference is that the bottom chip 22 does not require the fabrication of the first copper pillar 211. Instead, it only requires the fabrication of pads 221 at predetermined positions to form a bottom chip 22 with a second adhesive layer 222. The first adhesive layer 212 and the second adhesive layer 222 can be DAF films, i.e., the polymer adhesive layer is a DAF film. It should be noted that the electroplating, thinning, and cutting processes used in the fabrication of the top chip 21 and the bottom chip 22 are all existing processes and will not be described in detail here.When bottom chip 22 and bottom chip 21 are stacked, a vision alignment system can be used to ensure submicron level alignment accuracy by utilizing high-precision optical or laser alignment technology. Bottom chip 22 and top chip 21 are picked up from the cutting tape by a vacuum nozzle or mechanical ejector and stacked. After stacking, a pressure oven is used for baking at a temperature of 150 degrees Celsius to ensure that air bubbles in the first adhesive layer 212 and the second adhesive layer 222 are expelled.

[0050] In this embodiment of the invention, the metal connection structure further includes a plurality of third bonding metals 42 corresponding to the second copper pillar 13. Step S4, which involves covering the capping wafer 20 onto the metal barrier 11 and connecting the first bonding metal 41 to the metal barrier 11 via metal bonding, includes: S410. The capped wafer 20 is placed on the metal barrier 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding. The second bonding metal 43 is connected to the first copper pillar 211 by metal bonding, and the third bonding metal 42 is connected to the second copper pillar 13 by metal bonding. Specifically, when the first bonding metal 41 is bonded to the metal barrier 11, the second bonding metal 43 is simultaneously bonded to the first copper pillar 211, and the third bonding metal 42 and the second copper pillar 13 are also simultaneously bonded. Thus, the connection between the metal barrier 11 and the first bonding metal 41, the second bonding metal 43 and the first copper pillar 211, and the third bonding metal 42 and the second copper pillar 13 can be achieved through a single metal bonding process. The process is simple, the structure is compact, and the design is ingenious. It should be noted that the metal bonding process is an existing technology and will not be described in detail here.

[0051] Of course, in some other specific embodiments, the electrical connection structure of the bottom chip 22 can also be set as a copper pillar, so as to be directly bonded to the metal connection structure on the cap substrate 4.

[0052] In embodiments of the present invention, such as Figure 7As shown, the top surface of the metal barrier 11, the top surface of the second copper pillar 13, and the top surface of the first copper pillar 211 of the top chip 21 located in the groove 14 are all flush with each other; the bottom surfaces of the first bonding metal 41, the third bonding metal 42, and the second bonding metal 43 are all flush with each other. Specifically, the top surfaces of the metal barrier 11 and the second copper pillar 13 are flush to facilitate their fabrication. By controlling the height of the first copper pillar 211, after the top chip 21 is installed in the groove 14, the top surface of the first copper pillar 211 is flush with the top surface of the second copper pillar 13. Furthermore, multiple first through holes and several second through holes are provided on the cap substrate 4 on the capping wafer 20. The second bonding metal 43 fills the first through holes, and the third bonding metal 42 fills the second through holes. The lower surfaces of the third bonding metal 42 and the second bonding metal 43 protrude from the second and first through holes respectively, flush with the lower surface of the first bonding metal 41. Thus, when the capping wafer 20 is placed on the metal barrier 11, the first bonding metal 41... When the bonding metal 41 contacts the metal barrier 11, the third bonding metal 42 contacts the second copper pillar 13, and the second bonding metal 43 contacts the first copper pillar 211, which facilitates process control. Of course, in some other specific embodiments, the top surface of the metal barrier 11, the top surface of the second copper pillar 13, and the top surface of the first copper pillar 211 of the top chip 21 located in the groove 14 may not be flush with each other, and the bottom surfaces of the first bonding metal 41, the third bonding metal 42, and the second bonding metal 43 may not be flush with each other, as long as when the metal barrier 11 and the first bonding metal 41 are connected, the second copper pillar 13 and the third bonding metal 42 are in contact and connected, and the first copper pillar 211 is in contact and connected with the second bonding metal 43.

[0053] In this embodiment of the invention, after step S4, which involves covering the capped wafer 20 onto the metal barrier 11 and connecting the first bonding metal 41 to the metal barrier 11 via metal bonding to seal the chip between the carrier substrate 1 and the capped substrate 4, the method further includes: S5. A redistribution layer 30 is provided on the side of the capping wafer 20 away from the carrier wafer 10. The redistribution layer 30 includes a plurality of redistribution units 301 corresponding to the capping substrate 4. The redistribution units 301 are electrically connected to the second bonding metal 43 and the third bonding metal 42. The redistribution units 301 are provided with a docking portion for electrical connection with the outside world; specifically, as shown in... Figures 7 to 8As shown, the cap substrate 4 is provided with a plurality of first through holes and a plurality of second through holes. The second bonding metal 43 is filled in the first through holes to be electrically connected to the redistribution unit 301 and the first copper pillar 211 respectively. The third bonding metal 42 is filled in the second through holes to be electrically connected to the redistribution unit 301 and the second copper pillar 13 respectively. Through the setting of the first through holes and the second through holes, the redistribution layer 30 on the outside of the cap substrate 4 is connected to the bottom chip 22 and the top chip 21 on the inside. The structure is simple. The mating part can be a solder ball 302, such as a solder ball.

[0054] S6. The capping wafer 20 and the carrier wafer 10 are diced to form a single packaged chip integrating the carrier substrate 1, metal barrier 11, bottom chip 22, top chip 21, cap substrate 4, redistribution unit 301, and mating portion. Specifically, as shown... Figures 8 to 9 As shown, before cutting the capping wafer 20 and the carrier wafer 10, the carrier wafer 10 can be thinned first, and then the capping wafer 20 and the carrier wafer 10 can be cut at the wafer level to divide them into a single packaged chip that integrates the carrier substrate 1, the metal barrier 11, the bottom chip 22, the top chip 21, the cap substrate 4, the redistribution unit 301 and the docking part. The process is simple.

[0055] This invention employs wafer-level packaging technology, which involves batch processing on a single wafer and directly forming individual packaged chips after dicing. This reduces intermediate steps and lowers labor and equipment costs. Furthermore, wafer-level packaging concentrates dicing and testing steps at the wafer stage, shortening the production cycle. Additionally, wafer-level packaging has shorter interconnects, lower parasitic inductance and capacitance, making it suitable for high-frequency, high-speed scenarios (such as 5G filters), reducing signal attenuation by more than 30%. Moreover, the size of wafer-level packaging is close to that of a bare die, enabling chip-level packaging (CSP) to meet the miniaturization requirements of mobile terminals. Wafer-level packaging can be combined with technologies such as 2.5D / 3D stacking to achieve system-in-package (SiP), suitable for high-integration scenarios (such as RF front-end modules). The short interconnects and compact structure of wafer-level packaging also improve heat dissipation efficiency, making it suitable for scenarios with high thermal management requirements, such as 5G base stations and AI chips.

[0056] Example 3 The difference between this embodiment and Embodiment 2 is that: instead of providing a capped wafer 20, several capped substrates 4 are directly provided. Correspondingly, the hermetic packaging method for the chip includes the following steps: S10. A carrier wafer 10 is provided, on which a plurality of carrier substrates 1 are divided. Each carrier substrate 1 has a groove 14 recessed into its center, and a metal barrier 11 surrounds the edge of each carrier substrate 1; specifically, as shown in... Figures 1 to 3As shown, the carrier wafer 10 can be a silicon wafer, and the metal barrier 11 is arranged around the perimeter of the groove 14.

[0057] S20. Provide a chip and place the chip in the recess 14; such as Figures 4 to 5 As shown, by setting the groove 14 to accommodate the chip, the size of the packaged chip can be effectively reduced, resulting in a more compact structure.

[0058] S30. Provide a plurality of cap substrates 4, each cap substrate 4 having a first bonding metal 41 corresponding to the metal barrier 11; specifically, directly provide a plurality of individual cap substrates 4, and provide the first bonding metal 41 on the cap substrate 4. The first bonding metal 41 is disposed around the edge of the cap substrate 4. The first bonding metal 41 can be formed by electroplating process and is disposed on the surface of the cap substrate 4.

[0059] S40. Several cap substrates 4 are placed on corresponding metal barriers 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding to seal the chip between the carrier substrate 1 and the cap substrate 4. Specifically, each cap substrate 4 is placed on the corresponding metal barrier 11, and the metal barrier 11 is connected to the first bonding metal 41 by bonding process to ensure the connection effect between the metal barrier 11 and the first bonding metal 41, so that the packaged chip has good hermeticity, compact structure, light weight and low cost.

[0060] In this embodiment of the invention, step S10, providing a carrier wafer 10, the carrier wafer 10 being divided into a plurality of carrier substrates 1, each carrier substrate 1 having a groove 14 recessed into the center of its center, and each carrier substrate 1 having a metal barrier 11 surrounding its edge, includes the following steps: S110. A carrier wafer 10 is provided, on which a plurality of carrier substrates 1 are defined, and each carrier substrate 1 has a recessed area in the middle; specifically, as shown in... Figure 1 as well as Figure 2 As shown, the division of the carrier wafer 10 into several carrier substrates 1 refers to the pre-planning of several carrier substrate 1 areas on the carrier wafer 10, specifically as follows: Figures 1 to 2 As shown by the dashed line in the image.

[0061] S120. Using wafer-level processes, metal barriers 11 are provided on the carrier wafer 10 corresponding to each carrier substrate 1. The metal barriers 11 surround the edge of the carrier substrate 1. Specifically, the metal barriers 11 can be formed on the carrier substrate 1 by electroplating.

[0062] S130, the groove region of the carrier wafer 10 is etched to form a groove 14 recessed into the interior of the carrier wafer 10. Specifically, the structure and fabrication method of the carrier wafer 10 in this embodiment are the same as those in Embodiment 2, and will not be repeated here.

[0063] In this embodiment of the invention, the cap substrate 4 is further provided with a through-hole metal connection structure, and the chip is provided with an electrical connection structure. The metal connection structure is electrically connected to the electrical connection structure. Specifically, by providing a metal connection structure on the cap substrate 4 and using the metal connection structure to electrically connect with the chip, the chip can be electrically connected to external circuit boards and other devices.

[0064] In this embodiment of the invention, the chip includes a top chip 21, the electrical connection structure on the top chip 21 is a plurality of first copper pillars 211, and the metal connection structure includes a plurality of second bonding metals 43 disposed corresponding to the plurality of first copper pillars 211. In step S40, the step of covering a plurality of cap substrates 4 onto the corresponding metal barrier 11 and connecting the first bonding metals 41 to the metal barrier 11 by metal bonding includes: S401. Several cap substrates 4 are placed on the corresponding metal barrier 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding, and the second bonding metal 43 is connected to the first copper pillar 211 by metal bonding.

[0065] Furthermore, the chip also includes a bottom chip 22, the electrical connection structure of which consists of multiple pads 221. The bottom chip 22 is located at the bottom of the recess 14, and the top chip 21 is stacked on the bottom chip 22, exposing the pads 221 of the bottom chip 22. In step S120, a metal barrier 11 is set on the carrier wafer 10 corresponding to each carrier substrate 1 using a wafer-level process. The metal barrier 11 surrounds the edge of the carrier substrate 1. The step includes: S1201. Using wafer-level processes, electrical connection lines 12, metal barriers 11, and several second copper pillars 13 are provided on the carrier wafer 10 for each carrier substrate 1. The metal barriers 11 surround the edge of the carrier substrate 1, the electrical connection lines 12 are located between the metal barriers 11 and the groove 14 area, and the several second copper pillars 13 are disposed on the electrical connection lines 12. Specifically, the manufacturing process of the metal barriers 11, electrical connection lines 12, and second copper pillars 13 is the same as that of the metal barriers 11, electrical connection lines 12, and second copper pillars 13 in Embodiment 2, and will not be repeated here.

[0066] Step S20, providing a chip, placing the chip in the recess 14, further includes: S201. The pad 221 of the bottom chip 22 is electrically connected to the electrical connection line 12 through the lead 3. Specifically, the connection method between the bottom chip 22 and the electrical connection line 12 is the same as that in Embodiment 2, and will not be described again here.

[0067] In this embodiment of the invention, the metal connection structure further includes a plurality of third bonding metals 42 corresponding to the second copper pillar 13. Step S40, which involves covering the corresponding metal barrier 11 with a plurality of cap substrates 4 and connecting the first bonding metal 41 to the metal barrier 11 via metal bonding, includes: In step S4010, the cap substrate 4 is placed on the corresponding metal barrier 11, and the first bonding metal 41 is connected to the metal barrier 11 by metal bonding, the second bonding metal 43 is connected to the first copper pillar 211 by metal bonding, and the third bonding metal 42 is connected to the second copper pillar 13 by metal bonding.

[0068] It is understood that in the embodiments of the present invention, each cap substrate 4 is provided with a redistribution unit 301 on the side away from the carrier wafer 10. The redistribution unit 301 is electrically connected to the second bonding metal 43 and the third bonding metal 42. The redistribution unit 301 is provided with a docking part for electrical connection with the outside. Specifically, the docking part can be a solder ball 302, and the solder ball 302 can be, for example, a solder ball.

[0069] S60. The carrier wafer 10 is cut along the gap between adjacent cap substrates 4 to form a single packaged chip integrating the carrier substrate 1, metal barrier 11, bottom chip 22, top chip 21, cap substrate 4, redistribution unit 301, and mating portion. Specifically, as shown... Figure 9 As shown.

[0070] The above-disclosed examples are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention shall still fall within the scope of the present invention.

Claims

1. A hermetically sealed structure of a chip, characterized by, The application relates to a chip sealing structure, which comprises the following parts: a bearing substrate, a middle part of the bearing substrate is provided with a groove recessed to the inside of the bearing substrate, the edge of the bearing substrate is surrounded by a metal barrier wall, the groove is located on the inside of the metal barrier wall, and a chip is arranged in the groove; a cap substrate, the cap substrate is provided with first bonding metals corresponding to the metal barrier wall, the cap substrate is arranged on the metal barrier wall, and the first bonding metals are connected with the metal barrier wall through metal bonding to seal the chip between the bearing substrate and the cap substrate.

2. The hermetic package structure of a chip according to claim 1, wherein The cap substrate is further provided with metal connection structures penetrating the cap substrate, the chip is provided with electric connection structures, and the metal connection structures are electrically connected with the electric connection structures.

3. The hermetic package structure of a chip according to claim 2, wherein The chip comprises a top chip, the electric connection structures on the top chip are a plurality of first copper columns, the metal connection structures comprise a plurality of second bonding metals arranged corresponding to the first copper columns, and the second bonding metals are connected with the first copper columns through metal bonding to electrically connect the top chip with the second bonding metals.

4. The hermetic package structure of a chip according to claim 3, wherein The chip further comprises a bottom chip, the electric connection structures on the bottom chip are a plurality of pads, the bottom chip is arranged at the bottom of the groove, the top chip is arranged on the bottom chip and exposes the pads of the bottom chip, the bearing substrate is further provided with an electric connection circuit, the electric connection circuit is located between the metal barrier wall and the groove, a plurality of second copper columns are arranged on the electric connection circuit, and the pads of the bottom chip are electrically connected with the electric connection circuit. The metal connection structures further comprise a plurality of third bonding metals arranged corresponding to the second copper columns, and the third bonding metals are connected with the second copper columns through metal bonding to electrically connect the bottom chip with the third bonding metals.

5. The hermetic package structure of a chip according to claim 4, wherein The bottom chip is at least two, the at least two bottom chips are stacked and arranged in a staggered mode to expose the pads on the bottom chip, the top chip is arranged in a staggered mode with the adjacent bottom chip to expose the pads on the bottom chip, and the pads of the bottom chip are connected with the electric connection circuit through a lead wire.

6. The hermetic package structure of a chip according to claim 5, wherein The cap substrate is further provided with a rewiring unit on the side away from the bearing substrate, the rewiring unit is electrically connected with the metal connection structures, and the rewiring unit is provided with a docking part for electrically connecting with the outside.

7. A method of hermetically packaging a chip, characterized by, The application further relates to a chip sealing method, which comprises the following steps: providing a bearing wafer, the bearing wafer is divided into a plurality of bearing substrates, a middle part of each bearing substrate is provided with a groove recessed to the inside of the bearing substrate, and the edge of each bearing substrate is surrounded by a metal barrier wall; providing a chip and arranging the chip in the groove; providing a cover wafer, the cover wafer is divided into a plurality of cap substrates corresponding to the plurality of bearing substrates, and each cap substrate is provided with first bonding metals corresponding to the metal barrier wall; arranging the cover wafer on the metal barrier wall and connecting the first bonding metals with the metal barrier wall through metal bonding to seal the chip between the bearing substrate and the cap substrate.

8. The method of hermetically packaging a chip according to claim 7, wherein The application provides a carrier wafer, which is divided into a plurality of carrier substrates, a recess is arranged in the middle of each carrier substrate, and a metal barrier wall is arranged around the edge of each carrier substrate. The application provides a carrier wafer, which is divided into a plurality of carrier substrates, and a recess region is arranged in the middle of each carrier substrate. The application adopts a wafer-level process to arrange a metal barrier wall on the carrier wafer corresponding to each carrier substrate, and the metal barrier wall is arranged around the edge of the carrier substrate. The application etches the recess region of the carrier wafer to form a recess recessed into the carrier wafer.

9. The method of hermetically packaging a chip according to claim 8, wherein The cap substrate is further provided with a metal connection structure penetrating the cap substrate, the chip is provided with an electrical connection structure, the metal connection structure is electrically connected with the electrical connection structure, the chip comprises a top chip, the electrical connection structure on the top chip is a plurality of first copper columns, and the metal connection structure comprises a plurality of second bonding metals arranged corresponding to the plurality of first copper columns. The application arranges the cover wafer on the metal barrier wall and connects the first bonding metal and the metal barrier wall through metal bonding. The application arranges the cover wafer on the metal barrier wall and connects the first bonding metal and the metal barrier wall through metal bonding, and connects the second bonding metal and the first copper column through metal bonding.

10. The method of hermetically packaging a chip according to claim 9, wherein The chip further comprises a bottom chip, the electrical connection structure on the bottom chip is a plurality of pads, the bottom chip is arranged at the bottom of the recess, and the top chip is arranged on the bottom chip and exposes the pads of the bottom chip. The application adopts a wafer-level process to arrange a metal barrier wall on the carrier wafer corresponding to each carrier substrate, and the metal barrier wall is arranged around the edge of the carrier substrate. The application further comprises the following steps after the step of arranging the chip in the recess: The application connects the pads of the bottom chip and the electrical connection line through a lead. The metal connection structure further comprises a plurality of third bonding metals arranged corresponding to the second copper columns, the application arranges the cover wafer on the metal barrier wall and connects the first bonding metal and the metal barrier wall through metal bonding. The application arranges the cover wafer on the metal barrier wall and connects the first bonding metal and the metal barrier wall through metal bonding, and connects the second bonding metal and the first copper column through metal bonding and connects the third bonding metal and the second copper column through metal bonding.

11. The method of hermetically packaging a chip according to claim 10, wherein The application arranges the cover wafer on the metal barrier wall and connects the first bonding metal and the metal barrier wall through metal bonding to seal the chip between the carrier substrate and the cap substrate. A redistribution layer is arranged on the side of the cover wafer away from the carrier wafer, the redistribution layer comprising a plurality of redistribution units arranged corresponding to the cap substrates, the redistribution units being electrically connected with the second bonding metal and the third bonding metal, and the redistribution units being provided with a docking portion for electrical connection with the outside world; The cover wafer and the carrier wafer are cut to form a single packaged chip integrating the carrier substrate, the metal barrier, the bottom chip, the top chip, the cap substrate, the redistribution unit and the docking portion.

12. A method of hermetically packaging a chip, characterized by, The method comprises the following steps: A carrier wafer is provided, the carrier wafer being divided into a plurality of carrier substrates, each of the carrier substrates being provided with a recessed groove in the middle portion of the carrier substrate, and each of the carrier substrates being surrounded by a metal barrier at the edge thereof; A chip is provided and arranged in the recessed groove; A plurality of cap substrates are provided, each of the cap substrates being provided with a first bonding metal corresponding to the metal barrier; The cap substrates are arranged on the corresponding metal barriers, and the first bonding metal is connected with the metal barrier by metal bonding to seal the chip between the carrier substrate and the cap substrate.

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