Single-frequency laser interference rapid distance measurement method based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a single-frequency laser interference rapid distance measurement method based on an FPGA, and the method comprises the steps: transmitting four paths of interference electric signals to a four-channel AD conversion daughter card through a photoelectric detector, and converting the four paths of interference electric signals into four paths of interference digital signals; the FPGA main board receives the four interference digital signals and transmits the four interference digital signals to a cache region in an FPGA chip; the method comprises the following steps: designing an FPGA (Field Programmable Gate Array) parallel pipeline architecture, synchronously carrying out differential calculation on received signals to obtain two paths of interference signals while receiving the signals, and simultaneously detecting extreme values of the two paths of interference signals for error correction; the two paths of corrected interference signals are subjected to arc tangent operation through the CORDIC IP core in sequence to obtain phase data, and finally the phase data are subjected to unwrapping and direction distinguishing processing and are converted into displacement data. The method can effectively improve the calculation speed of a laser interference distance measurement algorithm, realizes real-time displacement detection while guaranteeing the nanoscale measurement precision, and has a wide engineering application prospect in the fields of precision measurement, semiconductor manufacturing and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA hardware algorithm acceleration, and particularly relates to a single-frequency laser interference fast ranging method based on FPGA. BACKGROUND

[0002] With the development of nanometer processing, precision manufacturing, precision assembly and other industries, the demand for high-precision micro displacement measurement is increasing. In the field of high-precision displacement measurement, single-frequency laser interference technology is widely used in semiconductor manufacturing, precision machining and metrology detection due to its stable wavelength, high precision and strong anti-interference ability.

[0003] The traditional single-frequency laser interference ranging system usually relies on CPU or GPU for signal processing. Such general processing platforms mainly use serial processing architecture and need to bear additional overheads such as multi-task scheduling and system resource allocation, resulting in significant computational delay of signal processing, insufficient real-time response capability, difficulty in matching MHz-level high-speed sampling frequency in nanometer resolution scenarios, and inability to process continuously output interference signals synchronously. Moreover, the traditional interference signal error correction algorithm mostly uses an ellipse fitting algorithm, which needs to solve model parameters through complex matrix operation and iterative optimization, and has high computational complexity and large amount of calculation, making it difficult to adapt to the real-time processing needs of high-speed measurement scenarios, and thus becoming a key technical bottleneck restricting the measurement accuracy and response speed of the system.

[0004] In view of the poor real-time performance of the existing single-frequency laser interference ranging, Simon Rerucha proposed a nonlinear error correction scheme based on vector method and trigonometric function in the article “Detection of Interference Phase by Digital Computation of Quadrature Signals in Homodyne Laser Interferometry correction”, which effectively simplifies the algorithm process and significantly reduces the amount of calculation. However, this method still relies on the host computer for core calculation, which is difficult to adapt to the real-time needs of displacement measurement. SUMMARY

[0005] In order to overcome the shortcomings of the above-mentioned prior art, the present application provides a single-frequency laser interference fast ranging method based on FPGA. This method utilizes the parallel processing capability and pipeline structure design of FPGA to modularize and optimize the processes of interference signal collection, difference, extreme value detection, bias and amplitude correction, non-orthogonal error elimination, phase calculation and unwrapping, realizes real-time response and efficient processing of four-way interference signals, and finally achieves high-speed real-time output of displacement data.

[0006] The technical solution for achieving this invention is: a fast single-frequency laser interferometry ranging method based on FPGA, comprising the following steps:

[0007] S1 uses a single-frequency laser interferometric rangefinder to detect and collect the interference light intensity signal generated by the movement of the object under test. The photodetector receives four interference light intensity signals and converts them into four interference electrical signals. The four-channel AD conversion card receives four interference electrical signals and converts them into four interference digital signals. The FPGA motherboard receives four interference digital signals and transmits them to the FPGA on-chip buffer area, then proceeds to S2.

[0008] S2 utilizes an FPGA parallel pipeline architecture to perform real-time differential operations on the four interferometric digital signals while they are continuously transmitted and input, obtaining two interferometric signals. These two interferometric signals are then fed in parallel into an extremum detection unit to obtain the maximum value of the first interferometric signal in real time. and minimum value The maximum value of the second interference signal and minimum value Then switch to S3.

[0009] S3, utilizing extreme values , , , Real-time DC bias correction and AC unequal amplitude correction are performed on the two interference signals to obtain two interference signals after eliminating DC and AC errors. While completing the correction of the current clock cycle, the above extreme parameters are updated for real-time correction in the next clock cycle, and then the process proceeds to S4.

[0010] S4 performs non-orthogonal error correction on the two interference signals after eliminating DC and AC errors, resulting in two orthogonal interference signals, and then proceeds to S5.

[0011] S5, normalize the two orthogonal interference signals to obtain two normalized orthogonal interference signals, then proceed to S6.

[0012] S6: Perform arctangent operation on the two normalized orthogonal interference signals to obtain the phase data of the orthogonal interference signals, and then proceed to S7.

[0013] S7: Perform differential operation on the phase data of the orthogonal interference signal between adjacent sampling points to obtain phase difference data. Simultaneously perform phase expansion and direction discrimination processing on the phase difference data to obtain unwrapped phase difference data, and then proceed to S8.

[0014] S8 converts the unwrapped phase difference data into displacement difference data based on the linear relationship between phase and displacement, and calculates the displacement value by accumulating the data, thereby realizing real-time detection of the displacement of the object under test.

[0015] Compared with the prior art, the present application has the following advantages: the present application provides a single-frequency laser interference fast ranging method based on FPGA, which uses FPGA as the core computing power support to realize algorithm hardware acceleration, and uses a parallel pipeline architecture to synchronize and cooperate with each processing link, thereby greatly improving the algorithm processing efficiency; meanwhile, through real-time detection and dynamic updating of signal parameters, the algorithm process is further simplified, and finally the calculation processing speed is significantly improved under the premise of ensuring the measurement accuracy, thereby effectively meeting the real-time ranging demand in high-speed scenarios.

[0016] Figure 1 A flowchart of a single-frequency laser interference fast ranging method based on FPGA. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0018] In combination Figure 1 A single-frequency laser interference fast ranging method based on FPGA, and the steps are as follows:

[0019] S1, a single-frequency laser interferometer is used to detect and collect the interference light intensity signals generated by the movement of a to-be-measured object, four interference light intensity signals are received by a photoelectric detector and converted into four interference electric signals, a four-channel AD conversion subcard receives the four interference electric signals and converts them into four interference digital signals, and an FPGA mainboard receives the four interference digital signals and transmits them to an FPGA on-chip buffer area.

[0020] The to-be-measured object in the single-frequency laser interferometer is driven to displace by a PZT, and the four interference light intensity signals formed during the movement of the to-be-measured object are received by a photoelectric detector; four photoelectric detectors perform voltage amplification and low-pass filtering on the collected four interference light intensity signals to form four interference electric signals, which are transmitted to a four-channel AD conversion subcard through an SMA interface; the four-channel AD conversion subcard completes analog-to-digital conversion on the four interference electric signals to generate four interference digital signals, which are transmitted to an FPGA on-chip buffer area through an FMC interface.

[0021] Go to S2.

[0022] S2, using the FPGA parallel pipeline architecture, while the four-way interference digital signals are continuously transmitted, the FPGA performs real-time difference operation on the four-way interference digital signals to obtain two-way interference signals; the two-way interference signals are sent into the extreme value detection unit in parallel to obtain the maximum value and the minimum value of the first-way interference signal and the maximum value and the minimum value of the second-way interference signal .

[0023] The difference calculation divides the four-way interference digital signals into two groups by performing two-way difference operation on the four-way interference digital signals, and obtains two-way interference signals by performing difference operation on the two-way interference digital signals in the same group; the extreme value detection unit adopts a parallel comparison structure to realize real-time extreme value monitoring of the difference interference signals and dynamically update the maximum value and the minimum value of the two-way interference signals in the continuous signal sampling process 、 、 、 .

[0024] The innovation of the application lies in that the parallel comparison structure is adopted to continuously and dynamically update the extreme value in the continuous signal sampling process, which always matches the current signal state, greatly improves the accuracy of error correction, and further guarantees the accuracy of subsequent phase calculation and displacement conversion.

[0025] Turn to S3.

[0026] S3, using the extreme value 、 、 、 to perform real-time direct current bias correction and alternating current unequal amplitude correction on the two-way interference signals to obtain two-way interference signals after eliminating direct current and alternating current errors, while completing the correction in the current clock period, the above extreme value parameters are updated for real-time correction in the next clock period.

[0027] The direct current bias correction and alternating current unequal amplitude correction are the maximum value and the minimum value 、 、 、 of the two-way interference signals 、 、 、 corresponding correction parameters are calculated, the two-way interference signals are corrected in real time by using the correction parameters to obtain two-way interference signals after eliminating direct current and alternating current errors; the correction parameters are updated at the same time, the direct current bias and amplitude correction parameters are adaptively changed, so that the dynamic real-time correction of the interference signals is realized; the corresponding direct current bias correction and alternating current unequal amplitude correction formula is:

[0028] ,

[0029] wherein represents the first path interference signal, represents the second path interference signal, represents the first path interference signal after eliminating DC and AC errors, represents the second path interference signal after eliminating DC and AC errors; , , , all represent correction parameters.

[0030] Go to S4.

[0031] S4, non-orthogonal error correction is performed on the two paths of interference signals after eliminating DC and AC errors, to obtain two paths of orthogonal interference signals.

[0032] The non-orthogonal error correction is to eliminate non-orthogonal errors by using addition and subtraction operations on the two paths of interference signals after eliminating DC and AC errors. The specific formula is:

[0033] ,

[0034] wherein represents the first path orthogonal interference signal, represents the second path orthogonal interference signal.

[0035] Go to S5.

[0036] S5, normalization processing is performed on the two paths of orthogonal interference signals, to obtain two paths of normalized orthogonal interference signals.

[0037] The normalization processing reads the maximum value and the minimum value of the two paths of orthogonal interference signals by extreme value detection, respectively, and then performs division operation on the two paths of orthogonal interference signals and the corresponding maximum values, respectively, to complete the normalization processing; the normalization operation and the above-mentioned AC unequal amplitude correction adopt consistent extreme value driving mechanism and synchronous updating rules, to ensure that the two paths of corrected signals meet the subsequent phase calculation requirements in terms of amplitude consistency and orthogonality.

[0038] Go to S6.

[0039] S6, arctangent operation is performed on the two paths of normalized orthogonal interference signals, to obtain orthogonal interference signal phase data.

[0040] The arccotangent operation is implemented by a CORDIC IP core to implement arccotangent calculation, and the IP core is used for coordinate rotation and shift operation of preset angles by iteration to approach a target angle to obtain the phase data of the quadrature interference signal.

[0041] The innovation of the present application is that the CORDIC IP core is used to implement the arccotangent operation of the interference signal to reduce the FPGA resource consumption while ensuring high-precision phase data, and to adapt to the real-time processing requirements of laser interferometric distance measurement.

[0042] Go to S7.

[0043] S7, difference operation is performed on the phase data of the quadrature interference signal to obtain phase difference data, and the phase difference data is simultaneously subjected to phase unwrapping and direction discrimination processing to obtain unwrapped phase difference data.

[0044] The difference operation is a subtraction operation on adjacent sampling points of the phase data of the quadrature interference signal according to a sampling sequence to obtain phase difference data; and the phase difference data is simultaneously subjected to phase unwrapping and direction discrimination processing based on a preset reference threshold, wherein the phase unwrapping is used to eliminate the ambiguity error of the phase data, and the direction discrimination processing is used to determine the moving direction of the object to be measured. Finally, the unwrapped phase difference data without ambiguity and with clear direction is obtained.

[0045] Go to S8.

[0046] S8, according to the linear relationship between the phase and the displacement, the unwrapped phase difference data is converted into displacement difference data, and the displacement change is calculated by accumulation to realize real-time detection of the displacement of the object to be measured.

[0047] The linear relationship between the phase and the displacement is used to convert the unwrapped phase difference data into displacement difference data, and then the displacement difference data under continuous time sequence is calculated in real time according to the sampling time sequence to obtain the displacement value of the object to be measured.

[0048] The innovation of the present application is that the parallel processing characteristics of FPGA are used to realize real-time accumulation calculation of displacement, which realizes real-time output of displacement change and continuously reflects the cumulative displacement state of the object to be measured in the whole measurement process, solving the problem that the traditional non-real-time processing cannot synchronously track the displacement change in the whole process.

[0049] In summary, the present application uses FPGA to replace the traditional computing platform, relies on parallel pipeline architecture to greatly improve the algorithm processing efficiency, and further simplifies the algorithm process through real-time detection and dynamic update of signal parameters, finally significantly improves the calculation speed under the premise of ensuring measurement accuracy, and meets the real-time measurement requirements in high-speed scenarios.

[0050] Example 1:

[0051] This invention employs a single-frequency laser interferometric rangefinder to detect and acquire interference signals generated by the movement of the object under test. A photodetector receives four interference light intensity signals and converts them into four interference electrical signals. A four-channel AD conversion daughter card receives the four interference electrical signals and converts them into four interference digital signals. The FPGA motherboard receives the four interference digital signals and transmits them to the FPGA's on-chip buffer. The photodetector module has a bandwidth of 10MHz, a wavelength range of 400~1100nm, a photosensitive surface diameter of 1.2mm, and a maximum output voltage of 5V. The AD conversion daughter card uses an LTC2270 chip, which has dual-channel synchronous sampling capability, adopts a 16-bit A / D converter structure, and has a power bandwidth of 200MHz. The core chip of the FPGA motherboard is a Xilinx Kintex UltraScale XCKU115, providing 1451K system logic units, 75.9 Mb of Block RAM, and 5520 DSP units.

[0052] S1, the photodetector receives the corresponding four interference light intensity signals during the movement of the object under test, and inputs them to the AD conversion card via the SMA interface. The AD conversion card converts the four interference analog signal data into four interference digital signals. , , , The data is transmitted to the FPGA motherboard via the FMC interface.

[0053] S2 performs differential operations on the four-channel interferometric digital signal streams, subtracting adjacent sets of signals to obtain two corresponding differential signals.

[0054] The formula for calculating the difference is:

[0055] ,

[0056] in Indicates the first The first interference signal at each sampling time, Indicates the first The second interference signal at each sampling time. Indicates the first The first interference digital signal at each sampling time, Indicates the first The second interferometric digital signal at each sampling time, Indicates the first The third interferometric digital signal at each sampling time, Indicates the first The fourth interferometric digital signal at each sampling time.

[0057] Simultaneously, a parallel comparison hardware structure is employed to synchronously acquire the maximum value of the corresponding first interference signal. Minimum value Maximum value of cosine differential signal Minimum value In practice, the maximum and minimum values ​​mentioned above within the first interference cycle are read as initial error correction parameters. Subsequently, in the second interference cycle, these parameters are dynamically updated based on the differential signal acquired in real time, thereby achieving accurate tracking of the extreme value characteristics of the differential signal and real-time optimization of error correction.

[0058] S3, utilizing , , , Calculate the DC and AC correction parameters, and perform DC bias correction and amplitude normalization on the two interference signals.

[0059] The formulas for DC bias correction and AC unequal amplitude correction are as follows:

[0060] ,

[0061] in Indicates the first The first interference signal after eliminating DC and AC errors at each sampling time. Indicates the first The interference signal after eliminating DC and AC errors at each sampling time is the second path.

[0062] when , , , When an update occurs, the correction parameters are updated synchronously in the next clock cycle, and the updated correction parameters are used to perform DC bias correction and amplitude normalization update operations on the differential signal in the next clock cycle.

[0063] S4, for the two interference signals after eliminating DC and AC errors. , Perform non-orthogonal error correction.

[0064] The formula for calculating non-orthogonal error correction is:

[0065] ,

[0066] in Indicates the first The first orthogonal interference signal at each sampling time. Indicates the first The second orthogonal interference signal at each sampling time.

[0067] S5, using parallel comparison hardware structure, synchronously obtaining the maximum value , the maximum value , based on the extreme value, calculating the corresponding normalized correction parameter, and performing normalization processing on the two-way orthogonal interference signal; when detecting that the extreme value is updated, synchronously and dynamically updating the correction parameter, and immediately applying it to the normalization process of the subsequent signal, to ensure real-time matching of the correction accuracy and the signal characteristics.

[0068] The normalization calculation formula is:

[0069] ,

[0070] wherein denotes the first normalized orthogonal interference signal at the i-th sampling moment, denotes the second normalized orthogonal interference signal at the i-th sampling moment.

[0071] S6, using the Vivado CORDIC IP core to perform arctangent calculation on the normalized orthogonal interference signal, and performing corresponding configuration on the IP core: selecting Arc Tan function in mode, setting the architecture to parallel mode, setting the pipeline mode to optimal, setting the output format to Scaled Radians, and setting the input and output bit width to 16 bits, to realize the arctangent calculation function based on Cartesian coordinate input through clock and asynchronous reset control, and finally obtain the phase data of the orthogonal interference signal.

[0072] S7, performing beat processing on the phase data to delay it by one clock period; subtracting the original phase data stream from the beat-processed phase data stream to obtain the phase difference data between adjacent sampling intervals; performing phase unwrapping on the phase difference data, and combining the reference threshold to perform phase direction determination to obtain continuous phase difference data.

[0073] The phase unwrapping and direction determination formula is:

[0074] ,

[0075] ,

[0076] ,

[0077] ,

[0078] ,

[0079] wherein, denotes the i-th sampling moment, ​​Phase difference data at each sampling time, Indicates the first Phase data of orthogonal interference signals at each sampling time.

[0080] S8 combines the laser wavelength parameters to convert continuous phase difference data into displacement difference data; finally, the displacement difference data under continuous time series is accumulated and calculated in real time according to the sampling time sequence to obtain the displacement value of the object under test.

[0081] The displacement calculation formula is:

[0082] ,

[0083] in, Indicates the first Displacement difference data at each sampling time. This represents the displacement value at time n, where n represents the total number of sampling times. This indicates the center wavelength of the laser.

[0084] In summary, this application proposes a fast single-frequency laser interferometric ranging method based on FPGA. By building a parallel pipeline framework within the FPGA, operations such as differential calculation, extremum identification, and phase solving of the interference signal are migrated to the FPGA for hardware-level acceleration. Furthermore, the algorithm is decomposed into multiple functional modules for cascaded processing. This design effectively reduces the overall latency, thereby achieving real-time displacement detection while ensuring nanometer-level measurement accuracy.

[0085] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to the above embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0086] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A FPGA-based single-frequency laser interference fast ranging method, characterized in that, It comprises the following steps: S1, using a single frequency laser interferometer to detect the interference light intensity signal generated by the movement of the object to be measured, the photoelectric detector receives four-way interference light intensity signal into four-way interference electric signal, four-channel AD conversion sub-card receives four-way interference electric signal into four-way interference digital signal, FPGA mainboard receives four-way interference digital signal, and transmits to FPGA chip cache area, and turns into S2; S2 utilizes an FPGA parallel pipeline architecture to perform real-time differential operations on the four interferometric digital signals while they are continuously transmitted and input, obtaining two interferometric signals. These two interferometric signals are then fed in parallel into an extremum detection unit to obtain the maximum value of the first interferometric signal in real time. and minimum value The maximum value of the second interference signal and minimum value Switch to S3; S3, using the extreme value , , , The two-way interference signal is corrected in real time by direct current bias and alternating current unequal amplitude, and the two-way interference signal after eliminating direct current and alternating current error is obtained. While completing the correction of the current clock period, the extreme value parameter is updated for real-time correction of the next clock period, and S4 is entered. S4, the two-way interference signal after eliminating direct current and alternating current error is corrected, and two-way orthogonal interference signal is obtained, and S5 is turned into; S5, the two-way orthogonal interference signal is normalized, and two-way normalized orthogonal interference signal is obtained, and S6 is turned into; S6, the two-way normalized orthogonal interference signal is operated by inverse tangent, and the phase data of the orthogonal interference signal is obtained, and S7 is turned into; S7, the phase data of the orthogonal interference signal is operated by adjacent sampling point difference, and the phase difference data is obtained, and the phase difference data is simultaneously operated by phase unfolding and direction identification, and the unwrapped phase difference data is obtained, and S8 is turned into; S8, according to the linear relationship between phase and displacement, the unwrapped phase difference data is converted into displacement difference data, and the displacement value is obtained by accumulation calculation, so as to realize real-time detection of the displacement of the object to be measured.

2. The FPGA-based single-frequency laser interference fast ranging method according to claim 1, characterized in that, S1, as follows: The object to be measured in the single frequency laser interferometer is driven by the PZT to displace, and the four-way interference light intensity signal formed in the movement process is received by the photoelectric detector; four photoelectric detectors amplify and low-pass filter the four-way interference light intensity signal collected, form four-way interference electric signal, and transmit to four-channel AD conversion sub-card through SMA interface; four-channel AD conversion sub-card completes analog-digital conversion of four-way interference electric signal, generates four-way interference digital signal, and transmits to FPGA chip cache area through FMC interface.

3. The FPGA-based single-frequency laser interference fast ranging method according to claim 2, characterized in that, S2, as follows: The difference calculation divides the four-way interference digital signals into two groups by performing two-way difference operation on the four-way interference digital signals, and obtains two-way interference signals by performing difference operation on two-way interference digital signals in the same group. , , , .

4. The FPGA-based single-frequency laser interference fast ranging method according to claim 3, characterized in that, S3, as follows: Maximum and minimum values of two-path interference signals 、 、 、 corresponding correction parameters are calculated, the two-path interference signals are corrected in real time by direct current bias correction and alternating current unequal amplitude correction using the correction parameters, and two-path interference signals after eliminating direct current and alternating current errors are obtained; 、 、 、 The correction parameters are updated synchronously at the same time, and the direct current bias and amplitude correction parameters are adaptively changed, so that dynamic real-time correction of the interference signals is realized. Wherein, the formula of direct current bias correction and alternating current unequal amplitude correction is: ， wherein represents the first interference signal, represents the second interference signal, represents the first interference signal after elimination of DC and AC errors, represents the second interference signal after elimination of DC and AC errors; , , , all represent correction parameters.

5. The FPGA-based single-frequency laser interference fast ranging method according to claim 4, characterized in that, In S4, two-way interference signal after eliminating direct current and alternating current error is corrected by addition and subtraction operation to eliminate non-orthogonal error, and two-way orthogonal interference signal is obtained, as follows: ， wherein represents the first path quadrature interferometric signal, represents the second path quadrature interferometric signal.

6. The FPGA-based single-frequency laser interference fast ranging method according to claim 5, characterized in that, In S5, two-way orthogonal interference signal is normalized to obtain two-way normalized orthogonal interference signal, as follows: The two orthogonal interference signals are normalized, that is, the maximum values of the two orthogonal interference signals are respectively read through extreme value detection and the minimum values are read, and then the two orthogonal interference signals are respectively divided by the corresponding maximum values to complete the normalization processing; the normalization operation and the above-described AC unequal amplitude correction adopt consistent extreme value driving mechanisms and synchronous updating rules to ensure that the corrected two signals meet the subsequent phase calculation requirements in terms of amplitude consistency and orthogonality.

7. The FPGA-based single-frequency laser interference fast ranging method according to claim 6, characterized in that, In S6, two-way normalized orthogonal interference signal is operated by inverse tangent to obtain interference signal phase data, as follows: CORDIC IP core is used to realize inverse tangent calculation, and the above IP core is used to approximate the target angle by coordinate rotation and shift operation of preset angle through iteration, and the orthogonal interference signal phase data is obtained.

8. The FPGA-based single-frequency laser interference fast ranging method according to claim 7, characterized in that: In S7, the phase data of the quadrature interference signal is sequentially subjected to subtraction operation on adjacent sampling points in a sampling sequence to obtain phase difference data; based on a preset reference threshold, the phase difference data is simultaneously subjected to phase unwrapping and direction discrimination processing, wherein the phase unwrapping is used to eliminate the ambiguity error of the phase data, and the direction discrimination processing is used to determine the moving direction of the object to be measured, so as to finally obtain the unwrapped phase difference data without ambiguity and with clear direction. In S7, the phase data of the quadrature interference signal is sequentially subjected to subtraction operation on adjacent sampling points in a sampling sequence to obtain phase difference data; based on a preset reference threshold, the phase difference data is simultaneously subjected to phase unwrapping and direction discrimination processing, wherein the phase unwrapping is used to eliminate the ambiguity error of the phase data, and the direction discrimination processing is used to determine the moving direction of the object to be measured, so as to finally obtain the unwrapped phase difference data without ambiguity and with clear direction.

9. The FPGA-based single-frequency laser interference fast ranging method according to claim 8, characterized in that: In S8, according to the linear relationship between phase and displacement, the unwrapped phase difference data is converted into displacement difference data, and then the displacement difference data under continuous time sequence is accumulated and calculated in real time according to sampling time sequence, and the displacement value of the object to be measured is obtained.

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