Preparation method of multi-depth silicon waveguide

Abstract

The invention provides a preparation method of a multi-depth silicon waveguide, which comprises the following steps of: providing a semiconductor substrate provided with a lower cladding and a silicon layer which are sequentially stacked from bottom to top, forming a hard mask layer on the silicon layer, patterning the hard mask layer based on a first photomask to form a first opening and a second opening, forming a first photoresist layer on the hard mask layer and patterning the first photoresist layer based on a second photomask, etching the silicon layer to form a first groove with a first depth in a first preset groove region, removing the first photoresist layer, and forming a second groove with a second depth in a second preset groove region; and forming a second photoresist layer on the hard mask layer and patterning the second photoresist layer based on a third photomask, etching the silicon layer to form a second groove with a second depth in a second preset groove region, the second depth being different from the first depth, and removing the second photoresist layer. According to the preparation method of the multi-depth silicon waveguide, the photomask cost in process preparation can be saved, and the process steps are simplified.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of silicon optoelectronics, and relates to a preparation method of a multi-depth silicon waveguide. BACKGROUND

[0002] In a silicon-based photonic device, a silicon waveguide mainly undertakes the functions of optical wave transmission and connection of different optical devices. In order to realize low-loss optical transmission, a silicon waveguide device with low roughness and high verticality needs to be prepared. In addition, the silicon waveguide often has several different depths, such as 70 nm, 150 nm and 220 nm. In the process preparation, it is usually necessary to repeatedly perform the steps of "hard mask deposition, photolithography, etching, trench filling, hard mask deposition, photolithography, etching, trench filling..." to realize the preparation of different depths. This set of method is complex in process and high in cost.

[0003] Therefore, how to provide a preparation method of a multi-depth silicon waveguide to save the mask cost in the process preparation, reduce the deposition times of the thin film, and maintain good etching performance while simplifying the process steps has become an important problem to be solved by the person skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of the person skilled in the art. The above technical scheme cannot be considered as known to the person skilled in the art only because it is described in the background section of the present application. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a preparation method of a multi-depth silicon waveguide, which is used to solve the problems of complex process preparation and high cost of the multi-depth silicon waveguide in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a multi-depth silicon waveguide, which at least comprises the following steps:

[0007] A semiconductor substrate is provided, and a lower cladding layer and a silicon layer are sequentially stacked on the semiconductor substrate from bottom to top, wherein the silicon layer comprises a first preset groove area and a second preset groove area;

[0008] A hard mask layer is formed on the silicon layer, and the hard mask layer is patterned based on a first mask to form a first opening and a second opening which respectively expose the first preset groove area and the second preset groove area;

[0009] A first photoresist layer is formed on the hard mask layer, and the first photoresist layer is patterned based on a second mask, wherein the patterned first photoresist layer covers the second opening and exposes the first opening;

[0010] etching the silicon layer based on the patterned first photoresist layer to form a first recess having a first depth in the first pre-set recess region, and then removing the first photoresist layer;

[0011] forming a second photoresist layer on the hard mask layer, patterning the second photoresist layer based on a third mask, the patterned second photoresist layer covering the first opening and exposing the second opening;

[0012] etching the silicon layer based on the patterned second photoresist layer to form a second recess having a second depth in the second pre-set recess region, the second depth being different from the first depth, and then removing the second photoresist layer.

[0013] Optionally, the first depth is less than the second depth.

[0014] Optionally, the first depth ranges from 60 nm to 80 nm.

[0015] Optionally, the second depth ranges from 140 nm to 160 nm.

[0016] Optionally, the silicon layer further comprises a third pre-set recess region, after patterning the hard mask layer based on the first mask, the hard mask layer further comprises a third opening exposing the third pre-set recess region, and before removing the hard mask layer, a step of forming a third recess is further included:

[0017] forming a third photoresist layer on the hard mask layer, patterning the third photoresist layer based on a fourth mask, the patterned third photoresist layer covering the first opening and the second opening and exposing the third opening;

[0018] etching the silicon layer based on the patterned third photoresist layer to form the third recess in the third pre-set recess region, and then removing the third photoresist layer.

[0019] Optionally, the second mask and the third mask have a precision less than that of the first mask.

[0020] Optionally, the third recess has a third depth, and the third depth is greater than the second depth.

[0021] Optionally, the third depth ranges from 210 nm to 230 nm.

[0022] Optionally, the hard mask layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence from bottom to top.

[0023] Optionally, the method further comprises a step of removing the hard mask layer.

[0024] As described above, the method for preparing a multi-depth silicon waveguide of the present application comprises the steps of: providing a semiconductor substrate, the semiconductor substrate having a lower cladding layer and a silicon layer stacked in sequence from bottom to top, the silicon layer comprising a first preset recess region and a second preset recess region; forming a hard mask layer on the silicon layer, patterning the hard mask layer based on a first mask to form a first opening and a second opening respectively exposing the first preset recess region and the second preset recess region; forming a first photoresist layer on the hard mask layer, patterning the first photoresist layer based on a second mask, the patterned first photoresist layer covering the second opening and exposing the first opening; etching the silicon layer based on the patterned first photoresist layer to form a first recess with a first depth in the first preset recess region, and then removing the first photoresist layer; forming a second photoresist layer on the hard mask layer, patterning the second photoresist layer based on a third mask, the patterned second photoresist layer covering the first opening and exposing the second opening; etching the silicon layer based on the patterned second photoresist layer to form a second recess with a second depth in the second preset recess region, the second depth being different from the first depth, and then removing the second photoresist layer. The method for preparing a multi-depth silicon waveguide of the present application transfers the patterns of silicon waveguiders with different depths onto the hard mask layer at the same time through one high-precision mask, and then covers the areas that do not need to be etched in each step by several low-precision photoresist layers to etch the recesses with corresponding depths, thereby saving the cost of masks in the process of preparation, reducing the number of thin film deposition, and maintaining good etching performance while simplifying the process steps. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 shows a structural schematic diagram of a multi-depth silicon waveguide.

[0026] Figure 2 shows a schematic diagram of the structure of a semiconductor substrate in the method for preparing a multi-depth silicon waveguide of the present application.

[0027] Figure 3 shows a schematic diagram of the structure obtained after forming a hard mask layer in the method for preparing a multi-depth silicon waveguide of the present application.

[0028] Figure 4 shows a schematic diagram of the structure obtained after forming a first opening and a second opening in the method for preparing a multi-depth silicon waveguide of the present application.

[0029] Figure 5 shows a schematic diagram of the structure obtained after forming a first photoresist layer in the method for preparing a multi-depth silicon waveguide of the present application.

[0030] Figure 6A schematic diagram showing the structure obtained after forming a first recess in the preparation method of the multi-depth silicon waveguide of the present application.

[0031] Figure 7 A schematic diagram showing the structure obtained after forming a second photoresist layer in the preparation method of the multi-depth silicon waveguide of the present application.

[0032] Figure 8 A schematic diagram showing the structure obtained after forming a second recess in the preparation method of the multi-depth silicon waveguide of the present application.

[0033] Figure 9 A schematic diagram showing the structure obtained after forming a third photoresist layer in the preparation method of the multi-depth silicon waveguide of the present application.

[0034] Figure 10 A schematic diagram showing the structure obtained after forming a third recess in the preparation method of the multi-depth silicon waveguide of the present application.

[0035] Figure 11 A schematic diagram showing the structure of the multi-depth silicon waveguide of the present application.

[0036] BRIEF DESCRIPTION OF DRAWINGS

[0037] 101 Silicon substrate 102 Silicon oxide layer 103 Top silicon layer 104, 104a, 104b, 104c Groove 201 Semiconductor substrate 202 Lower cladding layer 203 Silicon layer 204 Hard mask layer 2041 First silicon oxide layer 2042 Silicon nitride layer 2043 Second silicon oxide layer 205 First opening 206 Second opening 207 Third opening 208 First photoresist layer 209 First groove 210 Second photoresist layer 211 Second groove 212 Third photoresist layer 213 Third groove I First preset groove area II Second preset groove area III Third preset groove area D1 First depth D2 Second depth D3 Third depth S1-S6 Step DETAILED DESCRIPTION

[0038] Referring to Figure 1 , a schematic diagram showing the structure of a multi-depth silicon waveguide, comprising a silicon substrate 101, a silicon oxide layer 102 and a top layer of silicon 103, a plurality of recesses 104 are formed in the top layer of silicon 103, and the plurality of recesses 104 have three different depths, wherein one of the recesses 104a has a depth of 700 angstroms, another of the recesses 104b has a depth of 1500 angstroms, and the other of the recesses 104c has a depth of 2200 angstroms. Due to the different depths of the recesses 104, in the process of preparation, it is usually necessary to go through multiple steps of "hard mask deposition, photolithography, etching, trench filling, hard mask deposition, photolithography, etching, trench filling…" to realize the preparation of the recesses, which makes the preparation method process complex and the cost relatively high.

[0039] To this end, the present application proposes a preparation method of a multi-depth silicon waveguide, which can save the cost of the mask in the process of preparation, reduce the number of times of thin film deposition, and maintain good etching performance while simplifying the process steps by introducing a plurality of photoresist layers to cover the hard mask layer.

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0042] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0043] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0045] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] Please see Figure 2 The diagram shows a process flow chart of the fabrication method of the multi-depth silicon waveguide of the present invention, which includes at least the following steps:

[0048] S1: providing a semiconductor substrate, the semiconductor substrate has a lower cladding layer and a silicon layer stacked in sequence from bottom to top, the silicon layer includes a first preset recessed area and a second preset recessed area;

[0049] S2: forming a hard mask layer on the silicon layer, patterning the hard mask layer based on a first mask to form a first opening and a second opening respectively exposing the first preset recessed area and the second preset recessed area;

[0050] S3: forming a first photoresist layer on the hard mask layer, patterning the first photoresist layer based on a second mask, the patterned first photoresist layer covers the second opening and exposes the first opening;

[0051] S4: etching the silicon layer based on the patterned first photoresist layer to form a first recess with a first depth in the first preset recessed area, and then removing the first photoresist layer;

[0052] S5: forming a second photoresist layer on the hard mask layer, patterning the second photoresist layer based on a third mask, the patterned second photoresist layer covers the first opening and exposes the second opening;

[0053] S6: etching the silicon layer based on the patterned second photoresist layer to form a second recess with a second depth in the second preset recessed area, the second depth is different from the first depth, and then removing the second photoresist layer.

[0054] The specific implementation of each step will be described in detail in combination with the structural diagram.

[0055] First, please refer to Figure 3 , execute step S1: provide a semiconductor substrate 201, the semiconductor substrate 201 has a lower cladding layer 202 and a silicon layer 203 stacked in sequence from bottom to top, the silicon layer 203 includes a first preset recessed area I and a second preset recessed area II.

[0056] As an example, the semiconductor substrate 201 adopts a silicon substrate as a physical support, does not participate in light transmission, and only provides mechanical stability.

[0057] As an example, the lower cladding layer 202 adopts a silicon dioxide layer, the refractive index of silicon dioxide is 1.45, and the refractive index of the silicon layer 203 is 3.45, so that the vertical confinement of light can be realized through the refractive index difference between the two.

[0058] Please refer to Figure 4, performing step S2: forming a hard mask layer 204 on the silicon layer 203, patterning the hard mask layer 204 based on a first mask to form a first opening 205 and a second opening 206 respectively exposing the first preset groove region I and the second preset groove region II.

[0059] As an example, the hard mask layer 204 includes a first silicon oxide layer 2041, a silicon nitride layer 2042 and a second silicon oxide layer 2043 stacked in sequence from bottom to top.

[0060] Please refer to Figure 5 , performing step S3: forming a first photoresist layer 208 on the hard mask layer 204, patterning the first photoresist layer 208 based on a second mask, and the patterned first photoresist layer 208 covers the second opening 206 and exposes the first opening 205.

[0061] Specifically, the first photoresist layer 208 covers the hard mask layer 204 on the region outside the first preset groove region I.

[0062] Please refer to Figure 6 , performing step S4: etching the silicon layer 203 based on the patterned first photoresist layer 208 to form a first groove 209 with a first depth D1 in the first preset groove region I, and then removing the first photoresist layer 208.

[0063] As an example, the first depth D1 ranges from 60 nm to 80 nm, for example, the first depth D1 is 65 nm, 70 nm, 75 nm.

[0064] As an example, the number of the first grooves 209 is multiple, in this embodiment, the number of the first grooves 209 is three, accordingly, the number of the first preset groove regions I is multiple, the number of the first openings 205 is multiple, that is, the number of the first grooves 209, the first preset groove regions I and the first openings 205 remains equal, in this embodiment, the number of the first preset groove regions I is three, the number of the first openings 205 is three.

[0065] Please refer to Figure 7 , performing step S5: forming a second photoresist layer 210 on the hard mask layer 204, patterning the second photoresist layer 210 based on a third mask, and the patterned second photoresist layer 210 covers the first opening 205 and exposes the second opening 206.

[0066] Specifically, the second photoresist layer 210 covers the hard mask layer 204 on the region outside the second preset groove region II.

[0067] Referring back to Figure 8 , a step S6 is performed: etching the silicon layer 203 based on the patterned second photoresist layer 210 to form a second recess 211 with a second depth D2 in the second predetermined recess region II, the second depth D2 being different from the first depth D1, and then removing the second photoresist layer 210.

[0068] As an example, the first depth D1 is less than the second depth D2.

[0069] As an example, the second depth D2 ranges from 140 nm to 160 nm, for example, the second depth D2 is 145 nm, 150 nm, or 155 nm.

[0070] In the embodiment, the number of the second recess 211 is one, and in other embodiments, the number of the second recess 211 can also be multiple, and correspondingly, the number of the second predetermined recess region II can also be multiple, and the number of the second opening 206 can also be multiple, that is, the numbers of the second recess 211, the second predetermined recess region II, and the second opening 206 remain equal.

[0071] The preparation method shown in the above steps S1 to S6 can realize etching of multiple recesses with different depths through one hard mask layer 204, avoiding repeated steps of hard mask deposition, hard mask lithography, and hard mask etching, simplifying the process steps, and at the same time, using the same hard mask layer 204 can also reduce the risk of cumulative defects such as lithography alignment error and etching deviation, so as to maintain good etching performance and save process cost.

[0072] As an example, referring to Figure 9 and Figure 10 , the silicon layer 203 further includes a third predetermined recess region III, after the hard mask layer 210 is patterned based on the first mask, the hard mask layer 210 further includes a third opening 207 that exposes the third predetermined recess region III, and before the hard mask layer 210 is removed, a step of forming a third recess 213 is further included:

[0073] (1) Referring back to Figure 9 , a third photoresist layer 212 is formed on the hard mask layer 204, and the third photoresist layer 212 is patterned based on a fourth mask, and the patterned third photoresist layer 212 covers the first opening 205 and the second opening 206 and exposes the third opening 207;

[0074] (2) Referring back to Figure 10etching the silicon layer 203 based on the third photoresist layer 212 after the patterning, to form the third groove 213 in the third preset groove area III, and removing the third photoresist layer 212.

[0075] For example, the second mask and the third mask have a precision less than that of the first mask, that is, a high-precision mask is used to transfer different-depth silicon waveguide patterns to the hard mask layer 204 at the same time, and then a plurality of low-precision photoresist layers (including the first photoresist layer 208, the second photoresist layer 210, and the third photoresist layer 212) are used to cover areas that do not need to be etched at each step, so as to etch the corresponding-depth pattern groove (including the first groove 209, the second groove 211, and the third groove 213). This can save mask costs in the process of preparation, reduce the number of thin film deposition, and simplify the process steps while maintaining good etching performance.

[0076] For example, the third groove 213 has a third depth D3, and the third depth D3 is greater than the second depth D2.

[0077] For example, the third depth D3 is in the range of 210 nm to 230 nm, for example, the third depth D3 is 215 nm, 220 nm, or 225 nm.

[0078] In this embodiment, the number of the third groove 213 is one, and in other embodiments, the number of the third groove 213 can also be multiple, and correspondingly, the number of the third preset groove area III can also be multiple, and the number of the third opening 207 can also be multiple, that is, the number of the third groove 213, the third preset groove area III, and the third opening 207 is equal.

[0079] For example, refer to Figure 11 The method further includes the step of removing the hard mask layer 204.

[0080] In summary, the preparation method of the multi-depth silicon waveguide includes the following steps: providing a semiconductor substrate, the semiconductor substrate is sequentially stacked with a lower cladding layer and a silicon layer from bottom to top, the silicon layer includes a first preset recessed groove area and a second preset recessed groove area; forming a hard mask layer on the silicon layer, patterning the hard mask layer based on a first mask to form a first opening and a second opening which respectively expose the first preset recessed groove area and the second preset recessed groove area; forming a first photoresist layer on the hard mask layer, patterning the first photoresist layer based on a second mask, the patterned first photoresist layer covers the second opening and exposes the first opening; etching the silicon layer based on the patterned first photoresist layer to form a first recessed groove with a first depth in the first preset recessed groove area, and then removing the first photoresist layer; forming a second photoresist layer on the hard mask layer, patterning the second photoresist layer based on a third mask, the patterned second photoresist layer covers the first opening and exposes the second opening; etching the silicon layer based on the patterned second photoresist layer to form a second recessed groove with a second depth in the second preset recessed groove area, the second depth is different from the first depth, and then removing the second photoresist layer. The preparation method of the multi-depth silicon waveguide transfers the silicon waveguide patterns with different depths onto the hard mask layer at the same time through one high-precision mask, and then covers each area that does not need to be etched by several low-precision photoresist layers in subsequent etching with different depths, and etches the recessed groove with the corresponding depth. In this way, the mask cost in the process preparation can be saved, the number of thin film deposition times is reduced, and the etching performance is maintained while the process steps are simplified. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0081] The above embodiments only illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a multi-depth silicon waveguide, comprising: The method comprises the following steps: providing a semiconductor substrate, wherein a lower cladding layer and a silicon layer are sequentially stacked on the semiconductor substrate from bottom to top, and the silicon layer comprises a first preset recess region and a second preset recess region; forming a hard mask layer on the silicon layer, and patterning the hard mask layer based on a first mask to form a first opening and a second opening respectively exposing the first preset recess region and the second preset recess region; forming a first photoresist layer on the hard mask layer, patterning the first photoresist layer based on a second mask, and the patterned first photoresist layer covers the second opening and exposes the first opening; etching the silicon layer based on the patterned first photoresist layer to form a first recess with a first depth in the first preset recess region, and then removing the first photoresist layer; forming a second photoresist layer on the hard mask layer, patterning the second photoresist layer based on a third mask, and the patterned second photoresist layer covers the first opening and exposes the second opening; etching the silicon layer based on the patterned second photoresist layer to form a second recess with a second depth in the second preset recess region, the second depth being different from the first depth, and then removing the second photoresist layer.

2. The method of claim 1, wherein: The first depth is less than the second depth.

3. The method of claim 1, wherein: The first depth ranges from 60 nm to 80 nm.

4. The method of claim 1, wherein: The second depth ranges from 140 nm to 160 nm.

5. The method of claim 1, wherein the method further comprises: The silicon layer further comprises a third preset recess region, after patterning the hard mask layer based on the first mask, the hard mask layer further has a third opening exposing the third preset recess region, and before removing the hard mask layer, a step of forming a third recess is further included: forming a third photoresist layer on the hard mask layer, patterning the third photoresist layer based on a fourth mask, and the patterned third photoresist layer covers the first opening and the second opening and exposes the third opening; etching the silicon layer based on the patterned third photoresist layer to form the third recess in the third preset recess region, and removing the third photoresist layer.

6. The method of claim 5, wherein: The accuracy of the second mask and the third mask is less than the accuracy of the first mask.

7. The method of claim 5, wherein: The third recess has a third depth, and the third depth is greater than the second depth.

8. The method of claim 7, wherein: The third depth ranges from 210 nm to 230 nm.

9. The method of claim 1, wherein: The hard mask layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer sequentially stacked from bottom to top.

10. The method of claim 1, wherein: The method further comprises a step of removing the hard mask layer.

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