PCIe data link recovery method and PCIe system

Abstract

The invention provides a PCIe data link recovery method and a PCIe system, and relates to the technical field of PCIe communication. When it is determined that the current board card is an EP end, obtaining an MODprel signal, and determining whether the MODprel signal is a low level; wherein the MODprel signal is used for indicating whether the optical module is in place or not; if the MODprel signal is at the low level, acquiring a first RXLOS signal, and judging whether the first RXLOS signal is at the low level or not; wherein the first RXLOS signal is used for indicating whether the optical signal is in place; if yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so that the data link is recovered; wherein the RSSI signal is used for representing the magnitude of the optical power. The PCIe system has the effect that the PCIe system can automatically reestablish the link after the optical module or the optical fiber cable is plugged and unplugged.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of PCIe communication, in particular to a PCIe data link recovery method and a PCIe system. BACKGROUND

[0002] The PCIe (Peripheral Component Interconnect express) interface is a standard interface for connecting components to a computer. The uplink PCIe interface is used for communication with the motherboard CPU (Central Processing Unit), and the downlink port is used for PCIe peripheral communication; dynamic configuration can also be performed through the PCIe pseudo port. The application of PCIe generally includes the following cases: 1. In a high-performance computing platform, the motherboard may be integrated with multiple CPUs, GPUs (Graphic Processing Unit) or other accelerators, and connected through a PCIe bus.

[0003] 2. In a high-performance storage solution, NVMe SSD (Non-Volatile Memory Express Solid State Drive) occupies a key position, and multiple NVMe SSDs need to be connected to the motherboard through a PCIe bus.

[0004] 3. In various AICs (Add-In Cards) including AI (Artificial Intelligence) accelerators, NICs (Network Interface Controllers), and storage expansion cards, they are also basically interconnected with server devices through PCIe interfaces.

[0005] In the above PCIe application scenarios, the problem of long PCIe signal line paths caused by large-scale integration or size structure needs to be solved. Currently, an optical transmission solution combining retimer (re-timer) technology and optical modules can be used. This combination can support transmission distances of up to tens of meters. When using optical fibers for high-speed data transmission, the retimer chip helps to convert and recover electrical signals, effectively overcoming the problems of signal attenuation and distortion caused by fiber length and medium differences. Therefore, this solution not only ensures the data transmission rate and stability under long distances, but also provides a flexible and reliable interconnection means for large-scale data centers.

[0006] However, due to the hot-pluggable nature of the optical module itself, the optical fiber line also has pluggability, so after stable chain transmission, if some conditions (such as replacing the optical module or the optical fiber) occur, the optical module is hot-plugged or the optical fiber is plugged, the data link will be interrupted, and after the optical path is restored, the PCIe system cannot automatically complete the re-chain, and manual intervention is required to reset the RC end (Root Complex, root end) or the EP end (Endpoint, endpoint) to restore the chain of the entire PCIe system, and the flexibility is poor, which is inconvenient for use.

[0007] In summary, the prior art has the problem that the PCIe system cannot automatically complete the re-chain when the optical module is hot-plugged or the optical fiber is plugged. SUMMARY

[0008] The purpose of the present application is to provide a PCIe data link recovery method and a PCIe system to solve the problem that the PCIe system cannot automatically complete the re-chain when the optical module is hot-plugged or the optical fiber is plugged in the prior art.

[0009] In order to achieve the above-mentioned purpose, the technical solutions adopted by the embodiments of the present application are as follows: On the one hand, the embodiments of the present application provide a PCIe data link recovery method, which is applied to the MCU of the EP end in the PCIe system, the EP end further includes a retimer chip and an optical module, and the MCU is connected with the retimer chip and the optical module respectively; the method comprises: When it is determined that the current board card is the EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is low; wherein the MODprel signal is used to indicate whether the optical module is in place; If the MODprel signal is low, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low; wherein the first RXLOS signal is used to indicate whether the optical signal is in place; If yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so as to restore the data link; wherein the RSSI signal is used to represent the size of the optical power.

[0010] Optionally, the step of resetting the PCIe data link according to the value of the RSSI signal to restore the data link comprises: When the value of the RSSI signal is greater than a threshold value, the PCIe data link is reset; A second RXLOS signal is acquired, and it is determined whether the second RXLOS signal is low; If no, it is determined whether the data link is recovered; If yes, it is determined whether to continue resetting the PCIe data link according to the number of times of resetting the PCIe data link.

[0011] Optionally, the step of determining whether to continue resetting the PCIe data link according to the number of times of resetting the PCIe data link comprises: determining whether the number of times of resetting the PCIe data link is greater than a set value; If yes, a fault signal is generated, and the resetting of the PCIe data link is stopped; If no, the PCIe data link is reset again, and a counter is incremented by one.

[0012] Optionally, the EP end further comprises a power supply unit for supplying power to the retimer chip, and the power supply unit is connected with the MCU, and the step of resetting the PCIe data link comprises: controlling the power supply unit to perform a power-off first and then power-on operation, or controlling the retimer chip to reset.

[0013] Optionally, after the step of acquiring the RSSI signal, the method further comprises: determining whether the RSSI signal has a return value; If yes, the step of resetting the PCIe data link according to the value of the RSSI signal is performed; If no, the step of acquiring the MODprel signal and determining whether the MODprel signal is a low level is returned.

[0014] Optionally, before the step of determining that the current board card is an EP end, the method further comprises: when the end device selection pin of the MCU is a high level signal, it is determined that the current board card is an EP end; when the end device selection pin of the MCU is a low level signal, it is determined that the current board card is an RC end.

[0015] Optionally, after the step of determining that the current board card is an RC end, the method further comprises: providing an RC end normal power-on condition, and continuously acquiring the signal of the optical module.

[0016] Optionally, after the step of determining whether the MODprel signal is a low level, the method further comprises: when the MODprel signal is a high level, the MODprel signal is continuously acquired, and in the case that the MODprel signal jumps from a high level to a low level, the step of acquiring the RSSI signal is performed.

[0017] Optionally, after the step of determining whether the first RXLOS signal is low, the method further comprises: If the first RXLOS signal is high, it is determined that the data link is working normally.

[0018] In another aspect, the embodiments of the present application also provide a PCIe system, which comprises an RC end and an EP end, the RC end and the EP end each comprise a retimer chip and an optical module, and the RC end and the EP end are connected through the optical module; the EP end further comprises an MCU, and the MCU is used to execute the PCIe data link recovery method.

[0019] Compared with the prior art, the present application has the following beneficial effects: The present application provides a PCIe data link recovery method and a PCIe system, the method is applied to an MCU of an EP end in a PCIe system, the EP end further comprises a retimer chip and an optical module, and the MCU is connected with the retimer chip and the optical module respectively; when it is determined that the current board card is the EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is low; wherein the MODprel signal is used to indicate whether the optical module is in place; if the MODprel signal is low, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low; wherein the first RXLOS signal is used to indicate whether the optical signal is in place; if yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so as to recover the data link; wherein the RSSI signal is used to represent the size of the optical power. In the PCIe data link recovery method provided by the present application, the MCU comprehensively determines the current optical path condition by monitoring the MODprel signal, the RXLOS signal and the RSSI signal of the optical module pin, and determines to reset the PCIe data link in combination with the signal condition, thereby realizing data link recovery, and realizing the effect that the PCIe system can automatically re-establish a link and recover the data communication function when the optical module is plugged in or out at the EC side or the EP side, or the optical fiber line is plugged in or out.

[0020] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are referred to for detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0022] Figure 1 The structure schematic diagram of the PCIe system provided by the present application.

[0023] Figure 2 The exemplary flowchart of the PCIe data link recovery method provided by the present application.

[0024] Figure 3 The module schematic diagram of the EP end provided by the present application.

[0025] Figure 4 The overall flowchart of the PCIe data link recovery method provided by the present application.

[0026] In the drawings: 110-MCU; 120-retimer chip; 130-optical module; 140-power supply unit. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of the present application.

[0029] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0030] It should be noted that, in this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0031] Some embodiments of the present application will be described in detail with reference to the drawings, which are shown by way of illustration. The following examples and features of the examples can be combined with each other, without conflict.

[0032] As described in the background, in the current PCIe scenario, most of them are faced with the problem of long PCIe signal line path due to large-scale integration or size structure. In order to solve this problem, generally through the way of adding PCIe retimer chip on the signal path to maintain the integrity of the signal. With the use of PCIe retimer chip, the problem of signal attenuation caused by long distance transmission can be effectively overcome, and the stability and efficiency of data transmission can be ensured, so as to support complex computing requirements and high-performance operation environment, even on the design of complex large-size motherboard, reliable high-speed data transmission can be realized.

[0033] However, in practical application, even if the PCIe retimer supported line insertion loss is added, the maximum insertion loss is only 36db, and the maximum transmission cable supported is not more than 1 meter. With the continuous development of technology, the further improvement of signal bandwidth, the emergence of larger-scale integrated computing platform, server platform, and some new application environments (such as vehicle-mounted), the traditional way of expanding PCIe wiring path through retimer chip shows more and more limitations. Taking the PCIe 5.0 retimer chip as an example, it can support a maximum of 1000mil board-level wiring and 2 connect (independent physical connection point or connector) path insertion loss, facing higher PCIe transmission rate (PCIe 6.0\7.0), and more complex integrated environment, the line supported by PCIe retimer chip cannot meet the demand.

[0034] Therefore, in order to realize the demand for long-distance high-speed data transmission, such as high-speed interconnection inside the data center or the data center machine room, it is necessary to use an optical transmission solution combining retimer technology and optical modules. This combination can support transmission distances of up to tens of meters. When using optical fiber for high-speed data transmission, the retimer chip helps to convert and restore electrical signals, effectively overcoming the problems of signal attenuation and distortion caused by the length of optical fiber and the difference in medium. Therefore, this scheme not only ensures the data transmission rate and stability under long distance, but also provides a flexible and reliable interconnection means for large-scale data centers.

[0035] However, in the scheme combining the retimer technology and the optical module, since the optical module itself has the hot-pluggable characteristic, the optical fiber line also has the pluggable characteristic, and thus after the stable link transmission, if some situation (such as replacing the optical module or the optical fiber) occurs, the data link will be interrupted when the optical module is hot-plugged or the optical fiber is plugged. After the optical path is recovered, the PCIe system cannot automatically complete the re-linking, and manual intervention is required to reset the RC end or the EP end, and then the PCIe system recovers the link, and the flexibility is poor, which is inconvenient for use.

[0036] Therefore, in order to solve the above problems, the PCIe data link recovery method is provided to automatically re-establish the data link after the optical module and the optical fiber are plugged, so as to achieve the purpose of recovering the data communication function.

[0037] It should be noted that the PCIe data link recovery method provided by the present application is applied to the MCU of the EP end in the PCIe system, and the structure of the PCIe system provided by the present application is shown in Figure 1

[0038] As shown in Figure 1 The PCIe system includes the RC end (the left part in the figure) and the EP end (the right part in the figure), and the structures of the RC end and the EP end are basically the same, and both include the PCIe board card (CEM board in the figure), the retimer chip 120 and the optical module 130 (QSFP_DD in the figure). For the RC end, the retimer chip 120 is arranged on the PCIe board card and is inserted into the gold finger slot of the server end through the gold finger, and the server end is provided with a CPU. The data is converted into the optical signal through the 2 QSFP-DD packaged LPO (Linear-drive Pluggable Optics, linear-drive pluggable optical module) to build 16 PCIe electrical signals, and is connected with the PCIe board card of the EP end through the optical fiber.

[0039] ​For the EP end, the retimer chip 120 is also arranged on the PCIe board card, and the optical module 130 of the EP end converts the optical signal into an electrical signal to access the retimer chip 120, and then is connected to the corresponding EP device through a slot (slot in the figure) on the PCIe board card to realize signal transmission. Once the optical module 130 is plugged or the optical fiber is plugged, the PCIe data link needs to be rebuilt to realize data transmission between the RC end and the EP end. It should be noted that the plugging described in the present application refers to the operation of first unplugging and then plugging the optical module 130 or the optical fiber. For example, taking the optical module 130 as an example, the optical module 130 is connected to the PCIe board card in a plug-in manner, the plug-in interface is connected to the retimer chip 120, and then after the optical module 130 is plugged into the PCIe board card, the optical module 130 and the retimer chip 120 can realize communication. When in some working conditions, for example, when the optical module 130 needs to be repaired, the optical module 130 needs to be unplugged from the plug-in interface, and after the repair is completed, the optical module 130 is plugged into the plug-in interface, and the operation of plugging and unplugging the optical module 130 is completed.

[0040] After the optical module 130 is plugged or unplugged, the optical module 130 of the RC end and the optical module 130 of the EP end in the prior art cannot automatically re-establish the link to realize communication. Therefore, the present application realizes the automatic re-establishment of the data link by the MCU 110 (not shown in the figure) on the EP end PCIe board card in combination with the PCIe data link recovery method, so as to achieve the purpose of recovering the data communication. Figure 1

[0041] The PCIe data link recovery method provided by the present application will be described below: As an implementation manner, please refer to Figure 2 The method comprises the following steps: S102, when it is determined that the current board card is an EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is a low level; wherein the MODprel signal is used to indicate whether the optical module is in place; if yes, S104 is executed, and if no, S105 is executed.

[0042] S104, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is a low level; wherein the first RXLOS signal is used to indicate whether the optical signal is in place; if yes, S106 is executed, and if no, S107 is executed.

[0043] S105, the MODprel signal is continuously acquired, and in the case that the MODprel signal jumps from a high level to a low level, S106 is executed.

[0044] ​S106, acquiring an RSSI signal, and resetting the PCIe data link according to a value of the RSSI signal, so as to make the data link recover; wherein the RSSI signal is used to represent a size of optical power.

[0045] S107, determining that the data link works normally.

[0046] In the application, the MCU 110 of the EP is used to control the data link to be rebuilt, therefore, it is necessary to determine whether the current PCIe board card is the EP. In an implementation manner, please refer to Figure 3 , a schematic diagram of a module of the EP in the application is shown as Figure 3 , a dial switch is arranged in the PCIe system, the dial switch is connected with the MCU 110, and the dial switch is used to indicate whether the current PCIe board card is the EP. For example, after the working staff inserts or pulls out the optical module 130, the dial switch is dialled to point to the EP, so that the MCU 110 determines that the current board card is the EP.

[0047] In another implementation manner, the MCU 110 can also be connected with an external processor and the like, so as to receive a corresponding signal, to determine whether the current PCIe board card is the EP.

[0048] It should be noted that since the MCU 110 is arranged in the EP and the RC, the MCU 110 is provided with a device selection pin, when the device selection pin of the MCU 110 is a high level signal, it is determined that the current board card is the EP; when the device selection pin of the MCU 110 is a low level signal, it is determined that the current board card is the RC. Of course, it can also be set that when the device selection pin of the MCU 110 is a high level signal, it is determined that the current board card is the RC; when the device selection pin of the MCU 110 is a low level signal, it is determined that the current board card is the EP, which is not limited herein.

[0049] When it is determined that the current PCIe board card is the RC, the MCU 110 controls the PCIe system to work normally, provides a normal power-on condition for the RC, and continuously acquires the signal of the optical module 130, so as to determine whether a communication failure and the like occurs from the acquired signal.

[0050] When it is determined that the current PCIe board card is the EP, the MODprel signal is acquired, and it is determined whether the MODprel signal is a low level. As shown in Figure 3As shown, in the running process of the optical module 130, the internal sensor thereof continuously collects relevant running data, such as voltage, temperature, size of output optical power, size of input optical power, and the like. Therefore, the optical module 130 needs to feed back signals to the MCU 110 in real time in the running process, and the feedback signals include the MODprel signal, the RXLOS, and the RSSI signal.

[0051] It should be noted that, Figure 3 In the embodiment, in order to construct the 16-way communication link of the PCIe system, two optical modules 130 are used at the EP end and the RC end, and the two optical modules 130 are powered by a power supply. For example, the two optical modules 130 are powered by a 3.3V power supply. One of the optical modules 130 is used to provide N / 2-way communication links, and the other optical module 130 is used to provide another N / 2-way communication links, so that the retimer chip 120 constructs N-way communication links. As shown in the embodiment, Figure 3 As shown in the embodiment, one of the optical modules 130 is used to provide N / 2-way communication links of lan0-(n / 2-1), and the other optical module 130 is used to provide N / 2-way communication links of lan(n / 2)-(n-1). The optical modules 130 are connected to the retimer chip 120 through lan0-(n / 2-1) and lan(n / 2)-(n-1), and the N-way communication links lan0-(n-1) of the retimer chip 120 are connected to the gold finger and connected to the EP device at the back end through the gold finger. Therefore, the MCU 110 of the application can obtain signals of the two optical modules 130 at the same time. The application does not specifically limit the value of N. For example, N can be 16 or 32. When N is 16, one of the optical modules 130 is used to provide 8-way communication links of lan0-7, and the other optical module 130 is used to provide 8-way communication links of lan8-15. The optical modules 130 are connected to the retimer chip 120 through lan0-7 and lan8-15, and the N-way communication links lan0-15 of the retimer chip 120 are connected to the gold finger.

[0052] The MODprel signal is used to indicate whether the optical module 130 is in place, that is, whether the optical module 130 has been inserted by the worker. If the optical module 130 has been inserted by the worker, the MODprel signal is low. If the optical module 130 has not been inserted, the MODprel signal is high.

[0053] As can be seen, if the MODprel signal is low, the next signal, that is, the RXLOS signal, can be judged. If the MODprel signal is high, as Figure 2As shown in the figure, the MCU 110 continuously acquires the MODprel signal and monitors the state of the MODprel signal. Once the MODprel signal is captured from high to low, it indicates that the staff has inserted the optical module 130 at this time, and the MCU 110 directly judges the RSSI signal at this time. It should be noted that when the MODprel signal is captured from high to low, the judgment of the first RXLOS signal is skipped, and the RSSI signal is directly judged to improve the efficiency of data link recovery.

[0054] The first RXLOS signal is used to indicate whether the optical signal is in place, that is, whether the optical signal is present on the opposite board, that is, whether the optical signal is present on the PCIe board at the RC end. When the first RXLOS signal is high, it indicates that the optical signal is present on the opposite board. When the first RXLOS signal is low, it indicates that there is no optical signal on the opposite board, for example, the optical module 130 at the RC end is not inserted, or the optical module 130 is inserted but no signal is sent, or the optical module 130 is inserted and has sent a signal, but due to link failure, the EP end cannot normally receive the optical signal and convert it into an electrical signal.

[0055] It should be noted that when the first RXLOS signal is high, it indicates that the RC end board has normally sent an optical signal and has been recognized by the EP end, so the MCU 110 can directly determine that the data link is normal and end the entire process. In some implementations, the start of data link recovery is automatically performed by the MCU 110. At this time, after determining that the first RXLOS signal is high, the MCU 110 will immediately or after a period of time return to step S102. If the first RXLOS signal is low, the data link recovery process continues. In other implementations, the start of data link recovery can also be started by the staff. For example, a data link self-recovery button is set. When the staff inserts the optical module 130, the data link self-recovery button can be pressed, and the MCU 110 starts the data link recovery action. In this way, after determining that the first RXLOS signal is high, the entire data link recovery process ends.

[0056] When the first RXLOS signal is detected to be low, it indicates that the optical signal is not in place, which can be caused by various factors. Therefore, the MCU 110 continues to acquire the RSSI signal, and resets the PCIe data link according to the value of the RSSI signal. The RSSI signal is used to represent the size of the optical power. Specifically, the RSSI signal is used to represent the value of the optical power received by the EP end through the optical module 130.

[0057] After the step of acquiring the RSSI signal, the method further comprises: S081, determine whether the RSSI signal has a return value. If yes, execute S1082, if not, return to execute S102.

[0058] S1082, execute the step of resetting the PCIe data link according to the value of the RSSI signal.

[0059] It can be understood that when the first RXLOS signal is low, the reason why the optical signal is not in place can be the failure of the RC end optical signal, or the link failure, or the failure of the optical module 130 itself. Among them, when it is the failure of the RC end optical signal, for example, the RC end is not inserted with the optical module 130, or the optical module 130 is inserted but no optical signal is emitted, then the RSSI signal of the EP end has no return value; if the RC end optical signal is normal, then the RSSI signal of the EP end has a return value.

[0060] When the RSSI signal of the EP end has no return value, then return to execute the step of judging whether the MODprel signal is low until the RSSI signal of the EP end has a return value. If the RSSI signal of the EP end has a return value, then further reset the PCIe data link according to the value of the RSSI signal.

[0061] Among them, S106 includes: S1061, when the value of the RSSI signal is greater than the threshold value, reset the PCIe data link.

[0062] S1062, obtain the second RXLOS signal and determine whether the second RXLOS signal is low; if not, execute S1063, if yes, execute S1064.

[0063] S1063, then determine that the data link is recovered.

[0064] S1064, determine whether to continue to reset the PCIe data link according to the number of times of resetting the PCIe data link.

[0065] When the RSSI signal has a return value, there can also be a link failure condition, for example, the optical power attenuation caused by the link failure, therefore, it is necessary to further determine whether the value of the RSSI signal is greater than the threshold value, if the value of the RSSI signal is less than the threshold value, then execute the step of re-obtaining the value of the RSSI signal and determining whether the RSSI signal has a return value.

[0066] If the value of the RSSI signal is greater than the threshold value, the PCIe data link is reset, thereby realizing resetting of the data link. After the data link is reset, the MCU 110 continues to acquire the second RXLOS signal and determines whether the second RXLOS signal is at a low level. It can be understood that in the present application, the first RXLOS signal is the signal acquired by the MCU 110 before the data link is reset, and the second RXLOS signal is the signal acquired by the MCU 110 after the data link is reset.

[0067] If the second RXLOS signal is at a high level, it indicates that the data link after reset is normal, and the PCIe data link has been restored. If the second RXLOS signal is at a low level, it indicates that a fault may occur after the data link is reset, and the data link needs to be reset again until the number of resets exceeds a set value.

[0068] In the process of resetting the data link, the retimer chip 120 is actually reset. Please refer to Figure 3 In an implementation mode, the EP end further includes a power supply unit 140, and the reset of the retimer chip 120 is realized by resetting the power supply unit 140. Specifically, the MCU 110 first sets the Power_en to a low level, so that the power supply unit 140 stops supplying power to the retimer chip 120, and then sets the Power_en to a high level, so that the power supply unit 140 supplies power to the retimer chip 120. For the retimer chip 120, it completes the process of powering off first and powering on later, thereby realizing the reset of the retimer chip 120. In another implementation mode, the MCU 110 can directly reset the retimer chip 120, and the retimer chip 120 is directly reset by setting the reset to a high level.

[0069] In addition, when determining whether to continue resetting the PCIe data link according to the number of times of resetting the PCIe data link, it can be determined whether the number of times of resetting the PCIe data link is greater than a set value. If the number of times of resetting has exceeded the set value, it indicates that a fault of the optical module 130 itself may occur, and at this time, the MCU 110 generates a fault signal and stops resetting the PCIe data link. Please continue to refer to Figure 2The EP end further comprises an indicator light connected with the MCU 110. When the MCU 110 generates a fault signal, the indicator light is used for indication, thereby prompting the staff to maintain the optical module 130. If the number of resets does not exceed the set value, the PCIe data link is reset again, and the counter is incremented by one. The application does not limit the set value. For example, the set value can be set to 2. When the number of resets reaches 3, the MCU 110 generates a fault signal and controls the indicator light to light up.

[0070] Referring to Figure 4 The overall flowchart of the PCIe data link recovery method provided by the application is shown in the figure. First, it is determined whether the current board card is an EP end. Then, it is determined in sequence whether the MODprel signal is low, whether the first RXLOS signal is low, whether the RSSI signal has a return value, and whether the RSSI signal is greater than the threshold value. Then, the PCIe data link is reset. Then, it is determined whether the second RXLOS signal is low. If yes, the PCIe data link is reset again. If no, the flow is ended.

[0071] It can be understood that the PCIe board card with the retimer chip and the optical module is used to realize the link establishment and long-distance transmission between the RC side and the EP side. When the optical module of the RC side or the EP side is plugged or the optical fiber line is plugged, the MCU on the EP side board card can judge the current optical path condition by reading the high and low states of the MODprel signal and the RXLOS signal of the optical module and the size of the RSSI. According to the MCU control logic, the EP side retimer chip is reset to realize automatic re-linking and recover the PCIe data link.

[0072] In summary, the application provides a PCIe data link recovery method and a PCIe system. The method is applied to an MCU of an EP end in the PCIe system. The EP end further includes a retimer chip and an optical module. The MCU is connected with the retimer chip and the optical module respectively. When it is determined that the current board is the EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is low. The MODprel signal is used to indicate whether the optical module is in place. If the MODprel signal is low, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low. The first RXLOS signal is used to indicate whether the optical signal is in place. If yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so as to recover the data link. The RSSI signal is used to represent the size of the optical power. In the PCIe data link recovery method provided by the application, the MCU comprehensively determines the current optical path condition by monitoring the MODprel signal, the RXLOS signal and the RSSI signal of the optical module pin, and determines to reset the PCIe data link in combination with the signal condition, so as to recover the data link, and the PCIe system can automatically re-establish the link and recover the data communication function when the optical module is plugged in or out at the EC side or the EP side, or the optical fiber is plugged in or out.

[0073] The above only describes preferred embodiments of the application and is not intended to limit the application. The application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

[0074] It is obvious for those skilled in the art that the application is not limited to the details of the above exemplary embodiments, and the application can be implemented in other specific forms without departing from the spirit or essential characteristics of the application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the application. Any reference signs in the claims should not be regarded as limiting the claims.

Claims

1. A PCIe data link recovery method, characterized in that, The method is applied to an MCU of an EP end in a PCIe system, the EP end further comprises a retimer chip and an optical module, and the MCU is connected with the retimer chip and the optical module respectively; the method comprises: When it is determined that the current board card is the EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is low; wherein the MODprel signal is used to indicate whether the optical module is in place; If the MODprel signal is low, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low; wherein the first RXLOS signal is used to indicate whether the optical signal is in place; If yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so as to restore the data link; wherein the RSSI signal is used to represent the size of the optical power.

2. The PCIe data link recovery method of claim 1, wherein, The step of resetting the PCIe data link according to the value of the RSSI signal to restore the data link comprises: When the value of the RSSI signal is greater than a threshold value, the PCIe data link is reset; A second RXLOS signal is acquired, and it is determined whether the second RXLOS signal is low; If no, it is determined that the data link is restored; If yes, it is determined whether to continue to reset the PCIe data link according to the number of times of resetting the PCIe data link.

3. The PCIe data link recovery method of claim 2, wherein, The step of determining whether to continue to reset the PCIe data link according to the number of times of resetting the PCIe data link comprises: It is determined whether the number of times of resetting the PCIe data link is greater than a set value; If yes, a fault signal is generated, and the resetting of the PCIe data link is stopped; If no, the PCIe data link is reset again, and the counter is controlled to be incremented by one.

4. The PCIe data link recovery method of claim 2, wherein, The EP end further comprises a power supply unit for supplying power to the retimer chip, and the power supply unit is connected with the MCU, and the step of resetting the PCIe data link comprises: The power supply unit is controlled to perform a power-down first and then power-up operation, or the retimer chip is controlled to be reset.

5. The PCIe data link recovery method of claim 1, wherein, After the step of acquiring the RSSI signal, the method further comprises: It is determined whether the RSSI signal has a return value; If yes, the step of resetting the PCIe data link according to the value of the RSSI signal is executed; If no, the step of acquiring the MODprel signal and determining whether the MODprel signal is low is returned.

6. The PCIe data link recovery method of claim 1, wherein, Before the step of determining that the current board card is the EP end, the method further comprises: When the end device selection pin of the MCU is a high level signal, it is determined that the current board card is the EP end; When the end device selection pin of the MCU is a low level signal, it is determined that the current board card is the RC end.

7. The PCIe data link recovery method of claim 6, wherein, After the step of determining that the current board card is the RC end, the method further comprises: A normal power-on condition of the RC end is provided, and signals of the optical module are continuously acquired.

8. The PCIe data link recovery method of claim 1, wherein, After the step of determining whether the MODprel signal is low, the method further comprises: When the MODprel signal is at a high level, the MODprel signal is continuously acquired, and in a case where the MODprel signal jumps from a high level to a low level, the step of acquiring the RSSI signal is performed.

9. The PCIe data link recovery method of claim 1, wherein, After the step of judging whether the first RXLOS signal is at a low level, the method further comprises: If the first RXLOS signal is at a high level, it is determined that the data link is in normal operation.

10. A PCIe system, characterized by, The PCIe system comprises an RC end and an EP end, the RC end and the EP end each comprise a retimer chip and an optical module, and the RC end and the EP end are connected through the optical modules; the EP end further comprises an MCU, and the MCU is used to execute the PCIe data link recovery method according to any one of claims 1 to 9.

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