AHB bus matrix and system on chip

Abstract

The invention provides an AHB bus matrix and a system on chip, the AHB bus matrix comprises a plurality of master control modules, each master control module is correspondingly connected with a master device and is used for receiving a target address of an access request from the corresponding master device and selecting a corresponding slave control module according to the target address; a plurality of slave control modules, each slave control module is correspondingly connected with one slave device, and each master control module is connected with each slave control module through the on-chip internet; the slave control module is used for forwarding the access request to the corresponding slave device and detecting the response duration of the corresponding slave device for executing the access request; and the slave control module is also used for feeding back an error response to the master device initiating the access request when the response duration exceeds a preset threshold. According to the AHB bus matrix and the system on chip provided by the invention, the technical problem that the master equipment cannot execute subsequent operation when the slave equipment responds abnormally is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chips, in particular to an AHB bus matrix and a system on chip. BACKGROUND

[0002] AHB (Advanced High-performance Bus) is a kind of high-performance bus widely used in system on chip, which is used to connect CPU, memory controller, DMA controller and various peripheral controllers and other devices. In a system with multiple master devices (Master) and multiple slave devices (Slave), an AHB bus matrix is usually used to realize the interconnection and communication between master devices and slave devices.

[0003] The existing AHB bus matrix has obvious defects when the slave device responds abnormally. When a master device accesses a slave device with a long response time, the master device will be in a waiting state for a long time, resulting in reduced bus efficiency. At the same time, if the slave device fails to respond, the master device will continue to wait and cannot perform subsequent operations, which seriously affects the system reliability and real-time performance. Therefore, there is room for improvement. SUMMARY

[0004] The present application provides an AHB bus matrix and a system on chip to solve the technical problem that the master device cannot perform subsequent operations when the slave device responds abnormally.

[0005] The present application provides an AHB bus matrix connected between multiple master devices and multiple slave devices of a system on chip, which comprises: a plurality of master control modules, each master control module being connected to a master device, for receiving and selecting a corresponding slave control module according to the target address of the access request from the corresponding master device; a plurality of slave control modules, each slave control module being connected to a slave device, and each master control module being connected to each slave control module through an on-chip interconnection network; the slave control module is used to forward the access request to the corresponding slave device and detect the response time of the corresponding slave device executing the access request; the slave control module is also used to feed back an error response to the master device initiating the access request when the response time exceeds a preset threshold.

[0006] In an embodiment of the present application, the master control module comprises: a cache unit connected to the master device, for receiving and caching the access request from the master device; a master control unit connected to the cache unit, for selecting a corresponding slave control module according to the target address of the access request in the cache unit.

[0007] In an embodiment of the present application, the slave control module comprises: The slave unit is connected with the master unit through the on-chip interconnection network, and is configured to forward the access request to the corresponding slave device; when multiple master units simultaneously access the slave unit through the on-chip interconnection network, the slave unit is further configured to sequentially process the access request of the corresponding master unit according to a preset master device priority; The timeout detection unit is connected between the slave unit and the slave device, and is configured to detect a response time length of the corresponding slave device performing the access request, and feed back an error response to the master device initiating the access request when the response time length exceeds a preset threshold.

[0008] In an embodiment of the present application, when the access request is a write request, the cache unit is configured to sequentially receive and cache the write request and write data from the master device, and synchronously feed back the corresponding write response to the master device after caching each write data; The cache unit is further configured to pause receiving the new write request and the corresponding write data of the master device when the idle storage space is less than the preset threshold; The cache unit is further configured to release the corresponding storage space after the master unit completes processing the current write request and the corresponding write data; The cache unit is further configured to receive the next write request and the corresponding write data of the master device after the corresponding storage space is released.

[0009] In an embodiment of the present application, the master unit is configured to sequentially process the write request in the cache unit, and select the corresponding slave unit according to the target address of the write request, so as to forward the write request and the corresponding write data to the selected slave unit; The slave unit is configured to process the next write request forwarded by the master unit after receiving the success response fed back by processing the current write request; The slave unit processing is further configured to abort processing the next write request forwarded by the master unit after receiving the error response fed back by processing the current write request, and feed back the error response to the master device initiating the access request.

[0010] In an embodiment of the present application, the timeout detection unit is configured to detect the response time length of the slave device performing the write request when the slave unit receives the write request and the corresponding write data forwarded to the corresponding slave device; The timeout detection unit is further configured to feed back the corresponding error response to the slave unit when the response time length exceeds the preset time length; The timeout detection unit is further configured to feed back the corresponding success response to the slave unit when the response time length does not exceed the preset time length.

[0011] In an embodiment of the present application, when the access request is a read request, the cache unit is configured to receive the read request from the master device; The cache unit is further configured to receive read data read out by the master unit according to the read request, and read out the read data to the host device initiating the access request, and receive a next read request of the host device.

[0012] In an embodiment of the present application, the master unit is configured to select a corresponding slave unit according to a target address of the read request in the cache unit, and forward the read request to the selected slave unit. The master unit is further configured to read out the read data to the cache unit after receiving a success response and corresponding read data of the slave unit processing the read request. The master unit is further configured to feed back an error response to the host device initiating the access request after receiving an error response of the slave unit processing the read request.

[0013] In an embodiment of the present application, the timeout detection unit is configured to detect a response time of the slave device executing the read request when the slave unit forwards the received read request to a corresponding slave device. The timeout detection unit is further configured to feed back a corresponding error response to the slave unit when the response time exceeds a preset time length. The timeout detection unit is further configured to feed back a corresponding success response to the slave unit when the response time does not exceed the preset time length, and read out read data read out by the slave device to the slave unit.

[0014] The present application further provides an on-chip system comprising an AHB bus matrix, a plurality of host devices, and a plurality of slave devices, wherein the AHB bus matrix is connected between the plurality of host devices and the plurality of slave devices.

[0015] The present application has the following beneficial effects: by introducing the response time detection and error response mechanism, the problem of host device blocking caused by abnormal response of the slave device in the prior art is effectively solved. When the response time of the slave device executing the access request exceeds a preset threshold, the slave module will immediately feed back an error response to the host device, so that the host device can terminate the waiting in time and perform error processing or subsequent operation, thereby avoiding long-term occupation of the bus resource, and significantly improving the bus utilization efficiency and system throughput. At the same time, the mechanism ensures that the host device will not be in indefinite waiting when the slave device is faulty or responds too slowly, enhances the reliability and real-time performance of the system, and guarantees stable operation in the multi-host device environment. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. It is to be understood that the drawings are designed solely for purposes of illustration to be used in conjunction with the description in

[0017] In the drawings: Figure 1 A schematic diagram of a system-on-chip is provided for an embodiment of the present application.

[0018] Reference signs are as follows: 100, master device; 210, cache unit; 220, master control unit; 230, slave control unit; 240, timeout detection unit; 300, slave device. DETAILED DESCRIPTION

[0019] The present application is described by way of specific examples, and as will be apparent to those of ordinary skill in the art, other advantages and benefits will become apparent. The application can be implemented in any of the several different ways discussed in this specification. These and other embodiments and examples of the present application are described without intent to limit the application to those described. Choosing these embodiments and examples is not intended to limit alternatives that can be apparent to those of ordinary skill in the art and that can be made as appropriate to the application without departing from the spirit of the application.

[0020] It should be noted that the drawings included in the following embodiments are only schematic and are not drawn to scale. They are provided to aid in understanding the present application and are not provided to limit the present application. The objects shown in the drawings can be implemented in any of numerous ways, and their configuration is not intended to limit the present application. Similarly, each block in the drawings, and combinations of blocks in one or more drawings, can be implemented in numerous ways, and the ordering of the blocks is not intended to limit the present application.

[0021] In the following description, numerous specific details are discussed to provide a thorough understanding of embodiments of the application. One of ordinary skill in the art, however, will realize that the application can be practiced without one or more of the specific details. In other instances, well-known structures and devices are not shown or described in order not to obscure aspects of embodiments of the application. Embodiments of the application can be implemented in various ways, e.g., in hardware, software, or a combination thereof. Portions of the application can be implemented as a system, method, or computer program product.

[0022] Reference will now be made to Figure 1The application discloses a system on chip, which comprises an AHB bus matrix, a plurality of master devices 100 and a plurality of slave devices 300, wherein the AHB bus matrix is connected between the plurality of master devices 100 and the plurality of slave devices 300. The plurality of devices contained in the system on chip can be CPU, memory controller, DMA controller and various peripheral controllers. When data communication is needed between the devices, the device initiating the access request acts as the master device 100 in the communication process, and the device being accessed acts as the slave device 300 in the communication process. The AHB bus matrix can manage and forward all access transactions between the master devices 100 and the slave devices 300, and ensure the orderly communication.

[0023] Referring to Figure 1 In some embodiments, the AHB bus matrix can comprise a plurality of master modules and a plurality of slave modules. Each master module is connected with a master device 100, and is used for receiving and selecting a corresponding slave module according to a target address of an access request from the corresponding master device 100. Each slave module is connected with a slave device 300, and each master module is connected with each slave module through an on-chip interconnection network; the slave module is used for forwarding the access request to the corresponding slave device, and detecting a response time length of the corresponding slave device 300 performing the access request; and the slave module is further used for feeding back an error response to the master device 100 initiating the access request when the response time length exceeds a preset threshold.

[0024] In some embodiments, the on-chip interconnection network is a core interconnection component of the AHB bus matrix, and constitutes a global communication infrastructure, which connects all the master modules and the slave modules together. Each master module has an independent communication path to all the slave modules, and the full-connection topology ensures that any master module can directly and unblockedly communicate with any slave module after obtaining the access permission, thereby providing a basis for high-concurrency and low-delay data transmission in physical connection.

[0025] Referring to Figure 1 In some embodiments, the master module comprises a cache unit 210 and a master control unit 220. The cache unit 210 is connected with the master device 100, and is used for receiving and caching the access request from the master device 100. The master control unit 220 is connected with the cache unit 210, and is used for selecting a corresponding slave module according to a target address of the access request in the cache unit 210.

[0026] In some embodiments, the cache unit 210 is connected to the master device 100 directly as the front-end interface of the master module, and is responsible for receiving the access request initiated by the master device 100 and performing cache management. The master control unit 220 is connected to the cache unit 210 directly as the back-end processing core of the master module, and is responsible for processing the request in the cache unit 210 and forwarding it to the slave module.

[0027] In some embodiments, the core function of the cache unit 210 is to implement efficient cache and flow control of the access request. When the master device 100 initiates an access, whether it is a read request or a write request, the request is first sent to the cache unit 210.

[0028] In some embodiments, the master control unit 220 is the scheduling and routing center of the master module, responsible for extracting the accepted access request from the cache unit 210 in sequence and processing it.

[0029] Please refer to Figure 1 In some embodiments, the slave module includes a slave unit 230 and a timeout detection unit 240. The slave unit 230 is connected to the master control unit 220 through the on-chip interconnection network, and is used to forward the access request to the corresponding slave device 300; wherein when multiple master control units 220 access the slave unit 230 through the on-chip interconnection network at the same time, the slave unit 230 is also used to process the access request of the corresponding master control unit 220 in turn according to the preset master device priority. The timeout detection unit 240 is connected between the slave unit 230 and the slave device 300, and is used to detect the response time of the corresponding slave device 300 executing the access request, and when the response time exceeds the preset threshold, an error response is fed back to the master device 100 initiating the access request.

[0030] In some embodiments, the slave unit 230 is the request processing and arbitration center of the slave module, one end of which is connected to all master control units 220 that can access the slave device 300 through the on-chip interconnection network, and the other end leads to the slave device 300. The slave unit 230 can receive the access request routed through the on-chip interconnection network and forward it to the corresponding slave device 300.

[0031] In some embodiments, when multiple master units 220 attempt to access the same slave unit 230 at the same time through the on-chip interconnection network, access conflicts inevitably occur. To solve this problem, the slave unit 230 is internally integrated with an arbitration mechanism. The arbitration mechanism sorts all the simultaneously-arriving access requests according to a pre-set, fixed master priority order, and selects the access request from the master unit 220 with the highest priority to grant access and forward the access request to the slave device 300 for execution. Other simultaneously-arriving access requests with lower priority are temporarily blocked, and the slave unit 230 will re-arbitrate after the high-priority access transaction is completed to select the next access request to be serviced. This arbitration mechanism ensures that in the presence of concurrent access competition, the bus resources can be reasonably and orderly allocated according to the established priority order, avoiding data confusion and ensuring the access performance of the master device 100.

[0032] In some embodiments, the timeout detection unit 240 is a component that guarantees robustness and implements error isolation function. The timeout detection unit 240 is connected between the slave unit 230 and the slave device 300, and continuously monitors the communication signals therebetween. The timeout detection unit 240 can accurately measure the response time of the slave device 300 in processing a single access request.

[0033] In some embodiments, when the access request is a write request, the cache unit 210 is configured to sequentially receive and cache the write request and write data from the master device 100, and synchronously feed back the corresponding write response to the master device 100 after each write data is cached.

[0034] In some embodiments, the cache unit 210 sequentially receives and caches the write request and write data from the master device 100 in a first-in-first-out order. When the master device 100 initiates a write operation, the write request and the corresponding write data are transmitted to the cache unit 210. The cache unit 210 internally includes a cache area composed of multiple storage entries, which can temporarily store multiple write data at the same time. When receiving the write data, the cache unit 210 stores the write data in the cache area according to the order of arrival of the write data, ensuring that the order of the write request is strictly maintained.

[0035] In some embodiments, the cache unit 210 feeds back a corresponding write response to the host device 100 immediately after successfully storing each write data. Specifically, when the write data is successfully written into the cache region of the cache unit 210, the cache unit 210 generates and sends the write response to the host device 100 immediately without waiting for the write data to be processed by the subsequent master unit 220 and finally written into the target slave device 300. This immediate response mechanism enables the host device 100 to be quickly released from a single write transaction, greatly reducing the access delay of the host device 100 and improving the bus utilization efficiency.

[0036] In some embodiments, the cache unit 210 is further configured to suspend receiving new write requests and corresponding write data from the host device 100 when the free storage space is less than a preset threshold.

[0037] In some embodiments, the cache unit 210 continuously monitors the free storage space of its internal cache region. A preset space threshold is provided in the cache unit 210. When it is monitored that the current free storage space is less than the preset threshold, it indicates that the cache region is about to be full. At this time, the cache unit 210 sends a backpressure signal to the host device 100, which informs the host device 100 to temporarily stop sending new write requests and corresponding write data, which can effectively prevent data loss or errors caused by cache region overflow and ensure the reliability of data transmission.

[0038] In some embodiments, the cache unit 210 is further configured to release the corresponding storage space after the master unit 220 processes the current write request and corresponding write data.

[0039] In some embodiments, the cache unit 210 releases the storage space occupied by the write request after the master unit 220 processes the current write request and corresponding write data. When the master unit 220 successfully forwards a write request and its data to the slave module and finally receives a successful response or a timeout error response from the slave device 300, it indicates that the write transaction has been completed in the subsequent process of the cache unit 210. At this time, the cache unit 210 marks the corresponding storage as free and recycles the storage space for subsequent write operations.

[0040] In some embodiments, the cache unit 210 is further configured to receive the next write request and corresponding write data from the host device 100 after the corresponding storage space is released.

[0041] In some embodiments, the cache unit 210 actively releases the back pressure state to the host device 100 after the corresponding storage space is released, i.e. when there is new free space in the cache area. Once the back pressure state is released, the cache unit 210 immediately resumes receiving the next write request and corresponding write data sent by the host device 100, thereby continuing the new round of caching, responding and forwarding processes, ensuring the continuity of the write operation data stream and the system throughput.

[0042] In some embodiments, the master unit 220 is configured to process the write requests in the cache unit 210 in sequence, and select the corresponding slave unit 230 according to the target address of the write request, so as to forward the write request and corresponding write data to the selected slave unit 230.

[0043] In some embodiments, the master unit 220 continuously monitors the state of the cache area of the cache unit 210, and once it detects that there are write requests that have been received but not yet processed in the cache unit 210, it extracts and processes these write requests one by one in the order in which they entered the cache unit 210, thereby ensuring that the execution order of the write operation is completely consistent with the order initiated by the host device 100, and avoiding data consistency problems.

[0044] In some embodiments, the master unit 220 can select the corresponding slave unit 230 according to the target address contained in the write request after extracting the write request. The master unit 220 is internally integrated with address decoding logic, which parses the target address of the write request and compares it with the address space range of each slave device 300 defined in advance. Through this address matching operation, the master unit 220 can uniquely determine the target slave device 300 that the current write request needs to access, and further determine the slave unit 230 responsible for managing the slave device 300. After determining the slave unit 230, the master unit 220 forwards the current write request being processed and the corresponding write data read from the cache unit 210 to the selected slave unit 230 through the on-chip interconnection network.

[0045] In some embodiments, the slave unit 230 is configured to receive and process the next write request forwarded by the master unit 220 after receiving the success response feedback of the current write request.

[0046] In some embodiments, after sending the write request, the master unit 220 enters a waiting state for a response, and its subsequent operation depends on the state of the slave unit 230. When the slave unit 230 receives a success response for processing the current write request, it indicates that the write request has been correctly received and executed by the slave device 300. At this time, the master unit 220 performs two subsequent actions: one is to notify the cache unit 210, indicating that the write transaction has been successfully completed, and the cache unit 210 can safely release the storage space occupied by the write request and the corresponding write data; the other is that the master unit 220 itself turns to process the next sequential write request in the cache unit 210, continuing to advance the write operation pipeline.

[0047] In some embodiments, after receiving an error response for processing the current write request, the slave unit 230 also stops processing the next write request forwarded by the master unit 220 and feeds back an error response to the host device 100 that initiates the access request.

[0048] In some embodiments, when the slave unit 230 receives an error response for processing the current write request, it indicates that the current write request cannot be normally executed by the slave device 300. After receiving the error response, the master unit 220 immediately stops the processing flow of the subsequent write request in the cache unit 210, preventing the subsequent request that may depend on this failed operation from continuing to execute. At the same time, the slave unit 230 feeds back an error response to the host device 100 that initiates the write request, informing the host device 100 that the write operation fails. This mechanism ensures that the host device 100 can learn about the fault state in time, so that appropriate error recovery measures can be taken at the software or hardware level, rather than waiting indefinitely for a success response that never comes, greatly enhancing the reliability and controllability of the system.

[0049] In some embodiments, the system-on-chip further includes a processing module (not shown in the figure) that can be connected to all host devices 100 and connected to all slave units 230. When the slave unit 230 receives an error response for processing the current write request, it feeds back the corresponding error response to the processing module, and finally the processing module feeds back the error response to the corresponding host device 100.

[0050] In some embodiments, the timeout detection unit 240 is configured to detect the response time of the slave device 300 for executing the write request when the slave unit 230 forwards the received write request and corresponding write data to the corresponding slave device 300.

[0051] In some embodiments, the timeout detection unit 240 starts its monitoring function immediately when the slave unit 230 forwards the received write request and corresponding write data to the corresponding slave device 300. The trigger condition for the timeout detection unit 240 to work is to monitor the hreadyout signal returned from the slave device 300 indicating the transmission ready state is pulled low. When the slave unit 230 initiates an access and hands over the control to the slave device 300, if the slave device 300 is unable to complete the operation immediately due to internal processing busy, encountering errors or functional failure, it will indicate that it is in a busy state and not ready to end the transmission by continuously maintaining the hreadyout signal at low level. Once the timeout detection unit 240 detects that the hreadyout signal becomes low, its internal monitoring mechanism is activated.

[0052] In some embodiments, the timeout detection unit 240 internally contains a configurable counter to accurately measure the time that the slave device 300 remains in a busy state, i.e. the response time. The counter starts counting from zero after the hreadyout signal becomes low. The timeout detection unit 240 will continuously compare the current count value with a pre-set threshold value, which represents the maximum time limit allowed for the slave device 300 to process a single operation. The counting rhythm of the counter is synchronized with the bus clock to ensure the accuracy of time measurement.

[0053] In some embodiments, the timeout detection unit 240 is also used to feed back a corresponding error response to the slave unit 230 when the response time exceeds the pre-set time limit.

[0054] In some embodiments, when the counter value inside the timeout detection unit 240 exceeds the pre-set threshold value, it is determined that the response of the slave device 300 is timed out. At this time, the timeout detection unit 240 will immediately take over the control of the output signal and will forcibly pull the hreadyout signal output to the slave unit 230 high, simulating a transmission end timing. At the same time, the timeout detection unit 240 will drive the response signal hresp to high, indicating that it is an error response. This forced behavior effectively terminates the access transaction that has been in a long waiting state. At the same time, the timeout detection unit 240 will latch and record the target address of the access request that caused this timeout, and generate an error response for reporting, providing key information for subsequent error diagnosis, log recording and possible recovery operations.

[0055] In some embodiments, the timeout detection unit 240 is also used to feed back a corresponding success response to the slave unit 230 when the response time does not exceed the pre-set time limit.

[0056] In some embodiments, if the count value has not reached the preset threshold during the incrementing of the counter, the slave device 300 completes the operation and pulls up its hreadyout signal, indicating that the operation has been completed normally. Upon detecting this situation, the timeout detection unit 240 immediately resets its internal counter to zero, preparing for monitoring the next operation. Meanwhile, the timeout detection unit 240 allows the normal signals generated by the slave device 300 (including the pulled-up hreadyout and the hresp indicating success) to pass through and be delivered to the slave control unit 230, i.e., feeding back a successful response, thereby ensuring that the normal access flow can be completed smoothly. Through this mechanism, the timeout detection unit 240 achieves seamless monitoring of the behavior of the slave device 300, intervening only when an exception occurs, ensuring stable operation in both normal and abnormal situations.

[0057] In some embodiments, when the access request is a read request, the cache unit 210 is configured to receive the read request from the master device 100. The cache unit 210 is also configured to receive read data read out by the master control unit 220 according to the read request, and read out the read data to the master device 100 that initiates the access request, and receive the next read request from the master device 100.

[0058] In some embodiments, when the access request is a read request, the cache unit 210 serves as an interface between the master device 100 and the master control unit 220, responsible for coordinating the initiation of the read operation and the data return process. The cache unit 210 first receives the read request from the master device 100. The master device 100 generates a read request when it needs to read data from the slave device 300, which contains the target address. This read request is sent to the cache unit 210 connected directly to it. The cache unit 210 receives the read request and temporarily stores it or directly notifies the master control unit 220 of the new read request to be processed. Unlike the write operation, for the read request, the cache unit 210 usually does not immediately return data to the master device 100 in the receiving stage, because the valid data needs to be obtained from the target slave device 300 in the subsequent stage.

[0059] In some embodiments, the cache unit 210 then enters a data waiting state, preparing to receive the read data read out by the master control unit 220 according to the read request. After receiving the read request delivered by the cache unit 210, the master control unit 220 performs address decoding, routes the read request to the slave control unit 230 through the on-chip interconnection network, and finally initiates the read operation to the slave device 300 by the slave control unit 230. When the slave device 300 returns the read data, the data returns along the original path, passing through the slave control unit 230, the on-chip interconnection network, and finally reaching the master control unit 220. The master control unit 220, upon obtaining the read data, delivers it back to the cache unit 210. The cache unit 210 is responsible for receiving and temporarily holding the read data.

[0060] In some embodiments, after successfully receiving the read data returned by the master unit 220, the cache unit 210 can read out the read data to the host device 100 that initiates the access request. The cache unit 210 can actively drive the temporarily stored read data to the data bus of the host device 100, and send a corresponding transmission completion signal to the host device 100 to indicate that the requested data is valid and available. The host device 100 can then sample the data to complete the read transaction. Once the data delivery of the current read request is completed, the cache unit 210 can immediately release the related resources and prepare to receive the next read request from the host device 100, so as to maintain the continuous operation of the read operation pipeline.

[0061] In some embodiments, the master unit 220 is configured to select a corresponding slave unit 230 according to the target address of the read request in the cache unit 210, so as to forward the read request to the selected slave unit 230.

[0062] In some embodiments, after receiving the read request delivered by the cache unit 210, the master unit 220 can first perform an address resolution operation, i.e., select a corresponding slave unit 230 according to the target address contained in the read request. After completing the address decoding and selecting the slave unit 230, the master unit 220 can accurately forward the read request received from the cache unit 210 to the selected slave unit 230 through the on-chip interconnection network, and start the subsequent read data acquisition process.

[0063] In some embodiments, the master unit 220 is further configured to read out the read data to the cache unit 210 after receiving the successful response and corresponding read data from the slave unit 230 in response to the read request.

[0064] In some embodiments, after successfully forwarding the read request, the master unit 220 can continuously wait for a response from the slave unit 230. When the slave unit 230 feeds back a successful response and corresponding read data in response to the read request, it indicates that the target slave device 300 has successfully completed the data read and the data is valid. At this time, the master unit 220 can perform a data transfer operation to read out the read data received from the slave unit 230 and immediately write or transmit it to the cache unit 210.

[0065] In some embodiments, the master unit 220 is further configured to feed back an error response to the host device 100 that initiates the access request after receiving an error response from the slave unit 230 in response to the read request.

[0066] In some embodiments, when the master unit 220 receives an error response fed back by the slave unit 230 in processing a read request, the error response is usually caused by the timeout detection unit 240 in the slave module determining that the slave device 300 response timeout, or the slave device 300 itself returns an error indication. This indicates that this read request fails to successfully obtain data from the target slave device 300. In this case, the master unit 220 does not transmit any read data to the cache unit 210, but directly feeds back an error response to the master device 100 initiating the read request. Through this operation, the master unit 220 timely informs the master device 100 that this read operation fails, so that it can determine the subsequent process according to the error state, thereby avoiding the problem of system suspension or performance degradation caused by the master device 100 waiting for the read data that cannot be returned for a long time.

[0067] In some embodiments, the timeout detection unit 240 is configured to detect the response time of the slave device 300 executing the read request when the slave unit 230 forwards the received read request to the corresponding slave device 300.

[0068] In some embodiments, the timeout detection unit 240 starts its monitoring function immediately when the slave unit 230 forwards the received read request to the corresponding slave device 300. The trigger condition and judgment mechanism of its monitoring are similar to those of the write operation. When the slave unit 230 issues a read request to the slave device 300, if the slave device 300 cannot immediately return data due to internal processing delay or failure, and pulls down the hreadyout signal to indicate busy, the counter in the timeout detection unit 240 starts counting from zero, accurately measuring the response time of the slave device 300 to this read request.

[0069] In some embodiments, the timeout detection unit 240 is also configured to feed back a corresponding error response to the slave unit 230 when the response time exceeds the preset time.

[0070] In some embodiments, the timeout detection unit 240 feeds back a corresponding error response to the slave unit 230 when the response time exceeds the preset time. When the count value of the internal counter exceeds the preset preset time, the timeout detection unit 240 determines that this read operation has timed out. At this time, it immediately intervenes forcibly: the hreadyout signal output to the slave unit 230 is forcibly pulled up, and the response signal hresp is driven to the state indicating an error. This operation forcibly terminates the waiting process and indicates to the slave unit 230 that the read transaction has failed. At the same time, the timeout detection unit 240 records the target address of this timeout read request and generates an error response.

[0071] In some embodiments, the timeout detection unit 240 is further configured to feed back a corresponding success response to the slave control unit 230 and read out the read data read from the slave device 300 to the slave control unit 230 when the response duration does not exceed the preset duration.

[0072] In some embodiments, if the slave device 300 completes the data read and pulls up the ready signal hreadyout before the counter reaches the preset threshold, it indicates that the read operation is successful. The timeout detection unit 240 will immediately clear its internal counter and allow all read data generated by the slave device 300 to pass normally.

[0073] In some embodiments, when the timeout detection unit 240 determines that the slave device 300 is in timeout and performs the forced operation, i.e., the internal counter value exceeds the preset duration, the hreadyout signal output to the slave control unit 230 is forced to be pulled up and the hresp signal is set to an error response, and the access transaction is considered to be completed for the master device 100. However, at the hardware bottom, the slave device 300 may not immediately stop the current operation due to the delay of its internal logic or state machine, but finally complete the read or write operation and set its own hreadyout signal to be valid after the timeout determination occurs.

[0074] In some embodiments, in this scenario, the timeout detection unit 240 continues to monitor the real hreadyout signal state of the slave device 300. When the timeout detection unit 240 detects that the slave device 300 still pulls up its hreadyout signal after the timeout event occurs, it indicates that the slave device 300 has actually completed the original operation. Specifically, the control logic inside the timeout detection unit 240 changes its connection path, no longer forces the output of the hreadyout signal to be high, but instead directly transmits the real hreadyout signal generated by the slave device 300 to the slave control unit 230.

[0075] In some embodiments, the switching of the control right ensures that the new access operation sent to the slave device 300 after the current timeout transaction can be normally performed. Once the control right is returned, the timeout detection unit 240 resumes its normal monitoring mode for the subsequent access transaction, i.e., the counting is restarted from zero from the next access, and the normal transmission of the success response or the triggering of the timeout protection mechanism in the new cycle is determined according to the state of the real hreadyout signal of the slave device 300. This design ensures the self-recovery capability of the system on chip, and the temporary delay of a single slave device 300 or a single timeout event will not permanently damage the normal communication link between the slave device 300 and the AHB bus matrix, thereby maintaining the long-term stability and reliability of the system on chip. Through the intelligent control right management of the timeout detection unit 240, the balance between error isolation and function recovery is achieved.

[0076] It can be seen that in the above scheme, by introducing the response time detection and error response mechanism, the problem of blocking of the master device caused by abnormal response of the slave device in the prior art is effectively solved. When the response time of the slave device performing the access request exceeds the preset threshold, the slave control module immediately feeds back an error response to the master device, so that the master device can terminate the waiting in time and perform error processing or subsequent operation, thereby avoiding long-term occupation of the bus resources, and significantly improving the bus utilization efficiency and system throughput. At the same time, the mechanism ensures that the master device will not be in indefinite waiting when the slave device fails or responds too slowly, enhances the reliability and real-time performance of the system, and guarantees the stable operation in the multi-master device environment.

[0077] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. An AHB bus matrix, characterized by The AHB bus matrix is connected between a plurality of master devices and a plurality of slave devices of a system on chip, and comprises: a plurality of master modules, each of which is connected with a master device, and is configured to receive an access request from the master device and select a corresponding slave module according to a target address of the access request; a plurality of slave modules, each of which is connected with a slave device, and each of which is connected with each of the master modules through an on-chip interconnection network; the slave module is configured to forward the access request to the corresponding slave device, and detect a response time of the corresponding slave device for executing the access request; and the slave module is further configured to feed back an error response to the master device that initiates the access request when the response time exceeds a preset threshold.

2. The AHB bus matrix according to claim 1, characterized in that, The master module comprises: a cache unit connected with the master device, and configured to receive and cache the access request from the master device; a master control unit connected with the cache unit, and configured to select the corresponding slave module according to the target address of the access request in the cache unit.

3. An AHB bus matrix as claimed in claim 2, characterized in that, The slave module comprises: a slave control unit connected with the master control unit through the on-chip interconnection network, and configured to forward the access request to the corresponding slave device; when a plurality of master control units simultaneously access the slave control unit through the on-chip interconnection network, the slave control unit is further configured to sequentially process the access requests of the corresponding master control units according to preset master device priorities; a timeout detection unit connected between the slave control unit and the slave device, and configured to detect the response time of the corresponding slave device for executing the access request, and feed back an error response to the master device that initiates the access request when the response time exceeds a preset threshold.

4. An AHB bus matrix as claimed in claim 3, characterized in that, When the access request is a write request, the cache unit is configured to sequentially receive and cache the write request and write data from the master device, and synchronously feed back a corresponding write response to the master device after caching each write data; the cache unit is further configured to pause receiving a new write request and corresponding write data from the master device when the idle storage space is less than a preset threshold; the cache unit is further configured to release the corresponding storage space after the master control unit processes the current write request and corresponding write data; the cache unit is further configured to receive a next write request and corresponding write data from the master device after the corresponding storage space is released.

5. The AHB bus matrix according to claim 4, characterized in that, The master control unit is configured to sequentially process the write requests in the cache unit, and select the corresponding slave module according to the target address of the write request, so as to forward the write request and corresponding write data to the selected slave module; the slave control unit is configured to process a next write request forwarded by the master control unit after receiving a success response fed back for processing the current write request; the slave control unit is further configured to suspend processing the next write request forwarded by the master control unit after receiving an error response fed back for processing the current write request, and feed back an error response to the master device that initiates the access request.

6. The AHB bus matrix according to claim 5, characterized in that, The timeout detection unit is configured to detect the response time of the slave device for executing the write request when the slave control unit forwards the write request and corresponding write data received to the corresponding slave device; the timeout detection unit is further configured to feed back a corresponding error response to the slave control unit when the response time exceeds a preset time length; and the timeout detection unit is further configured to feed back a corresponding error response to the slave control unit when the response time exceeds a preset time length. The timeout detection unit is further configured to feed back a corresponding successful response to the slave control unit when the response duration does not exceed the preset duration.

7. The AHB bus matrix according to claim 3, characterized in that, When the access request is a read request, the cache unit is configured to receive the read request from the master device; The cache unit is further configured to receive read data read out by the master control unit according to the read request, and read out the read data to the master device initiating the access request, and receive a next read request of the master device.

8. The AHB bus matrix according to claim 7, characterized in that, The master control unit is configured to select a corresponding slave control unit according to a target address of the read request in the cache unit, so as to forward the read request to the selected slave control unit; The master control unit is further configured to read out the read data to the cache unit after receiving the successful response and the corresponding read data fed back by the slave control unit in processing the read request; The master control unit is further configured to feed back an error response to the master device initiating the access request after receiving an error response fed back by the slave control unit in processing the read request.

9. The AHB bus matrix according to claim 8, characterized in that, The timeout detection unit is configured to detect a response duration of the slave device in executing the read request when the slave control unit forwards the received read request to a corresponding slave device; The timeout detection unit is further configured to feed back a corresponding error response to the slave control unit when the response duration exceeds the preset duration; The timeout detection unit is further configured to feed back a corresponding successful response to the slave control unit when the response duration does not exceed the preset duration, and read out read data read out by the slave device to the slave control unit.

10. A system on chip, characterized by An AHB bus matrix, a plurality of master devices and a plurality of slave devices, wherein the AHB bus matrix is connected between the plurality of master devices and the plurality of slave devices, and the AHB bus matrix comprises any one of the AHB bus matrixs in claims 1-9.

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