Programmable logic circuit device and FPGA (Field Programmable Gate Array) using same

Abstract

In conventional eFPGAs, there is a problem of improving the package logic density, and therefore there is a need for a programmable logic circuit having a novel structure that can solve the problem. A programmable logic circuit includes a plurality of channels sequentially connected in a direction in which an input signal of the programmable logic circuit flows, and each of the plurality of channels includes one or more logic cells. An input signal flowing to a channel is input to each logic cell via an input-side selector circuit capable of program control, and an output signal from each logic cell is output as an input signal flowing to a next channel connected to the channel, and / or as an output signal of the programmable logic circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a programmable logic circuit device suitable for mounting on an application specific integrated circuit (ASIC) such as a system on chip (SoC), and an FPGA (Field Programmable Gate Array) using the same. BACKGROUND

[0002] There is an IC (Integrated Circuit) product called an ASIC (Application Specific Integrated Circuit) that is designed and manufactured to order for a specific purpose. An ASIC is a semiconductor integrated circuit that is designed and manufactured to combine the logic functions required for a certain specific device or purpose, but it is sometimes difficult to change the logic functions mounted thereon after manufacture.

[0003] However, in recent years, with the large-scale and high-cost of ASICs, the cases where the logic is to be modified due to defects found after manufacture, or the cases where new functions are to be added, are increasing. Therefore, people have gradually adopted a method of mounting a programmable logic circuit block such as an FPGA (Field Programmable Gate Array) device on an ASIC so that defects can be modified or functions can be added. Here, the FPGA portion mounted on the ASIC is referred to as an "eFPGA (Embedded FPGA)".

[0004] The logic cells of an eFPGA use LUTs (Look Up Tables) that directly express truth tables. Regarding the memory used in the LUT, compared to the case where SRAM (Static Random Access Memory) is used in a standard FPGA that is not mounted on an ASIC, it is not easy to design to use a large number of small SRAM memories in an ASIC. Therefore, in an eFPGA within an ASIC, FFs (Flip-Flops) are used. However, FFs generally require several times (for example, 6 to 10 times) the area compared to SRAM. Also, when a LUT with multiple outputs (for example, a 4-input 3-output LUT) is used, FFs are required for all of the outputs (in the case of a 4-input 3-output LUT, a total of 3 FFs). Therefore, in an eFPGA, compared to a standard FPGA, the area of the logic cells that can be packaged with the same amount of logic will also become several times. Therefore, there are certain problems from the viewpoint of packing logic density.

[0005] In addition, when the wiring connection structure of the eFPGA is a structure called "island type", programmable logic blocks (LBs) are arranged in a lattice shape, and a structure is formed in which the LBs are connected by connection boxes (CBs) and switch boxes (SBs). Furthermore, a plurality of logic cells are provided in the LBs, and the logic cells are connected to each other by local connection blocks (LCBs). The logic cells in the LBs are typically LUTs (Look Up Tables) of M outputs and N inputs, but in the connection by the LCBs, most of the connections are "full crossbar connections" in which the outputs of all the logic cells are connected to the inputs of all the logic cells, and thus the number of multiplexers and configuration memories required for switching the wiring increases. This is also a factor that prevents an increase in the packaging logic density of the eFPGA. SUMMARY

[0006] As described above, in the conventional eFPGA, there is a problem in that the packaging logic density cannot be increased, and thus there is a demand for a programmable logic circuit having a new structure that can solve the problem.

[0007] The present application has been achieved in view of the above-described circumstances, and has an object to provide a programmable logic circuit having a new structure that can solve the above-described problem, an FPGA using the programmable logic circuit, and a logic block of the FPGA.

[0008] In order to solve the above-described problem, the inventors of the present application have conceived that a wiring architecture different from the conventional one can be provided by focusing on the structure of a netlist that is a form of expression of a logic circuit to be packaged, and thus have completed the programmable logic circuit, the FPGA using the programmable logic circuit, and the logic block of the FPGA of the present application.

[0009] According to the present application, the following application can be provided.

[0010] (1) A programmable logic circuit characterized by comprising: In the programmable logic circuit, a plurality of lanes are connected in series in a direction in which an input signal flows in the programmable logic circuit, The plurality of lanes each have one or more logic cells, input an input signal flowing to the lane to each of the logic cells via an input-side selector circuit that is programmable, and output an output signal from each of the logic cells as an input signal flowing to a next lane connected to the lane and / or as an output signal of the programmable logic circuit, The above-mentioned logic unit has a basic logic unit of a node of a netlist of a gate level, The basic logic unit is a programmable circuit constituted by adding a programmable non-circuit to the input and output of a basic logic operation element. (2) The programmable logic circuit according to the above (1), characterized in that, The input signal of each of the channels includes an input signal of the programmable logic circuit. (3) The programmable logic circuit according to the above (2), characterized in that, At least one of the channels receives an input signal of the programmable logic circuit from a previous channel connected to the channel. (4) The programmable logic circuit according to the above (1), characterized in that, At least one of the channels has a wiring that feeds back an output signal from the logic unit as an input signal of a previous channel connected to the channel or the channel. (5) The programmable logic circuit according to the above (1), characterized in that, At least one of the channels has a wiring that feeds forward an output signal from the logic unit as an input signal of a next channel connected to the channel. (6) The programmable logic circuit according to the above (1), characterized in that, At least one of the channels has a wiring that skips output of an output signal from the logic unit as an input signal of another programmable logic circuit. (7) The programmable logic circuit according to the above (1), characterized in that, Each of the channels is constituted by mapping nodes of a netlist of a logic unit level, which constitute the netlist according to a hierarchy along a direction flowing from an input side to an output side, to the logic units provided in each of the channels. (8) The programmable logic circuit according to the above (7), characterized in that, The mapping of the nodes is mapping to the logic units provided in each of the channels according to a connection order number of the channels in the programmable logic circuit. (9) The programmable logic circuit according to the above (1), characterized in that, A flip-flop (FF) is provided at an output side of the logic unit provided in each of the channels. (10) The programmable logic circuit according to the above (1), characterized in that, An output side selector circuit is provided at an output side of the logic unit provided in each of the channels. (11) The programmable logic circuit according to the above (1), characterized in that, The above logic unit is programmable by switching the input and output of the above basic logic unit according to the connection relationship of the nodes in the above netlist. (12) The programmable logic circuit according to the above (11), wherein The above logic unit has a combination logic unit formed by combining a plurality of the above basic logic units, The combination logic unit has a plurality of basic logic units covering a plurality of nodes of a graph constituting a netlist. (13) The programmable logic circuit according to the above (12), wherein In a case where the number of the above combined basic logic units is set to an integer n of 2 or more, and the number of inputs of each basic logic unit is set to an integer m of 2 or more, The above combination logic unit is an (m-1) x n + 1 input n output logic unit formed by combining n basic logic units in a manner capable of switching input signals in order to express node connections of 2 or more patterns. (14) The programmable logic circuit according to the above (12), wherein The above combination logic unit has a plurality of outputs, The above programmable logic circuit has: one or more selectors configured to be input with at least two or more output signals from the above combination logic unit and configured to output a selected signal; and a flip-flop (FF) configured to be input with an output signal from the above selector. (15) The programmable logic circuit according to the above (14), wherein The above one or more selectors are configured to be further input with a constant signal. (16) The programmable logic circuit according to the above (1), wherein The programmable logic circuit is a logic block of an FPGA. (17) An FPGA in which the programmable logic circuit according to the above (1) is packaged as a logic block. (18) A programmable logic circuit packaged in a logic block (LB) constituting an FPGA, The programmable logic circuit has: a combination logic unit (PAE) formed by combining a plurality of basic logic units (PA), programmed to switch the input and output of the above basic logic units according to the connection relationship of the nodes in a netlist, and output a plurality of output signals; and 1 or more selectors configured to be input with at least 2 or more output signals from the above-mentioned combinational logic units, and configured to output a selected signal; and a flip-flop (FF) configured to be input with an output signal from the above-mentioned selector.

[0011] According to such a configuration, the nodes on the netlist (nodes constituting the netlist according to the levels in the direction flowing from the input side to the output side) can be mapped to the logic units provided in the plurality of channels according to the number of levels of the channels. Thus, it is not necessary to provide a "full crossbar connection" that connects the outputs of all the logic units provided in the programmable logic circuit to the inputs of all the logic units, and thus the number of configuration memories required for programming can be reduced.

[0012] Note that the following embodiments describe features and other configurations of the present application from other aspects, and the drawings illustrate the same. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A mode diagram showing the wiring architecture of an island-style FPGA.

[0014] Figure 2 A mode diagram showing the logic units of an LCB having a full crossbar connection.

[0015] Figure 3 A mode diagram showing a netlist of a logic unit.

[0016] Figure 4 A mode diagram showing a logic unit related to one embodiment of the present application.

[0017] Figure 5 An explanatory diagram showing mapping of a logic unit.

[0018] Figure 6 A mode diagram showing a channel in a logic unit related to Modification 1 of one embodiment.

[0019] Figure 7 A mode diagram showing a logic unit related to Modification 1.

[0020] Figure 8 A mode diagram showing a logic unit related to Modification 1.

[0021] Figure 9 A mode diagram showing a logic unit related to Modification 2 of one embodiment.

[0022] Figure 10 A mode diagram showing the structure of a PAE.

[0023] Figure 11A mode chart for explaining a technology mapping of a PAE.

[0024] Figure 12 A mode chart for explaining a technology mapping of a PAE.

[0025] Figure 13 A mode chart for showing a structure of a PAE.

[0026] Figure 14 A mode chart for showing a modification example of a PAE.

[0027] Figure 15 A mode chart for showing a modification example of a PAE.

[0028] Figure 16 A mode chart for showing a modification example of a PAE.

[0029] Figure 17 A mode chart for showing a modification example of a PAE.

[0030] Figure 18 A mode chart for showing a modification example of a logic unit.

[0031] Figure 19 A mode chart for showing a modification example of a logic unit.

[0032] Figure 20 A mode chart for showing a modification example of a wiring of a logic unit.

[0033] Figure 21 A mode chart for showing a modification example of a wiring of a logic unit.

[0034] Figure 22 A mode chart for showing a modification example of a wiring of a logic unit.

[0035] Figure 23 A mode chart for showing a modification example of a wiring of a logic unit.

[0036] Figure 24 A mode chart for showing a modification example of a wiring of a logic unit.

[0037] Figure 25 A mode chart for showing a modification example of a wiring of a logic unit.

[0038] Figure 26 A mode chart for showing a modification example of a wiring of a logic unit. DETAILED DESCRIPTION

[0039] Hereinafter, one embodiment of the present application will be explained in detail with reference to the drawings.

[0040] First, the basic concept of the present application is explained in comparison with the conventional structure.

[0041] (Basic Concept) As described above, the conventional full crossbar connection of the logic cells within the LCB takes a LUT capable of switching the input as the main object, and although the degree of freedom of the wiring is high, a large number of extra wirings and configuration memories for switching the above wirings are required accordingly, and there is a limit in realizing the reduction of the packaging density.

[0042] In view of this, the inventors of the present application have realized that if the signal flow from the input to the output in the netlist is considered, the number of wirings and the number of configuration memories can be greatly reduced compared with the conventional full crossbar connection, and thus the present application has been completed.

[0043] (Wiring Architecture of Island FPGA) Figure 1 To show the schematic diagram of the conventional island FPGA 1, Figure 2 To show the conceptual diagram of the wiring architecture provided in the logic block 2 of the FPGA 1.

[0044] In the island FPGA 1, as shown in Figure 1 , the logic blocks (LB) 2 are provided in a two-dimensional matrix, and these logic blocks 2 are connected via programmable wirings such as the switch blocks (SB) 3 and the connection blocks (CB) 4. As shown in Figure 2 , a plurality of 4-input LUTs (Look-Up Tables) 5 are provided in the above logic blocks 2 as logic cells, and the plurality of LUTs 5 are locally wired by the crossbar connection realized by the local connection blocks (LCB) 6. In the crossbar connection, a wiring architecture in which the outputs of arbitrary LUTs 5 are all connected to all the inputs of arbitrary logic cells is adopted in consideration of the flexibility of the logic circuit design. Therefore, it is called "full crossbar connection".

[0045] In the case of the above full crossbar connection, the number of configuration memories required for the wiring within the logic block 2 is calculated in the following manner. For example, in the case where the LUTs (logic cells) 5 packaged in the logic block are 4-input 3-output LUTs, and the 4-input 3-output LUTs are full crossbar connected in a 4-in-line manner, regarding the number of outputs of the LCB 6 providing the full crossbar connection, since each logic cell is 4-input, the total of 4 logic cells is 16 (= 4 inputs x 4). On the other hand, the number of inputs is the number of inputs 10 from the outside and the number of feedback lines 12 (= 3 x 4) from each logic cell, totaling 22 inputs.

[0046] Therefore, in the case of the LCB 6, the number of configuration memories required for switching the internal wiring of the logic block 2 is calculated in the following equation, and is 80 bits.

[0047] 4 x 4 x ceil(log2(22)) = 16 x 5 = 80 bit In addition, in the case of the LCB6 of 22 inputs and 16 outputs, since there are 16 multiplexers (MUXs) of 2-to-1 of 22 inputs and 1 output, 21 multiplexers of 2-to-1 of 16 sets are required. Therefore, in the LCB6, a total of 336 (=21 x 16) multiplexers of 2-to-1 are required.

[0048] (Wiring architecture of the present application) Compared with the wiring architecture using the conventional LCB6 as described above, the present application focuses on a netlist, and provides a new wiring architecture that takes into account the signal flow from the input to the output that is considered to be common in the netlist.

[0049] Figure 3 As shown in the middle symbol 8, in logic synthesis, the netlist of the gate level is replaced with the netlist of the 4-input 3-output logic cell. In such a netlist 8, generally, the signal of the calculation result flows from the input (i0 to i8) to the output (P0[0] to P0[2]). Therefore, when designing the wiring architecture based on such a netlist 8, it is not necessary to connect the output of an arbitrary logic cell to all the inputs of an arbitrary logic cell as in the full crossbar connection.

[0050] Based on the above insight, the logic block in the FPGA of the present application does not perform the full crossbar connection for all the logic cells, but provides a wiring architecture that arranges a plurality of channels in order as a basic unit of a plurality of logic cells (channels) and focuses on the connection of the output and the input between the adjacent channels.

[0051] Figure 4 A logic block 10 of the FPGA related to the 1st embodiment of the present application is shown. In the logic block 10, a 1st channel 11 (order level 1) configured to be connected in order from the input side toward the output side of the logic block 10 and a 2nd channel 12 (order level 2) configured to be arranged on the output side are provided. In the logic block 10, 2 of the 4 logic cells 13 are encapsulated in the 1st channel 11 and 2 are encapsulated in the 2nd channel 12, respectively.

[0052] Ten external input signals 14 are supplied to the logic block 10, and four input signals are each selected from the ten external input signals by input selector circuits (MUXs: multiplexers) 16 and input to the respective logic cells 13 provided in the first channel 11. Subsequently, the ten external input signals are selected by input selector circuits (MUXs) 17 in combination with the six internal input signals output from the respective logic cells 13 of the first channel 11, so that four input signals are respectively input to the respective logic cells 13 provided in the second channel 12.

[0053] Subsequently, the output signals 15 of the logic block 10 are output via output selector circuits 18, 19 provided on the output side of the respective logic cells 13, and the number of the output signals is six from the first channel 11 and six from the second channel 12, for a total of twelve.

[0054] Note that although not shown in the figure, additional wirings can be provided. For example, a wiring (skip wiring) that skips connection of a specific wiring of the first channel 11 to another wiring block can be provided via an optional flip-flop (FF) as needed. In addition, as in the present example, the output of the logic cells 13 within the channel can pass through FFs 21, 22. In this case, in order to suppress the output signals that cause an increase in the wirings, output selector circuits (MUXs) 18, 19 can be added.

[0055] Further, although not shown in the figure, unnecessary wirings can be deleted. For example, each input selector circuit 17 of each logic cell 13 of the second channel 12 can delete a part of the ten external input signals and the six signals from the first channel 11, and select from fewer wirings.

[0056] For the logic block 10, the number of configuration memories required is calculated in the following manner.

[0057] That is, of the total four 4-input 3-output logic cells 13 packaged in the logic block, two logic cells 13 are provided in the first channel 11 and two logic cells 13 are provided in the second channel 12. In this case, the number of configuration memories for selecting the input signals of each logic cell 13 of the first channel 11 is calculated in the following equation, and is 32 bits.

[0058] 4 x 2 x ceil(log2(10)) = 8 x 4 = 32 Next, since the number of inputs is 16, the number of configuration memories for selecting the input signals of each logic cell 13 of the second channel 12 is calculated in the following equation, and is 32 bits.

[0059] 4 x 2 x ceil(log2(16)) = 8 x 4 = 32 Therefore, the number of configuration memories required to switch the internal wiring of the logic block is 64 bits (= 32 + 32) in total, which is 20% less than 80 bits in the case of the full crossbar connection.

[0060] In the case of the connection architecture, there are 4 input multiplexers each of which is 10-input in each of the 2 logic units 13 of the 1st channel, for a total of 8, so if this is converted to 2-input 1 -output (2-to-1) multiplexers, this is 10-1 = 9, and therefore the number of 2-input 1 -output multiplexers of the 1st channel is 2 x 4 x 9 = 72.

[0061] Next, when the same calculation is performed for the 2nd channel, there are 8 16-input multiplexers, and the 16-input multiplexers are equivalent to 15 2-input 1 -output multiplexers, so the number of 2-input 1 -output multiplexers of the 2nd channel is 8 x 15 = 120.

[0062] Thus, in the logic block, a total of 192 (= 72 + 120) multiplexers are required.

[0063] Therefore, the scale of the multiplexers can be reduced by at least 43% compared to the conventional 336.

[0064] (Clustering based on netlist) Next, a method of clustering a netlist using the logic block (regarded as 1 cluster) of the present application will be described with reference to FIG. 8. Figure 3 The netlist 8 using the 4-input 3 -output logic unit shown in FIG. 8 will be described. Note that hereinafter, the 1st channel 11 and the 2nd channel 12 will be referred to as the order level 1, the order level 2, and the order level N, respectively, according to the hierarchy (depth) of the netlist.

[0065] First, for the purpose of clustering, the logic block 10 of the 1st embodiment is described by the following conditions.

[0066] • Number of logic units in a cluster = 4 • Number of channels of a cluster (channel order) = 2 • Maximum number of input signals = 10 • Maximum number of logic units of the 1st channel (order level 1) = 2 • Maximum number of logic units of the 2nd channel (order level 2) = 2 In clustering, from the nodes (black dots in the netlist) constituting the netlist, the nodes satisfying the above conditions, i.e., the logic units 13, are determined as clustering candidates. Figure 3

[0067] ​First, as Step 1, the number of stages of the channels within the logic block 10 is determined. In the case of the present embodiment, since it is composed of the number of stages 1 and the number of stages 2, it is "2". In the case where the number of stages is "2", the logic block 10 can be mapped so as to cover specific 2 levels in the hierarchy of the netlist. Note that mapping can also be performed within 1 level.

[0068] Next, as Step 2, from the level located closest to the input side in the netlist, a combination of logic units (nodes) satisfying the above level condition is selected. Subsequently, the selected candidate is added to the selection candidate list as a candidate logic unit in turn.

[0069] Further, as Step 3, from among the combinations of logic units added to the selection candidates, a logic unit satisfying all the other conditions is finally selected, thereby performing clustering, and finally, as Step 4, the selected (clustered) logic unit is deleted from the candidates.

[0070] Then, the above Steps 2 to 4 are repeated to fill each cluster with a logic unit reaching the maximum value of the above conditions. Then, if it cannot be continued, the un-mapped node is taken as an object, and the clustering is started again from Step 1.

[0071] In the case of the above example of the netlist, as shown in Figure 5 , it is possible to cluster into 2 logic clusters C1, C2. These C1, C2 clusters respectively correspond to the above logic block 10.

[0072] Thus, in the case where a specific netlist is mapped by the logic block 10 of the present embodiment, as a result, compared to the case where the same number of logic units are mapped under the premise of the conventional logic block 2 having a full crossbar connection LCB6, the area of the selector circuit used for the internal wiring of the logic block 10 can be reduced by at least 43%, and the configuration memory number of the selector circuit used for the internal wiring can be reduced by at least 20%.

[0073] According to such a structure, it is possible to provide a new-structure programmable logic circuit which solves the problem of improving the logic density existing in the conventional eFPGA, an FPGA using the same, and a logic block of the FPGA. Note that, in the case where the FPGA is configured using the logic block 10 of the above embodiment, the logic block 2 shown in Figure 1 may be replaced with the logic block 10 of the present embodiment, but the wiring concept and the number of wirings between the logic blocks are not limited to the case shown in Figure 1 .

[0074] (Modified Example 1) The logic block 10 of the above embodiment has two channels 11 and 12, and a total of four logic units 13, two of which are distributed in each channel. However, it is not limited to this. The channel order, the number of logic units 13 in the channel, the number of inputs of selector circuits 16 and 17, and the input signals can be customized according to the target netlist.

[0075] In other words, in this invention, the invention is not limited to the above-described embodiment in the following aspects: the total number of inputs and outputs, the number of logic units 13, the number of inputs and connection methods of input selector circuits 16 and 17; the number of output selector circuits 18 and 19, the number of inputs and connection methods of output selector circuits 18 and 19; the channel of the connection target, and whether it includes output flip-flops (FF) 21 and 22.

[0076] For example, in Figure 6 In the example of channel 23 shown, four logic units are configured in one channel 23. Furthermore, in this example, an output selector circuit 18 is shared between the two output terminals of logic unit 13. Further, in this example, a wiring and signal selector 25 (multiplexer) is provided for extracting signals to be skipped (signals destined for the next channel).

[0077] The two signal selectors 25 shown in the figure are used to connect the output of the logic unit 13 in this channel 23 to the input selector circuit of the channel other than the next channel. For example, they can be connected to the input selector circuit X (feedback wiring) of the logic unit of the channel before the order n (including itself (n=0)), or to the input selector circuit (feedforward wiring) of the channel after the order m. In addition, although there are two signal selectors 25 for skipping in the figure, their number and the connection method of the inputs can be freely set. In addition, in this figure, a portion of all outputs (totaling 3×4=12) of the logic units in the interval extraction channel are connected to the output selector 25, but the interval extraction method is not limited to this, and all outputs can also be connected.

[0078] It should be noted that... Figure 6 Examples and Figure 2 As with previous examples of crossbar switch connections, four logic units are arranged side-by-side. Therefore, for convenience, in this example, the required number of configuration memories is calculated as follows.

[0079] That is, four 4-input, 3-output logic units 13 are encapsulated in channel 23. In this case, if the number of inputs to the input multiplexer is set to 16, the number of configuration memories used to select the input signals of each logic unit 13 of the first channel 23 is calculated as follows, which is 64 bits.

[0080] 4 x 4 x ceil(log2(16)) = 16 x 4 = 64 Further, in the case of this configuration, since there are 4 input multiplexers each of which is 10-input in each of the 4 logical units 13 of the 1st channel, the total is 16, and if this is converted into a 2-input 1 -output (2-to-1) multiplexer, this is 10-1 = 9, and therefore the number of 2-input 1 -output multiplexers of the 1st channel is 4 x 4 x 9 = 144.

[0081] On the other hand, in this example, as described above, 1 output selector circuit 18 is shared between 2 output terminals of the logical unit 13. Further, 1 output selector circuit is shared between 2 logical units. In the example shown in this figure, the number of FFs and output multiplexers is 8 each. Since this is 12 in the above embodiment, the configuration is simplified accordingly. Although 6 x 1 = 6 bits of configuration memory are added due to the addition of the output selector circuit 18, and 2 x 2 = 4 bits of configuration memory are added due to the addition of the output selector circuit 25, the total is 10 bits of configuration memory added, but compared to the embodiment of Figure 2 the embodiment of

[0082] In addition, Figure 7 is an example of a logical block of the channel 23 shown, Figure 6 is a figure in which 3 channels 23 are provided in 1 logical block 10 and the wiring between different logical blocks 10 is shown. In this example, the configuration is the same as the above-described Figure 8 and Figure 2 compared to the example of Figure 4 has twice the number of logical units, although it is not possible to simply compare this to the above-described prior art, but compared to a logical block connected to a crossbar switch having the same number of logical units, it is possible to reduce a considerable amount of configuration memory.

[0083] (Regarding the logical unit) In addition, in the above-described embodiment, although it is also possible to use a conventional LUT as the logical unit, if a "PAE circuit (combinational logic unit)" which is able to reduce the number of configuration memories of the logical unit itself compared to a conventional LUT is used, it is possible to improve the packaging density in addition to reducing the number of configuration memories required for the above-described wiring.

[0084] Figure 9 an example in which 3 levels of channels are provided as the logical block 10", and 3 4-input 3 -output PAE circuits 26 are provided as the logical unit in each channel is shown. This PAE circuit 26 is, for example, as shown in Figure 10(a), (b), three PA circuits (programmable AND circuit: basic logic unit) 27 are connected in a manner that enables switching. Further, each PA circuit 27 is a programmable circuit configured by attaching a programmable NOT circuit 29 to a basic logic operation element (AND gate, OR gate, NOT gate, etc.) 28, and enables programming in a manner that switches the input and output of the basic logic unit 27 according to the connection relationship of the nodes in the netlist described above.

[0085] Regarding the number of configuration memories used for the PAE circuit 26, in the case of the conventional logic unit, i.e., a 4-input LUT (4LUT), the number of configuration memories used is 16 bits, and in contrast, the 4-input PAE circuit 26 of the present embodiment is 8 bits, which is half of the former.

[0086] As the embodiment, although only the conventional 4-input 3-output LUT is replaced by a 4-input 3-output PAE as the logic unit of the first embodiment, the effect of reducing the number of configuration memories can be obtained, but if the process mapping using the PAE is performed in the following manner, the practical packaging density can be further improved.

[0087] That is, in this case, the netlist at the gate level (AIG) shown in Figure 11 is used.

[0088] (1) Any one of the node graphs (node graphs that exhibit the PAE circuit) of 12 (a) (b) (c) is matched from the AIG; (2) Mapped to the logic unit; (3) Returns to (1) until all nodes are covered; (4) Ends when all nodes are mapped.

[0089] When mapping the netlist shown in Figure 11 using a 4-input 3-output PAE, as shown by the lasso in the figure, coverage can be performed. When mapped to the PAE circuit of the present embodiment, since the output from the node within the range to be covered can be used, there is no case where the target node is repeatedly covered. As a result, in this example, eight 4-input 3-output combinational logic units (8 bits of configuration memory) can be mapped, and the configuration memory amount is 8 bits x 8 = 64 bits. In the case of a 4-LUT, according to the result of the process mapping, 14 are required, i.e., 16 bits x 14 = 224 bits. Thus, the configuration memory amount when using the PAE circuit is less than 1 / 3 of that when using the LUT.

[0090] Further, the average coverage of the netlist of the present embodiment is 2.52 nodes, which exceeds the 2.43 nodes of the LUT. As a result, in the evaluation using 29 benchmark circuits in the present embodiment, the average configuration memory reduction rate reached 51.6%, and it was possible to halve the configuration memory. Furthermore, the maximum configuration memory reduction rate was 66.5%, and the minimum configuration memory reduction rate was 23.0%, and the memory was reduced from the LUT of the past.

[0091] According to the example described above, there is provided a programmable logic circuit (PAE and combination thereof) which is a logic cell for an embedded FPGA mounted on an ASIC, has a basic logic cell (PX circuit) which is a node of a netlist constituting a gate level, and is a programmable circuit constituted by attaching a programmable non-circuit to a basic logic operation element, and which is programmable in a manner of switching input and output of the basic logic cell according to a connection relationship of the node in the above-described netlist.

[0092] Note that the PAE circuit 26 described above is a 4-input 3-output, but the number of inputs of the basic logic operation element is not limited to 2, and the PAE circuit is not limited thereto.

[0093] According to the present embodiment, when a combination logic cell is constituted by combining a graph of 2 or more n-connected m-input basic logic cells, the number of inputs is (m-1) x n + 1, and the number of outputs is n. m and n can be any number of 2 or more.

[0094] Figure 13 To amplify the PAE circuit 26 shown in Figure 10 (b), the graph is shown in (c). Furthermore, in the graph, the basic logic cell 27 in (b) is denoted by PX. Figure 10 In this example, a PAE circuit 26 is shown in which the number of inputs m of the basic logic cell (PX) 27 is 2, and the number of connection cells n is 3. The number of inputs of the PAE circuit 26 is (m-1) x n + 1 = (2-1) x 3 + 1 = 4, and the number of outputs is n, i.e., 3. The number of inputs m of the basic logic cell 27 is 2, and the connection relationship of the graph formed by connecting n = 3 of the above-described basic logic cells 27 is as described above Figure 12 (a) to (c), there are 3 patterns (circles indicate basic logic cells). To realize such a plurality of node connection relationships, the present PAE circuit 26 has a function of switching the connection relationship of the internal logic nodes by a multiplexer or the like (denoted by a symbol 30 in Figure 13 ). Furthermore, the PAE circuit 26 has a memory (denoted by a symbol 32 in Figure 13(represented by symbol 31), which can be used to set the internal memory 31 of PAE circuit 26 in conjunction with the connection pattern of the nodes that constitute the netlist.

[0095] Furthermore, in the example of basic logic unit 27 connecting n=4 inputs and m=2 inputs, the number of diagrams is 7 patterns (not shown). Combining these 7 patterns with 2 diagrams forms a (2-1)×4+1=5 input, 4-output combinational logic unit, for example, as shown below. Figures 14-17 As shown.

[0096] In these examples, a combinational logic unit is used to implement the connection relationship between two basic logic units (nodes), but it is not limited to two types. A combinational logic unit can also be used to implement more than two types of node connection relationships.

[0097] In addition, the above example is for the case where there are 4 basic logic units, but the number n can be any value.

[0098] It should be explained that Figure 10 (b) The programmable NOT circuit 29 of the PA circuit 27 shown can be used as follows Figure 18 As shown in (a), this can be implemented using NOT gates and multiplexers, or as shown in [the diagram]. Figure 18 As shown in (b), this is implemented using an XOR gate. Additionally, as a basic logic element 28, as... Figure 19 As shown, in addition to AND gates and OR gates, NAND gates, NOR gates, etc. can also be used to construct them.

[0099] In the example above, a programmable NOT circuit is configured at one input of the basic logic element, but it can also be configured as follows: Figure 20 As shown in (a), programmable NOT circuits are set at both inputs. Additionally, as... Figure 20 As shown in (b), the number of inputs to the basic logic unit is not limited to 2. (Comparison of the number of configured memory modules) The number of configured memories is compared for the case where there are 4 logic units as described above, as shown in the table below.

[0100] It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without changing the spirit of the present invention.

[0101] For example, one of the above-described embodiments ( Figure 4 The input selector circuit 17 of each logic unit 13 in the second channel 12 is selected from 10 external input signals to the second channel 12 and 6 signals from the first channel 11, but is not limited to this, and some wiring can also be deleted.

[0102] For example, the logic unit 13 on the left side of the second channel 12 selects the left 4 of the 6 outputs from the 2 logic units 13 of the first channel 11, and similarly, the logic unit on the right side of the second channel 12 selects the right 4 of the 6 outputs from the 2 logic units 13 of the first channel 11. Further, the second channel 12 each selects 4 different signals from the 10 external input signals. According to this configuration, each input selector circuit 17 of the second channel 12 can select from 8 wires.

[0103] Further, as another example, in the logic unit 13 of the second channel 12, only the leftmost input signal of the 4 input signals is selected from the 16 signals, and the remaining 3 input signals each select 2 different signals from the 6 output signals of the first channel 11 and the external input signals. Thus, in the logic unit 13 of the second channel 12, only the leftmost input is selected from the 16 wires, and the remaining 3 inputs can be selected from the 8 wires.

[0104] Further, as another example, in each channel of the embodiment, it is possible to perform the wiring as shown in Figures 21-26

[0105] Figure 21 In the example of Figure 22 , the number of inputs of the input selector 18 of the logic unit 13 is 4. In contrast, in another example shown in Figure 21 , the number of inputs of the input selector 18 of the logic unit 13 is 2. In the input wires of the input selector 18 described above, Figure 22 , the number of inputs is halved. In this case, as shown in Figure 22 , it is preferable to stagger the selected wires. In this example, the amount of staggering is one by one, but the staggering method is not limited thereto, and it is also possible to stagger every n wires, or to select any 2 wires.

[0106] Further, in this example, although the number of inputs of the input selector is reduced from 4 inputs to 2 inputs, it is also possible to directly reduce the original number of inputs. For example, if the original number of inputs is 20 inputs (external inputs, first channel, skip wires), it is possible to reduce it to 8 inputs, in which case, it is possible to arrange the 20 inputs as appropriate, and select 8 input wires from the 20 wires, staggering one by one.

[0107] Further, as shown in Figure 23 , it is also possible to arrange the logic unit 13 of Figure 21 and the logic unit 13 of Figure 22 side by side within one channel, and connect them by wires. ​

[0108] Further, as shown in Figure 24 , a wiring 28 can be provided in one channel, which connects the output of the logic unit 13 to the input selector 18 of the other logic unit 13 (in this example, the adjacent logic unit).

[0109] Further, in the example shown in Figure 4 , the FF is connected to all the outputs of the logic unit 13, but it can also be connected to only some of the outputs, as shown in Figure 25 . In this example, the FF is connected to only one of the three outputs.

[0110] Further, as shown in Figure 26 , a variation of the example shown in Figure 6 is shown. In this example, as in the example of Figure 9 , four logic units are arranged in one channel 23. Further, one output selector circuit 18 is shared between two output terminals of the logic unit 13, and a wiring and a signal selector 25 (multiplexer) for extracting a signal to be skipped (a signal to the next channel) are provided. However, in this example, a constant (0 or 1) is supplied from a memory provided in the logic block or an external input to each selector 18, 25, and the output is configured so that the output value from the above-described logic selector can also be selected. Further, in this example, a constant input is installed not only for the output selector 18, 25, but also for the input selector 16 and the output FF 19 of the logic unit 13. Note that in the case of a channel having a structure as shown in Figures 21-26 , even in a logic block 10 that does not necessarily have two or more channels, a certain effect can be obtained in terms of reducing the arrangement of memories and reducing the package area.

[0111] Further, in the above-described one embodiment, although the logic units are assumed to be LUTs and PAEs, they can also be used in combination. For example, LUTs and PAEs can be used in combination as the logic units in one channel, or LUTs and PAEs can be used for each channel. Further, a programmable logic circuit using only LUTs as the logic units and a programmable logic circuit using only PAEs can be packaged in combination in one FPGA.

[0112] Further, in the above-described one embodiment, the number of logic units used in the first channel and the second channel is the same, but the number of logic units used between channels can also be made different.

[0113] Further, in the above-described one embodiment, the programmable logic circuit (each circuit of PA, PX, and PAE) of the present application is embedded in the logic block of the FPGA, but it can also be applied to a reconfigurable logic device other than the FPGA. That is, the most direct application example of the present BLE is an eFPGA (embedded FPGA). In the case where a reconfigurable logic region is provided inside an SoC (System on Chip) or an ASIC (Application Specific Integrated Circuit), by embedding the programmable logic circuit of the present application, a high degree of control can be achieved while ensuring area efficiency and flexibility. Legend

[0114] 1…FPGA 2…Logic block 3…Switch block 4…Connection block 5…LUT 6…Local connection block 8…Net list 10…Logic block 11…1st channel 12…2nd channel 13…Logic unit 16, 17…Input selector circuit 18, 19…Output selector circuit 21, 22…Output flip-flop 23…Channel 25…Signal selector 26…PAE circuit 27…PA circuit

Claims

1. A programmable logic circuit, characterized by: in the programmable logic circuit, a plurality of channels connected in series in a direction in which an input signal of the programmable logic circuit flows, the plurality of channels each having one or more logic units, inputting an input signal flowing to the channel to each logic unit via an input-side selector circuit capable of being programmed, and outputting an output signal from each logic unit as an input signal flowing to a next channel connected to the channel and / or as an output signal of the programmable logic circuit, the logic unit having a basic logic unit constituting a node of a netlist of a gate level, the basic logic unit being a programmable circuit constituted by attaching a non-circuit capable of being programmed to an input and output of a basic logic operation element.

2. The programmable logic circuit according to claim 1, characterized in that: the input signal of each channel includes an input signal of the programmable logic circuit.

3. The programmable logic circuit according to claim 2, characterized in that: at least one of the channels receives the input signal of the programmable logic circuit from a previous channel connected to the channel.

4. The programmable logic circuit according to claim 1, characterized in that: at least one of the channels has a wiring feeding back an output signal from the logic unit as an input signal of a previous channel connected to the channel or the channel.

5. The programmable logic circuit according to claim 1, characterized in that: at least one of the channels has a wiring feeding forward an output signal from the logic unit as an input signal of a next channel connected to the channel.

6. The programmable logic circuit according to claim 1, characterized in that: at least one of the channels has a wiring skipping an output of an output signal from the logic unit as an input signal of another programmable logic circuit.

7. The programmable logic circuit according to claim 1, characterized in that: each channel is constituted by mapping a node constituting a netlist on a logic unit level according to a hierarchy in a direction in which an input signal flows from an input side to an output side to each logic unit provided in the channel.

8. The programmable logic circuit according to claim 7, characterized in that: the mapping of the node is mapping to each logic unit provided in the channel according to a connection order number of the channel in the programmable logic circuit.

9. The programmable logic circuit according to claim 1, characterized in that: a flip-flop (FF) is provided at an output side of the logic unit provided in the channel.

10. The programmable logic circuit according to claim 1, characterized in that: an output-side selector circuit is provided at an output side of the logic unit provided in the channel.

11. The programmable logic circuit according to claim 1, characterized in that: the logic unit is programmable in a manner of switching an input and output of the basic logic unit according to a connection relationship of a node in the netlist.

12. The programmable logic circuit according to claim 11, characterized in that: The logic unit has a combination logic unit formed by combining a plurality of the basic logic units, The combination logic unit has a plurality of basic logic units covering a plurality of nodes of a graph constituting a netlist.

13. The programmable logic circuit according to claim 12, wherein In a case where the number of the combined basic logic units is set to an integer n of 2 or more, and the number of inputs of each basic logic unit is set to an integer m of 2 or more, The combination logic unit is an (m-1) x n + 1-input n-output logic unit in which n basic logic units are combined in a manner that enables switching of input signals in order to express connection of nodes of 2 or more patterns.

14. The programmable logic circuit according to claim 12, wherein The combination logic unit has a plurality of outputs, The programmable logic circuit further has: one or more selectors configured to be input with at least 2 or more output signals from the combination logic unit and configured to output a selected signal; and a flip-flop (FF) configured to be input with an output signal from the selector.

15. The programmable logic circuit according to claim 14, wherein The one or more selectors are configured to be further input with a constant signal.

16. The programmable logic circuit according to claim 1, wherein The programmable logic circuit is a logic block of an FPGA.

17. An FPGA that packages the programmable logic circuit according to claim 1 as a logic block.

18. A programmable logic circuit that is packaged as a logic block (LB) constituting an FPGA, The programmable logic circuit has: a combination logic unit (PAE) formed by combining a plurality of basic logic units (PA), programmed to switch input and output of the basic logic units according to connection of nodes in a netlist, and output a plurality of output signals; and one or more selectors configured to be input with at least 2 or more output signals from the combination logic unit and configured to output a selected signal.

19. The programmable logic circuit according to claim 18, further having a flip-flop (FF) provided at a stage subsequent to the selector and configured to be input with an output signal from the selector.

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