Chip design tool, method, equipment and computer medium

Abstract

The invention discloses a chip design tool, method and device and a computer medium, and the tool comprises a chip connection relation setting module, a chip layout module and a chip wiring module. The chip connection relation setting module is used for setting the connection relation among a plurality of devices in the chip; the chip layout module is used for setting the layout relationship of the plurality of devices in the chip, and the layout relationship comprises the spatial positions of the plurality of devices in the chip and the relative positions of the plurality of devices; and the chip wiring module is used for carrying out wiring on the plurality of devices based on the connection relationship and the layout relationship to obtain a chip design result, and can play a role in improving the flexibility of chip design.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip design, and particularly relates to a chip design tool, method, device and computer medium. BACKGROUND

[0002] Computer aided design (CAD) software has gradually penetrated into various industries, bringing great convenience to designers in various industries. Among them, CAD software specially used for electronic design, also known as electronic design automation (EDA) software, can assist electronic design engineers to complete electronic design, simulation, verification and other processes. Moreover, with the increasing integration of electronic circuits, the number of transistors contained in today's very large scale integrated circuits is in the tens of thousands, and manual design has become an unrealistic task. EDA software tools have become an indispensable part of modern electronic design.

[0003] Since the design of electronic circuits is a very professional and complex task, and EDA software needs to be highly compatible with each link of electronic circuit design, the functions and types of EDA software are very diverse, such as system simulation design, printed circuit board design and verification, integrated circuit layout design, digital logic circuit design, analog circuit design, digital-analog hybrid design, system on chip design, etc. Although the current EDA tools are very rich, they still cannot meet the ever-increasing design requirements in the electronic design process, and the related circuit design software cannot meet the more flexible design requirements, and the flexibility is poor.

[0004] In 2.5D / 3D packaging design, the design of electronic circuits presents a new form and raises new issues to the industry, which changes from the connection between transistors to the connection between chiplet modules. Correspondingly, EDA design tools also face completely different problems and challenges from the past: from focusing on circuit connection between transistors to focusing on packaging structure design and die layout and circuit connection. At present, chiplet technology is in its infancy, and there is no mature tool in the EDA market for this design technology, which can provide a complete process operation platform from chiplet device selection, layout placement to chiplet wiring and DRC, to help 2.5D / 3D packaging design personnel to conveniently and quickly perform chip design work. SUMMARY

[0005] The embodiments of the present application provide an implementation scheme different from the related art, to solve the technical problem that the related circuit design software cannot meet the more flexible design requirements and the flexibility is poor in the related art.

[0006] In a first aspect, the present application provides a chip design tool, comprising a chip connection relationship setting module, a chip layout module, and a chip wiring module;

[0007] The chip connection relationship setting module sets the connection relationship between the plurality of devices in the chip.

[0008] The chip layout module sets the layout relationship of the plurality of devices in the chip, the layout relationship comprising the spatial positions of the plurality of devices in the chip and the relative positions between the plurality of devices.

[0009] The chip wiring module is configured to wire the plurality of devices based on the connection relationship and the layout relationship, to obtain a chip design result.

[0010] In a second aspect, the present application provides a chip design method applied to a chip design tool, the chip design tool comprising a chip connection relationship setting module, a chip layout module, and a chip wiring module, the chip connection relationship setting module comprising a first chip connection relationship setting module based on a schematic diagram and a second chip connection relationship setting module based on a netlist; the method comprising:

[0011] Obtaining the connection relationship between the plurality of devices in the chip set by a user through the first chip connection relationship setting module or the second chip connection relationship setting module;

[0012] Obtaining the layout relationship of the plurality of devices in the chip through the chip layout module, the layout relationship comprising the spatial positions of the plurality of devices in the chip and the relative positions between the plurality of devices.

[0013] Wiring the plurality of devices based on the connection relationship and the layout relationship through the chip wiring module, to obtain a chip design result.

[0014] In a third aspect, the present application provides an electronic device, comprising:

[0015] A processor; and

[0016] A memory configured to store executable instructions of the processor.

[0017] The processor is configured to execute any method in the second aspect or the possible implementation manners of the second aspect by executing the executable instructions.

[0018] In a fourth aspect, the present application provides a computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement any method in the second aspect or the possible implementation manners of the second aspect.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program which, when executed by a processor, implements the method of the second aspect or any possible implementation of the second aspect.

[0020] The chip design tool provided by the present application comprises a chip connection relationship setting module, a chip layout module and a chip wiring module. The chip connection relationship setting module sets the connection relationship between a plurality of devices in a chip. The chip layout module sets the layout relationship of the plurality of devices in the chip, and the layout relationship comprises the spatial positions of the plurality of devices in the chip and the relative positions between the plurality of devices. The chip wiring module is used to wire the plurality of devices based on the connection relationship and the layout relationship, and obtain a chip design result. Through the scheme of the present application, the user can first set the logical connection relationship from the chip connection relationship setting module, and then set the physical layout and wiring relationship through the chip layout module and the chip wiring module. The flexibility of chip design is greater, and the design efficiency is higher. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiment or related art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. In the drawings:

[0022] Figure 1a The structural schematic diagram of the chip design tool provided by an embodiment of the present application;

[0023] Figure 1b The schematic diagram of the chip layout page provided by an embodiment of the present application;

[0024] Figure 1c The page diagram of the interlayer related setting when the type of the interlayer is embedded provided by an embodiment of the present application;

[0025] Figure 1d The page of the interlayer related setting when the type of the interlayer is non-embedded provided by an embodiment of the present application;

[0026] Figure 1e The schematic diagram of the setting page of the stack provided by an embodiment of the present application;

[0027] Figure 1f The schematic diagram of the schematic diagram editing page provided by an embodiment of the present application;

[0028] Figure 1g The schematic diagram of the content displayed when the device library button of the schematic diagram editing page is clicked by the related personnel provided by an embodiment of the present application;

[0029] Figure 1h A schematic diagram of a chip design process is provided for an embodiment of the present application;

[0030] Figure 1i A schematic diagram of a chip design process is provided for another embodiment of the present application;

[0031] Figure 1j A schematic diagram of a chip design process is provided for another embodiment of the present application;

[0032] Figure 1k A schematic diagram of an architecture of a chip design tool is provided for another embodiment of the present application;

[0033] Figure 2 A flowchart of a chip design method is provided for an embodiment of the present application;

[0034] Figure 3 A schematic diagram of a structure of a chip design apparatus is provided for an embodiment of the present application;

[0035] Figure 4 Magnetic adsorption effect for device pin;

[0036] Figure 5 A schematic diagram of a structure of an electronic device is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0037] Embodiments of the present application are described below in detail, examples of which are shown in the accompanying drawings. The embodiments described below by reference to the drawings are examples and are intended to explain the present application, and should not be understood as limiting the present application.

[0038] The terms "first" and "second" and the like in the present application are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0039] First, the following explains and describes some of the terms in the embodiments of the present application, so as to facilitate understanding by those skilled in the art.

[0040] Die: refers to the chip produced in the factory, which only has a pad for packaging and cannot be directly applied to the actual circuit.

[0041] Chiplet: refers to a pre-manufactured die with specific functions that can be integrated and combined. It can also be an integrated functional chip (i.e., a chip after die packaging).

[0042] Design rules checking (DRC): through checklist and report checking methods, focusing on avoiding major design defects such as open circuits and short circuits. The inspection is carried out while following the printed circuit board (PCB) design quality control process and method.

[0043] Jump wire: also known as jump line, refers to a method of connecting two nodes on a printed circuit board directly with a wire due to design defects, testing purposes or other design considerations.

[0044] Interposer: an interposer, commonly used in distributed systems, can help exchange information between upper and lower nodes (such as connecting two chips).

[0045] Substrate: refers to a substrate or substrate, which is a board used for electronic product packaging, providing support and electrical connection for electronic components. The substrate material can be silicon, ceramic or organic material, and the specific selection of material depends on the specific requirements of the application.

[0046] The following specific examples will be described in detail. The following specific examples can be combined with each other, and the same or similar concepts or processes may not be described in some examples. The following will be described in conjunction with the accompanying drawings.

[0047] Figure 1a A structural diagram of a chip design tool is provided for an exemplary embodiment of the present application, which includes a chip connection relationship setting module 10, a chip layout module 13, and a chip wiring module 14;

[0048] The chip connection relationship setting module sets the connection relationship between multiple devices in the chip.

[0049] The chip layout module sets a layout relationship of the plurality of devices in the chip, and the layout relationship includes spatial positions of the plurality of devices in the chip and relative positions between the plurality of devices.

[0050] The chip wiring module is configured to wire the plurality of devices based on the connection relationship and the layout relationship, and obtain a chip design result.

[0051] In the embodiments of the present application, the connection relationship set by the chip connection relationship setting module can be understood as a logical connection relationship, the layout relationship set by the chip layout module can be understood as a physical layout, and the wiring set by the chip wiring module can be understood as a physical wiring. That is, the present application first sets the logical connection relationship between the devices, and then determines the physical layout and wiring to obtain the chip design result.

[0052] In the embodiments of the present application, the chip connection relationship setting module 10 can include a first chip connection relationship setting module 11 based on a schematic diagram and a second chip connection relationship setting module 12 based on a netlist, wherein a user sets the connection relationship between the plurality of devices in the chip through the first chip connection relationship setting module 11 or the second chip connection relationship setting module 12.

[0053] In some optional embodiments, the first chip connection relationship setting module 11 can further include a first display module configured to display a schematic diagram editing page, and a user can perform chip design by drawing a schematic diagram on the schematic diagram editing page.

[0054] In some optional embodiments, the second chip connection relationship setting module 12 can further include a second display module configured to display a netlist editing page, and a user can set netlist information on the netlist editing page.

[0055] The netlist information can include parameters of the netlist, and some of the parameters can be edited (such as pin network names), and some of the parameters cannot be edited (such as device names and pin numbers). A user can set the connection relationship of the pins of the devices by defining the pin network names.

[0056] In some optional embodiments, the chip design tool further includes a device library including a plurality of devices, and a user sets the connection relationship between the plurality of devices in the chip through the device library and the first chip connection relationship setting module, or sets the connection relationship between the plurality of devices in the chip through the device library and the second chip connection relationship setting module.

[0057] For example, a user can select a desired device in the device library, and then the user-selected device is displayed on a schematic editing page, and the user can edit the schematic pin information of the device, and then set the connection relationship between devices. Illustratively, a user can double-click a pin of a device schematic, and then set the network name to which the pin belongs. Similarly, a user can select a desired device in the device library, and then on a netlist editing page, the user can add a device, and then set the pin library name, the network name to which the pin belongs, and the like, to set the connection relationship between devices. In embodiments of the present application, the connection relationship between the above-mentioned multiple devices and the connection relationship between pins should be understood as a logical connection relationship.

[0058] In some optional embodiments, the devices in the device library include at least one of the following: chiplets, dies, interposers, and passive devices. For example, the devices in the device library include chiplets, dies, interposers, or passive devices; the interposer can be a passive interposer or an active interposer; the chiplet or die can be a logic chip or a memory chip; the device library classifies and displays the foregoing devices, and the classification categories include at least one of the following: sensors, power supplies, radio frequency circuits, memories, clocks, passive devices, and interposers.

[0059] In some embodiments, the passive device further includes an integrated passive device.

[0060] In some optional embodiments, the types of the foregoing interposers can include embedded and non-embedded types, and specifically, refer to Figure 1b the schematic diagram of the chip layout page shown in FIG. 6, Figure 1c the page schematic diagram of interposer-related settings when the type of the interposer is embedded, and Figure 1d the page schematic diagram of interposer-related settings when the type of the interposer is non-embedded.

[0061] In embodiments of the present application, the chip layout page can be understood as the page corresponding to the chip layout module.

[0062] Further, refer to Figure 1c the page diagram of interposer-related settings when the type of the interposer is embedded, and in some embodiments, the embedded depth of the interposer in the substrate can be 7 microns. As for the setting of the stack, it can be manually set by relevant personnel, and it can also be set by importing a tech file.

[0063] Further, further refer to Figure 1dWhen the type of the interposer is non-embedded, the page of the interposer related setting is shown in some embodiments, and the setting parameters for Ball can refer to Figure 1d As shown, the setting parameters for Ball can include row, column, pitch, and number, where the row can be 10, the column can be 20, the pitch can be 2 microns, and the number can be 200. As for the setting of the stack, it can be manually set by the relevant personnel, or it can be set by importing a tech file. Alternatively, the content of the setting page of the stack or the tech file can refer to Figure 1e As shown, details are not described herein.

[0064] In some embodiments, the chip design tool further includes a stack setting module, which receives user inputted stack setting to generate stack information for the above-mentioned device, and the stack information includes at least two stacks.

[0065] The setting of the stack includes at least one of the following: the wiring direction in the stack, the type of the stack, the material of the stack, the thickness of the stack, and the name of the stack.

[0066] In the embodiments of the present application, the interposer, RDL, and substrate can be designed in a stack. The user can set the number of stacks, the physical direction of the wiring in the stack, the type of the stack, and other parameters according to the requirements. For example, the user can set the wiring direction in the stack to be horizontal or vertical, or can also set it to be horizontal / vertical (i.e., both).

[0067] In some optional embodiments, the parameters of the netlist include the name of the device selected by the user from the device library, the pin number of the device, and the connection relationship between any devices, which are not limited by the present application.

[0068] In some optional embodiments, the connection relationship between the device pins is set by defining the pin network name of the pin. For example, the pins with the same pin network name are connected to each other.

[0069] In some optional embodiments, the aforementioned netlist information is displayed on the netlist editing page after being set.

[0070] In some optional embodiments, the aforementioned netlist information can be determined according to the netlist uploaded by the user. When the netlist information is determined by the netlist uploaded by the user, the tool can further include a prompt module for prompting the user to upload the netlist.

[0071] In some optional embodiments, the user can also download the current netlist to the local computer, so as to use other professional netlist editing tools to edit and input the netlist information.

[0072] In some optional embodiments of the present application, after the setting of the netlist information part is completed or all the settings are completed, the user can search for part of the netlist information through a filtering condition, where the filtering condition can be the name of a device, a pin number, etc.

[0073] In the embodiments of the present application, the netlist editing interface can edit an interposer, a redistribution layer (RDL) or a substrate, such as editing a pin number, a pin library name and a network name of a pin, etc.

[0074] In some optional embodiments of the present application, the tool further includes a switching module, configured to display a schematic diagram editing page corresponding to the first chip connection relationship setting module when detecting that the user triggers to start the first chip connection relationship setting module; and configured to display a netlist editing page corresponding to the second chip connection relationship setting module when detecting that the user triggers to start the second chip connection relationship setting module; where the schematic diagram editing page and the netlist editing page are used for the user to set the connection relationship between multiple devices in the chip.

[0075] Optionally, the switching module can be configured to switch from the netlist editing page to the chip layout page; and switch from the chip layout page to the netlist editing page.

[0076] Further, the user can select a device in a device library into a chip design in the schematic diagram editing page, specifically, the logical connection relationship between any devices can be designed. Specifically, the connection relationship between devices can include the connection relationship between device pins.

[0077] In some optional embodiments of the present application, Figure 1f For the schematic diagram of the schematic diagram editing page, in Figure 1f , the list of selected devices is below the group, and the schematic diagram editing area displays the pin numbers of the specific devices (i.e. Figure 1f “1”, “2” and the like in ), and the user's setting of the network of each pin, where when the networks of the pins of two devices are the same, the pins with the same network can be interactive. Further, the schematic diagram editing page can further include multiple icons that can operate on the device, such as edit, left-right mirror, up-down mirror, move, method, save, previous step, next step, and delete.

[0078] In some optional embodiments of the present application, the schematic diagram editing page further includes a button of a device library, when a relevant person clicks the button, the display content can refer to Figure 1g .

[0079] Optionally, the user can see all available devices in the device library on the schematic editing page, and can introduce the device needed by the user by dragging, and then define the logical connection relationship between the pins of each device in the form of drawing the circuit schematic, so as to realize the logic design of the chip.

[0080] In some optional embodiments of the present application, the connection relationship between the plurality of devices in the chip set by the user through the second chip connection relationship setting module 12, i.e. the netlist editing, is synchronized to the first chip connection relationship setting module 11 and the chip layout module in real time, so that the connection relationship between the plurality of devices set by the user through the second chip connection relationship setting module 12 can be displayed through the first display module, and the plurality of devices used by the user through the second chip connection relationship setting module 12 can also be presented through the chip layout module.

[0081] In some optional embodiments of the present application, the connection relationship between the plurality of devices in the chip set by the user through the first chip connection relationship setting module 11, i.e. the schematic editing, is synchronized to the second chip connection relationship setting module 12 and the chip layout module in real time, so that the connection relationship between the plurality of devices set by the user through the first chip connection relationship setting module 11 can be displayed through the second display module, and the plurality of devices used by the user through the first chip connection relationship setting module 11 can also be presented through the chip layout module.

[0082] In some optional embodiments, the user can select one of the first chip connection relationship setting module 11 and the above-mentioned second chip connection relationship setting module 12 to set the connection relationship between the plurality of devices in the chip.

[0083] In some optional embodiments of the present application, the aforementioned tool can be a client, and the user can view the historical chip design results created by the user in the aforementioned tool, wherein the chip design result mentioned in the present application can be saved as a chip project.

[0084] In some optional embodiments of the present application, when the user opens the chip design tool and creates a new chip project, the user can select only one of the first chip connection relationship setting module 11 and the above-mentioned second chip connection relationship setting module 12 to set the connection relationship between the plurality of devices in the chip through corresponding selection, so as to avoid the data processing delay caused by the synchronous update between the first chip connection relationship setting module 11 and the second chip connection relationship setting module 12.

[0085] In some optional embodiments of the present application, an interposer whose circuit design and wiring design have been completed can be imported into a device library as a standard device and reused by multiple users. At this time, the interposer can be directly selected and the connection relationship between the pins of the interposer and the pins of the chiplets can be edited on a schematic editing page or a netlist editing page.

[0086] Optionally, the interposer in the device library can be a silicon substrate without any wiring, and when interconnection between the chiplets or dies through the interposer is needed (i.e., 2.5D packaging), after the connection relationship between the chiplets or dies is determined, the layout relationship between the chiplets and the interposer is designed on a chip layout page, and after the design is completed, the internal wiring of the interposer is designed in a chip wiring module, thereby interconnecting the chiplets. Each completed interposer is captured by the device library to generate a new interposer device, so that the interposer can be reused in subsequent projects.

[0087] It can be understood that the user can set the layer parameters of the device through a layer setting module, and after the layer setting is completed, physical wiring can be performed. Optionally, the chip wiring module can automatically obtain the layer information set by the user from the layer setting module and the pin information that has been set from the chip layout module to generate corresponding pins in the layer; the user generates wiring on the layer based on the pins generated on the layer and the set logical connection relationship.

[0088] It can be understood that the layer information is generated according to actual conditions, such as 5 layers or 7 layers, and the metal layer in the layer can be understood as the layer of actual physical wiring, which carries physical wiring and further carries physical connection between other devices. Therefore, the top layer and the bottom layer of multiple layers generate corresponding pins based on the pin information that has been set, and the middle layers are used to set vias, through holes or shapes. In the embodiments of the present application, the via can be understood as a connection structure between metal layers, the through hole can be understood as a connection between the bottommost metal layer (layer) and the substrate, and the shape can be a rectangle, a polygon, etc., and can set an octagonal pad on the layer or set a chip name on the layer.

[0089] In some embodiments, the connection relationship includes pin information, and the chip wiring module obtains the layer information from the layer setting module to generate a layer;

[0090] The chip wiring module obtains the pin information from the chip layout module to generate corresponding pins in the layer;

[0091] The user generates the wiring on the stack based on the pins generated on the stack and the connection relationship.

[0092] Optionally, the chip wiring module can generate the pins in the pin information in the top stack and the bottom stack. Taking the interposer as an example, the upper surface of the interposer is a plurality of dies (i.e., the upper surface is the pins connected between the interposer and the dies), and the lower surface is the generated pins (ball). Therefore, the chip wiring module generates the pins connected between the dies in the top stack, and generates the ball in the bottom stack. The middle stack can generate a via according to the logical connection relationship to realize physical wiring.

[0093] In some embodiments, the stack can be displayed in whole or in part by layer, such as the top stack or the bottom stack can be displayed, the top stack and the second stack can be displayed, and the like. The via situation, the through-hole situation, and the graphic situation can also be displayed separately. Optionally, different color display effects can be set for each stack.

[0094] In some embodiments, in response to the user's selection operation on the wiring, the chip wiring module displays a line width adjustment button to facilitate the user to adjust the line width. Optionally, the chip wiring module can perform parameter calculation based on the current line width of the wiring, such as calculation of resistance, capacitance, inductance, delay, and impedance.

[0095] In some embodiments, on the chip wiring page, the user can first set the wiring, and then draw the wiring on the stack. The above wiring setting includes line width setting, wiring angle setting (such as 45-degree wiring), corner length setting, starting stack and ending stack setting, and wiring network setting.

[0096] In some embodiments, the chip wiring module is also used to display a flying wire based on the pin information of the device, and the flying wire display effect is different from the above wiring display effect. For example, the interface can include a flying wire display switch button, and after the flying wire display switch is turned on, the flying wire is displayed in the interface. In order to improve the display effect, the color of the flying wire can be set to be different from the color of other wirings.

[0097] In some optional embodiments of the present application, the device library in the present application can be edited by the user.

[0098] In some optional embodiments of the present application, the device library in the present application can be a device library uploaded by the user.

[0099] In some optional embodiments of the present application, the device library in the present application supports user import of device data, export of device data, viewing of device data, and the like.

[0100] Editing device data. The device data refers to device data of devices included in the device library.

[0101] In some optional embodiments of the present application, the user can also select a device in the device library on the chip layout page, and can drag the selected device to the display area of the chip layout. The display area of the chip layout specifically refers to the display area of the chip layout result.

[0102] As shown in the figure, in some optional embodiments of the present application, the user can select a device in the device library on the chip layout page. The tool can also present a magnetic attraction effect based on the pin position relationship below the device, and automatically attract and connect the corresponding pin when the device is clicked or dragged. Specifically, this function can be implemented based on the aforementioned chip layout module. Figure 4

[0103] In some optional embodiments of the present application, the devices displayed in the display area of the chip layout result are consistent with the devices set by the first chip connection relationship setting module 11 and the devices set by the second chip connection relationship setting module.

[0104] In some optional embodiments of the present application, when the user views multiple devices included in the device library, secondary filtering is supported. The first filtering and the second filtering can respectively refer to the major category and the minor category of the devices in the device library.

[0105] In some optional embodiments of the present application, the aforementioned sensor, power supply, radio frequency circuit, memory, clock, and passive device are major categories in the device library classification.

[0106] In some optional embodiments of the present application, the user can expand and reduce the device library, for example, the user can add new device information to the device library.

[0107] In some optional embodiments, the aforementioned tool also includes an identification module that can automatically identify new device information and classify it into the device library. The new device information that can be identified by the identification module can come from the netlist.

[0108] In some optional embodiments, the aforementioned tool also includes a prompt module that will prompt the user to create a corresponding device when the user inputs a device in the netlist that does not exist in the device library.

[0109] Further, the tool in the present application can also support the design of redistribution layers and bump maps for functional chip particle connections. The tool in the present application can also support fine bump map position error evaluation and analysis, which is not limited by the present application.

[0110] ​Further, the tool of the present application can also be applied to 3D-sip (system in package), ATE (automstic test equipment) test channel connection design, simulation.

[0111] In some optional embodiments of the present application, the aforementioned tool of the present application further comprises a message log module, wherein the message log module is configured to allow the user to acquire log information generated by various operations in real time, to facilitate the user to understand various data of the operation process, and to automatically send an alarm. Optionally, the tool can also highlight the abnormality generated in the operation process based on yellow color.

[0112] In some optional embodiments of the present application, the aforementioned chip design tool further comprises an interposer adding module configured to display the interposer on the chip layout page in response to the user's operation of adding the interposer.

[0113] In some optional embodiments of the present application, the aforementioned chip design tool further comprises a substrate adding module configured to display the substrate on the chip layout page in response to the user's operation of adding the substrate.

[0114] In the present application, the chip layout module 13 can be used for the user to add interposer and other interposer devices on the chip layout page, and can be used for the user to define the spatial position relationship of each unit, interposer and other devices on the chip layout page, including but not limited to the mutual position of each device in the horizontal plane, the rotation angle of the device, the stacking relationship between part of the devices, the contact relationship between the device and the pin / pin and pin, and the like. Wherein, the chip layout page is a three-dimensional view page. Further, the user can also define the pin distribution of the interposer and the corresponding network on the chip layout page through the chip layout module 13.

[0115] In some optional embodiments of the present application, the parameters that the user can define when adding the interposer include: coordinates, size, stacking, bump arrangement, network allocation, and pins (newly generated pins need to be manually allocated network). At the same time, it supports importing tech files and importing interposer definitions. In addition, the user can also edit the coordinates, size, stacking, ball arrangement, and network allocation of the substrate. At the same time, it also supports the user to import the substrate file, so as to add the substrate.

[0116] After the bump in the interposer is edited, the bump pad on the substrate can be automatically generated and correspond to one-to-one.

[0117] In some optional embodiments of the present application, in the chip layout module 13, the stacking or moving of the devices can be achieved by mouse dragging, input coordinates, etc.; at the same time, it can also be selected: embedded, stacked above (directly find the upper surface); it can also be selected: common stacking mode: EMIB, 2.5D, 3D.

[0118] In some optional embodiments of the present application, the chip layout module is further configured to: obtain a preset layout rule; and perform layout on the plurality of devices based on the preset layout rule.

[0119] In some optional embodiments of the present application, the chip routing module 14 is configured to enable an automatic routing operation by a user in a three-dimensional view page, and present a result of the automatic routing in the form of a three-dimensional model. The user can select to display or hide the entire physical routing result, or select to display or hide the routing corresponding to a specific network, or highlight the physical routing line corresponding to a specific network. In addition, the routing scheme of each layer in the interposer can be selected to be displayed separately.

[0120] In some optional embodiments of the present application, in addition to defining the spatial position of the device, the user can also highlight the selected device through the physical layout module and switch between transparent and opaque modes.

[0121] It can be understood that the chip connection relationship setting module sets the logical connection relationship between the devices, and the physical layout and physical routing relationship of each device in the chip also need to be designed. In the embodiments of the present application, the chip layout module can be understood as a physical layout module, and the chip routing module can be understood as a physical chip routing module. In the chip layout module, the user can set the layout relationship of the devices in the chip, and the layout relationship includes the spatial position of the devices in the chip and the relative position between the devices, so as to determine the layout relationship of the devices.

[0122] In some embodiments, the user can select a device in the chip layout page, and then set the pin type and pad type of the device, generate the pins of the device based on the selected pin type and pad type, obtain the pin information, and display the connection relationship between the pins with the same network name.

[0123] Optionally, in the chip layout page, in response to a selection operation on a target device, device information of the target device is displayed, and the device information includes device position coordinates, angles, bit numbers, device names, device library names, and pin numbers; or

[0124] In response to the selection operation on the target pin, pin information of the target pin is displayed, the pin information including pin coordinates, a pin number, a pin library name, a pin material, a pin direction, a pin angle, and a network to which the pin belongs

[0125] In some optional embodiments of the present application, when a user clicks on a certain frame of a netlist during editing of the netlist, the frame can be highlighted.

[0126] In some optional embodiments of the present application, the chip design tool further includes a chip detection module configured to:

[0127] In response to a detection operation of the chip design result by the user, design rule information is acquired;

[0128] Based on the design rule information, the chip design result is checked to obtain a checking result;

[0129] The checking result is displayed.

[0130] In some optional embodiments of the present application, a button corresponding to the chip detection module can be arranged on the chip layout page, and when an operation of the button by the user is detected, it is considered that the detection operation of the chip design result by the user is received.

[0131] In some optional embodiments of the present application, the design rule information is mainly DRC rules, and the specific rule content can be set by a related packaging or chip design personnel, which needs to be determined according to the specific project requirements. Different projects have different packaging requirements and chip design needs.

[0132] In some optional embodiments of the present application, the chip design tool further includes an import module configured to import a netlist by the user.

[0133] In some optional embodiments of the present application, the chip design tool further includes a response module configured to:

[0134] In response to a drag operation of the user on any device of the plurality of devices on the chip layout page, the any device is controlled to move correspondingly.

[0135] In some optional embodiments of the present application, the chip design tool further includes an export module configured to:

[0136] In response to an operation of the user to export the chip design result, the chip design result is exported.

[0137] The scheme of the present application proposes a new chip design tool, which can take dies or small chips as operating devices, complete the logic design of the chip by defining the logical connection relationship between them, and then complete the physical layout and wiring of each die device in the chip in the form of a three-dimensional view, and finally perform DRC checking and complete the design of the entire chip. Moreover, the tool provided in the embodiments of the present application allows the user to set the logical relationship between units in the form of a netlist or a schematic diagram, and then present it in the form of a flying wire in a three-dimensional view. Then, the user can complete the spatial layout of each unit through operations such as dragging, and can use custom DRC rules to check the layout result.

[0138] Moreover, the tool in the present application also supports automatic wiring function, specifically, the chip can be wired by the chip wiring module 14 to obtain the chip design result. When the chip wiring module 14 specifically wires, the real three-dimensional space line between each chiplet can be calculated, and the custom DRC rule is allowed to be used to check the spatial wiring result.

[0139] In some optional embodiments of the present application, the aforementioned prompt module is also used to present the exceptions and errors generated in the chip design process in real time, while displaying the intermediate data generated in each calculation link in real time.

[0140] The following will be further described in combination with Figure 1h Further, when using the tool of the present application, the user can specifically select devices through the first chip connection relationship setting module or the second chip connection relationship setting module, and edit the logical connection relationship between the devices. After editing the logical connection relationship between the devices, the user can further perform physical layout based on the chip layout module, and perform physical layout DRC based on the chip detection module. Further, the user can perform physical wiring based on the chip wiring module, and perform physical layout DRC based on the chip detection module, and perform design result export based on the export module.

[0141] Further referring to Figure 1i As shown in Figure 1j As shown in the schematic diagram, the user can set the connection relationship between multiple devices in the chip by importing a netlist or directly opening a netlist tool, and editing in the netlist page to edit the logical connection relationship between the devices. Alternatively, the user can also set the connection relationship between multiple devices in the chip by directly opening a schematic diagram, and editing in the schematic diagram page. Alternatively, the user can import a netlist before opening the netlist. Alternatively, the timing of the user selecting a device from the device library is not limited by the present application, for example, the user can select a device from the device library when opening a netlist, importing a netlist, opening a schematic diagram, or drawing a schematic diagram, or before that. Alternatively, after opening the schematic diagram tool, the user can also switch to importing a netlist.

[0142] Specifically, the user selects the device first, and then sets the connection relationship between the plurality of devices in the chip. The schematic diagram can be seen from Figure 1h The user selects the device first, and then sets the connection relationship between the plurality of devices in the chip. The schematic diagram can be seen from Figure 1i The user selects the device first, and then sets the connection relationship between the plurality of devices in the chip. The schematic diagram can be seen from Figure 1j The user selects the device first, and then sets the connection relationship between the plurality of devices in the chip. The schematic diagram can be seen from

[0143] In some optional embodiments of the present application, the chip layout page can be seen from Figure 1b The specific parameter setting can be seen from the figure, which will not be described here.

[0144] Further, the present application also provides a software architecture schematic diagram of the tool in the present application, which can be seen from Figure 1k Specifically, the product framework of the tool proposed in the present application includes: device selection, logic connection, space layout, wiring pre-check, design export, and offline production; the business core module includes: three-dimensional model interaction, packaging architecture model, netlist logic connection, design sample library, automatic layout, device library, automatic wiring, Test Bench, DRC pre-check, assembly process animation, pin distribution design, real-time cost estimation, simulation effect presentation, background management system; the technical foundation module includes: external database docking, external service docking, external EDA file analysis, external EDA file generation, K85 micro-service framework, Kafka message queue, Java, micro-frontend APP Shell, log system, JavaScript, React application framework, plug-in system, Python, Three three-dimensional framework, message system, Postgre SQL, multi-tenant account system, background task, MongoDB, payment system, AI assistance, and Redis.

[0145] The chip design tool provided by the present application comprises: a first chip connection relationship setting module based on a schematic diagram, a second chip connection relationship setting module based on a netlist, a chip layout module, and a chip wiring module; wherein the user sets the connection relationship between the plurality of devices in the chip through the first chip connection relationship setting module or the second chip connection relationship setting module; the chip layout module is used to display the chip layout result corresponding to the plurality of devices based on the plurality of devices on a chip layout page; and the chip wiring module is used to wire the chip based on the connection relationship and the chip layout result to obtain a chip design result. Through the scheme of the present application, the user can select one of the schematic diagram design and the netlist design to design the chip, the flexibility of the chip design is larger, and the design efficiency is higher.

[0146] The embodiment of the present application further provides a chip design method, Figure 2 The flowchart of the chip design method provided by the embodiment of the present application includes at least the following steps S201-S203:

[0147] S201, obtaining the connection relationship between the plurality of devices in the chip set by the user through the first chip connection relationship setting module based on the schematic diagram or the second chip connection relationship setting module based on the netlist.

[0148] In some optional embodiments, the first chip connection relationship setting module can further include a first display module for displaying a schematic diagram editing page, and the user can perform chip design by drawing a schematic diagram on the schematic diagram editing page.

[0149] In some optional embodiments, the second chip connection relationship setting module can further include a second display module for displaying a netlist editing page, and the user can set netlist information on the netlist editing page.

[0150] The netlist information can include parameters of the netlist, and part of the parameters of the netlist can be edited, for example, modified, and part of the parameters of the netlist cannot be edited.

[0151] S202, obtaining the layout relationship of the plurality of devices in the chip by a chip layout module, and the layout relationship includes the spatial position of the plurality of devices in the chip and the relative position between the plurality of devices.

[0152] In the present application, the chip layout module can be used for the user to add an interposer and other interlayer devices on a chip layout page, and can be used for the user to define the spatial position relationship of each unit, interposer and other devices on the chip layout page, including but not limited to the mutual position of each device in three-dimensional space, the rotation angle of the device, the stacking relationship between part of the devices, the contact relationship between the device and the pin / pin and pin, and the like. Wherein, the chip layout page is a three-dimensional view page. Further, the user can also define the pin distribution of the interposer and other interlayer devices and the corresponding belonging network on the chip layout page through the chip layout module.

[0153] In some optional embodiments of the present application, the parameters that the user can define when adding the interposer include: coordinates, size, layer, ball arrangement, network allocation, pins (newly generated pins need to be manually allocated a network). At the same time, importing a tech file and importing interposer definition are supported. In addition, the user can also edit the coordinates, size, layer, ball arrangement, and network allocation of the substrate. At the same time, the user can import a substrate file to add the substrate.

[0154] In some embodiments, the obtaining, by the chip layout module, the layout relationship of the plurality of devices in the chip includes:

[0155] The chip layout module obtains the position information of the devices input by the user, and generates pins of the devices based on the pin type and the pad type selected by the user at positions corresponding to the position information, to obtain the layout relationship.

[0156] Optionally, the chip layout module displays a connection relationship between pins with the same network name.

[0157] S203, by the chip routing module, routing the plurality of devices based on the connection relationship and the layout relationship, to obtain a chip design result.

[0158] For example, the user can select a device (such as a substrate) from the chip layout page, and then switch from the chip layout page to the routing page of the device. In the embodiments of the present application, the chip routing module can interact with the layer setting module.

[0159] In some embodiments, the chip design tool further includes a layer setting module; and the chip design method further includes:

[0160] The layer setting module generates layer information of the devices based on the layer setting input by the user, and the layer information includes at least two layers.

[0161] The layer setting includes at least one of the following: wiring direction in the layer, type of the layer, material of the layer, thickness of the layer, and name of the layer.

[0162] The user can choose to display or hide the entire physical routing result, or choose to display or hide the routing corresponding to a specific network, or highlight the physical routing line corresponding to a specific network. In addition, the wiring scheme of each layer in the layer can be individually selected for display.

[0163] Optionally, the connection relationship includes pin information, and the chip design method further includes:

[0164] The chip wiring module generates wiring on the stack based on the pin information generated on the stack and the connection relationship input by the user.

[0165] The chip wiring module obtains the pin information from the chip layout module to generate corresponding pins in the stack.

[0166] The chip wiring module generates wiring on the stack based on the pin information generated on the stack and the connection relationship input by the user.

[0167] In some optional embodiments of the present application, the aforementioned tool can be a client, and the user can view historical chip design results created by the user in the aforementioned tool. In the present application, a chip design result can be saved as a chip project.

[0168] In an optional embodiment of the present application, the method further comprises:

[0169] The first chip connection relationship setting module displays a schematic diagram editing page;

[0170] In response to the operation of selecting the first device from the device library triggered by the user on the schematic diagram editing page, the device information of the first device is displayed on the schematic diagram editing page;

[0171] Or

[0172] The second chip connection relationship setting module displays a netlist editing page;

[0173] In response to the operation of selecting the first device from the device library triggered by the user on the netlist editing page, the device information of the first device is displayed on the netlist editing page;

[0174] The schematic diagram editing page and the netlist editing page are used for the user to set the connection relationship between the plurality of devices in the chip.

[0175] In an optional embodiment of the present application, the chip design method further comprises the following S01-S03:

[0176] S01, in response to the detection operation of the user on the chip design result, obtaining design rule information;

[0177] S02, checking the chip design result based on the design rule information to obtain a checking result;

[0178] S03, displaying the checking result.

[0179] In an optional embodiment of the present application, the method further comprises: in response to the drag operation of the user on the chip layout page for any device of the plurality of devices, controlling the corresponding movement of the any device.

[0180] The specific implementation of the embodiment can be referred to the foregoing content, and will not be described here.

[0181] Figure 3 A structure schematic diagram of a chip design device is provided for an exemplary embodiment of the present application, wherein the device comprises:

[0182] The chip connection relationship setting module 31 sets the connection relationship between the plurality of devices in the chip.

[0183] The chip layout module 32 sets the layout relationship of the plurality of devices in the chip, and the layout relationship comprises the spatial position of the plurality of devices in the chip and the relative position between the plurality of devices.

[0184] The chip wiring module 33 is configured to wire the plurality of devices based on the connection relationship and the layout relationship, and obtain a chip design result.

[0185] It should be understood that the device embodiment and the method embodiment can correspond to each other, and similar descriptions can be referred to the method embodiment. To avoid repetition, the foregoing and other operations and / or functions of each module in the device will not be described here. Specifically, the device can perform the method embodiment described above, and the foregoing and other operations and / or functions of each module in the device are respectively for the corresponding process in each method in the method embodiment. For the sake of brevity, the foregoing will not be described here.

[0186] The device of the embodiment of the present application is described above in combination with the drawings from the perspective of the functional module. It should be understood that the functional module can be realized in the form of hardware, or in the form of instructions of software, or in the form of a combination of hardware and software modules. Specifically, each step of the method embodiment in the embodiment of the present application can be completed by the integrated logic circuit of hardware and / or software instructions in the processor. The steps of the method disclosed in the embodiment of the present application can be directly embodied as hardware code processor execution completion, or executed by a combination of hardware and software modules in the code processor. Alternatively, the software module can be located in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, register, etc. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps in the method embodiment.

[0187] Figure 5 is a schematic block diagram of an electronic device provided by the embodiment of the present application, which can comprise:

[0188] a memory 401 for storing a computer program and transmitting the program code to the processor 402. In other words, the processor 402 can call and run the computer program from the memory 401 to implement the method in the embodiments of the present application. For example, the processor 402 can be used to execute the above-mentioned method embodiments according to the instructions in the computer program.

[0189] In some embodiments of the present application, the processor 402 can include but is not limited to:

[0190] general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, and the like.

[0191] In some embodiments of the present application, the memory 401 includes but is not limited to:

[0192] volatile memory and / or non-volatile memory. Among them, the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM) or flash memory. The volatile memory can be random access memory (Random Access Memory, RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (synch link DRAM, SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0193] In some embodiments of the present application, the computer program can be divided into one or more modules, which are stored in the memory 401 and executed by the processor 402 to complete the method provided by the present application. The one or more modules can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the electronic device.

[0194] As shown in Figure 5 The electronic device can further include:

[0195] The transceiver 403 can be connected to the processor 402 or the memory 401.

[0196] The processor 402 can control the transceiver 403 to communicate with other devices, specifically, can send information or data to other devices, or receive information or data sent by other devices. The transceiver 403 can include a transmitter and a receiver. The transceiver 403 can further include an antenna, and the number of antennas can be one or more.

[0197] It should be understood that various components in the electronic device are connected through a bus system, wherein the bus system includes a data bus, a power supply bus, a control bus and a state signal bus in addition to a data bus.

[0198] The present application also provides a computer readable storage medium having a computer program stored thereon, which, when executed by a computer, enables the computer to perform the method of the above method embodiments. Alternatively, the present application embodiment also provides a computer program product containing instructions, which, when executed by a computer, enables the computer to perform the method of the above method embodiments.

[0199] When implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired computer program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, or a twisted pair, as examples, then the coaxial cable, fiber optic cable, or twisted pair are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), and Blu-Ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0200] In one embodiment, the techniques described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the software can be executed in a computer system, which can include one or more computers. The software can be stored on one or more computer readable media, such as a magnetic disk, optical disk, or solid state memory. The computer readable media can be distributed among one or more computer systems.

[0201] In several embodiments provided in the present application, it should be understood that the disclosed system, device, and method can be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and the division of the modules is merely a logical function division. In actual implementation, another division manner can be used, for example, a plurality of modules or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed modules can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical, mechanical or other forms.

[0202] The modules illustrated as separate components may or may not be physically separate, and the components illustrated as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules in various embodiments of the present application can be integrated in one processing module, or each module can be physically present separately, or two or more modules can be integrated in one module.

[0203] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip design tool, characterized by, The chip connection relationship setting module, the chip layout module, and the chip wiring module; The chip connection relationship setting module sets the connection relationship between the plurality of devices in the chip; The chip layout module sets the layout relationship of the plurality of devices in the chip, the layout relationship including the spatial position of the plurality of devices in the chip and the relative position between the plurality of devices; The chip wiring module is configured to wire the plurality of devices based on the connection relationship and the layout relationship to obtain a chip design result.

2. The chip design tool of claim 1, wherein, The chip connection relationship setting module includes a first chip connection relationship setting module based on a schematic diagram and a second chip connection relationship setting module based on a netlist.

3. The chip design tool of claim 2, wherein, Further comprising a device library; the device library includes the plurality of devices; The user sets the connection relationship between the plurality of devices in the chip through the device library and the first chip connection relationship setting module, or sets the connection relationship between the plurality of devices in the chip through the device library and the second chip connection relationship setting module.

4. The chip design tool of claim 1, wherein, The chip layout module sets the layout relationship of the plurality of devices in the chip, including: The chip layout module obtains the position information of the device input by the user, generates the pin of the device based on the pin type and the pad type selected by the user at the position corresponding to the position information, to obtain the layout relationship.

5. The chip design tool according to any one of claims 1-4, wherein, Further comprising a layer setting module; the layer setting module receives the layer setting input by the user to generate layer information for the device, the layer information including at least two layers; The layer setting includes at least one of the following: wiring direction in the layer, type of the layer, material of the layer, thickness of the layer, and name of the layer.

6. The chip design tool of claim 5, wherein, The connection relationship includes pin information, and the chip wiring module obtains the layer information from the layer setting module to generate a layer; The chip wiring module obtains the pin information from the chip layout module to generate corresponding pins in the layer; The user generates wiring on the layer based on the pins generated on the layer and the connection relationship.

7. The chip design tool of claim 6, wherein, The chip wiring module obtains the pin information from the chip layout module to generate corresponding pins in the layer, including: The chip wiring module generates the pins in the pin information in the top layer and the bottom layer.

8. The chip design tool of claim 7, wherein, The layer is used to generate at least one of the following: via, through hole, and pattern.

9. The chip design tool according to any of claims 3-8, wherein, The parameters in the netlist include device name, pin number, and pin network name; the user sets the connection relationship of the pins of the device by defining the pin network name.

10. The chip design tool of claim 9, wherein, The devices in the device library include at least one of the following: chip, bare die, interposer, and passive device.

11. The chip design tool of claim 3, wherein, The device library displays devices in categories, and the categories include sensors, power supplies, radio frequency circuits, memories, clocks, passive devices, and interposers.

12. The chip design tool of claim 1, wherein, Further comprising: A chip detection module configured to: In response to a detection operation of the user on the chip design result, obtain design rule information; Based on the design rule information, check the chip design result to obtain a check result; Display the check result.

13. The chip design tool of claim 2, wherein, The switching module is further configured to display a schematic diagram editing page corresponding to the first chip connection relationship setting module when detecting that a user triggers to start the schematic diagram editing page. The switching module is further configured to display a netlist editing page corresponding to the second chip connection relationship setting module when detecting that a user triggers to start the netlist editing page. Alternatively, the switching module is further configured to switch from the netlist editing page to a chip layout page corresponding to the layout module. The schematic diagram editing page and the netlist editing page are configured to allow a user to set a connection relationship between a plurality of devices in the chip.

14. The chip design tool of claim 16, wherein, In the chip layout page, in response to a selection operation on a target device, device information of the target device is displayed, and the device information includes device position coordinates, an angle, a pin number, a device name, a device library name, and a pin number. In response to a selection operation on a target pin, pin information of the target pin is displayed, and the pin information includes pin coordinates, a pin number, a pin library name, a pin material, a pin direction, a pin angle, and a network to which the pin belongs.

15. A method of chip design, characterized by, The method is applied to a chip design tool, and the chip design tool includes a chip connection relationship setting module, a chip layout module, and a chip routing module. The chip connection relationship setting module includes a first chip connection relationship setting module based on a schematic diagram and a second chip connection relationship setting module based on a netlist. The method includes: Obtaining a connection relationship between a plurality of devices in a chip set by the first chip connection relationship setting module or the second chip connection relationship setting module.

16. The method of claim 15, wherein, Obtaining a layout relationship of the plurality of devices in the chip by the chip layout module, and the layout relationship includes spatial positions of the plurality of devices in the chip and relative positions between the plurality of devices. Obtaining a routing result of the plurality of devices by the chip routing module based on the connection relationship and the layout relationship.

17. The method of claim 16, wherein, The method further includes: The chip layout module displays a connection relationship between pins with the same network name.

18. The method according to any one of claims 15-17, characterized by, The chip design tool further includes a layer setting module, and the method further includes: The layer setting module receives layer setting input by a user to generate layer information for the devices, and the layer information includes at least two layers. The layer setting includes at least one of a routing direction in a layer, a type of a layer, a material of a layer, a thickness of a layer, and a name of a layer.

19. The method of claim 18, wherein, The connection relationship includes pin information, and the method further includes: The chip routing module obtains the layer information from the layer setting module to generate a layer. The chip wiring module obtains the pin information from the chip layout module to generate corresponding pins in the stack; The chip wiring module generates wiring on the stack based on wiring setting information input by the user based on the generated pins on the stack and the connection relationship.

20. The method of claim 19, wherein, The chip wiring module obtains the pin information from the chip layout module to generate corresponding pins in the stack, comprising: The chip wiring module generates pins in the pin information in the top layer stack and the bottom layer stack.

21. The method of claim 20, wherein, The stack is used to generate at least one of the following: via, through hole, pattern.

22. The method of any one of claims 15-21, wherein, The method further comprises: displaying a schematic diagram editing page through the first chip connection relationship setting module; in response to the user triggering the operation of selecting the first device from the device library on the schematic diagram editing page, displaying the device information of the first device on the schematic diagram editing page; or displaying a netlist editing page through the second chip connection relationship setting module; in response to the user triggering the operation of selecting the first device from the device library on the netlist editing page, displaying the device information of the first device on the netlist editing page; wherein the schematic diagram editing page and the netlist editing page are used for the user to set the connection relationship between the plurality of devices in the chip.

23. An electronic device, comprising: comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the method of any one of claims 15-22 by executing the executable instructions.

24. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the method of any one of claims 15-22.

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