Integrated circuit device design method and system

Abstract

The invention relates to an integrated circuit device design method and system. A method of designing an integrated circuit (IC) device includes: specifying a standard set corresponding to an IC manufacturing process; using a processor to generate a design rule by applying the design rule instruction to the standard set; generating a design rule manual (DRM), the DRM being an electronic file including the design rules; performing a design rule check (DRC) on a layout of at least a portion of the IC device using the design rules from the DRM; and storing an IC layout map including the layout on a non-transitory computer-readable medium based on verifying the layout by performing the DRC.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 201910976697.9, filed on October 15, 2019, entitled “Integrated Circuit Device Design Method and System.” TECHNICAL FIELD

[0002] The present disclosure relates to integrated circuit device design method and system. BACKGROUND

[0003] The continuing trend toward miniaturization of integrated circuits (ICs) has resulted in progressively smaller and lower power devices that provide enhanced functionality at high speeds. The miniaturization process has also resulted in increasingly stringent design and manufacturing specifications. Various electronic design automation (EDA) tools have been developed to generate, optimize, and verify designs of semiconductor devices while ensuring compliance with the design and manufacturing specifications. SUMMARY

[0004] According to one embodiment of the present disclosure, a method of designing an integrated circuit (IC) device is provided, the method comprising: receiving, at a processor, a standard set corresponding to an IC manufacturing process; generating, with the processor, design rule instructions that define one or more macros that allocate conditions and define relationships within the standard set; generating, with the processor and in response to the generated design rule instructions, design rules by executing the design rule instructions; generating, with the processor and based on the design rules, a design rule manual (DRM), wherein the DRM is an electronic file that includes the design rules; performing, with the processor and based on the design rules from the DRM, a design rule check (DRC) on a layout of at least a portion of the IC device; verifying, with the processor and in response to the DRC, the layout; and storing, with the processor and based on the verified layout, an IC layout map that includes the layout on a non-transitory computer readable medium.

[0005] According to another embodiment of the present disclosure, a non-transitory computer readable medium comprising computer executable instructions configured to perform a method of designing an integrated circuit (IC) device is provided, the method comprising: receiving, from an input / output (I / O) interface, a standard set corresponding to an IC manufacturing process; generating design rule instructions by defining one or more computer executable macros based on the IC manufacturing process, and storing the design rule instructions; generating design rules by applying the stored design rule instructions to the standard set, the design rules specifying design constraints for a layout of at least a portion of the IC device; receiving input from the I / O interface; and in response to the input, generating a design rule manual (DRM), the DRM being an electronic file that includes the design rules.

[0006] According to yet another embodiment of the disclosure, there is provided an integrated circuit (IC) device design system, comprising: at least one processor; and at least one memory including computer program code of one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the IC device design system to perform the following operations: receive a standards set from an input / output (I / O) interface, the standards set corresponding to an IC manufacturing process; obtain design rule instructions from the at least one memory, or import the design rule instructions into the IC device design system, the design rule instructions being one or more computer executable macros configured to incorporate one or more parameters and context information from the standards set; generate design rules by applying the design rule instructions to the standards set, the design rules specifying design constraints for a layout of at least a portion of an IC device; generate a design rule manual (DRM) including the design rules; and store the DRM in the at least one memory, or export the DRM from the IC device design system. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. FIG. 1 is a block diagram of an example system for designing an integrated circuit (IC) device, in accordance with some embodiments.

[0008] Figure 1A is a flowchart of a method of designing an IC device, in accordance with some embodiments.

[0009] Figure 1B is a flowchart of a method of generating design rule instructions, in accordance with some embodiments.

[0010] Figure 2 depicts a non-limiting example of a displayed list of design rule instructions, in accordance with some embodiments.

[0011] Figure 3 depicts a non-limiting example of a displayed table of design rule types, in accordance with some embodiments.

[0012] Figure 4 depicts a non-limiting example of a displayed list of design rule layer definitions, in accordance with some embodiments.

[0013] Figure 5 depicts a non-limiting example of a displayed design rule template, in accordance with some embodiments.

[0014] Figure 6A non-limiting example of a design rule manual (DRM) in accordance with some embodiments is depicted.

[0015] Figure 7 is a block diagram of an IC device design system in accordance with some embodiments.

[0016] Figure 8 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0018] Also, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Such spatially relative terms can be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated at 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] In various embodiments, a method includes specifying a set of standards corresponding to an IC manufacturing process, applying design rule instructions to the set of standards to generate design rules, and generating a design rule manual (DRM) file including the design rules. By applying the instructions to automatically generate the design rules and the DRM, the IC device design method and system are more efficient and can reduce error-related activities (as compared to a method in which the design rules and the DRM are not generated by applying the design rule instructions to automatically generate the design rules).

[0020] Figure 1A is a flow diagram of a method 100A of designing an IC device in accordance with one or more embodiments. The method 100A can be used with an IC device design system (e.g., the IC device design system 100 described below with reference toFigure 7 The IC device design system 700 discussed below, and / or the IC fabrication system (e.g., the IC fabrication system 800 discussed below) are used together. Figure 8 The IC device design system 700 discussed below, and / or the IC fabrication system (e.g., the IC fabrication system 800 discussed below) are used together.

[0021] The operations of the method 100A are illustrated in Figure 1A order for illustration purposes only; the operations of the method 100A can be performed in an order different than the order described. In some embodiments, one or more operations are performed concurrently, in parallel, or in Figure 1A some embodiments, one or more operations are performed before, between, during, or after one or more of the illustrated operations. In some embodiments, one or more operations of the method 100A are operations of a method of operating I / O circuitry. Figure 1A Figure 1A In some embodiments, one or more operations of the method 100A are a subset of operations of a method of designing an IC device. In some embodiments, one or more operations of the method 100A are a subset of operations of a method of fabricating an IC device. In various embodiments, one or more operations of the method 100A are performed using one or more processors (e.g., the processor 702 discussed below with reference to the IC device design system 700 and

[0022] In some embodiments, one or more operations of the method 100A are a subset of operations of a method of designing an IC device. In some embodiments, one or more operations of the method 100A are a subset of operations of a method of fabricating an IC device. In various embodiments, one or more operations of the method 100A are performed using one or more processors (e.g., the processor 702 discussed below with reference to the IC device design system 700 and Figure 7

[0023] At operation 110, in some embodiments, design rule instructions are generated. The design rule instructions are one or more computer-executable instructions configured to cause a software tool to perform one or more activities on a set of standards input to the software tool to generate design rules. The design rules are an expression of one or more constraints that an IC designer follows during design and fabrication of an IC device. In some embodiments, generating the design rule instructions includes performing some or all of the method 100B discussed below with reference to Figure 1B-4

[0024] In various embodiments, the design rules include one or more parameters and context information that can be used by an IC device manufacturer to verify correctness of a mask set, or to specify geometry and / or connectivity restrictions to ensure that there is sufficient margin to account for variability in one or more IC fabrication processes. In some embodiments, the design rules are specific to a particular IC fabrication process, e.g., a fabrication process based on standard feature sizes of IC devices manufactured using the particular IC fabrication process.

[0025] ​​​In various embodiments, the design rules include information that can be used to ensure one or more relationships between or within features and / or layers in a layout of an IC device. In various embodiments, the one or more relationships include a distance (e.g., width, spacing, gap, overlap, or extension) along a given direction or in any direction, an area, a density, a ratio, or a prohibition or restriction applicable to one or more features and / or layers, in various embodiments, ensuring the relationship includes ensuring that one or a combination of the features or layers is greater than, equal to, or less than a predetermined value, or is within a predetermined range. In various embodiments, the features and / or layers include one or more layers that define a mask (e.g., mask 845 discussed below with reference to Figure 8 the one or more masks, or one or more features or layers resulting from performing one or more manufacturing operations based on the one or more masks.

[0026] Using one or more design rules to ensure feature and / or layer relationships in a layout of an IC device provides a guarantee that an IC device can be formed during a manufacturing process based on an IC layout that includes the layout of the IC device. In some embodiments, the information in the design rules can be used by a software tool (e.g., an EDA tool) to perform a design rule check (DRC) on the layout of the IC device, as discussed below with respect to operation 150.

[0027] Generating the design rule instructions includes defining one or more computer executable instructions such that a software tool generates design rules including one or more parameters and context information according to a standard set. In some embodiments, the standard set corresponds to a particular IC manufacturing process. In various embodiments, the standard set includes one or more of the following: a design rule identifier, definition, and / or description; a feature and / or layer identifier, definition, and / or description; a feature type identifier, definition, and / or description; an association to a device or device type; a tag; a cell; a value or value range; or one or more other parameters corresponding to an aspect of an IC manufacturing process.

[0028] Generating the design rule instructions includes assigning a condition to the standard set, and / or defining a relationship within the standard set, such that one or more constraints expressed in the design rules point to the standard set, and in some embodiments, to a corresponding IC manufacturing process.

[0029] In embodiments in which the standard set corresponds to an IC manufacturing process, the design rule instructions are thereby generated so as to apply conditions and relationships common to multiple IC manufacturing processes to the particular IC manufacturing process corresponding to the standard set.

[0030] In some embodiments, generating design rule instructions include capturing one or more inputs to a software tool, as these inputs are used to generate design rules from one or more data bits. In some embodiments, the software tool includes a spreadsheet application, and generating design rule instructions include using the spreadsheet application to record macros. In some embodiments, generating design rule instructions are performed using a tool such as Excel®, available from Microsoft Corporation, or other suitable software tools.

[0031] In some embodiments, generating design rule instructions includes copying and / or modifying one or more previously generated design rule instructions. In some embodiments, generating design rule instructions includes using software tools (e.g., a software development platform or a text editing tool) to generate one or more computer-executable instructions.

[0032] In some embodiments, generating design rule instructions includes storing the design rule instructions on a non-transitory computer-readable storage medium. In various embodiments, storing the design rule instructions includes storing the design rule instructions on a non-transitory computer-readable storage medium on which software tools are stored, or storing them on another non-transitory computer-readable storage medium.

[0033] In some embodiments, generating design rule instructions includes generating a plurality of design rule instructions that include the design rule instructions. In some embodiments, storing design rule instructions includes storing a plurality of design rule instructions that include the design rule instructions.

[0034] Figure 1B This is a flowchart of a method 100B for generating design rule instructions according to some embodiments. One or more operations of method 100B can be used as some or all of operations 110, and are... Figure 2-4 Non-restrictive examples are shown.

[0035] The operation of method 100B is as follows: Figure 1B The order described is for illustrative purposes only; the operation of method 100B can be performed in accordance with... Figure 1B The described order is executed in a different order. In some embodiments, in Figure 1B The operations described are performed before, between, during, and / or after the operations, except for Figure 1B Operations other than those described.

[0036] At operation 110A, in some embodiments, design rule instructions are categorized based on design rule type. Categorizing design rule instructions based on design rule type includes identifying a design rule type corresponding to a relationship between or within features and / or layers in the layout of the IC device.

[0037] Classifying design rule instructions based on design rule type facilitates generating multiple design rules corresponding to particular feature and / or layer relationships, enabling multiple design rules to be generated for various features and / or layers while having a consistent format, identifier, definition, and description.

[0038] Figure 2 A non-limiting example of a displayed list 200 of design rule instructions is depicted in accordance with some embodiments. In the displayed list 200, design rule instructions are classified as MACRO type, including MACRO type corresponding to particular width, spacing, extension, and restriction, for example.

[0039] Each MACRO type is associated with a design rule number and a design rule description. A first subset of MACRO types is further associated with a constraint selection and a value, the constraint selection including “a: >=” corresponding to a greater than or equal to relationship, “b: =” corresponding to an equal relationship, and “c: <=” corresponding to a less than or equal to relationship. A second subset of MACRO types corresponds to a restriction, each restriction being fully expressed within the description associated with the respective MACRO type.

[0040] At operation 110B, in some embodiments, design rule instructions are classified based on design rule category. Classifying design rule instructions based on design rule category includes classifying design rule instructions according to feature or feature type, layer or layer type, derived layer or derived layer type, device or device type, device or isolation region, or other structure-oriented basis associated with an IC device layout.

[0041] Classifying design rule instructions based on design rule category facilitates grouping multiple design rules corresponding to particular features, layers, devices, regions, or other criteria, enabling multiple design rules to be selected, displayed, and / or generated based on the category associated with the multiple design rules.

[0042] Figure 3 A non-limiting example of a displayed table 300 of multiple design rule types is depicted in accordance with some embodiments. In the displayed table 300, design rule instructions are arranged into multiple groups based on design rule instruction classification, including device and layer type, for example.

[0043] At operation 110C, in some embodiments, a definition of a derived layer is generated. Generating a definition of a derived layer includes assigning a derived layer number, a term, and a definition to a derived layer in an IC device layout. In various embodiments, generating a definition includes associating one or more notes with the derived layer, and / or linking one or more rules links to the derived layer.

[0044] Generating the definitions of the derived layers facilitates generating design rules corresponding to the derived layers having consistent formats, identifiers, definitions, and descriptions, thereby minimizing the risk of errors related to layers resulting from performing one or more manufacturing operations based on one or more masks.

[0045] Figure 4 A non-limiting example of a displayed list 400 of design rule layer definitions is depicted in accordance with some embodiments. In the displayed list 400, each derived layer includes a derived layer number associated with a term, a definition, a note (and, in some cases, rule link information).

[0046] At operation 120, in some embodiments, a set of criteria is specified. Specifying the set of criteria includes identifying one or more data bits that can be used by the design rule instructions to generate the design rules. In some embodiments, the one or more data bits correspond to a particular IC manufacturing process. In some embodiments, specifying the set of criteria includes specifying at least one of: a value (e.g., a feature size, a feature geometry, a spacing between features, or a feature overlap size), a cell, or a layer, device, or device type identifier of an IC manufacturing process.

[0047] In some embodiments, specifying the set of criteria includes receiving the set of criteria with the software tool discussed above with respect to operation 110. In some embodiments, specifying the set of criteria includes receiving the set of criteria through a template. In some embodiments, specifying the set of criteria includes receiving the set of criteria through a user interface (e.g., the I / O interface 710 discussed below with respect to the IC device design system 700). Figure 7

[0048] In some embodiments, specifying the set of criteria includes a user manually entering the set of criteria into a user interface. In various embodiments, specifying the set of criteria includes the system automatically importing the set of criteria from one or more electronic files into the software tool, either automatically or initiated by one or more user inputs. In some embodiments, specifying the set of criteria includes specifying a plurality of sets of criteria including the set of criteria.

[0049] Figure 5 A non-limiting example of a displayed template 500 that can be used to specify a set of criteria is depicted in accordance with some embodiments. The template 500 includes a section for each design rule instruction type, where MACRO_W corresponds to a width relationship, MACRO_S corresponds to a spacing relationship, MACRO_E corresponds to an extension relationship, and MACRO_O corresponds to an overlap relationship.

[0050] Within each section, the design rule instruction type is further specified, for example, by a "1" or "1b" to select a plurality of constraints (e.g., a minimum, a maximum, or a range) for the design rule instruction type. Figure 2 ​A constraint to be applied to a design rule from the set of constraints depicted in the design rule instruction MACRO_E_1. The additional criteria include a design rule identifier "Rule No.," layer identifiers "Layer 1" and "Layer 2," a description "Condition" and "Label," and a value "Value" for each instance of the specified design rule instruction type and constraint.

[0051] At operation 130, the design rule instructions are applied to the set of criteria to generate the design rules discussed above with respect to operation 110. Generating the design rules includes executing the design rule instructions on a software tool. In various embodiments, the design rule instructions are executed in response to one or more user inputs to the software tool, or one or more computer-executable instructions (e.g., a batch file or another design rule instruction configured to initiate application of the design rule instructions).

[0052] As a non-limiting example, based on the second instance of the design rule instruction MACRO_E_1 depicted in the set of criteria, the design rule includes a design rule formatted according to the design rule instruction MACRO_E_1c format and includes a design rule identifier "HVPO.E.1," layers "PO" and "POO," a description "Non-HV device," a constraint ">=" and a value "0.4." Figure 5

[0053] In some embodiments, generating the design rules includes retrieving the design rule instructions from a non-transitory computer-readable storage medium. In various embodiments, retrieving the design rule instructions includes retrieving the design rule instructions from a non-transitory computer-readable storage medium on which the software tool is stored or from another non-transitory computer-readable storage medium.

[0054] In some embodiments, generating the design rules includes displaying the design rules on a user interface. In some embodiments, displaying the design rules includes displaying a plurality of design rules including the design rules. In some embodiments, generating the design rules includes verifying compatibility between the set of criteria and the design rule instructions and displaying a result of the verification on the user interface.

[0055] In some embodiments, generating the design rules includes storing the design rules on a non-transitory computer-readable storage medium. In various embodiments, storing the design rules includes storing the design rules on a non-transitory computer-readable storage medium on which the software tool is stored or on another non-transitory computer-readable storage medium.

[0056] ​In some embodiments, generating a design rule includes generating a plurality of design rules that include the design rule. In various embodiments, generating a plurality of design rules includes applying a single design rule instruction to a plurality of standard sets, applying a plurality of design rule instructions to a single standard set, applying each of the plurality of design rule instructions to a corresponding standard set in a plurality of standard sets, or a combination thereof.

[0057] At operation 140, DRM is generated from the design rules. DRM is an electronic document that includes the design rules, and generating DRM involves using software tools to generate the electronic document. In various embodiments, the electronic document is an ASCII text file or other suitable file type, such as a WORD® compatible file or a Portable Document Format (PDF) file.

[0058] Figure 6 A non-limiting example of a portion of a DRM 600 according to some embodiments is depicted. The DRM 600 is generated according to operation 140 and includes a first table and a second table, the first table including a set of design rules in which each rule corresponds to a single design constraint, and the second table including a set of design rules in which each design rule corresponds to multiple design constraints.

[0059] In the first table, the fourth design rule corresponds to the non-restrictive example discussed above for operation 130, where the design rule “HVPO.E.1” includes layers “PO” and “POO”, a description of “non-HV device”, constraints ">=", and a value “0.4”, each formatted according to the design rule instruction MACRO_E_1c.

[0060] In some embodiments, generating a DRM includes storing the DRM on a non-transitory computer-readable storage medium. In various embodiments, storing the DRM includes storing the DRM on a non-transitory computer-readable storage medium on which software tools are stored, or storing it on another non-transitory computer-readable storage medium. In some embodiments, storing the DRM includes retrieving it from an IC device design system (e.g., referred to below). Figure 7 The IC device design system 700 discussed derives the DRM.

[0061] In some embodiments, generating DRM includes importing the DRM using a different software tool than the one used to generate the DRM. In various embodiments, the different software tools execute on the same processor or on separate processors. In some embodiments, the separate processors are connected via a network (e.g., hereinafter referred to as IC device design system 700 and...). Figure 7 The discussion network 714) is connected. In some embodiments, the import of DRM is performed by an EDA tool.

[0062] Generating the DRMs is performed by a software tool. In various embodiments, the DRMs are generated in response to one or more user inputs to the software tool or one or more computer-executable instructions (e.g., a batch file configured to initiate generation of the DRMs). In some embodiments, the DRMs are generated using the DRM generation instructions created in the manner described above for design rule instructions, e.g., by capturing one or more inputs to the software tool when generating the DRMs from the design rules.

[0063] In some embodiments, generating the DRMs includes generating a DRM that includes a design rule group (also referred to as a design rule set, which includes design rules). In some embodiments, the design rule group is one group of a plurality of design rule groups, and generating the DRMs includes selecting the group from the plurality of groups.

[0064] In some embodiments, the design rule group is selected in response to one or more user inputs to the software tool. In some embodiments, selecting the design rule group is performed by the DRM generation instructions in response to one or more user inputs to the software tool. In some embodiments, the design rule group is selected in response to one or more user inputs received through a user interface (e.g., the I / O interface 710 discussed below for the IC device system 700 and Figure 7

[0065] In some embodiments, selecting the group from the plurality of groups includes classifying the plurality of design rules into the plurality of groups. In some embodiments, the plurality of design rules are classified in response to one or more user inputs to the software tool. In some embodiments, the design rule groups are classified in response to one or more user inputs received through a user interface (e.g., the I / O interface 710 discussed below for the IC device system 700 and Figure 7

[0066] In various embodiments, classifying the plurality of design rules into the plurality of groups is based on one or more of a device type, a device region type, a device feature type, or a design rule instruction type.

[0067] At operation 150, in some embodiments, a DRC is performed on a layout of at least a portion of the IC device using the design rules from the DRMs, the IC layout is verified or modified based on a result of the DRC, and a layout map of the IC layout is stored on a non-transitory computer-readable medium. In some embodiments, performing the DRC includes performing the DRC using a plurality of design rules that includes the design rules. ​​

[0068] Performing DRC includes applying one or more design rules in the DRM to one or more features of at least a portion of the IC device in the IC layout using a software tool, and verifying that the layout of the one or more features complies with the one or more design rules. In some embodiments, the design rule check is performed by the EDA tool. In various embodiments, the EDA tool and the software tool used to generate the DRM are executed on the same processor or on separate processors. In some embodiments, the separate processors are connected by a network (e.g., network 714 discussed below with respect to IC device design system 700 and Figure 7

[0069] In some embodiments, DRC is performed during the generation of the IC layout. In some embodiments, the tool used to generate the IC layout is also used to perform DRC. In some embodiments, the layout editor includes one or more files used by the EDA tool to edit the IC layout of the IC device. In various embodiments, the layout editor is generated by the EDA tool or by a software tool other than EDA and used by the EDA tool. In some embodiments, DRC is performed by a separate tool after the layout map of the IC layout is generated.

[0070] If the IC layout is not verified by the first DRC using the DRM, the IC layout is modified, additional DRC is performed, and the sequence is repeated if necessary until the IC layout is verified by a subsequent DRC using the DRM. In these cases, verifying the IC layout includes modifying the IC layout.

[0071] Based on verifying the IC layout by performing DRC, the IC layout map including the IC layout is stored on a non-transitory computer readable medium. In various embodiments, storing the IC layout map is performed before, during, or after verifying the IC layout by performing DRC. In various embodiments, storing the IC layout map includes storing the IC layout map on a non-transitory computer readable storage medium on which the tool used to generate the IC layout (e.g., the EDA tool) is stored, or on another non-transitory computer readable storage medium.

[0072] At operation 160, in some embodiments, at least one of the one or more semiconductor masks is manufactured, or at least one component in a layer of the semiconductor IC is manufactured, based on the IC layout map. Manufacturing the one or more semiconductor masks or at least one component in a layer of the semiconductor IC is discussed below with respect to Figure 8

[0073] At operation 170, in some embodiments, one or more manufacturing operations are performed based on the IC layout map. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout map. Performing the one or more photolithography exposures is discussed below with respect to​​Figure 8 discussing performing one or more manufacturing operations (e.g., one or more photolithography exposures) based on the IC layout.

[0074] By performing some or all of the operations of method 100A, design rules included in the DRM are generated using the design rule instructions so that IC devices are more efficiently designed and manufactured and can have fewer errors (as compared to methods in which the design rules and DRM are not produced by applying the design rule instructions to automatically generate the design rules).

[0075] Further, automatically generating and managing the design rules according to method 100A using the design rule instructions enables quality control and source data tracking of the design rules included in the DRM to be more efficiently performed (as compared to methods in which the design rules and DRM are not produced by applying the design rule instructions to automatically generate the design rules).

[0076] Additional details regarding IC device design systems and methods can be found, for example, in U.S. Patent No. 9,372,954, issued June 21, 2016, the entirety of which is incorporated by reference herein.

[0077] Figure 7 is a block diagram of an IC device design system 700 according to some embodiments. The above reference Figure 1A-6 One or more operations of methods 100A and 100B discussed above can be implemented using IC device design system 700 according to some embodiments.

[0078] In some embodiments, IC device design system 700 is a computing device that includes a hardware processor 702 and a non-transitory computer-readable storage medium 704. The non-transitory computer-readable storage medium 704 is encoded with (i.e., stores) computer program code 706 (i.e., a set of executable instructions) among other things. The hardware processor 702 executes the instructions 706 (at least partially) to implement, for example, the above reference Figure 1A discussed method 100A and / or the above reference Figure 1B discussed method 100B (hereinafter, the proposed process and / or method) in part or in whole.

[0079] The processor 702 is electrically coupled via the bus 708 to the non-transitory computer readable storage medium 704. The processor 702 is also electrically coupled through the bus 708 to the I / O interface 710. The network interface 712 is also electrically connected to the processor 702 via the bus 708. The network interface 712 is connected to the network 714, enabling the processor 702 and the non-transitory computer readable storage medium 704 to connect to external elements via the network 714. The processor 702 is configured to execute the computer program code 706 encoded in the non-transitory computer readable storage medium 704, such that the IC device design system 700 is operable to perform part or all of the proposed processes and / or methods. In one or more embodiments, the processor 702 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0080] In one or more embodiments, the non-transitory computer readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the non-transitory computer readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments that use optical disks, the non-transitory computer readable storage medium 704 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0081] In one or more embodiments, the non-transitory computer readable storage medium 704 stores computer program code 706 configured to enable the IC device design system 700 to perform part or all of the proposed processes and / or methods. In one or more embodiments, the non-transitory computer readable storage medium 704 also stores information that facilitates performance of part or all of the proposed processes and / or methods. In various embodiments, the non-transitory computer readable storage medium 704 stores one or a combination of at least one design rule instruction 720, at least one standard set 722, at least one design rule 724, and / or at least one DRM 726, each as outlined above with respect to the methods 100A and 100B and Figure 1A-6 as discussed.

[0082] The IC device design system 700 includes the I / O interface 710. The I / O interface 710 is coupled to external circuits. In various embodiments, the I / O interface 710 includes one or a combination of a keyboard, a keypad, a mouse, a trackball, a touchpad, a display, a touchscreen, and / or a cursor direction key for communicating information and commands to and from the processor 702.

[0083] The IC device design system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 allows the system 700 to communicate with a network 714 to which one or more other computer systems are connected. The network interface 712 includes a wireless network interface (e.g., BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA); or a wired network interface (e.g., ETHERNET, USB, or IEEE- 1364). In one or more embodiments, part or all of the presented processes and / or methods are implemented in two or more systems 700.

[0084] The IC device design system 700 is configured to receive information through the I / O interface 710. The information received through the I / O interface 710 includes one or a combination of at least one design rule instruction, at least one standard set, at least one design rule, at least one DRM, and / or other parameters for the processor 702 to process. The information is transferred to the processor 702 via the bus 708. The IC device design system 700 is configured to send and / or receive information related to a user interface through the I / O interface 710.

[0085] In some embodiments, part or all of the presented processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the presented processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the presented processes and / or methods are implemented as a plug-in of a software application. In some embodiments, at least one of the presented processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, an IC layout is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc, or other appropriate layout generation tool.

[0086] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units such as an optical disc (e.g., a DVD), a magnetic disc (e.g., a hard disc), a semiconductor memory (e.g., a ROM, a RAM, a memory card), and the like.

[0087] By being operable to implement one or more operations of the method 100A as discussed above with respect to Figure 1A-6 The IC device design system 700 and the non-transitory computer-readable recording medium (e.g., the non-transitory computer-readable recording medium 704) realize the benefits discussed above with respect to the method 100A by being operable to implement one or more operations of the method 100A as discussed above with respect to

[0088] Figure 8 is a block diagram of an IC manufacturing system 800 and IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 800 based on a layout.

[0089] In Figure 8 , the IC manufacturing system 800 includes entities, e.g., a design house 820, a mask house 830, and an IC manufacturer / fabricator (“fab”) 850, that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 860. The entities in the system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, e.g., an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 820, the mask house 830, and the IC manufacturer 850 are owned by a single larger company. In some embodiments, two or more of the design house 820, the mask house 830, and the IC manufacturer 850 coexist in a common facility and use common resources.

[0090] The design house (or design team) 820 generates an IC design layout 822 based on the method 100A discussed above with reference to Figure 1A-6 The IC design layout 822 includes various geometric patterns that correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC devices 860 to be manufactured. Various layer combinations form various IC features. For example, a portion of the IC design layout 822 includes various IC features, e.g., active regions, gate electrodes, source and drain, metal lines or vias for interlayer interconnects, and openings for pads to be bonded (formed on a semiconductor substrate (e.g., a silicon wafer) and various metal layers disposed on the semiconductor substrate). The design house 820 implements an appropriate design process (the method 100A discussed above with reference to Figure 1A-6 to form the IC design layout 822. The design process includes one or more of logic design, physical design, or layout and routing. The IC design layout 822 is represented in one or more data files with information of the geometric patterns. For example, the IC design layout 822 can be represented in a GDSII file format or a DFII file format.

[0091] The mask room 830 includes data preparation 832 and mask manufacturing 844. The mask room 830 uses the IC design layout 822 to manufacture one or more masks 845 to be used to manufacture various layers of the IC device 860 according to the IC design layout 822. The mask room 830 performs mask data preparation 832 in which the IC design layout 822 is converted into a representative data file ("RDF"). The mask data preparation 832 provides the RDF to the mask manufacturing 844. The mask manufacturing 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, e.g., a mask (reticle) 845 or a semiconductor wafer 853. The design layout 822 is manipulated by the mask data preparation 832 to conform to the particular characteristics of the mask writer and / or the requirements of the IC manufacturer 850. In Figure 8 In some embodiments, the mask data preparation 832 and the mask manufacturing 844 can be collectively referred to as mask data preparation.

[0092] In some embodiments, the mask data preparation 832 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, e.g., that can be caused by diffraction, interference, other processing effects, etc. The OPC adjusts the IC design layout 822. In some embodiments, the mask data preparation 832 also includes resolution enhancement techniques (RET), e.g., off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used that treat the OPC as an inverse imaging problem.

[0093] In some embodiments, the mask data preparation 832 includes a mask rule checker (MRC) that checks the IC design layout 822 that has been processed in the OPC with a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability of the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 822 to compensate for limitations during the mask manufacturing 844 that can undo portions of the modifications performed by the OPC in order to satisfy the mask creation rules.

[0094] In some embodiments, mask data preparation 832 includes lithography process check (LPC), which simulates the processes to be implemented by IC manufacturer 850 to manufacture IC device 860. LPC simulates the processes based on IC design layout 822 to create a simulated manufactured device, e.g., IC device 860. Process parameters in the LPC simulation can include parameters associated with various processing of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, e.g., aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after a simulated manufactured device has been created by the LPC, if the simulated device is not close enough in shape to satisfy design rules, then OPC and / or MRC are repeated to further refine IC design layout 822.

[0095] It should be appreciated that the above description of mask data preparation 832 has been simplified for clarity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOP) to modify IC design layout 822 according to manufacturing rules. Furthermore, the processing applied to IC design layout 822 during data preparation 832 can be performed in a variety of different orders.

[0096] After mask data preparation 832 and during mask manufacturing 844, a mask 845 or a set of masks 845 is manufactured based on the modified IC design layout 822. In some embodiments, mask manufacturing 844 includes performing one or more photolithography exposures based on the IC design layout 822. In some embodiments, based on the modified IC design layout 822, a mechanism of electron beams (e-beams) or multiple e-beams is used to form a pattern on a mask (photomask or reticle) 845. The mask 845 can be formed using various techniques. In some embodiments, the mask 845 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation (e.g., a beam of ultraviolet (UV) light) used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 845 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 845 is formed using phase shift techniques. In a phase shift mask (PSM) version of the mask 845, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 844 are used in various processes. For example, such mask(s) are used in ion implantation processes to form various doped regions in a semiconductor wafer 853, in etching processes to form various etched regions in the semiconductor wafer 853, and / or in other suitable processes.

[0097] An IC manufacturer 850 includes wafer fabrication 852. The IC manufacturer 850 is an IC fabrication business that includes one or more fabrication facilities for fabricating various different IC products. In some embodiments, the IC manufacturer 850 is a semiconductor foundry. For example, there can be a fabrication facility for front-end fabrication of multiple IC products (a front-end (FEOL) manufacturer), while a second fabrication facility can provide back-end fabrication (a back-end (BEOL) manufacturer) for interconnection and packaging of the IC products, and a third fabrication facility can provide other services for the foundry business.

[0098] IC manufacturer 850 uses one or more masks 845 manufactured by mask chamber 830 to manufacture IC device 860. Therefore, IC manufacturer 850 uses IC design layout 822 at least indirectly to manufacture IC device 860. In some embodiments, semiconductor wafer 853 is manufactured by IC manufacturer 850 using one or more masks 845 to form IC device 860. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 853 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0099] Regarding IC manufacturing systems (e.g., Figure 8 Details of the system 800 and its associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of each of which are incorporated herein by reference.

[0100] In some embodiments, a method for designing an IC device includes: specifying a set of standards corresponding to an IC manufacturing process; generating design rules using a processor by applying design rule instructions to the set of standards; generating a Design Rule Registry (DRM), wherein the DRM is an electronic file including the design rules; performing Design Rule Control (DRC) on a layout of at least a portion of the IC device using the design rules from the DRM; and storing an IC layout diagram including the layout on a non-transitory computer-readable medium based on the layout verification by performing the DRC.

[0101] In some embodiments, a non-transitory computer-readable medium including computer-executable instructions configured to perform a method of designing an integrated circuit (IC) device. The method includes: receiving a set of standards from an I / O interface, the set of standards corresponding to an IC manufacturing process; generating design rules by applying stored design rule instructions to the set of standards, the design rules specifying design constraints for the layout of at least a portion of the IC device; receiving input from the I / O interface; and generating a design management file (DRM) in response to the input, the DRM being an electronic document including the design rules.

[0102] In some embodiments, an IC device design system, comprising: at least one processor; and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to perform the following operations: receive a set of standards from an I / O interface, the set of standards corresponding to an IC manufacturing process; obtain, from the at least one memory, or import into the IC device design system, design rule instructions; generate design rules that specify design constraints for a layout of at least a portion of an IC device by applying the design rule instructions to the set of standards; generate a DRM that includes the design rules; and store the DRM in the at least one memory, or export the DRM from the IC device design system.

[0103] One of ordinary skill in the art will readily see, after reading the foregoing specification, that one or more embodiments disclosed herein, realize the advantages mentioned above. Numerous other advantages, one or more embodiments, will be readily apparent to those skilled in the art from the foregoing description. The mere fact that an advantage is mentioned in the foregoing description is not an admission that the advantage is required by the application. Moreover, the advantages described above are not necessarily the only advantages of one or more embodiments. It should also be understood that the recitation of a list of advantages is merely a description of potential advantages and is not an admission that such advantages are required, or that the described advantages are the only advantages of one or more embodiments.

[0104] Example 1. A method of designing an integrated circuit (IC) device, the method comprising: specifying a set of standards corresponding to an IC manufacturing process; generating, using a processor, design rules by applying design rule instructions to the set of standards; generating a design rule manual (DRM), wherein the DRM is an electronic file that includes the design rules; performing a design rule check (DRC) on a layout of at least a portion of the IC device using the design rules from the DRM; and storing an IC layout map that includes the layout on a non-transitory computer readable medium based on verifying the layout by performing the DRC.

[0105] Example 2. The method of example 1, further comprising: based on the IC layout map, performing at least one of: fabricating at least one component in a layer of the IC device, or performing one or more operations of the IC manufacturing process.

[0106] Example 3. The method of example 1, wherein specifying the set of standards comprises specifying at least one of: a feature size, a feature geometry, a spacing between features, a feature overlap size, or a layer, device, or device type identifier of the IC manufacturing process.

[0107] Example 4. The method of example 1, wherein specifying the set of standards comprises: receiving the set of standards in a template.

[0108] Example 5. The method of example 1, wherein applying the design rule instruction to the standard set comprises executing a previously stored series of inputs to a user interface.

[0109] Example 6. The method of example 1, wherein the standard set is one of a plurality of standard sets corresponding to the IC manufacturing process, the design rule instruction is one of a plurality of design rule instructions, the design rule is one of a set of design rules included in the DRM, and the method further comprises applying at least one additional design rule instruction of the plurality of design rule instructions to at least one additional standard set of the plurality of standard sets to generate at least one additional design rule of the set of design rules.

[0110] Example 7. The method of example 6, wherein the set of design rules is a subset of a plurality of design rules, and generating the DRM comprises selecting the subset from the plurality of design rules.

[0111] Example 8. The method of example 7, wherein selecting the subset from the plurality of design rules comprises: classifying the plurality of design rules into a plurality of groups; and selecting a group from the plurality of groups.

[0112] Example 9. The method of example 8, wherein classifying the plurality of design rules into the plurality of groups is based on one or more of a device type, a device region type, a device feature type, or a design rule instruction type.

[0113] Example 10. The method of example 1, further comprising generating the design rule instruction using the processor.

[0114] Example 11. A non-transitory computer-readable medium comprising computer- executable instructions configured to perform a method of designing an integrated circuit (IC) device, the method comprising: receiving a standard set from an input / output (I / O) interface, the standard set corresponding to an IC manufacturing process; generating a design rule by applying a stored design rule instruction to the standard set, the design rule specifying a design constraint for a layout of at least a portion of the IC device; receiving an input from the I / O interface; and in response to the input, generating a design rule manual (DRM), the DRM being an electronic file comprising the design rule.

[0115] Example 12. The non-transitory computer-readable medium of example 11, wherein the method further comprises: generating the stored design rule instructions from a series of previous inputs from the I / O interface; and storing the design rule instructions on one of the non-transitory computer-readable medium or another non-transitory computer-readable medium.

[0116] Example 13. The non-transitory computer-readable medium of example 11, wherein the design rule is one of a plurality of design rules, and the method further comprises, in response to another input received from the I / O interface: categorizing the plurality of design rules into a plurality of groups; and causing the plurality of design rules to be displayed on the I / O interface as divided into the plurality of groups.

[0117] Example 14. The non-transitory computer-readable medium of example 13, wherein categorizing the plurality of design rules is based on one or more of a device type, a device region type, a device feature type, or a design rule instruction type.

[0118] Example 15. The non-transitory computer-readable medium of example 13, wherein generating the DRM is in response to receiving an input from the I / O indicating a selection of a group from the plurality of groups displayed on the user interface.

[0119] Example 16. The non-transitory computer-readable medium of example 11, wherein the method further comprises: storing the DRM on one of the non-transitory computer-readable medium or another non-transitory computer-readable medium.

[0120] Example 17. An integrated circuit (IC) device design system comprising: at least one processor; and at least one memory including computer program code of one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to perform the following operations: receive a standard set from an input / output (I / O) interface, the standard set corresponding to an IC manufacturing process; retrieve design rule instructions from the at least one memory, or import the design rule instructions into the IC device design system; generate a design rule by applying the design rule instructions to the standard set, the design rule specifying a design constraint for a layout of at least a portion of the IC device; generate a design rule manual (DRM) including the design rule; and store the DRM in the at least one memory, or export the DRM from the IC device design system.

[0121] Example 18. The IC device design system of example 17, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the system to: receive a series of user inputs from the I / O interface; and generate the design rule instructions from the series of user inputs.

[0122] Example 19. The IC device design system of example 17, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the system to: display a set of design rule instructions on the I / O interface, the set of design rule instructions including the design rule instructions; and store or export the DRM based on a selection of the set of design rule instructions received from the I / O interface.

[0123] Example 20. The IC device design system of example 19, wherein the set of design rule instructions is one of a plurality of sets of design rule instructions, and the at least one memory and the computer program code are configured to, with the at least one processor, cause the system to: responsive to an input received from the I / O interface, sort the plurality of sets of design rule instructions; and display the sorted plurality of sets of design rule instructions as a table on the I / O interface.

Claims

1. A method of designing an integrated circuit (IC) device, the method comprising: receiving, at a processor, a standard set corresponding to an IC manufacturing process; generating, with the processor, design rule instructions that define one or more macros that assign conditions and define relationships within the standard set; generating, with the processor and in response to the generated design rule instructions, design rules by executing the design rule instructions; generating, with the processor and based on the design rules from the DRM, a design rule manual (DRM), wherein the DRM is an electronic file that includes the design rules; performing, with the processor and based on the design rules from the DRM, a design rule check (DRC) on a layout of at least a portion of the IC device; verifying, with the processor and in response to the DRC, the layout; and storing, with the processor and based on the verified layout, an IC layout map that includes the layout on a non-transitory computer readable medium.

2. The method of claim 1, further comprising: based on the IC layout map, at least one of: manufacturing at least one component in a layer of the IC device, or performing one or more operations of the IC manufacturing process.

3. The method of claim 1, wherein, receiving the standard set includes receiving at least one of: a feature size, a feature geometry, a spacing between features, a feature overlap size, or a layer, device, or device type identifier of the IC manufacturing process.

4. The method of claim 1, wherein, receiving the standard set includes receiving the standard set in a template.

5. The method of claim 1, wherein, generating the design rule instructions includes executing a previously stored series of inputs to a user interface.

6. The method of claim 1, wherein: the standard set is one of a plurality of standard sets corresponding to the IC manufacturing process, the design rule instructions are one of a plurality of design rule instructions, the design rule is one of a set of design rules included in the DRM, and the method further comprises applying at least one additional design rule instruction of the plurality of design rule instructions to at least one additional standard set of the plurality of standard sets to generate at least one additional design rule of the set of design rules.

7. The method of claim 6, wherein: the set of design rules is a subset of design rules of a plurality of design rules, and generating the DRM includes selecting the subset of design rules from the plurality of design rules.

8. The method of claim 7, wherein, selecting the subset of design rules from the plurality of design rules includes: categorizing the plurality of design rules into a plurality of groups; and selecting a group from the plurality of groups.

9. A non-transitory computer readable medium comprising computer executable instructions configured to perform a method of designing an integrated circuit (IC) device, the method comprising: receiving, from an input / output (I / O) interface, a standard set corresponding to an IC manufacturing process; generating design rule instructions by defining one or more computer executable macros based on the IC manufacturing process, and storing the design rule instructions; generating design rules by applying the stored design rule instructions to the standard set, the design rules specifying design constraints for a layout of at least a portion of the IC device; receiving input from the I / O interface; and in response to the input, generating a design rule manual (DRM), the DRM being an electronic file comprising the design rules.

10. An integrated circuit (IC) device design system, comprising: at least one processor; and at least one memory including computer program code of one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the IC device design system to perform the following operations: receiving a standard set from an input / output (I / O) interface, the standard set corresponding to an IC manufacturing process; obtaining design rule instructions from the at least one memory, or importing the design rule instructions into the IC device design system, the design rule instructions being one or more computer executable macros configured to incorporate one or more parameters and context information from the standard set; generating design rules by applying the design rule instructions to the standard set, the design rules specifying design constraints for a layout of at least a portion of an IC device; generating a design rule manual (DRM) comprising the design rules; and storing the DRM in the at least one memory, or exporting the DRM from the IC device design system.

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