Excitation vector acquisition method, simulation test method, device, equipment and medium

Abstract

The invention provides an excitation vector acquisition method, a simulation test method, a simulation test device, simulation test equipment and a medium, and relates to the field of simulation test. The excitation vector acquisition method comprises the following steps: acquiring all waveform files obtained by performing a simulation test on a specified module; determining a waveform file of the target port signal from all the waveform files; the target port is a port of a target module, and the target module is a subordinate module included in the specified module; for each clock period, port signal values of waveform files of all target port signals in the clock period are obtained, and excitation vectors are obtained; the excitation vector comprises signal values of all the target ports at the same moment, and the excitation vector is used for performing simulation test on the target module. The excitation vector of the subordinate module can be obtained by performing the simulation test on the superior module, so that the workload of an engineer is reduced, the engineer does not need to analyze and learn the internal structure and the working logic of the subordinate module, and the acquisition efficiency of the excitation vector is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of simulation testing, in particular to a stimulus vector acquisition method, a simulation testing method, a device, equipment and a medium. BACKGROUND

[0002] Due to the rapid increase of chip functions and complexity, the cost of chip tape-out also increases exponentially. In order to improve the success rate of chip tape-out, detailed simulation testing needs to be performed on the functions and performance of the chip and other related indicators during the chip design stage.

[0003] Currently, when performing simulation testing on a chip, an engineer usually develops a corresponding reference model for each functional module in the chip, and develops test cases according to the functions of the functional modules. Then, a test platform is built, and the test is performed according to the RTL (Register Transfer Level) code, the reference model and the test cases of the functional modules. When part of the structure of the functional module is improved, the improved functional module needs to be tested again. At this time, the entire functional module still needs to be taken as a test object, which results in a high time cost of testing. If the structure of the functional module is purchased, the reference model and the test cases need to be developed again, which greatly increases the workload of the engineer and requires a higher ability of the engineer. SUMMARY

[0004] The present application provides a stimulus vector acquisition method, a simulation testing method, a device, equipment and a medium to reduce the workload of engineers.

[0005] In a first aspect, the present application provides a stimulus vector acquisition method, comprising: acquiring all waveform files obtained by performing simulation testing on a specified module; determining a waveform file of a target port signal from the all waveform files; the target port is a port of a target module, and the target module is a subordinate module included in the specified module; for each clock cycle, acquiring a port signal value of the waveform file of all the target port signals in the clock cycle to obtain a stimulus vector; the stimulus vector includes signal values of all the target ports at the same time, and the stimulus vector is used for performing simulation testing on the target module.

[0006] In the embodiments of the present application, the waveform files of the lower-level modules included in the specified module are obtained by performing simulation testing on the specified module (the upper-level module of the target module). Since the input end of the internal lower-level module of the specified module receives correct control logic when the specified module is working, the excitation vector is directly obtained through the waveform files of the lower-level modules, so that the specific working logic and internal structure of the lower-level modules do not need to be concerned. The excitation vector of the lower-level module is directly obtained by performing simulation testing on the upper-level module, thereby reducing the workload of engineers and improving the efficiency of obtaining the excitation vector without the need for engineers to analyze and learn the internal structure and working logic of the lower-level module.

[0007] In some possible implementation manners of the above first aspect, after the waveform files of the target port signals are determined from the all waveform files, the method further includes: cutting all the waveform files of the target port signals to remove invalid content in the waveform files, to obtain valid waveform files of all the target port signals; wherein the invalid content is content corresponding to a time period during which the target module does not run in the waveform file; and correspondingly, for each clock cycle, the port signal values of the waveform files of all the target port signals in the clock cycle are obtained to obtain an excitation vector, including: for each clock cycle, the port signal values of all the valid waveform files in the clock cycle are obtained to obtain the excitation vector.

[0008] In the embodiments of the present application, during the simulation testing of the specified module, the target module may not be in a working state all the time. Therefore, in the waveform files of the ports of the target module obtained, there may be a large number of waveform signals (i.e., invalid content) in which the target module is in a standby or other non-working state. By removing the invalid content, the excitation vector obtained is the control logic when the target module is working, the number of excitation vectors obtained is reduced, and the time required for subsequent simulation testing of the target module is reduced.

[0009] In some possible implementation manners of the above first aspect, cutting all the waveform files of the target port signals to remove invalid content in the waveform files, to obtain valid waveform files of all the target port signals, includes: cutting all the waveform files of the target port signals according to a preset start time and an end time, to obtain valid waveform files of all the target port signals; wherein the valid waveform file is a waveform file after the content before the start time and the content after the end time are cut off from the waveform file.

[0010] In the embodiments of the present application, by presetting the start time and the end time, the invalid content in the waveform file can be quickly removed to obtain the valid waveform file.

[0011] In some possible implementation manners of the first aspect, the invalid content includes multiple segments, and different segments of the invalid content correspond to different time ranges; the waveform files of all the target port signals are cropped to remove the invalid content in the waveform files, to obtain valid waveform files of all the target port signals, including: for the waveform file of each target port signal, the waveform file is cropped to remove all the invalid content in the waveform file, to obtain multiple valid content segments; and the multiple valid content segments are spliced to obtain the valid waveform file corresponding to the target port signal.

[0012] In the embodiments of the present application, since the working time of the target module can be intermittent, after the invalid content in the waveform file is removed, multiple valid content segments are obtained. In order to facilitate subsequent processing, the multiple valid content segments are spliced into one valid waveform file, so as to facilitate subsequent obtaining of the excitation vector.

[0013] In some possible implementation manners of the first aspect, for each clock cycle, the port signal value of the waveform file of all the target port signals in the clock cycle is obtained, including: for each clock cycle, the waveform signal included in the waveform file of all the target port signals in the clock cycle is sampled at a clock rising edge and / or a clock falling edge, to obtain the port signal value corresponding to the waveform file of each target port signal in the clock cycle.

[0014] In the embodiments of the present application, by sampling the waveform signal included in the waveform file at a clock rising edge and / or a clock falling edge, the port signal value corresponding to the waveform file of each target port signal in the clock cycle can be accurately obtained.

[0015] In some possible implementation manners of the first aspect, for each clock cycle, the waveform signal included in the waveform file of all the target port signals in the clock cycle is sampled at a clock rising edge or a clock falling edge, to obtain the port signal value corresponding to the waveform file of each target port signal in the clock cycle, including: for each clock cycle, the waveform signal included in the waveform file of all the target port signals in the clock cycle is oversampled at a clock rising edge or a clock falling edge, to obtain multiple initial port signal value groups, wherein each initial port signal value group includes the sampling value corresponding to each target port signal obtained by one sampling; and from the multiple initial port signal value groups, one initial port signal value group is determined as the port signal value corresponding to the waveform file of each target port signal in the clock cycle.

[0016] In the embodiments of the present application, the over-sampling sampling mode is used to obtain a plurality of initial port signal value groups, and then the port signal values corresponding to the waveform file of each target port signal in the clock cycle are determined from the plurality of initial port signal value groups. Thus, the interference of delay information and glitch signals can be reduced, and the sampling accuracy can be improved.

[0017] In combination with the technical solutions provided by the first aspect, in some possible implementation manners, for each clock cycle, the port signal values corresponding to the waveform file of each target port signal in the clock cycle are obtained by clock rising edge and falling edge sampling on the waveform signals included in the waveform file of all the target port signals in the clock cycle, including: for each clock cycle, the port signal values corresponding to the waveform file of each target port signal in the clock cycle are obtained by clock rising edge over-sampling on the waveform signals included in the waveform file of all the target port signals in the clock cycle, including: for each clock cycle, a plurality of initial rising edge port signal value groups are obtained by clock rising edge over-sampling on the waveform signals included in the waveform file of all the target port signals in the clock cycle, wherein each initial rising edge port signal value group includes the sampling value corresponding to each target port signal obtained by one rising edge sampling; a plurality of initial falling edge port signal value groups are obtained by clock falling edge over-sampling on the waveform signals included in the waveform file of all the target port signals in the clock cycle, wherein each initial falling edge port signal value group includes the sampling value corresponding to each target port signal obtained by one falling edge sampling; and one initial rising edge port signal value group and one initial falling edge port signal value group are determined from the plurality of initial rising edge port signal value groups and the plurality of initial falling edge port signal value groups, respectively, as the port signal values corresponding to the waveform file of each target port signal in the clock cycle.

[0018] In the embodiments of the present application, since the jump times of the signals of different ports of the target module can be different, the rising edge jump and the falling edge jump can exist at the same time, and therefore, in order to improve the sampling accuracy, the rising edge and the falling edge in each clock cycle are sampled. Moreover, the over-sampling sampling mode is used to obtain the port signal values corresponding to the waveform file of each target port signal in the clock cycle (including the port signal values corresponding to the rising edge and the port signal values corresponding to the falling edge). Thus, the interference of delay information and glitch signals can be reduced, and the sampling accuracy can be improved.

[0019] In a second aspect, the present application provides a simulation test method, comprising: obtaining an excitation vector file, wherein the excitation vector file comprises a plurality of excitation vectors, and each excitation vector is obtained by the method according to the first aspect and / or any possible implementation manner of the first aspect; converting the excitation vector file into an excitation waveform signal based on a preset clock signal; inputting the excitation waveform signal into a target module and an improved target module respectively, to obtain a first output signal of the target module and a second output signal of the improved target module respectively; wherein the improved target module is a module obtained by improving the structure of the target module; comparing the first output signal and the second output signal to obtain a comparison result; and in the case that the first output signal and the second output signal are the same, it is indicated that the improved target module and the target module realize the same function.

[0020] In the embodiments of the present application, since the improved target module is an improved target module, the functions realized by the two modules in the specified module should be the same. That is, in the case that the input control signals are the same, the outputs of the two modules should be consistent. Based on this, the unimproved target module can be used as a reference model of the improved target module, so that the engineers do not need to manually develop the reference model of the improved target module, thereby reducing the workload of the engineers. Moreover, by this way, the simulation test of the improved target module can be realized directly without putting the improved target module into the specified module to test the specified module. Compared with the way of testing the specified module to realize the test of the improved target module, the present application can reduce the time required for the test.

[0021] In a third aspect, the present application provides an excitation vector obtaining device, comprising: a first obtaining module, configured to obtain all waveform files obtained by simulating and testing a specified module; a processing module, configured to determine the waveform files of target port signals from the all waveform files; the target port is a port of a target module, and the target module is a subordinate module included in the specified module; for each clock cycle, the processing module is configured to obtain the port signal values of all the waveform files of the target port signals in the clock cycle, to obtain an excitation vector; the excitation vector comprises the signal values of all the target ports at the same time, and the excitation vector is used for simulating and testing the target module.

[0022] Fourthly, this application provides a simulation testing apparatus, comprising: a second acquisition module, configured to acquire an excitation vector file, the excitation vector file including a plurality of excitation vectors, each of the excitation vectors being an excitation vector obtained according to the method described in accordance with the first aspect and / or in combination with any possible implementation of the first aspect; a test signal generation module, configured to convert the excitation vector file into an excitation waveform signal based on a preset clock signal; inputting the excitation waveform signal into the target module and the improved target module respectively to obtain a first output signal of the target module and a second output signal of the improved target module respectively; wherein the improved target module is a module obtained by structurally improving the target module; and an output result comparison module, configured to compare the first output signal and the second output signal to obtain a comparison result; wherein, if the first output signal and the second output signal are the same, it indicates that the improved target module and the target module perform the same function.

[0023] Fifthly, this application provides an electronic device, comprising: a memory and a processor, the memory and the processor being connected; the memory being used to store a program; the processor being used to invoke the program stored in the memory to execute the method described in the first aspect and / or in combination with any possible implementation of the first aspect, or to execute the method described in the second aspect.

[0024] In a sixth aspect, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, performs the method described in the first aspect and / or in combination with any possible implementation of the first aspect, or performs the method described in the second aspect. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating an incentive vector acquisition method according to an embodiment of this application; Figure 2 This is a structural block diagram of a SYS module shown in an embodiment of this application; Figure 3 This is a schematic diagram of the port of a C2 module shown in an embodiment of this application; Figure 4A waveform signal schematic diagram of each port of a C2 module shown in an embodiment of the present application; Figure 5 A content format schematic diagram of an excitation vector text shown in an embodiment of the present application; Figure 6 A port text file schematic diagram of a C2 module shown in an embodiment of the present application; Figure 7 A flow schematic diagram of a simulation test method shown in an embodiment of the present application; Figure 8 A structure block diagram of an excitation vector acquisition device shown in an embodiment of the present application; Figure 9 A structure block diagram of a simulation test device shown in an embodiment of the present application; Figure 10 A structure block diagram of an electronic device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0028] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, thus, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the relationship terms such as “first”, “second” and the like are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, thus, the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device.

[0029] The technical solutions of the present application will be described in detail below with reference to the drawings.

[0030] Please refer to Figure 1 , Figure 1 An excitation vector acquisition method shown in an embodiment of the present application will be described below with reference to the steps contained therein. Figure 1

[0031] S110: acquiring all waveform files obtained by simulating and testing a specified module.

[0032] ​Each waveform file corresponds to a port. The waveform file is a file recording a waveform signal input into the port during simulation test of the specified module, or a file recording a waveform signal output from the port during simulation test of the specified module.

[0033] Optionally, among all the waveform files, there are waveform files corresponding to each port of the specified module, and waveform files corresponding to ports of a sub-module (e.g., a target module) in the specified module.

[0034] All the waveform files obtained through simulation test of the specified module can be pre-acquired and stored in a storage medium, and can be directly called when needed. Alternatively, the waveform files can be obtained through simulation test of the specified module.

[0035] In one implementation, during simulation test of the specified module by using a simulation test platform such as an EDA (Electronic Design Automation) simulation platform, an EMU (Emulator) platform, and an FPGA (Field Programmable Gate Array) platform, waveform signals of each port included in the specified module are recorded and stored, and are sampled based on a clock cycle to obtain waveform files of each port in each specified module. When a waveform file of a target port is needed, a waveform file corresponding to the target port is searched from all the recorded waveform files, and waveform files of all target port signals are obtained.

[0036] In one implementation, each waveform file can be named by using a name of a corresponding port, a hierarchical path of a module where the port is located, and the like. Thus, the name of each waveform file uniquely corresponds to the corresponding port. Thus, when a waveform file corresponding to a target port is needed, the corresponding waveform file can be quickly found according to the hierarchical path of the target module and the name of the target port.

[0037] Alternatively, a name of a corresponding port of each waveform file, a hierarchical path of a module where the port is located, and the like can be used as an index. Each index corresponds to a waveform file. When a waveform file corresponding to a target port is needed, the corresponding waveform file can be obtained by searching for a corresponding index according to the hierarchical path of the target module and the name of the target port.

[0038] The examples are only for understanding, and the storage of the waveform files and the searching of the waveform files are not limited to the examples.

[0039] S120: Determine the waveform file of the target port signal from all the waveform files.

[0040] The specified module can be a functional module included in a chip, or the specified module can also refer to the entire chip.

[0041] The target port is a port of a target module, and the target module is a subordinate module included in the specified module.

[0042] To facilitate understanding of the relationship between the specified module and the target module, the following will be described in conjunction with Figure 2 .

[0043] As shown in Figure 2 , the SYS module includes the A module, the B module, and the C module. The C module further includes the C1 module and the C2 module. For example, the SYS module can serve as the specified module, and the subordinate modules thereof are the A module, the B module, the C module, the C1 module, and the C2 module. For example, the C module can also serve as the specified module, and the subordinate modules thereof are the C1 module and the C2 module. The examples are only for facilitating understanding and should not be considered as a limitation on the present application.

[0044] Optionally, since the testing of the target module only requires the signal of the input port of the target module, the target port can also be the input port of the target module.

[0045] In an implementation, if each waveform file obtained can be named by using the name of the corresponding port, the hierarchical path of the module where the port is located, etc., or each waveform file obtained corresponds to an index (the index is composed of the name of the port corresponding to each waveform file, the hierarchical path of the module where the port is located, etc.), a port text file including each input port of the target module can also be stored. The name of each port recorded in the port text file includes the hierarchical path of the target module in the specified module and the name of the target port. The port text file can be used to quickly determine the waveform file corresponding to each target port of the target module from all the obtained waveform files.

[0046] For example, if each waveform file obtained can be named by using the name of the corresponding port, the hierarchical path of the module where the port is located, etc. The manner of determining the waveform file of the target port signal from all the waveform files can be: according to the content included in the port text file corresponding to the target module, searching for the waveform file whose name includes the hierarchical path of the target module in the specified module and the name of the target port from all the obtained waveform files. The waveform file whose name includes the hierarchical path of the target module in the specified module and the name of the target port is determined as the waveform file of the target port signal.

[0047] Alternatively, if each waveform file corresponds to an index, the index is composed of the name of the port corresponding to each waveform file, the hierarchical path of the module where the port is located, and the like. The manner of determining the waveform file of the target port signal from all waveform files can be: according to the content included in the port text file corresponding to the target module, determining the target index including the hierarchical path of the target module in the specified module and the name of the target port. The waveform file corresponding to the target index is the waveform file of the target port signal.

[0048] In an implementation, after determining the waveform file of the target port signal from all waveform files, the waveform files of all target port signals can be cropped to remove invalid content in the waveform files, to obtain valid waveform files of all target port signals. The invalid content is the content in the waveform file corresponding to the time period when the target module is not running.

[0049] Correspondingly, for each clock cycle, the manner of obtaining the port signal value of the waveform file of all target port signals in the clock cycle to obtain an excitation vector can be: for each clock cycle, obtaining the port signal value of the waveform file of all valid waveform files in the clock cycle to obtain the excitation vector.

[0050] Since the target module can not be in a working state during the simulation test of the specified module, there can be a large number of waveform signals (i.e., invalid content) of the target module in the standby state or other non-working states in the waveform file of the port of the target module. By removing the invalid content, the obtained excitation vector is the control logic when the target module is working, the number of obtained excitation vectors is reduced, and the time required for subsequent simulation test of the target module is reduced.

[0051] In an implementation, the manner of cropping all waveform files of target port signals to remove invalid content in the waveform files to obtain valid waveform files of all target port signals can be: cropping all waveform files of target port signals according to a preset start time and an end time to obtain valid waveform files of all target port signals.

[0052] The valid waveform file is: the waveform file after cropping the content before the start time and the content after the end time. That is, the waveform signal segment between the start time and the end time in the waveform file of the target port signal is the valid signal segment, that is, the target module is normally working between the start time and the end time. Therefore, the waveform signal segment between the start time and the end time is intercepted as the valid waveform file.

[0053] By presetting the start time and the end time, the invalid content in the waveform file can be quickly removed to obtain the valid waveform file.

[0054] Optionally, the preset start time and end time can include multiple groups, and there is no overlap in the time range corresponding to each start time and end time group. The manner of cutting the waveform file of all target port signals to remove the invalid content in the waveform file to obtain the valid waveform file of all target port signals can be: for each start time and end time group, cutting the waveform file of all target port signals according to the start time and end time included in the group to obtain the valid waveform file of all target port signals. In this case, each start time and end time group corresponds to a valid waveform file of a target port signal.

[0055] Optionally, the engineer can also manually remove the invalid content in the waveform file by analyzing the waveform file of all target port signals to obtain the valid waveform file of all target port signals.

[0056] In an implementation, if the invalid content includes multiple segments, the invalid content of different segments corresponds to different time ranges. The manner of cutting the waveform file of all target port signals to remove the invalid content in the waveform file to obtain the valid waveform file of all target port signals can be: for the waveform file of each target port signal: first, cut the waveform file to remove all invalid content in the waveform file to obtain multiple valid content segments. Then, splice the multiple valid content segments to obtain the valid waveform file corresponding to the target port signal.

[0057] Since the working time of the target module can be intermittent, after removing the invalid content in the waveform file, multiple valid content segments are obtained. In order to facilitate subsequent processing, the multiple valid content segments are spliced into one valid waveform file, thereby facilitating the subsequent obtaining of the excitation vector.

[0058] Optionally, the manner of cutting the waveform file to remove all invalid content in the waveform file to obtain multiple valid content segments can be: for each start time and end time group, cutting the waveform file of all target port signals according to the start time and end time included in the group to obtain the valid content segment corresponding to the start time and end time group. The preset start time and end time includes multiple groups, and there is no overlap in the time range corresponding to each start time and end time group.

[0059] Alternatively, the manner of cutting the waveform file to remove all invalid content in the waveform file to obtain multiple valid content segments can be: the engineer manually removes the invalid content in the waveform file by analyzing the waveform file of all target port signals to obtain multiple valid content segments.

[0060] S130: For each clock cycle, obtain the port signal value of the waveform file of all target port signals in the clock cycle to obtain an excitation vector.

[0061] The excitation vector includes the signal values of all target ports at the same time, and the excitation vector is used for simulation test of the target module.

[0062] For ease of understanding, it is assumed that the target module includes five target ports of WR, WADDR, WDATA, RD, and RADDR. If in the first clock cycle, the port signal value corresponding to WR is 0, the port signal value corresponding to WADDR is 1, the port signal value corresponding to WDATA is 1, the port signal value corresponding to RD is 0, and the port signal value corresponding to RADDR is 0. The excitation vector corresponding to the first clock cycle can be expressed as (0, 1, 1, 0, 0). The specific form of the excitation vector is not limited to the example.

[0063] In an implementation, for each clock cycle, the manner of obtaining the port signal value of the waveform file of all target port signals in the clock cycle can be that, for each clock cycle, the waveform signal included in the waveform file of all target port signals in the clock cycle is sampled at a clock rising edge and / or a clock falling edge to obtain the port signal value of the waveform file of each target port signal in the clock cycle.

[0064] By sampling the waveform signal included in the waveform file at a rising edge and / or a falling edge, the port signal value of the waveform file of each target port signal in the clock cycle can be accurately obtained.

[0065] The three sampling trigger mechanisms of rising edge sampling, falling edge sampling, or both rising edge and falling edge sampling can be selected according to actual needs.

[0066] For example, when all target port signals of the target module jump only at the rising edge of the clock signal, rising edge sampling can be selected. When all target port signals of the target module jump only at the falling edge of the clock signal, falling edge sampling can be selected.

[0067] When all target port signals of the target module include target port signals that jump at the rising edge of the clock signal and target port signals that jump at the falling edge of the clock signal, sampling is required at both the rising edge and the falling edge of the clock signal. The port signal value of the waveform file of each target port signal at the rising edge of the clock cycle and the port signal value of the waveform file of each target port signal at the falling edge of the clock cycle are obtained, respectively.

[0068] Optionally, when the sampling trigger mechanism requires sampling on both rising edge and falling edge, the obtained port signal values include the port signal values corresponding to the rising edge and the falling edge of the waveform file of each target port signal in the clock cycle. In this case, the obtained excitation vectors also include two, one excitation vector includes the port signal values corresponding to the rising edge of the clock cycle, and the other excitation vector includes the port signal values corresponding to the falling edge of the clock cycle.

[0069] In an embodiment, oversampling sampling mode can be used for sampling. Since the oversampling sampling mode can obtain multiple sets of sampling signal values for each trigger sampling (rising edge or falling edge), for each trigger sampling, one set of sampling signal values is selected as the port signal value of the waveform file of the target port signal in the clock cycle.

[0070] In an embodiment, the sampling trigger mechanism selects rising edge sampling or falling edge sampling. Then, for each clock cycle, the waveform signals included in the waveform file of all target port signals in the clock cycle are sampled on the rising edge or the falling edge of the clock to obtain the port signal value corresponding to the waveform file of each target port signal in the clock cycle. The method can be: for each clock cycle, the waveform signals included in the waveform file of all target port signals in the clock cycle are oversampled on the rising edge or the falling edge of the clock to obtain multiple initial port signal value sets. Each initial port signal value set includes the sampling value of each target port signal obtained by one sampling. Then, one initial port signal value set is determined from the multiple initial port signal value sets as the port signal value corresponding to the waveform file of each target port signal in the clock cycle.

[0071] Using the oversampling sampling mode, multiple initial port signal value sets are obtained, and then the final port signal value corresponding to the waveform file of each target port signal in the clock cycle is determined from the multiple initial port signal value sets. Thus, the interference of delay information and glitch signals can be reduced, and the accuracy of sampling can be improved.

[0072] Optionally, the method of determining one initial port signal value set from the multiple initial port signal value sets as the port signal value corresponding to the waveform file of each target port signal in the clock cycle can be: determining the initial port signal value set with the most initial port signal value sets as the port signal value corresponding to the waveform file of each target port signal in the clock cycle.

[0073] For the convenience of understanding, it is exemplified that the target module includes five target ports of WR, WADDR, WDATA, RD and RADDR. If five initial port signal value groups obtained by oversampling in the first clock cycle are (0, 1, 1, 0, 0), (0, 1, 1, 0, 0), (0, 1, 1, 0, 0), (0, 1, 1, 0, 0) and (0, 1, 1, 0, 1) (the values in the brackets from left to right are the port signal values corresponding to WR, WADDR, WDATA, RD and RADDR respectively), four of the initial port signal value groups are the same, i.e. (0, 1, 1, 0, 0), thus each port signal value in (0, 1, 1, 0, 0) is taken as the port signal value of each target port signal in the clock cycle corresponding to the waveform file. That is, it is determined that in the first clock cycle, the port signal value corresponding to WR is 0, the port signal value corresponding to WADDR is 1, the port signal value corresponding to WDATA is 1, the port signal value corresponding to RD is 0 and the port signal value corresponding to RADDR is 0. The example is only for the convenience of understanding and should not be regarded as a limitation to the present application.

[0074] Optionally, the way of determining one initial port signal value group from the plurality of initial port signal value groups as the port signal value of each target port signal in the clock cycle corresponding to the waveform file can be that one initial port signal value group is randomly determined from the plurality of initial port signal value groups as the port signal value of each target port signal in the clock cycle corresponding to the waveform file.

[0075] In one embodiment, the sampling trigger mechanism selects rising edge sampling and falling edge sampling. For each clock cycle, the waveform signals included in the waveform file of each target port signal in the clock cycle are sampled at the rising edge and the falling edge, and the way of obtaining the port signal value of each target port signal in the clock cycle corresponding to the waveform file can be that for each clock cycle: the waveform signals included in the waveform file of all target port signals in the clock cycle are oversampled at the rising edge to obtain a plurality of initial rising edge port signal value groups. Each initial rising edge port signal value group includes the sampling value corresponding to each target port signal obtained by one rising edge sampling. Then the waveform signals included in the waveform file of all target port signals in the clock cycle are oversampled at the falling edge to obtain a plurality of initial falling edge port signal value groups, each of which includes the sampling value corresponding to each target port signal obtained by one falling edge sampling. Finally, one initial rising edge port signal value group and one initial falling edge port signal value group are determined from the plurality of initial rising edge port signal value groups and the plurality of initial falling edge port signal value groups respectively as the port signal value of each target port signal in the clock cycle corresponding to the waveform file.

[0076] Since the rising and falling edges of the signals of different ports of the target module can be different, the rising and falling edges of the signals can exist simultaneously, in order to improve the accuracy of the sampling, the rising and falling edges in each clock cycle are sampled. Moreover, by using the oversampling sampling mode, the final waveform file of each target port signal in the port signal value (including the rising edge corresponding port signal value and the falling edge corresponding port signal value) of the clock cycle is obtained. Thus, the interference of the delay information and the glitch signal can be reduced, and the accuracy of the sampling can be improved.

[0077] The way of determining one initial rising edge port signal value group from the multiple initial rising edge port signal value groups, and the way of determining one initial falling edge port signal value group from the multiple initial falling edge port signal value groups are the same as the way of determining one initial port signal value group from the multiple initial port signal value groups as the port signal value of the waveform file of each target port signal in the clock cycle, for brevity, the details are not described here.

[0078] Optionally, for multiple excitation vectors of the same target module, the recording order of the port signal values of different target ports included in different excitation vectors is the same.

[0079] Optionally, when storing the excitation vector, one excitation vector can be saved as one row of data (one address space) so as to be initialized into the memory when used subsequently, and also to facilitate the reading logic circuit to read according to the period based on the MCLK clock signal.

[0080] In order to facilitate the understanding of the above-mentioned excitation vector acquisition method, the C2 module in Figure 2 will be taken as an example for description. The ports of the C2 module are as shown in Figure 3 , and the C2 module includes five input ports of WR, WADDR, WDATA, RD, RADDR, and one output port of RDATA.

[0081] Then, the waveform files of the port signals of the C2 module are acquired. The waveform signals of the ports of the C2 module are as shown in Figure 4 , wherein the MCLK is the clock signal.

[0082] Then, each target port (input port) of the C2 module is sampled at each rising edge of the clock signal, and the port signal value of each target port corresponding to each rising edge is obtained. The port signal value of each target port corresponding to the unified rising edge of the clock signal is recorded as an excitation vector.

[0083] As shown in Figure 4As shown in the figure, the sampling is performed at the rising edge of the first clock cycle, and the port signal values of the five input ports WR, WADDR, WDATA, RD and RADDR are 0, 00, 11, 0 and 00 in sequence, and thus the excitation vector corresponding to the rising edge of the first clock cycle is (0, 00, 11, 0, 00). The excitation vector is recorded in the excitation vector text. Similarly, the sampling is performed at the rising edge of the second clock cycle, and the excitation vector is (1, 01, AA, 0, 00); the sampling is performed at the rising edge of the third clock cycle, and the excitation vector is (1, 02, 55, 1, 01); and the sampling is performed at the rising edge of the fourth clock cycle, and the excitation vector is (0, 03, FF, 0, 02).

[0084] The content format of the excitation vector text can be as shown in the figure. Figure 5 The corresponding excitation vector is recorded according to the sampling clock cycle. Each excitation vector includes the port signal values of the five input ports WR, WADDR, WDATA, RD and RADDR. For example, Figure 5 As shown in the excitation vector text, at the sampling clock cycle 1, the port signal value corresponding to the target port WR is 0, the port signal value corresponding to WADDR is 00, the port signal value corresponding to WDATA is 11, the port signal value corresponding to RD is 0, and the port signal value corresponding to RADDR is 00.

[0085] Optionally, a port text file including each input port of the C2 module can also be stored, and the text file can be used to quickly determine the waveform file corresponding to each input port of the C2 module from the stored multiple waveform files. Each port name recorded in the port text file includes the hierarchical path of the C2 in the SYS module and the name of the port.

[0086] For example, the hierarchical path of the C2 module in the SYS module is SYS.C.C2, and the port WR can be recorded as SYS.C.C2.WR in the port text file. Similarly, the ports WADDR, WDATA, RD and RADDR can be recorded as SYS.C.C2.WADDR, SYS.C.C2.WDATA, SYS.C.C2.RD and SYS.C.C2.RADDR respectively. As shown in the figure. Figure 6

[0087] The examples are only for understanding and should not be regarded as a limitation of the present application.

[0088] Based on the same technical concept, the present application also provides a simulation test method, as shown in the figure. Figure 7 The content contained in the simulation test method will be described below. Figure 7

[0089] ​​S210: Obtain an excitation vector file.

[0090] The excitation vector file includes a plurality of excitation vectors, each of which is an excitation vector obtained according to the foregoing excitation vector obtaining method.

[0091] Optionally, the plurality of excitation vectors of the target module can be obtained by executing the foregoing excitation vector obtaining method based on a preset script when it is needed to obtain the excitation vector file. Alternatively, the plurality of excitation vectors of the target module can be obtained and stored in advance by the foregoing excitation vector obtaining method, and can be directly called when it is needed to use.

[0092] S220: Convert the excitation vector file into an excitation waveform signal based on a preset clock signal.

[0093] Optionally, the excitation vector file can be converted into the excitation waveform signal based on the preset clock signal in the following manner: each excitation vector included in the excitation vector file is read in a sampling order. For each excitation vector read, each port signal value recorded in the excitation vector is assigned to a clock period of the corresponding excitation waveform signal (if the excitation vector is obtained by double-edge sampling, the assignment is performed for a half clock period). The operation of reading the excitation vector and assigning is repeated, so that the excitation vector file can be converted into the excitation waveform signal.

[0094] S230: Input the excitation waveform signal into the target module and the improved target module respectively, and obtain a first output signal of the target module and a second output signal of the improved target module respectively.

[0095] The improved target module is a module obtained by improving the structure of the target module.

[0096] In the case where the target module includes a plurality of input ports, the excitation waveform signal also includes a plurality of excitation waveform signals. Therefore, each excitation waveform signal is input into the corresponding input port.

[0097] Optionally, inputting the excitation waveform signal into the target module and the improved target module respectively means that the excitation waveform signal is input as an input signal of the original code (such as RTL code) corresponding to the target module and the improved target module respectively.

[0098] S240: Compare the first output signal and the second output signal to obtain a comparison result.

[0099] In the case where the first output signal and the second output signal are the same, it indicates that the improved target module and the target module implement the same function.

[0100] In the case that the first output signal and the second output signal are different, it indicates that the improved target module cannot realize the function of the target module.

[0101] Since the improved target module is the improved target module, the functions realized by the two modules in the specified module should be the same. That is, the outputs of the two modules should be consistent in the case that the input control signals are the same. Based on this, the unimproved target module can be taken as the reference model of the improved target module, so that the engineers do not need to manually develop the reference model of the improved target module, thereby reducing the workload of the engineers. Moreover, by this way, the simulation test on the improved target module can be directly realized without putting the improved target module into the specified module to test the specified module. Compared with the way of testing the specified module to realize the test on the improved target module, the present scheme can reduce the time required for the test.

[0102] Based on the same technical concept, the present application further provides an excitation vector acquisition device, as shown in the figure, which comprises a first acquisition module 110 and a processing module 120. Figure 8 The first acquisition module 110 is used for acquiring all waveform files obtained by simulating and testing the specified module.

[0103] The first acquisition module 110 is used for acquiring all waveform files obtained by simulating and testing the specified module.

[0104] The processing module 120 is used for determining the waveform files of the target port signals from the all waveform files; the target port is the port of the target module, and the target module is a lower-level module included in the specified module; for each clock cycle, the port signal values of all the waveform files of the target port signals in the clock cycle are acquired to obtain an excitation vector; the excitation vector comprises the signal values of all the target ports at the same time, and the excitation vector is used for simulating and testing the target module.

[0105] After the waveform files of the target port signals are determined from the all waveform files, the processing module 120 is further used for cutting all the waveform files of the target port signals to remove the invalid contents in the waveform files to obtain the effective waveform files of all the target port signals; wherein the invalid contents are the contents corresponding to the time periods during which the target module does not run in the waveform files; for each clock cycle, the port signal values of all the effective waveform files in the clock cycle are acquired to obtain the excitation vector.

[0106] The processing module 120 is specifically configured to clip all waveform files of the target port signals according to preset start time and end time, to obtain effective waveform files of all the target port signals; wherein the effective waveform file is a waveform file after the content before the start time and the content after the end time are clipped.

[0107] The invalid content includes multiple segments, and different segments of invalid content correspond to different time ranges; the processing module 120 is specifically configured to, for the waveform file of each target port signal: clip the waveform file to remove all invalid content in the waveform file, to obtain multiple valid content segments; and splice the multiple valid content segments to obtain the effective waveform file corresponding to the target port signal.

[0108] The processing module 120 is specifically configured to, for each clock cycle, sample the waveform signal included in the clock cycle of all waveform files of the target port signals at the clock rising edge and / or falling edge, to obtain the port signal value corresponding to each waveform file of the target port signal in the clock cycle.

[0109] The processing module 120 is specifically configured to, for each clock cycle: oversample the waveform signal included in the clock cycle of all waveform files of the target port signals at the clock rising edge or falling edge, to obtain multiple initial port signal value groups, wherein each initial port signal value group includes the sampling value corresponding to each target port signal obtained by one sampling; and determine one initial port signal value group from the multiple initial port signal value groups as the port signal value corresponding to each waveform file of the target port signal in the clock cycle.

[0110] The processing module 120 is specifically configured to, for each clock cycle: oversample the waveform signal included in the clock cycle of all waveform files of the target port signals at the clock rising edge, to obtain multiple initial rising edge port signal value groups, wherein each initial rising edge port signal value group includes the sampling value corresponding to each target port signal obtained by one rising edge sampling; and oversample the waveform signal included in the clock cycle of all waveform files of the target port signals at the clock falling edge, to obtain multiple initial falling edge port signal value groups, wherein each initial falling edge port signal value group includes the sampling value corresponding to each target port signal obtained by one falling edge sampling; and determine one initial rising edge port signal value group and one initial falling edge port signal value group from the multiple initial rising edge port signal value groups and the multiple initial falling edge port signal value groups, respectively, as the port signal value corresponding to each waveform file of the target port signal in the clock cycle.

[0111] The implementation principle and the technical effects of the excitation vector obtaining apparatus 100 provided in the embodiments of the present application are the same as those of the foregoing excitation vector obtaining method embodiments. For brief description, the part of the apparatus embodiments not mentioned can be referred to the corresponding content in the foregoing excitation vector obtaining method embodiments.

[0112] Based on the same technical concept, the present application further provides a simulation test apparatus, as shown in the accompanying drawings, the simulation test apparatus 200 comprises a second obtaining module 210, a test signal generating module 220 and an output result comparing module 230. Figure 9

[0113] The second obtaining module 210 is configured to obtain an excitation vector file, wherein the excitation vector file comprises a plurality of excitation vectors, and each excitation vector is an excitation vector obtained according to the foregoing excitation vector obtaining method.

[0114] The test signal generating module 220 is configured to convert the excitation vector file into an excitation waveform signal based on a preset clock signal; input the excitation waveform signal into the target module and an improved target module respectively to obtain a first output signal of the target module and a second output signal of the improved target module respectively; and wherein the improved target module is a module obtained by improving the structure of the target module.

[0115] The output result comparing module 230 is configured to compare the first output signal and the second output signal to obtain a comparison result; and wherein in the case that the first output signal and the second output signal are the same, it indicates that the improved target module and the target module realize the same function.

[0116] Optionally, the simulation test apparatus can be a test platform built.

[0117] The implementation principle and the technical effects of the simulation test apparatus 200 provided in the embodiments of the present application are the same as those of the foregoing simulation test method embodiments. For brief description, the part of the apparatus embodiments not mentioned can be referred to the corresponding content in the foregoing simulation test method embodiments.

[0118] Please refer to Figure 10 , which is an electronic device 300 provided in the embodiments of the present application. The electronic device 300 comprises a processor 310 and a memory 320.

[0119] The memory 320 and the processor 310 are electrically connected with each other directly or indirectly to realize the transmission or interaction of data. For example, these elements can be electrically connected with each other through one or more communication buses or signal lines. Among them, the memory 320 is configured to store a computer program, such as storing an Figure 8 ​The software functional module shown is the excitation vector acquisition device 100; or it stores... Figure 9 The software functional modules shown are the simulation test device 200.

[0120] The excitation vector acquisition device 100 or simulation test device 200 includes at least one software function module that can be stored in the memory 320 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 300.

[0121] The processor 310 is used to execute executable modules stored in the memory 320, such as software function modules or computer programs included in the excitation vector acquisition device 100. At this time, the processor 310 is used to acquire all waveform files obtained from simulating a specified module; determine the waveform file of the target port signal from all the waveform files; the target port is a port of the target module, and the target module is a lower-level module included within the specified module; for each clock cycle, acquire the port signal values ​​of all the waveform files of the target port signals in that clock cycle to obtain an excitation vector; the excitation vector includes the signal values ​​of all the target ports at the same time, and the excitation vector is used to simulate the target module.

[0122] The processor 310 is used to execute executable modules stored in the memory 320, such as software function modules or computer programs included in the simulation test device 200. At this time, the processor 310 is used to acquire an excitation vector file, which includes multiple excitation vectors, each of which is an excitation vector obtained according to the aforementioned excitation vector acquisition method; based on a preset clock signal, the processor 310 converts the excitation vector file into an excitation waveform signal; the processor 310 inputs the excitation waveform signal into the target module and the improved target module respectively, to obtain a first output signal of the target module and a second output signal of the improved target module respectively; wherein, the improved target module is a module obtained by structurally improving the target module; the processor 310 compares the first output signal and the second output signal to obtain a comparison result; wherein, if the first output signal and the second output signal are the same, it indicates that the improved target module performs the same function as the target module.

[0123] The memory 320 can be, but is not limited to, a RAM (Random Access Memory), a ROM (Read Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electric Erasable Programmable Read-Only Memory), and the like.

[0124] The processor 310 can be an integrated circuit chip having a processing capability of signals. The processor can be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), and the like; or a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The processor can implement or execute the disclosed methods, steps, and logic block diagrams in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor 310 can also be any conventional processor.

[0125] The electronic device 300 can include, but is not limited to, a personal computer, a server, and the like.

[0126] The embodiments of the present application also provide a computer readable storage medium (hereinafter referred to as a storage medium) having a computer program stored thereon. When the computer program is run by a computer such as the electronic device 300, the above-described excitation vector acquisition method is executed. The computer readable storage medium includes a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and the like.

[0127] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for obtaining an excitation vector, characterized by, The method comprises the following steps: acquiring all waveform files obtained by simulating and testing a specified module; determining waveform files of target port signals from the all waveform files; the target port is a port of a target module, and the target module is a lower-level module included in the specified module; for each clock cycle, acquiring port signal values of the all waveform files of the target port signals in the clock cycle to obtain an excitation vector; the excitation vector comprises signal values of the all target ports at the same time, and the excitation vector is used for simulating and testing the target module.

2. The method of claim 1, wherein, After the waveform files of the target port signals are determined from the all waveform files, the method further comprises the following steps: trimming the all waveform files of the target port signals to remove invalid contents in the waveform files to obtain valid waveform files of the all target port signals; wherein the invalid contents are contents corresponding to time periods in which the target module does not run in the waveform files; correspondingly, for each clock cycle, acquiring port signal values of the all waveform files of the target port signals in the clock cycle to obtain an excitation vector, comprising: for each clock cycle, acquiring port signal values of the all valid waveform files in the clock cycle to obtain the excitation vector.

3. The method of claim 2, wherein, trimming the all waveform files of the target port signals to remove invalid contents in the waveform files to obtain valid waveform files of the all target port signals, comprising: trimming the all waveform files of the target port signals according to preset start time and end time to obtain valid waveform files of the all target port signals; wherein the valid waveform files are waveform files after contents before the start time and contents after the end time are trimmed from the waveform files.

4. The method of claim 2, wherein, the invalid contents comprise multiple segments, and different segments of the invalid contents correspond to different time ranges; trimming the all waveform files of the target port signals to remove invalid contents in the waveform files to obtain valid waveform files of the all target port signals, comprising: for each waveform file of the target port signals: trimming the waveform file to remove all invalid contents in the waveform file to obtain multiple valid content segments; splicing the multiple valid content segments to obtain a valid waveform file corresponding to the target port signal.

5. The method of claim 1, wherein, for each clock cycle, acquiring port signal values of the all waveform files of the target port signals in the clock cycle, comprising: for each clock cycle, performing clock rising edge and / or falling edge sampling on waveform signals included in the all waveform files of the target port signals in the clock cycle to obtain port signal values corresponding to each of the target port signals in the clock cycle.

6. The method of claim 5, wherein, for each clock cycle, performing clock rising edge or falling edge sampling on waveform signals included in the all waveform files of the target port signals in the clock cycle to obtain port signal values corresponding to each of the target port signals in the clock cycle, comprising: for each clock cycle: The waveform file of each target port signal is clocked up or down sampled at the rising or falling edge of the clock signal included in the clock cycle, to obtain a plurality of initial port signal value groups, wherein each initial port signal value group includes a sample value corresponding to each target port signal obtained by one sampling; From the plurality of initial port signal value groups, an initial port signal value group is determined as the port signal value corresponding to the waveform file of each target port signal in the clock cycle.

7. The method of claim 5, wherein, For each clock cycle, the waveform signal included in the waveform file of each target port signal in the clock cycle is clocked up and down sampled, to obtain the port signal value corresponding to the waveform file of each target port signal in the clock cycle, including: For each clock cycle: The waveform signal included in the waveform file of each target port signal in the clock cycle is clocked up sampled at the rising edge of the clock signal, to obtain a plurality of initial rising edge port signal value groups, wherein each initial rising edge port signal value group includes a sample value corresponding to each target port signal obtained by one rising edge sampling; The waveform signal included in the waveform file of each target port signal in the clock cycle is clocked down sampled at the falling edge of the clock signal, to obtain a plurality of initial falling edge port signal value groups, wherein each initial falling edge port signal value group includes a sample value corresponding to each target port signal obtained by one falling edge sampling; From the plurality of initial rising edge port signal value groups and the plurality of initial falling edge port signal value groups, an initial rising edge port signal value group and an initial falling edge port signal value group are respectively determined as the port signal value corresponding to the waveform file of each target port signal in the clock cycle.

8. A method of emulation testing, characterized by, It includes: Obtain an excitation vector file, wherein the excitation vector file includes a plurality of excitation vectors, and each excitation vector is obtained by the method according to any one of claims 1-7; Convert the excitation vector file into an excitation waveform signal based on a preset clock signal; Input the excitation waveform signal into the target module and the improved target module respectively, to obtain a first output signal of the target module and a second output signal of the improved target module respectively; wherein the improved target module is a module obtained by improving the structure of the target module; Compare the first output signal and the second output signal to obtain a comparison result; wherein in the case that the first output signal and the second output signal are the same, it indicates that the improved target module and the target module realize the same function.

9. An excitation vector acquisition device, characterized in that, It includes: A first obtaining module is configured to obtain all waveform files obtained by simulating and testing a specified module; A processing module is configured to determine a waveform file of a target port signal from the all waveform files; The target port is a port of a target module, and the target module is a lower-level module included in the specified module; for each clock cycle, a waveform file of all the target port signals is obtained to obtain a stimulus vector, the stimulus vector including signal values of all the target ports at the same time, and the stimulus vector being used for simulation testing of the target module.

10. An emulation test apparatus, characterized by, The method comprises the following steps: The second obtaining module is configured to obtain a stimulus vector file, the stimulus vector file including a plurality of stimulus vectors, each stimulus vector being obtained according to the method in any one of claims 1-7; The test signal generation module is configured to convert the stimulus vector file into a stimulus waveform signal based on a preset clock signal, input the stimulus waveform signal into the target module and an improved target module respectively to obtain a first output signal of the target module and a second output signal of the improved target module respectively, and compare the first output signal and the second output signal to obtain a comparison result, wherein the improved target module is a module obtained by improving the structure of the target module. The output result comparison module is configured to compare the first output signal and the second output signal to obtain a comparison result, wherein in the case that the first output signal and the second output signal are the same, it is indicated that the improved target module and the target module have the same function.

11. An electronic device, comprising: The method comprises the following steps: A memory and a processor are connected; The memory is configured to store a program; The processor is configured to call the program stored in the memory to execute the method in any one of claims 1-7 or execute the method in claim 8.

12. A computer-readable storage medium, characterized in that, A computer program is stored on the computer, and when the computer program is run by the computer, the method in any one of claims 1-7 is executed or the method in claim 8 is executed.

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