Method for checking design rules of chip layout and related equipment

Abstract

This application belongs to the field of semiconductor design automation technology, and proposes a method and related equipment for chip layout design rule checking. The method includes: acquiring a chip layout to be processed, including at least one pattern layer; acquiring the process rule spacing of a target pattern layer in the chip layout, and the factor weights of the target pattern layer on multiple process risk factors, wherein the process rule spacing is the minimum pattern spacing to meet process production requirements, and the factor weights characterize the degree of interference of the corresponding process risk factors on chip manufacturing; based on the process rule spacing, the factor weights, and the actual spacing between each adjacent pattern in the target pattern layer, calling a conflict quantification model to calculate the conflict risk value of each adjacent pattern in the target pattern layer; and performing design rule checking on the target pattern layer based on the conflict risk values. The technical solution provided by this application can improve the accuracy of chip layout design verification.

Description

Technical Field

[0001] This application belongs to the field of semiconductor design automation technology, and in particular relates to a method and related equipment for checking chip layout design rules. Background Technology

[0002] In the field of Electronic Design Automation (EDA), the design quality of chip layout directly determines the performance, yield, and reliability of chip manufacturing. Design rule checking is a critical step in the chip layout design process. Its core purpose is to verify whether the chip layout meets the various requirements of semiconductor process manufacturing and to identify and eliminate design defects that may lead to manufacturing failures in advance.

[0003] Chip layouts consist of multiple pattern layers, and the spacing between adjacent patterns within each layer is one of the core parameters affecting manufacturing feasibility. Traditional design rule checking methods typically use fixed process rule spacing as the judgment standard; that is, when the actual spacing between adjacent patterns is less than the preset process rule spacing, a violation is determined to exist.

[0004] However, with the continuous evolution of semiconductor process nodes, especially after entering advanced process nodes, chip layouts verified by traditional design rule checking methods can still exhibit manufacturing defects such as pattern distortion, short circuits, or open circuits during later chip manufacturing processes, leading to a significant decrease in chip yield. Therefore, improving the accuracy of chip layout design verification has become an urgent technical problem to be solved. Summary of the Invention

[0005] The embodiments of this application provide a method, apparatus, computer program product, computer-readable storage medium, and electronic device for checking chip layout design rules, which can improve the accuracy of chip layout design verification to a certain extent.

[0006] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0007] According to a first aspect of the embodiments of this application, a design rule checking method for a chip layout is provided. The method includes: acquiring a chip layout to be processed, the chip layout including at least one pattern layer; acquiring the process rule spacing of a target pattern layer in the chip layout and the factor weights of the target pattern layer on multiple process risk factors, wherein the process rule spacing is the minimum pattern spacing to satisfy process production, and the factor weights are used to characterize the degree of interference of the corresponding process risk factors on chip manufacturing; based on the process rule spacing, the factor weights, and the actual spacing of each adjacent pattern in the target pattern layer, calling a conflict quantification model to calculate the conflict risk value of each adjacent pattern in the target pattern layer; and performing a design rule check on the target pattern layer based on the conflict risk values ​​of each adjacent pattern in the target pattern layer.

[0008] In some embodiments of this application, based on the foregoing scheme, the conflict quantification model includes:

[0009]

[0010] in, This represents the conflict risk value of any two adjacent figures. The spacing of the process rules for the target graphic layer is quantitative; These respectively represent the target graphics layer in n Factor weights for each process risk factor , for quantitative purposes; The actual spacing between any two adjacent graphics in the target graphic layer is a variable.

[0011] In some embodiments of this application, based on the foregoing scheme, the process risk factors include one or more of the following: lithography risk factors, pattern feature factors, etching deviation factors, deposition deviation factors, and overlay mask error factors.

[0012] In some embodiments of this application, based on the foregoing scheme, if the target graphic layer is applied to a single graphic process, the step of performing a design rule check on the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer includes: obtaining a first risk value threshold set for the target graphic layer; and determining adjacent graphics in the target graphic layer whose conflict risk value exceeds the first risk value threshold as non-compliant graphics.

[0013] In some embodiments of this application, based on the foregoing scheme, if the target graphic layer is applied to a dual graphic process, the step of performing a design rule check on the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer includes: obtaining a second risk value threshold set for the target graphic layer, and defining adjacent graphics in the target graphic layer whose conflict risk value exceeds the second risk value threshold as conflict graphic pairs; constructing a conflict graph in the target graphic layer with graphics in the conflict graphic pairs as nodes and conflict relationships between graphics as connecting edges; detecting odd cycles in the conflict graph, and determining the graphics corresponding to the odd cycles as violation graphics, wherein the odd cycle is a closed loop formed by sequentially associating an odd number of graphics through connecting edges.

[0014] In some embodiments of this application, based on the foregoing scheme, the method further includes: dividing the target graphic layer into multiple first regions with similar numbers of odd rings, wherein the number of odd rings in each first region is less than or equal to a predetermined number; dividing each first region into at least two second regions of similar size, and defining the second regions as correction regions. Odd rings in the multiple correction regions are resolved in parallel, and the process returns to the step of calling the conflict quantization model to calculate the conflict risk value of each adjacent graphic in the target graphic layer, until no odd rings remain in the conflict graph.

[0015] In some embodiments of this application, based on the foregoing scheme, dividing the target graphic layer into multiple first regions with similar numbers of odd rings includes: sequentially traversing untraversed grid regions in the target graphic layer according to a set traversal order; each time the current grid region is traversed, counting the total number of odd rings in the traversed grid regions; if the total number of odd rings exceeds a set number, marking the traversed grid regions before traversing the current grid region as a first region, and resetting the traversed grid regions and the total number of odd rings; taking the current grid region as the first untraversed grid region, repeating the traversal process of the grid regions until all grid regions have been traversed.

[0016] In some embodiments of this application, based on the foregoing scheme, eliminating odd rings in the correction region includes: determining at least one target connecting edge to be eliminated in the correction region; performing shifting and / or cutting processing on one of the graphics associated with each target connecting edge to eliminate the odd ring to which each target connecting edge belongs.

[0017] In some embodiments of this application, based on the foregoing scheme, determining at least one target connecting edge to be resolved in the correction region includes: traversing each connecting edge in the correction region and recording the correspondence between each connecting edge and its corresponding odd cycle in a temporary table; counting the connecting edge with the most odd cycles in the temporary table as a pending connecting edge, and determining the pending connecting edge as a target connecting edge to be resolved; hiding the odd cycle to which the pending connecting edge belongs in the temporary table, and returning to the step of counting the connecting edge with the most odd cycles in the temporary table, until all the odd cycles recorded in the temporary table are hidden.

[0018] According to a second aspect of the embodiments of this application, a chip layout design rule checking apparatus is provided. The apparatus includes: a first acquisition unit, configured to acquire a chip layout to be processed, the chip layout including at least one pattern layer; a second acquisition unit, configured to acquire the process rule spacing of a target pattern layer in the chip layout and the factor weights of the target pattern layer on multiple process risk factors, wherein the process rule spacing is the minimum pattern spacing to satisfy process production, and the factor weights are used to characterize the degree of interference of the corresponding process risk factors on chip manufacturing; a calling unit, configured to call a conflict quantification model to calculate the conflict risk value of each adjacent pattern in the target pattern layer based on the process rule spacing, the factor weights, and the actual spacing of each adjacent pattern in the target pattern layer; and a checking unit, configured to perform design rule checking on the target pattern layer based on the conflict risk values ​​of each adjacent pattern in the target pattern layer.

[0019] According to a third aspect of the embodiments of this application, a computer program product is provided, the computer program product including computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the operations performed by the method described in the first aspect above.

[0020] According to a fourth aspect of the present application, a computer-readable storage medium is provided, wherein at least one computer program instruction is stored therein, the at least one computer program instruction being loaded and executed by a processor to perform the operation as described in the first aspect above.

[0021] According to a fifth aspect of the present application, an electronic device is provided, the electronic device including one or more processors and one or more memories, the one or more memories storing at least one computer program instruction, the at least one computer program instruction being loaded and executed by the one or more processors to perform the operation as described in the first aspect above.

[0022] Based on the technical solution proposed in this application, this method overcomes the limitations of traditional methods that rely solely on binary judgments based on fixed process rule spacing. By integrating process rule spacing, multi-process risk factor weights, and actual spacing between adjacent patterns through a conflict quantification model, it replaces the traditional compliance or non-compliance judgment with a quantified risk value. This approach fully considers the interference of various process risk factors, achieving accurate quantitative assessment of the conflict risk of adjacent patterns. It more accurately reflects the risk status in the actual manufacturing process, assisting designers in distinguishing between high-risk and low-risk areas and avoiding risk omissions or over-corrections due to a single judgment standard. This significantly improves the comprehensiveness and accuracy of design rule checks. Furthermore, it is applicable to chip layout checks for various process types and different process nodes, exhibiting good versatility and adaptability. This broadens the application scope of design rule checking methods. The entire check process is logically clear and the steps are well-defined, allowing for seamless integration with existing electronic design automation (EDA) workflows, facilitating engineering applications. Through accurate conflict risk assessment and comprehensive violation identification, it can eliminate more potential manufacturing defects in advance, reducing the probability of failures in the chip manufacturing process and significantly improving chip manufacturing yield.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0025] Figure 1 A flowchart of a chip layout design rule checking method according to an embodiment of this application is shown;

[0026] Figure 2 This illustration shows a schematic diagram of the target graphic layer in the chip layout of an embodiment of this application;

[0027] Figure 3 This illustration shows a schematic diagram of the target graphic layer in the chip layout of an embodiment of this application;

[0028] Figure 4 This illustration shows a schematic diagram of the target graphic layer in the chip layout of an embodiment of this application;

[0029] Figure 5 A block diagram of a chip layout design rule checking device according to an embodiment of this application is shown;

[0030] Figure 6A schematic diagram of the structure of an electronic device in an embodiment of this application is shown. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices. It should also be noted that, for the sake of simplicity, certain components in the drawings that do not affect the interpretation of the technical solution of this application have been appropriately omitted.

[0034] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0035] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0036] To enable those skilled in the art to better understand this application, a brief explanation of the technical concepts and application background involved in this application will be given first.

[0037] Integrated Circuit (IC): An integrated circuit, also known as a microchip or chip, is a miniature electronic device that uses semiconductor manufacturing processes (such as photolithography, etching, doping, deposition, etc.) to fabricate a large number of electronic components such as transistors, diodes, resistors, capacitors, and inductors, as well as the interconnection lines between these components, onto one or more semiconductor wafers (usually silicon wafers), insulating substrates, or other carriers, and then encapsulates them in a housing to form a miniature electronic device with specific circuit functions.

[0038] Chip Layout: Also known as chip physical layout, chip layout is the core intermediate carrier in the semiconductor chip design process, transitioning from logic design to physical manufacturing. It transforms the chip's logic functions and circuit structure into a two-dimensional / three-dimensional graphical description file that meets the requirements of semiconductor process manufacturing. It is also the direct basis for chip manufacturing, packaging, and testing.

[0039] Design Rule Check (DRC): Design rule check is a core verification step in the semiconductor chip design automation process. Its core purpose is to comprehensively verify the physical design of the chip layout according to the production requirements of specific semiconductor processes, identify and eliminate design defects that may lead to manufacturing failure, performance degradation or reliability reduction in advance, and ensure that the chip layout can adapt to the actual manufacturing process, thus guaranteeing the manufacturability, yield and stability of the chip.

[0040] Currently, with the continuous evolution of semiconductor process nodes, especially after entering advanced process nodes, chip layouts that have been verified by traditional design rule checking methods may still have manufacturing defects such as pattern distortion, short circuits or open circuits during the later chip production process, resulting in a significant drop in chip yield.

[0041] The inventors of this application have discovered that traditional design rule checking methods rely solely on fixed process rule spacing as the basis for judgment, ignoring the interference of various process risk factors on chip manufacturing. They fail to design differentiated checking logic for single-pattern and dual-pattern processes, and the binary "compliant / non-compliant" judgment logic cannot quantitatively assess the conflict risk of adjacent patterns. Furthermore, they lack a scientific screening mechanism in handling odd rings in dual-pattern processes, resulting in low efficiency in odd ring resolution and a high risk of initiating new conflicts. Therefore, this application proposes a chip layout design rule checking scheme to meet the high precision, comprehensiveness, and process adaptability requirements of advanced semiconductor processes for chip layout design verification.

[0042] The implementation details of the technical solutions in the embodiments of this application are described below:

[0043] Reference Figure 1The diagram illustrates a flowchart of a chip layout design rule checking method according to an embodiment of this application. This chip layout design rule checking method can be executed by a device with computing processing capabilities. (Refer to...) Figure 1 As shown, the design rule checking method for this chip layout includes at least steps 110 to 140, which are detailed below:

[0044] like Figure 1 In step 110, a chip layout to be processed is obtained, the chip layout including at least one graphics layer.

[0045] In this application, the chip layout to be processed is graphical data formed after the chip design is completed, which includes at least one pattern layer. Each pattern layer can correspond to a physical layer in the chip manufacturing process (such as a metal layer, via layer, dielectric layer, etc.). In the subsequent design rule checking process, the design rule checking method proposed in this application can be executed independently for each pattern layer to ensure that the design of each physical layer meets the corresponding process requirements.

[0046] Continue to refer to Figure 1 In step 120, the process rule spacing of the target pattern layer in the chip layout and the factor weights of the target pattern layer on multiple process risk factors are obtained. The process rule spacing is the minimum pattern spacing to meet the process production requirements, and the factor weights are used to characterize the degree of interference of the corresponding process risk factors on chip manufacturing.

[0047] In this application, the process rule spacing can be the minimum pattern spacing required for a specific semiconductor process, and is a quantitative parameter determined based on factors such as equipment capabilities, material properties, and manufacturing processes of the specific semiconductor process. The process rule spacing varies between different process nodes and different pattern layers. For example, the metal layer process rule spacing for a 14nm process may be 0.12μm, while the metal layer process rule spacing for a 7nm process may be 0.08μm.

[0048] In this application, the factor weights are used to characterize the degree of interference of each process risk factor on chip manufacturing, and are quantitative parameters. Process risk factors are key factors affecting chip manufacturing performance, and can be pre-set according to specific process types and manufacturing requirements.

[0049] In this application, the process risk factors may include one or more of the following: lithography risk factors, pattern feature factors, etching deviation factors, deposition deviation factors, and overlay mask error factors. Each risk factor corresponds to a weight value, and the larger the weight value, the greater the degree of interference of the factor with the manufacturing process.

[0050] In this application, different process risk factors can interfere with the actual manufacturing effect of the spacing between adjacent patterns from different perspectives. Specific details are as follows:

[0051] The risk factor of photolithography can characterize the risk of pattern distortion caused by factors such as light source characteristics, photoresist performance, and exposure dose control in the photolithography process. The photolithography process is a key step in transferring the layout pattern onto the wafer. Pattern distortion will directly cause the actual pattern spacing to deviate from the design spacing.

[0052] The graphic feature factor can characterize the influence of the graphic characteristics of each graphic layer in the chip layout (such as graphic size, shape, density, etc., or metal layers, via layers, etc.) on manufacturing. For example, high-density fine-line graphics are more likely to deform during manufacturing, resulting in spacing deviation.

[0053] The etching deviation factor can characterize the risks such as pattern sidewall tilting and linewidth deviation caused by factors such as uneven etching rate and insufficient mask selectivity in the etching process. The etching process is used to transfer the pattern formed by photolithography to the underlying material, and the deviation will affect the actual spacing between adjacent patterns.

[0054] The deposition deviation factor can characterize the pattern height deviation caused by factors such as uneven film deposition rate and poor thickness consistency in the deposition process, which in turn affects the insulation performance or connection reliability between adjacent patterns and indirectly affects the manufacturing effect related to spacing.

[0055] The mask stacking error factor can characterize the alignment error risk in the process of stacking multiple masks. Especially in processes that require multiple mask exposures, such as dual patterning processes, alignment errors will directly lead to deviations in pattern spacing and cause manufacturing conflicts.

[0056] Continue to refer to Figure 1 In step 130, based on the process rule spacing, the factor weight, and the actual spacing between each adjacent graphic in the target graphic layer, the conflict quantification model is invoked to calculate the conflict risk value of each adjacent graphic in the target graphic layer.

[0057] In this application, the conflict risk value of each adjacent graphic can be calculated by calling the conflict quantification model based on the obtained process rule spacing, factor weights, and the actual spacing of each adjacent graphic in the target graphic layer. This conflict quantification model can fully integrate the influence of process rule requirements and multiple process risk factors, and can accurately reflect the risk level of conflicts (such as short circuits, open circuits, etc.) that occur between adjacent graphics in the actual manufacturing process.

[0058] Specifically, in this application, the conflict quantification model can be as shown in formula (1):

[0059] (1)

[0060] in, This represents the conflict risk value of any two adjacent figures. The spacing of the process rules for the target graphic layer is quantitative; These respectively represent the target graphics layer in n Factor weights for each process risk factor , for quantitative purposes; The actual spacing between any two adjacent graphics in the target graphic layer is a variable.

[0061] In practical applications, one or more process risk factors can be selected and incorporated into the conflict quantification model based on the type of the target pattern layer in the chip layout and / or the specific semiconductor process type and manufacturing requirements, to ensure that the model can accurately reflect the risk situation in the actual manufacturing process.

[0062] For example, for a metal layer in a certain 10nm advanced process, the pattern density of this process is high, the photolithography and etching processes are difficult, and the thickness uniformity of the deposition process has a significant impact on the insulation performance between metal lines. Therefore, four process risk factors can be selected: photolithography risk factor, etching deviation factor, deposition deviation factor, and pattern feature factor. Based on the actual manufacturing data of this process, the factor weights are set to K1=0.15, K2=0.15, K3=0.08, and K4=0.05, respectively, to comprehensively cover the main manufacturing risks.

[0063] For example, for the dielectric layer of a mature 28nm single-pattern process, the lithography and etching processes are relatively stable. The main risk comes from the superposition mask error. Therefore, only the superposition mask error factor can be selected as the process risk factor. The factor weight K1=0.15 is set to simplify the inspection model while ensuring that the core risks are taken into account.

[0064] For example, the fabrication of doped layers mainly involves photolithography and ion implantation processes. Pattern features (such as the size and shape of the doped region) have a significant impact on the uniformity of doping concentration. Therefore, photolithography risk factors and pattern feature factors can be selected as process risk factors.

[0065] For example, the manufacturing of via layers mainly involves deposition, photolithography, etching, and multiple mask stacking processes, which involve many risk factors. Therefore, photolithography risk factor, etching deviation factor, deposition deviation factor, and stacking mask error factor can be selected as process risk factors.

[0066] Based on the above scheme, the specific types of major process risk factors in each key link of semiconductor manufacturing are clarified. These process risk factors have clear physical meanings and are closely integrated with the actual process principles of semiconductor manufacturing. They can comprehensively reflect the manufacturing risk characteristics of different processes and different pattern layers, ensuring the comprehensiveness of conflict risk assessment. At the same time, they support flexible combination and selection of process risk factors. Designers can select a single risk factor to simplify the model for simple processes or select multiple risk factors for comprehensive assessment for complex processes according to actual process requirements. This effectively balances assessment accuracy and computational efficiency, making the technical solution of this application more operable.

[0067] In this application, the conflict quantification model can be partially implemented using an exponential function. The process rule spacing comprehensively reflects the combined interference effects of process rule requirements and multiple process risk factors. A larger value indicates a more lenient requirement for spacing in the process, and a lower baseline risk value; while the weight of each process risk factor... The larger, The larger the value, the larger the result of the exponential part, and the higher the base risk value. Then, subtract the actual distance between adjacent graphs. The impact of actual spacing can be incorporated into the risk assessment; actual spacing The smaller the value, the denser the adjacent figures, and the higher the risk of conflict.

[0068] To enable those skilled in the art to better understand the conflict quantification model shown in formula (1) above, the following explanation is provided in conjunction with several specific embodiments:

[0069] In one embodiment of this application, it is assumed that the process rule spacing of a certain graphic layer is... The actual spacing between adjacent figures Two process risk factors were selected.

[0070] When factor weights , hour, ;

[0071] When factor weights , hour, .

[0072] It is evident that, when the process rule spacing and the actual spacing are the same, the greater the weight of the process risk factor (the higher the degree of interference), the greater the conflict risk value, which can accurately reflect the influence of process risk factors on manufacturing conflict risk.

[0073] In another embodiment of this application, it is assumed that the process rule spacing of a certain graphic layer is... Two process risk factors were selected, with the following weights: , .

[0074] When the actual spacing hour, ;

[0075] When the actual spacing hour, .

[0076] It is evident that, with the same process rule spacing and factor weights, the smaller the actual spacing between adjacent graphics, the greater the conflict risk value, which aligns with the reality that smaller spacing makes manufacturing conflicts more likely to occur.

[0077] In this application, based on the aforementioned conflict quantification model, the exponential function can achieve nonlinear superposition of risk factors, which can more accurately reflect the impact of the interaction between various factors on conflict risk. Compared with the linear model, it has higher evaluation accuracy. At the same time, it can accurately quantify the comprehensive impact of process rule spacing, multi-process risk factor weights, and actual spacing between adjacent patterns on conflict risk. The quantification results are strongly correlated with actual manufacturing risks, and all parameters in the model can be flexibly configured according to specific process characteristics, which can adapt to the inspection needs of different process nodes and different pattern layers. It has good flexibility and scalability. In addition, the model calculation process is simple and can quickly complete the calculation of conflict risk values ​​of a large number of adjacent patterns, which can meet the high efficiency requirements of chip layout design rule inspection.

[0078] Continue to refer to Figure 1 In step 140, the target graphic layer is subjected to design rule checks based on the conflict risk values ​​of each adjacent graphic in the target graphic layer.

[0079] In this application, based on the process type (single-pattern process or dual-pattern process) applied to the target graphic layer and combined with the conflict risk values ​​of each adjacent graphic, a corresponding design rule check process can be executed to identify and correct non-compliant graphics. Since the manufacturing principles and requirements of different process types vary, differentiated check logic can be designed to ensure the accuracy and applicability of the check results.

[0080] Based on the technical solutions in steps 110 to 140 above, this method overcomes the limitations of traditional methods that rely solely on fixed process rule spacing for binary judgment. By integrating process rule spacing, multi-process risk factor weights, and actual spacing between adjacent patterns through a conflict quantification model, it replaces the traditional compliance or non-compliance judgment with a quantified risk value. This approach fully considers the interference of various process risk factors, achieving accurate quantitative assessment of the conflict risk of adjacent patterns. It more accurately reflects the risk status in the actual manufacturing process, assisting designers in distinguishing between high-risk and low-risk areas, avoiding risk omissions or over-corrections due to a single judgment standard, and significantly improving the comprehensiveness and accuracy of design rule checks. Furthermore, it is applicable to chip layout checks for various process types and different process nodes, exhibiting good versatility and adaptability. This broadens the application scope of design rule checking methods, and the entire inspection process is logically clear and the steps are well-defined. It can be seamlessly integrated with existing electronic design automation processes, facilitating engineering applications. Through accurate conflict risk assessment and comprehensive violation identification, it can eliminate more potential manufacturing defects in advance, reduce the probability of failures in the chip manufacturing process, and significantly improve chip manufacturing yield.

[0081] In this application, if the target graphic layer is applied to a single graphic process, the step of performing a design rule check on the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer can be performed according to the following steps 141 to 142:

[0082] Step 141: Obtain the first risk value threshold set for the target graphics layer.

[0083] Step 142: Identify adjacent graphics in the target graphic layer whose conflict risk value exceeds the first risk value threshold as violation graphics.

[0084] In this application, single-pattern technology is a relatively basic process type in semiconductor manufacturing, and its design rule checking process is relatively straightforward. First, a first risk threshold needs to be pre-set based on the specific requirements of the single-pattern process, chip reliability standards, and manufacturing experience. This threshold is the key standard for determining whether adjacent patterns are non-compliant patterns. Setting the first risk threshold requires comprehensive consideration of factors such as process stability and chip application scenarios to ensure that high-risk patterns that may lead to manufacturing defects are effectively identified without over-correction due to an excessively low threshold, which would affect design efficiency. Then, the conflict risk values ​​of each adjacent pattern in the target pattern layer, calculated using a conflict quantification model, are compared with the first risk threshold. If the conflict risk value exceeds the threshold, it indicates a high probability of conflict during manufacturing, potentially leading to manufacturing defects such as short circuits or open circuits. Therefore, it is identified as a non-compliant pattern, and designers can perform corrections such as spacing adjustments for these non-compliant patterns.

[0085] In this application, for example, the first risk value threshold can be set to 0, -0.001, or 0.01. The setting of this threshold needs to balance design efficiency and manufacturing reliability. A threshold that is too high may lead to the omission of high-risk points, affecting chip yield. A threshold that is too low may result in too many violation patterns, increasing the workload of designers and reducing design efficiency. It is understood that the first risk value threshold can be set according to actual circumstances, and this application does not impose excessive restrictions on it.

[0086] In this application, after obtaining the first risk value threshold set for the target graphic layer, the conflict risk value of all adjacent graphics in the target graphic layer can be compared with the first risk value threshold. If the conflict risk value of an adjacent graphic exceeds the first risk value threshold, the adjacent graphic is directly identified as a violation graphic. Designers can correct these violation graphics by adjusting the graphic position to increase the actual spacing, optimizing the graphic shape, etc., to reduce the conflict risk.

[0087] To enable those skilled in the art to better understand steps 141 to 142 above, the following will be combined with... Figure 2 The following is an illustration using a specific example.

[0088] See Figure 2 This shows a schematic diagram of the target graphic layer in the chip layout of an embodiment of this application.

[0089] like Figure 2 As shown, assuming the target graphic layer is applied to a single graphic process, the conflict risk values ​​of each adjacent graphic are shown in Table 1 below.

[0090] Table 1. Example Table of Conflict Risk Values ​​for Adjacent Figures

[0091]

[0092] In this embodiment, assuming the first risk value threshold is set to 0, then based on Table 1, the violation graphics in the target graphics layer can be determined as follows: AB, AF, AG, AH, BC, BH, CD, DE, DG, EF, EG.

[0093] Based on the technical solutions in steps 141 to 142 above, a simple and efficient inspection process is designed for the characteristics of single-pattern processes. It directly determines the violation pattern based on the comparison between the conflict risk value and the threshold. This method is simple to operate, computationally inefficient, and highly efficient, adapting to the design requirements of single-pattern processes. The first risk value threshold can be flexibly adjusted according to process requirements, balancing design efficiency and manufacturing reliability to meet the quality requirements of different chip products. Furthermore, this method can accurately identify adjacent patterns with high conflict risk in single-pattern processes, eliminating potential manufacturing defects in advance and effectively improving chip manufacturing yield. The identification results of violation patterns are also intuitive, facilitating designers to quickly locate and correct problem areas, reducing design iteration costs.

[0094] In this application, if the target graphic layer is applied to a dual graphic process, the step of performing a design rule check on the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer can be performed according to the following steps 143 to 145:

[0095] Step 143: Obtain the second risk value threshold set for the target graphic layer, and define adjacent graphics in the target graphic layer whose conflict risk value exceeds the second risk value threshold as conflict graphic pairs.

[0096] Step 144: Using the graphics in the conflicting graphic pair as nodes and the conflict relationships between the graphics as connecting edges, construct a conflict graph in the target graphic layer.

[0097] Step 145: Detect odd cycles in the conflict graph and identify the graph corresponding to the odd cycle as a violation graph. The odd cycle is a closed loop formed by sequentially connecting an odd number of graphs through connecting edges.

[0098] In this application, dual patterning is a commonly used technique in advanced semiconductor processes. Its design rule inspection process is relatively complex, with a key focus on identifying odd ring structures. This process achieves smaller pattern spacing by splitting a single-layer pattern onto two masks for separate exposure, but it places stricter requirements on pattern layout. Therefore, a second risk threshold needs to be set separately for its characteristics. This threshold differs from the first risk threshold of the single patterning process and needs to be adjusted in conjunction with factors such as mask splitting requirements and alignment accuracy of the dual patterning process, fully considering the additional risks brought about by multiple mask stacking and pattern splitting.

[0099] In the design rule check of the dual-graphics process, adjacent graphics in the target graphics layer whose conflict risk value exceeds the second risk value threshold are first defined as conflicting graphics pairs. These graphics pairs have a high conflict risk during manufacturing and are the basis for constructing the conflict graph. Then, each graphic in the conflicting graphics pair is used as a node, and the conflict relationship between the graphics is used as a connecting edge to construct a conflict graph in the target graphics layer. This conflict graph, as an abstract graphical representation, can intuitively reflect the relationship between each conflicting graphic. Finally, odd cycles are detected in the conflict graph. Odd cycles are closed loops formed by an odd number of graphics connected sequentially through connecting edges. This structure will cause mask splitting failure in the dual-graphics process. Therefore, the graphics corresponding to the odd cycles need to be identified as violation graphics to provide a clear target for subsequent odd cycle resolution.

[0100] To enable those skilled in the art to better understand steps 143 to 145 above, the following will continue to combine... Figure 2 The following is an illustration using a specific example.

[0101] like Figure 2 As shown, assuming the target graphics layer is applied to a dual graphics process, the conflict risk values ​​of each adjacent graphics are shown in Table 1 above.

[0102] In this embodiment, assuming the second risk threshold is set to 0, the conflicting graphic pairs in the target graphic layer can be determined based on Table 1 as follows: AB, AF, AG, AH, BC, BH, CD, DE, DG, EF, EG. Using the graphics in the conflicting graphic pairs as nodes and the conflict relationships between graphics as connecting edges, a conflict graph 200 is constructed in the target graphic layer. It can be seen that the odd cycles included in the conflict graph 200 specifically include: ABHA, ABCDGA, ABCDGEFA, AHBCDEFA, DEGD, DEFAGD.

[0103] Based on the technical solutions in steps 143 to 145 above, and considering the unique characteristics of the dual-pattern process, a violation identification process based on conflict maps and odd ring detection is proposed. This accurately addresses the technical pain point that traditional methods cannot effectively identify odd ring violations in the dual-pattern process. The second risk threshold is set separately according to the characteristics of the dual-pattern process, ensuring the accuracy of conflict map filtering and providing a reliable foundation for subsequent odd ring detection. The construction of the conflict map visualizes the conflict relationships between patterns, facilitating rapid and accurate detection of odd ring structures, significantly improving the efficiency and accuracy of violation identification.

[0104] This process clarifies the definition and detection method of odd rings, making the violation identification process more operable. It provides a clear target for subsequent odd ring elimination, helping to improve the efficiency and accuracy of odd ring elimination. Furthermore, the accurate identification of odd rings effectively avoids mask splitting failures caused by odd rings, ensuring the smooth progress of the chip manufacturing process and thus improving chip manufacturing yield and design efficiency.

[0105] In this application, after step 145 above, that is, after an odd cycle is detected in the conflict graph, steps 151 to 153 may also be performed:

[0106] Step 151: Divide the target graphic layer into multiple first regions with similar numbers of odd rings, wherein the number of odd rings in each first region is less than or equal to a set number.

[0107] Step 152: Divide each first region into at least two second regions of similar size, and define the second regions as correction regions.

[0108] Step 153: In parallel, resolve odd cycles in multiple correction regions and return to the step of executing the call to the conflict quantization model to calculate the conflict risk value of each adjacent graph in the target graph layer, until there are no odd cycles in the conflict graph.

[0109] In this application, odd ring elimination is a key step in the dual-pattern process design rule check. This step can improve the efficiency of odd ring elimination through reasonable region division and parallel processing.

[0110] Specifically, the target pattern layer can first be divided into multiple first regions with a similar number of odd rings, where the number of odd rings in each first region is less than a set number. This division aims to decompose the large-scale chip layout into multiple appropriately sized regions, avoiding the problem of excessive odd rings in a single region leading to high resolution difficulty and low efficiency. Then, each first region is divided into at least two second regions of similar size, and these second regions are defined as correction regions. This step further refines the region division, ensuring that each correction region is of a suitable size for parallel processing, thus improving the overall efficiency of odd ring resolution. Finally, for multiple correction regions, odd ring resolution is performed simultaneously in parallel. That is, the odd ring resolution tasks for multiple correction regions can be executed concurrently on different processing threads or processors, significantly reducing the total time for odd ring resolution.

[0111] Furthermore, after completing one round of odd ring resolution, the process returns to step 130 above, which involves "calling the conflict quantization model to calculate the conflict risk value of each adjacent pattern in the target pattern layer." The conflict graph is then reconstructed, and odd rings are detected until no odd rings remain in the conflict graph, completing the design rule check for the dual-patterning process. The purpose of the iterative check is to verify whether any new odd rings are generated during the resolution process, ensuring that all odd rings are completely resolved and guaranteeing that the chip layout meets the manufacturing requirements of the dual-patterning process.

[0112] To enable those skilled in the art to better understand steps 151 to 153 above, the following will be combined with... Figure 3 The following is an illustration using a specific example.

[0113] See Figure 3 This shows a schematic diagram of the target graphic layer in the chip layout of an embodiment of this application.

[0114] like Figure 3 As shown, assuming a metal layer pattern 300 of a dual-patterning process contains 120 odd rings, and the number of odd rings in each first region is set to no more than 45, the pattern is divided into three first regions FR1, FR2, and FR3 using a region partitioning algorithm. The number of odd rings in each region is 42, 41, and 37, respectively. Then, the first regions FR1, FR2, and FR3 are further divided into second regions FR1-1 and FR1-2, second regions FR2-1 and FR2-2, and second regions FR3-1 and FR3-2, respectively, as correction regions. The number of odd rings in each correction region is between 18 and 22, and the regions are of similar size, providing a basis for parallel resolution. Subsequently, the odd ring resolution tasks for the six correction regions are assigned to six processing threads for parallel execution. Each thread is responsible for the odd ring resolution of one correction region. Compared to serial processing, the total resolution time is reduced to about 1 / 6 of the original. After the first round of parallel resolution, the conflict risk value is recalculated, a conflict graph is constructed, and odd rings are detected. Suppose that there are 10 odd cycles that are not completely eliminated in the 6 correction regions, and 2 new odd cycles are generated, with a total of 12 odd cycles. Then, a second round of elimination is performed. After elimination, 3 odd cycles remain and no new odd cycles are generated. A third round of elimination is then performed. Finally, there are no odd cycles in the conflict graph, and the odd cycle elimination is completed.

[0115] Based on the technical solutions in steps 151 to 153 above, a phased region partitioning strategy is used to divide the large-scale chip layout, i.e., the target pattern layer, into multiple moderately sized correction regions with uniformly distributed odd rings. This effectively reduces the difficulty of odd ring elimination in a single region and supports parallel elimination processing of multiple correction regions, significantly improving the overall efficiency of odd ring elimination. This avoids the problem of low elimination efficiency caused by concentrated odd ring distribution or excessively large regions in traditional methods. The iterative checking mechanism ensures the thoroughness of odd ring elimination, avoids missing any unresolved odd rings, and promptly detects and processes new odd rings generated during the elimination process, ensuring the elimination effect and avoiding manufacturing risks caused by incomplete elimination in a single step. Furthermore, the logic of region partitioning and parallel processing is clear and can be combined with existing parallel computing technologies, facilitating engineering implementation and demonstrating good practicality. The efficient and thorough elimination of odd rings helps ensure the smooth progress of mask splitting in dual patterning processes, improves the success rate of chip manufacturing, shortens the chip design cycle, and enhances chip design efficiency and manufacturing yield.

[0116] In this application, in step 151 above, dividing the target graphic layer into multiple first regions with a similar number of odd rings can be performed according to steps 1511 to 1513 as follows:

[0117] Step 1511: According to the set traversal order, traverse the grid regions that have not yet been traversed in the target graphic layer in turn.

[0118] Step 1512: Whenever the current grid region is traversed, the total number of odd cycles in the traversed grid regions is counted. If the total number of odd cycles exceeds the set number, the grid regions traversed before the current grid region are traversed are marked as a first region, and the total number of traversed grid regions and the total number of odd cycles are reset.

[0119] Step 1513: Take the current grid region as the first untraversed grid region and repeat the grid region traversal process until all grid regions have been traversed.

[0120] In this application, the core of the region division method is to ensure that the number of odd rings in each first region is similar and does not exceed a set number, providing a good foundation for subsequent odd ring resolution. Specifically, firstly, a traversal order can be determined. The choice of traversal order can be determined based on factors such as the shape and distribution characteristics of the target graphic layer, such as from left to right, from top to bottom, or radiating from the center outwards, ensuring that the traversal process can cover the entire grid area of ​​the target graphic layer. Then, the untraversed grid areas are traversed sequentially according to this traversal order. During the traversal process, the total number of odd rings in the traversed grid areas is counted in real time. When the total number of odd rings exceeds the set number, it indicates that the number of odd rings in the currently traversed grid areas is too large. If subsequent grid areas are added, it will make the odd ring resolution in this area too difficult. Therefore, the previously traversed grid areas of the current grid area are marked as a first region, and the cumulative traversed grid areas and the total number of odd rings are reset, starting a new region division. Finally, the current grid region is taken as the first untraversed grid region, and the above traversal and statistical process is repeated until all grid regions have been traversed, thus completing the division of the first region.

[0121] For example, in a specific embodiment, the target graphic layer is divided into 5μm×5μm grid regions, and the number of odd rings in each first region is set to no more than 40. The traversal order is from left to right and from top to bottom. After starting the traversal, the (1,1), (1,2), ..., (1,5) grid regions are traversed in sequence. At this time, the total number of odd rings in the traversed grid regions is 38, which does not exceed the set number of 40. The (1,6) grid region is traversed, and the total number of odd rings becomes 42, which exceeds the set number of 40. At this time, the (1,1)-(1,5) grid regions are marked as first region 1, and the cumulative number of traversed grid regions and the total number of odd rings are reset. Then, the (1,6) grid region is regarded as the first untraversed grid region, and the (1,7), (1,8), and other grid regions are traversed, and the above statistical and marking process is repeated. When traversing to the (5,10)th grid region, the cumulative number of odd rings reaches 40, and the corresponding cumulative traversed grid region is marked as the first region n. Continue traversing the remaining grid regions until all 100 grid regions have been traversed, and finally divide the target graphic layer into multiple first regions with similar numbers of odd rings.

[0122] Based on the technical solutions in steps 1511 to 1513 above, by setting the traversal order and a real-time statistical mechanism to traverse the grid region and count the number of odd rings, it can be ensured that the number of odd rings in each first region does not exceed the set value and that the number of odd rings in each region is similar, resulting in a uniform and reasonable division. This avoids the difficulty of resolution caused by the excessive concentration of odd rings in some regions. At the same time, the traversal order can be flexibly set to adapt to chip layouts with different shapes and graphic distributions, exhibiting good adaptability. The division process is highly automated, requiring no manual intervention, and can quickly and accurately complete the first region division of large-scale chip layouts. It is easy to program and can be directly integrated into electronic design automation tools, showing good prospects for engineering applications. The uniform region division also helps to subsequently divide each first region into correction regions of similar size, providing good conditions for parallel resolution of odd rings, further improving the efficiency of odd ring resolution and shortening the chip design cycle.

[0123] In step 153 above, for each correction region, the odd cycles in the correction region are eliminated, which can be done according to steps 1531 to 1532 as follows:

[0124] Step 1531: Identify at least one target connection edge to be resolved in the correction region.

[0125] Step 1532: Perform a shifting and / or cutting process on one of the graphs associated with each target connecting edge to eliminate the odd cycle to which each target connecting edge belongs.

[0126] In this application, the core of odd-ring elimination is to process the graphics associated with the target connecting edge to break the closed structure of the odd-ring, thereby eliminating the odd-ring. First, the target connecting edge to be eliminated can be determined in the correction region. The selection of the target connecting edge is crucial; a reasonable selection can reduce the number of correction iterations and avoid triggering new conflicts. The target connecting edge is the connecting edge that plays a key supporting role in the odd-ring structure; deleting or modifying this connecting edge can effectively break the odd-ring. Then, a shifting and / or cutting process can be performed on one of the graphics associated with each target connecting edge. Shifting refers to moving the graphic a certain distance in the plane, changing the position of the graphic, thereby adjusting the spacing between adjacent graphics; cutting refers to removing a portion of the graphic, reducing the size of the graphic, and thus changing the relative position and spacing between adjacent graphics. Through these processes, the closed loop of the odd-ring can be broken, the odd-ring structure eliminated, and the mask splitting in the dual-graphics process can be successfully performed.

[0127] In addition, depending on the layout characteristics and manufacturing requirements of the graphic, both displacement and cutting processes can be used simultaneously to achieve a better resolution effect.

[0128] To enable those skilled in the art to better understand steps 1531 to 1532 above, the following will be combined with... Figure 4 The following is an illustration using a specific example.

[0129] See Figure 4 This shows a schematic diagram of the target graphic layer in the chip layout of an embodiment of this application.

[0130] like Figure 4 As shown, in the target graphic layer 400, graphic I, graphic J, and graphic K form an odd ring. For example... Figure 4 As shown in subgraph (a), by cutting the graphic K to eliminate the odd cycle, the result is as follows: Figure 4 The target graphic layer is shown in subgraph (b) in the image. For example... Figure 4 As shown in subgraph (c), by shifting graph K to eliminate the odd cycle, we obtain the following... Figure 4 The target graphic layer is shown in subgraph (d) in the image. For example... Figure 4 As shown in subgraph (e), by simultaneously performing cutting and shifting operations on graph K, the odd cycle is eliminated, resulting in the following... Figure 4 The target graphic layer is shown in subgraph (f) in the image.

[0131] Based on the technical solutions in steps 1531 to 1532 above, by determining the target connection edge and performing shifting and / or cutting processing on the associated graphics, the target connection edge can be effectively disconnected, and the odd ring structure in the correction area can be quickly eliminated, meeting the mask splitting requirements of the dual-patterning process. Compared with the traditional method of randomly selecting connection edges for correction, this method can accurately locate key connection edges, reduce the number of correction iterations, and improve the efficiency of odd ring elimination. At the same time, it supports the flexible selection and combination of multiple processing methods, and can adapt to the odd ring elimination requirements of different graphic layouts and different manufacturing constraints according to the specific situation of the graphics. It has good flexibility, and the processing is only performed on the single graphic associated with the target connection edge, with little impact on the surrounding graphics. It can reduce the risk of generating new conflicts during the elimination process, ensuring the design quality of the chip layout. This processing method is simple and efficient, without the need for complex graphic reconstruction, and can further improve the overall efficiency of design rule checking, help the smooth implementation of the dual-patterning process, and improve the yield and reliability of chip manufacturing.

[0132] In step 1531 above, determining at least one target connection edge to be resolved in the correction region can be performed according to steps 15311 to 15313 as follows:

[0133] Step 15311: Traverse each connecting edge in the correction region and record the correspondence between each connecting edge and its corresponding odd cycle in a temporary table.

[0134] Step 15312: Count the connecting edges with the most odd cycles in the temporary table, and use them as undetermined connecting edges, and determine the undetermined connecting edges as target connecting edges to be resolved.

[0135] Step 15313: Hide the odd cycle to which the pending connecting edge belongs in the temporary table, and return to the step of counting the connecting edge with the most odd cycles in the temporary table, until all odd cycles recorded in the temporary table are hidden.

[0136] In this application, the number of odd cycles belonging to each connecting edge is counted in a temporary table. The connecting edge with the most odd cycles is selected as the pending connecting edge and designated as the target connecting edge to be resolved. Prioritizing the connecting edge with the most odd cycles is because resolving this connecting edge can eliminate multiple odd cycles simultaneously, reducing the number of resolution iterations and improving resolution efficiency. Then, all odd cycles belonging to the pending connecting edge are hidden in the temporary table (i.e., odd cycles formed by this connecting edge are no longer included in subsequent statistics), and the process of "counting the connecting edge with the most odd cycles in the temporary table" is repeated until all odd cycles recorded in the temporary table are hidden, meaning that all odd cycles have found their corresponding target connecting edges.

[0137] Based on the above embodiments, it is easy to understand that the method for determining the target connecting edge proposed in this application can prioritize the correction of connecting edges that play a key role in multiple odd cycles, thereby improving the efficiency of odd cycle resolution. First, each connecting edge in the correction region is traversed to identify the odd cycle to which each connecting edge belongs, and this correspondence is recorded in a temporary table. This table clearly reflects the association between connecting edges and odd cycles. Then, the number of odd cycles to which each connecting edge belongs is counted in the temporary table, and the connecting edge with the most odd cycles is selected as the pending connecting edge, which is determined as the target connecting edge to be resolved. Because such connecting edges belong to multiple odd cycles simultaneously, correcting them can break the structure of multiple odd cycles at the same time, reducing the number of corrections and improving resolution efficiency. Next, the odd cycles to which the pending connecting edge belongs are hidden in the temporary table, meaning these odd cycles no longer participate in the subsequent statistical and selection process. Then, return to the step of executing the step that counts the number of odd cycles, select the target connecting edge again from the remaining connecting edges and odd cycles, and repeat the above process until all odd cycles recorded in the temporary table are hidden, that is, all odd cycles are covered by the corresponding target connecting edges, providing clear objects for subsequent odd cycle resolution.

[0138] To enable those skilled in the art to better understand steps 15311 to 15313 above, the following will continue to refer to the above. Figure 2 The following is an illustration using a specific example.

[0139] like Figure 2As shown, the correction region 200 includes: odd cycle 1: ABHA; odd cycle 2: ABCDGA; odd cycle 3: ABCDGEFA; odd cycle 4: AHBCDEFA; odd cycle 5: DEGD; odd cycle 6: DEFAGD. The correspondence between each connecting edge in the correction region 200 and its corresponding odd cycle is recorded in a temporary table, resulting in Table 2 below:

[0140] Table 2. Correspondence between connecting edges and their respective odd cycles.

[0141]

[0142] Based on the above steps and the temporary table shown in Table 2, it can be determined that either DG and BH can be identified as target edges to be eliminated, or DG and AH can be identified as target edges to be eliminated.

[0143] Based on the technical solutions in steps 15311 to 15313 above, a temporary table records the correspondence between connecting edges and odd cycles. Based on this correspondence, the number of odd cycles to which a connecting edge belongs is counted. Connecting edges that play a key role in multiple odd cycles (i.e., those with the most odd cycles) are prioritized as target connecting edges. This enables the simultaneous resolution of multiple odd cycles, reduces the number of correction iterations, and significantly improves the efficiency of odd cycle resolution. Compared to the traditional method of randomly selecting connecting edges, this method is more targeted and scientific, avoiding the inefficiency and new conflicts caused by blind correction, and reducing the risk of problems during the resolution process. The risk of generating new conflicts is reduced, improving the stability and reliability of odd ring resolution. The screening process is logically clear and easy to operate. The use of temporary tables makes the correspondence between connecting edges and odd rings clearer, facilitating statistics and selection. Target connecting edges can be quickly identified, meeting the needs of efficient inspection. Furthermore, this screening method has good versatility, adapting to different numbers and structures of odd ring combinations. It can be applied to various odd ring resolution scenarios using dual-patterning processes, providing efficient and accurate data for subsequent odd ring resolution, ensuring its smooth progress, and ultimately improving chip design efficiency and manufacturing yield.

[0144] The following describes an apparatus embodiment of this application, which can be used to execute the chip layout design rule checking method in the above embodiments of this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the chip layout design rule checking method described above.

[0145] See Figure 5 The diagram shows a block diagram of a chip layout design rule checking device in an embodiment of this application.

[0146] like Figure 5As shown, the chip layout design rule checking device 500 according to an embodiment of this application includes: a first acquisition unit 501, a second acquisition unit 502, a calling unit 503, and a checking unit 504.

[0147] The system includes a first acquisition unit 501 for acquiring a chip layout to be processed, the chip layout including at least one pattern layer; a second acquisition unit 502 for acquiring the process rule spacing of a target pattern layer in the chip layout and the factor weights of the target pattern layer on multiple process risk factors, the process rule spacing being the minimum pattern spacing to satisfy process production, and the factor weights being used to characterize the degree of interference of the corresponding process risk factors on chip manufacturing; a calling unit 503 for calling a conflict quantification model to calculate the conflict risk value of each adjacent pattern in the target pattern layer based on the process rule spacing, the factor weights, and the actual spacing of each adjacent pattern in the target pattern layer; and a checking unit 504 for performing a design rule check on the target pattern layer based on the conflict risk values ​​of each adjacent pattern in the target pattern layer.

[0148] In some embodiments of this application, based on the foregoing scheme, the conflict quantification model includes:

[0149]

[0150] in, This represents the conflict risk value of any two adjacent figures. The spacing of the process rules for the target graphic layer is quantitative; These respectively represent the target graphics layer in n Factor weights for each process risk factor , for quantitative purposes; The actual spacing between any two adjacent graphics in the target graphic layer is a variable.

[0151] In some embodiments of this application, based on the foregoing scheme, the process risk factors include one or more of the following: lithography risk factors, pattern feature factors, etching deviation factors, deposition deviation factors, and overlay mask error factors.

[0152] In some embodiments of this application, based on the foregoing scheme, the inspection unit 504 is configured to: if the target graphic layer is applied to a single graphic process, obtain a first risk value threshold set for the target graphic layer; and determine adjacent graphics in the target graphic layer whose conflict risk value exceeds the first risk value threshold as violation graphics.

[0153] In some embodiments of this application, based on the foregoing scheme, the inspection unit 504 is configured as follows: if the target graphic layer is applied to a dual graphic process, a second risk value threshold set for the target graphic layer is obtained, and adjacent graphics in the target graphic layer whose conflict risk value exceeds the second risk value threshold are defined as conflict graphic pairs; using the graphics in the conflict graphic pairs as nodes and the conflict relationship between graphics as connecting edges, a conflict graph is constructed in the target graphic layer; odd cycles are detected in the conflict graph, and the graphics corresponding to the odd cycles are determined as violation graphics, wherein the odd cycle is a closed loop formed by sequentially associating an odd number of graphics through connecting edges.

[0154] In some embodiments of this application, based on the foregoing scheme, the apparatus further includes: a resolution unit, configured to divide the target graphic layer into multiple first regions with similar numbers of odd rings, wherein the number of odd rings in each first region is less than or equal to a predetermined number; divide each first region into at least two second regions of similar size, and define the second regions as correction regions. Odd rings in the multiple correction regions are resolved in parallel, and the process returns to the step of calling the conflict quantification model to calculate the conflict risk value of each adjacent graphic in the target graphic layer, until no odd rings remain in the conflict graph.

[0155] In some embodiments of this application, based on the foregoing scheme, the resolution unit is configured to: sequentially traverse untraversed grid regions in the target graphics layer according to a set traversal order; whenever the current grid region is traversed, count the total number of odd cycles in the traversed grid regions; if the total number of odd cycles exceeds a set number, mark the traversed grid regions before traversing the current grid region as a first region, and reset the traversed grid regions and the total number of odd cycles; take the current grid region as the first untraversed grid region, and repeat the traversal process of the grid regions until all grid regions are traversed.

[0156] In some embodiments of this application, based on the foregoing scheme, the resolution unit is configured to: determine at least one target connection edge to be resolved in the correction region; and perform shifting and / or cutting processing on one of the graphics associated with each target connection edge to eliminate the odd cycle to which each target connection edge belongs.

[0157] In some embodiments of this application, based on the foregoing scheme, the resolution unit is configured to: traverse each connecting edge in the correction region, record the correspondence between each connecting edge and its corresponding odd cycle in a temporary table; count the connecting edge with the most odd cycles in the temporary table as a pending connecting edge, and determine the pending connecting edge as the target connecting edge to be resolved; hide the odd cycle to which the pending connecting edge belongs in the temporary table, and return to execute the step of counting the connecting edge with the most odd cycles in the temporary table, until all the odd cycles recorded in the temporary table are hidden.

[0158] Based on the same inventive concept, embodiments of this application provide a computer program product, the computer program product including computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor so as to cause a computer device having the processor to perform the operations performed by the chip layout design rule checking method as described above.

[0159] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing at least one computer program instruction, which is loaded and executed by a processor to perform the operations performed by the chip layout design rule checking method as described above.

[0160] Based on the same inventive concept, this application also provides an electronic device, see reference. Figure 6 The diagram shows a schematic of the structure of an electronic device in an embodiment of this application. The electronic device includes one or more memories 604, one or more processors 602, and at least one computer program (computer program instruction) stored in the memory 604 and executable on the processor 602. When the processor 602 executes the computer program, it implements the chip layout design rule checking method as described above.

[0161] Among them, Figure 6In this document, a bus architecture (represented by bus 600) is used. Bus 600 may include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 602 and memory represented by memory 604. Bus 600 may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 605 provides an interface between bus 600 and receiver 601 and transmitter 603. Receiver 601 and transmitter 603 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 602 is responsible for managing bus 600 and general processing, while memory 604 can be used to store data used by processor 602 during operation.

[0162] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Furthermore, the functional units may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0163] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0164] The units described as separate components may or may not be physically separate. Similarly, the components of the control device may or may not be physical units; they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0165] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing computer program instructions, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0166] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for checking design rules in chip layout, characterized in that, The method includes: Obtain the chip layout to be processed, the chip layout including at least one graphics layer; The process rule spacing of the target pattern layer in the chip layout is obtained, and the factor weight of the target pattern layer on multiple process risk factors is obtained. The process rule spacing is the minimum pattern spacing to meet the process production requirements. The factor weight is used to characterize the degree of interference of the corresponding process risk factor on chip manufacturing. The process risk factors include one or more of the following: lithography risk factor, pattern feature factor, etching deviation factor, deposition deviation factor, and overlay mask error factor. Based on the process rule spacing, the factor weights, and the actual spacing between each adjacent graphic in the target graphic layer, the conflict quantification model is invoked to calculate the conflict risk value of each adjacent graphic in the target graphic layer. Based on the conflict risk value of each adjacent graphic in the target graphic layer, a design rule check is performed on the target graphic layer; The conflict quantification model includes: in, This represents the conflict risk value of any two adjacent figures. The spacing of the process rules for the target graphic layer is quantitative; , , ..., These respectively represent the target graphics layer in n Factor weights for each process risk factor , for quantitative purposes; The actual spacing between any two adjacent graphics in the target graphic layer is a variable.

2. The method according to claim 1, characterized in that, If the target graphic layer is applied to a single graphic process, the design rule check of the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer includes: Obtain the first risk threshold value set for the target graphics layer; Adjacent graphics in the target graphic layer whose conflict risk value exceeds the first risk value threshold are identified as violation graphics.

3. The method according to claim 1, characterized in that, If the target graphic layer is applied to a dual-graphics process, the design rule check of the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer includes: Obtain a second risk value threshold set for the target graphic layer, and define adjacent graphics in the target graphic layer whose conflict risk value exceeds the second risk value threshold as conflict graphic pairs; Using the graphics in the conflicting graphic pair as nodes and the conflict relationships between the graphics as connecting edges, a conflict graph is constructed in the target graphic layer; In the conflict graph, odd cycles are detected, and the graphs corresponding to the odd cycles are identified as violation graphs. An odd cycle is a closed loop formed by an odd number of graphs connected sequentially through connecting edges.

4. The method according to claim 3, characterized in that, The method further includes: The target graphic layer is divided into multiple first regions with similar numbers of odd rings, and the number of odd rings in each first region is less than or equal to a set number; Each first region is divided into at least two second regions of similar size, and the second regions are defined as the correction regions; The process involves resolving odd cycles in multiple correction regions in parallel and then returning to the step of executing the called conflict quantization model to calculate the conflict risk value of each adjacent graph in the target graph layer until no odd cycles are found in the conflict graph.

5. The method according to claim 4, characterized in that, The step of dividing the target graphic layer into multiple first regions with a similar number of odd rings includes: According to the set traversal order, the grid regions that have not yet been traversed are traversed sequentially in the target graphics layer; Whenever the current grid region is traversed, the total number of odd cycles in the traversed grid regions is counted. If the total number of odd cycles exceeds the set number, the grid regions traversed before the current grid region are marked as a first region, and the total number of traversed grid regions and the total number of odd cycles are reset. The current grid region is taken as the first untraversed grid region, and the grid region traversal process is repeated until all grid regions have been traversed.

6. The method according to claim 4, characterized in that, Eliminating odd cycles in the modified region includes: In the correction region, at least one target connection edge to be resolved is identified; Perform shifting and / or cutting processing on one of the graphs associated with each target connecting edge to eliminate the odd cycle to which each target connecting edge belongs.

7. The method according to claim 6, characterized in that, The step of determining at least one target connection edge to be resolved in the correction region includes: Traverse each connecting edge in the correction region and record the correspondence between each connecting edge and its corresponding odd cycle in a temporary table; The connecting edge with the most odd cycles in the temporary table is counted as the undetermined connecting edge, and the undetermined connecting edge is determined as the target connecting edge to be resolved; Hide the odd cycle to which the pending connecting edge belongs in the temporary table, and return to the step of counting the connecting edge with the most odd cycles in the temporary table, until all odd cycles recorded in the temporary table are hidden.

8. A chip layout design rule checking device, characterized in that, The device includes: The first acquisition unit is used to acquire a chip layout to be processed, the chip layout including at least one graphics layer; The second acquisition unit is used to acquire the process rule spacing of the target pattern layer in the chip layout and the factor weight of the target pattern layer on multiple process risk factors. The process rule spacing is the minimum pattern spacing to meet the process production requirements. The factor weight is used to characterize the degree of interference of the corresponding process risk factor on chip manufacturing. The process risk factors include one or more of the following: lithography risk factor, pattern feature factor, etching deviation factor, deposition deviation factor, and overlay mask error factor. The calling unit is used to call the conflict quantification model to calculate the conflict risk value of each adjacent graphic in the target graphic layer based on the process rule spacing, the factor weight, and the actual spacing of each adjacent graphic in the target graphic layer. The inspection unit is used to perform design rule checks on the target graphic layer based on the conflict risk value of each adjacent graphic in the target graphic layer; The conflict quantification model includes: in, This represents the conflict risk value of any two adjacent figures. The spacing of the process rules for the target graphic layer is quantitative; , , ..., These respectively represent the target graphics layer in n Factor weights for each process risk factor , for quantitative purposes; The actual spacing between any two adjacent graphics in the target graphic layer is a variable.

9. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to perform the operations performed by the method as described in any one of claims 1 to 7.

11. An electronic device, characterized in that, The electronic device includes one or more processors and one or more memories, wherein at least one piece of program code is stored in the one or more memories, and the at least one piece of program code is loaded and executed by the one or more processors to implement the method as described in any one of claims 1 to 7.

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