A bandwidth-adjustable high-linearity current-mode low-pass filter

Abstract

The application discloses a bandwidth-adjustable high-linearity current-mode low-pass filter, and relates to the technical field of filters, comprising a differential input module, a first-stage filtering and current mirror unit, a first-stage operational amplifier, a second-stage current mirror and filtering unit, a second-stage operational amplifier and an output unit. The application is in the form of a current mirror, passes through a pi-type filter and a T-type filter. The resistance and capacitance of the pi-type and T-type filter circuits in the circuit can be set as variable resistance and capacitance, which is used for changing the filtering frequency, and the voltage across the current mirror is clamped by the operational amplifier to reduce the third harmonic of the circuit. Small noise is introduced, and high dynamic stray is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of filter, in particular to a bandwidth adjustable high linearity current mode low pass filter. BACKGROUND

[0002] In the field of signal receiving and transmitting, the processing of signals requires higher and higher speed and frequency. Meanwhile, the advanced process of integrated circuits is constantly improving, and the advantages of current form receivers are becoming greater and greater, and are constantly appearing in practical applications. For traditional reception and processing, most of them are voltage signals. In the current receiver, the voltage signal is converted into a current signal after passing through a low-noise trans-impedance amplifier, and then passes through a current processing module. The difference between voltage mode and current mode circuits is that the node impedance of the current mode circuit is smaller, because the voltage mode circuit needs to set a larger impedance node in the circuit to convert the current to the voltage. Therefore, the structure of the current mode circuit is relatively simple, and the introduced noise is smaller than that of the traditional voltage mode.

[0003] A current mode receiver and a receiving method are disclosed in Chinese patent application publication No. CN115765773, which discloses a filter circuit in current mode form, reduces the non-linear conversion of current to voltage, and realizes high bandwidth, low power consumption and simple structure of current filter. The defect of this structure is that the filter frequency cannot be changed, and it cannot be used for transmission. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a bandwidth adjustable high linearity current mode low pass filter. The following technical scheme is adopted:

[0005] A bandwidth adjustable high linearity current mode low pass filter, comprising a differential input module, a first stage filter and current mirror unit, a first stage operational amplifier, a second stage current mirror and filter unit, a second stage operational amplifier and an output unit;

[0006] The first stage filter and current mirror unit comprises symmetrically arranged T-shaped filter subunit, π-shaped filter subunit and cascode current mirror subunit, the T-shaped filter subunit and the π-shaped filter subunit cooperate to filter the high frequency components of the input signal, and the cascode current mirror subunit realizes current mirroring;

[0007] The first stage operational amplifier clamps the drain voltage of the current mirror transistor in the first stage filter and current mirror unit through the positive and negative input terminals;

[0008] The second stage current mirror and filter unit comprises symmetrically arranged PMOS current mirror subunit and π-shaped filter subunit, the π-shaped filter subunit filters the high frequency components of the signal twice, and the PMOS current mirror subunit realizes current mirroring;

[0009] The second-stage operational amplifier clamps the drain voltage of the current mirror transistor in the second-stage current mirror filter unit through the positive and negative input terminals;

[0010] The output unit converts the mirrored current signal into a voltage signal output, or directly outputs the current signal to a subsequent circuit;

[0011] The first-stage and second-stage filter and current mirror units are each provided with a variable resistance-capacitance element, and the filter bandwidth is adjusted by adjusting the parameters of the variable resistance-capacitance element.

[0012] Optionally, the differential input module includes a first input terminal VIN, a second input terminal VIP, a first bias current source IIN, a second bias current source IIP, a first bias voltage VB1, a second bias voltage VB2, a first NMOS transistor MN3, and a second NMOS transistor MN7; the drain of the first NMOS transistor MN3 is connected to the first bias current source IIN and the first-stage filter and current mirror unit, the gate is connected to the first bias voltage VB1, and the source is connected to the first input terminal VIN; the drain of the second NMOS transistor MN7 is connected to the second bias current source IIP and the first-stage filter and current mirror unit, the gate is connected to the second bias voltage VB2, and the source is connected to the second input terminal VIP.

[0013] Optionally, the T-type filter subunit includes a first variable resistor R1, a second variable resistor R2, and a first capacitor C1; one end of the first variable resistor R1 is connected to the drain of the first NMOS transistor MN3, and the other end is connected to one end of the first capacitor C1 and one end of the second variable resistor R2; the other end of the first capacitor C1 is grounded, and the other end of the second variable resistor R2 is connected to the corresponding cascode current mirror subunit; another set of T-type filter subunits includes a third variable resistor R3, a fourth variable resistor R4, and a second capacitor C2; one end of the third variable resistor R3 is connected to the drain of the second NMOS transistor MN7, and the other end is connected to one end of the second capacitor C2 and one end of the fourth variable resistor R4; the other end of the second capacitor C2 is grounded, and the other end of the fourth variable resistor R4 is connected to the corresponding cascode current mirror subunit.

[0014] Optionally, the cascode current mirror unit comprises a third NMOS tube MN1, a fourth NMOS tube MN2, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN4 and an eighth NMOS tube MN8; the drain of the third NMOS tube MN1 is connected with the first input end VIN, the source is grounded, and the gate is connected with the other end of the second variable resistor R2 and the π-type filter subunit respectively; the source of the fourth NMOS tube MN2 is grounded, the gate is connected with the π-type filter subunit, and the drain is connected with the source of the seventh NMOS tube MN4; the drain of the fifth NMOS tube MN5 is connected with the second input end VIP, the source is grounded, and the gate is connected with the other end of the fourth variable resistor R4 and the π-type filter subunit respectively; the source of the sixth NMOS tube MN6 is grounded, the gate is connected with the π-type filter subunit, and the drain is connected with the source of the eighth NMOS tube MN8.

[0015] Optionally, the π-type filter subunit comprises a fifth variable resistor R5, a sixth variable resistor R6, a third capacitor C3, a fourth capacitor C4, a seventh capacitor C7 and an eighth capacitor C8; the two ends of the fifth variable resistor R5 are connected with the gate of the third NMOS tube MN1 and the gate of the fourth NMOS tube MN2 respectively, one end of the third capacitor C3 is connected with the gate of the third NMOS tube MN1, and the other end is grounded, one end of the fourth capacitor C4 is connected with the gate of the fourth NMOS tube MN2, and the other end is grounded; the two ends of the sixth variable resistor R6 are connected with the gate of the fifth NMOS tube MN5 and the gate of the sixth NMOS tube MN6 respectively, one end of the seventh capacitor C7 is connected with the gate of the fifth NMOS tube MN5, and the other end is grounded, one end of the eighth capacitor C8 is connected with the gate of the sixth NMOS tube MN6, and the other end is grounded.

[0016] Optionally, the first operational amplifier AMP1 is a two-stage operational amplifier, the positive input end is connected with the first input end VIN and the second input end VIP respectively, the negative input end is connected with the source of the seventh NMOS tube MN4 and the source of the eighth NMOS tube MN8 respectively, and the output end is connected with the gate of the seventh NMOS tube MN4 and the gate of the eighth NMOS tube MN8 respectively; the first operational amplifier AMP1 clamps the drain voltages of the third NMOS tube MN1 and the fourth NMOS tube MN2, and the fifth NMOS tube MN5 and the sixth NMOS tube MN6 through the positive and negative input ends, and eliminates the channel modulation effect through negative feedback.

[0017] Optionally, the second-stage current mirror and one of the groups of PMOS current mirror sub-units of the filter unit include a first PMOS tube MP1, a second PMOS tube MP2 and a third PMOS tube MP3, the drain of the first PMOS tube MP1 is connected to the drain and the gate of the seventh NMOS tube MN4 respectively, the source is connected to a power supply, and the gate is further connected to the π-type filter sub-unit; the source of the second PMOS tube MP2 is connected to a power supply, the gate is connected to the π-type filter sub-unit, and the drain is connected to the source of the third PMOS tube MP3; another group of PMOS current mirror sub-units includes a fourth PMOS tube MP4, a fifth PMOS tube MP5 and a sixth PMOS tube MP6, the drain of the fourth PMOS tube MP4 is connected to the drain and the gate of the eighth NMOS tube MN8 respectively, the source is connected to a power supply, and the gate is further connected to the π-type filter sub-unit; the source of the fifth PMOS tube MP5 is connected to a power supply, the gate is connected to the π-type filter sub-unit, and the drain is connected to the source of the sixth PMOS tube MP6.

[0018] The π-type filter sub-unit of the second-stage current mirror and the filter unit includes a seventh variable resistor R7, an eighth variable resistor R8, a ninth capacitor C5, a tenth capacitor C6, an eleventh capacitor C9 and a twelfth capacitor C10; the two ends of the seventh variable resistor R7 are connected to the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 respectively, one end of the ninth capacitor C5 is connected to the gate of the first PMOS tube MP1, and the other end is connected to a power supply, one end of the tenth capacitor C6 is connected to the gate of the second PMOS tube MP2, and the other end is connected to a power supply; the two ends of the eighth variable resistor R8 are connected to the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5 respectively, one end of the eleventh capacitor C9 is connected to the gate of the fourth PMOS tube MP4, and the other end is connected to a power supply, one end of the twelfth capacitor C10 is connected to the gate of the fifth PMOS tube MP5, and the other end is connected to a power supply.

[0019] Optionally, the second operational amplifier AMP2 is a two-stage operational amplifier, the positive input end is connected to the drain of the first PMOS tube MP1 and the drain of the fourth PMOS tube MP4 respectively, the negative input end is connected to the drain of the second PMOS tube MP2 and the drain of the fifth PMOS tube MP5 respectively, and the output end is connected to the gate of the third PMOS tube MP3 and the gate of the sixth PMOS tube MP6 respectively; the second operational amplifier AMP2 clamps the drain voltages of the first PMOS tube MP1 and the second PMOS tube MP2, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 through the positive and negative input ends, and eliminates the channel modulation effect through negative feedback.

[0020] Optionally, the output module comprises a ninth variable resistor R9 and a tenth variable resistor R10; one end of the ninth variable resistor R9 is connected to the drain of the third PMOS tube MP3, and the other end is grounded or serves as a voltage output terminal; one end of the tenth variable resistor R10 is connected to the drain of the sixth PMOS tube MP6, and the other end is grounded or serves as a voltage output terminal; the drain of the third PMOS tube MP3 and the drain of the sixth PMOS tube MP6 can also directly serve as a current output terminal.

[0021] Optionally, by adjusting the resistance values of the first to tenth variable resistors or the capacitance values of the first to twelfth capacitors, the adjustment of the filter bandwidth is realized; by the clamping and negative feedback actions of the first operational amplifier and the second operational amplifier, the linearity of the filter is improved, and the harmonic distortion is reduced.

[0022] In summary, the present application comprises at least one of the following beneficial technical effects:

[0023] The present application can provide a bandwidth-adjustable high-linearity current-mode low-pass filter, which passes through a π-type filter and a T-type filter in the form of a current mirror. In the circuit, the resistors and capacitors of the π-type and T-type filter circuits can be set as variable resistors and capacitors, which are used to change the filter frequency, and the third harmonic of the circuit is reduced by clamping the voltage across the current mirror through the operational amplifier. A small noise is introduced to achieve a high dynamic stray. BRIEF DESCRIPTION OF DRAWINGS

[0024] Fig. 1 is a circuit structure schematic diagram of a bandwidth-adjustable high-linearity current-mode low-pass filter of the present application;

[0025] Fig. 2 is a circuit structure schematic diagram of a first operational amplifier of a bandwidth-adjustable high-linearity current-mode low-pass filter of the present application;

[0026] Fig. 3 is a circuit structure schematic diagram of a second operational amplifier of a bandwidth-adjustable high-linearity current-mode low-pass filter of the present application. DETAILED DESCRIPTION

[0027] The present application will be further described in detail below with reference to the accompanying drawings.

[0028] The present application discloses a bandwidth-adjustable high-linearity current-mode low-pass filter.

[0029] REFERENCE Figs. 1-3 , Embodiment 1, a bandwidth-adjustable high-linearity current-mode low-pass filter, comprising a differential input module, a first-stage filter and current mirror unit, a first-stage operational amplifier, a second-stage current mirror and filter unit, a second-stage operational amplifier, and an output unit;

[0030] The first-stage filter and current mirror unit comprises symmetrically arranged T-type filter subunit, π-type filter subunit and cascode current mirror subunit, the T-type filter subunit and the π-type filter subunit cooperate to filter high-frequency components of the input signal, and the cascode current mirror subunit realizes current mirroring.

[0031] The first-stage operational amplifier clamps the drain voltage of the current mirroring transistor in the first-stage filter and current mirror unit through the positive and negative input terminals.

[0032] The second-stage current mirror and filter unit comprises symmetrically arranged PMOS current mirror subunit and π-type filter subunit, the π-type filter subunit filters high-frequency components of the signal again, and the PMOS current mirror subunit realizes current mirroring.

[0033] The second-stage operational amplifier clamps the drain voltage of the current mirroring transistor in the second-stage current mirror and filter unit through the positive and negative input terminals.

[0034] The output unit converts the mirrored current signal into a voltage signal and outputs, or directly outputs the current signal to the subsequent circuit.

[0035] The first-stage and second-stage filter and current mirror units are each provided with a variable resistance-capacitance element, and the filter bandwidth is adjusted by adjusting the parameters of the variable resistance-capacitance element.

[0036] By adopting the above technical scheme, the differential input module provides differential input signal and bias current and bias voltage, establishes normal working conditions for the entire filter, and ensures stable start of the circuit and reception of the signal to be processed.

[0037] In the first-stage filter and current mirror unit, the symmetrically arranged T-type filter subunit and π-type filter subunit jointly act on the high-frequency components in the input signal to preliminarily filter the high-frequency components and reduce high-frequency interference; meanwhile, the cascode current mirror subunit mirrors and copies the filtered signal current to preliminarily transmit the current signal.

[0038] The first-stage operational amplifier is connected with the drain of the current mirroring transistor in the first-stage filter and current mirror unit through the positive and negative input terminals, clamps the voltage of the drain of the transistor, eliminates the channel modulation effect of the transistor by means of negative feedback, avoids the mirroring current deviation caused by the change of the drain voltage, improves the precision of the current mirroring, and reduces the harmonic distortion.

[0039] In the second-stage current mirror and filter unit, the symmetrically arranged π-type filter subunit filters the signal processed by the first stage again to further remove the residual high-frequency components; and the PMOS current mirror subunit mirrors the current signal filtered twice again to realize subsequent transmission of the current signal.

[0040] The second-stage operational amplifier is connected to the drains of the PMOS current mirror transistors in the second-stage current mirror and filter unit through its positive and negative input terminals, clamps the voltages of the drains of the transistors, eliminates the channel modulation effect by means of negative feedback, further improves the current mirror precision, and guarantees the linear transmission of signals.

[0041] The output unit receives the mirror current signals processed by two stages, can convert the current signals into voltage signals by means of the built-in resistance for output, or can directly deliver the current signals to the subsequent circuit, to meet the application requirements of different subsequent stages.

[0042] Variable resistance and capacitance elements are arranged in the first-stage and second-stage filter and current mirror units, the resistance or capacitance values of the variable resistance and capacitance elements are adjusted, the RC parameters of the filter circuit are changed, and thus the bandwidth of the filter is flexibly adjusted to adapt to the processing requirements of signals of different frequencies.

[0043] In the embodiment 2, the differential input module includes a first input terminal VIN, a second input terminal VIP, a first bias current source IIN, a second bias current source IIP, a first bias voltage VB1, a second bias voltage VB2, a first NMOS transistor MN3 and a second NMOS transistor MN7; the drain of the first NMOS transistor MN3 is connected to the first bias current source IIN and the first-stage filter and current mirror unit, the gate is connected to the first bias voltage VB1, and the source is connected to the first input terminal VIN; the drain of the second NMOS transistor MN7 is connected to the second bias current source IIP and the first-stage filter and current mirror unit, the gate is connected to the second bias voltage VB2, and the source is connected to the second input terminal VIP.

[0044] By adopting the above technical scheme, the first input terminal and the second input terminal serve as differential signal receiving terminals and receive differential current signals to be processed. The first bias current source and the second bias current source provide stable bias currents for the differential input module, ensure that the entire module and the subsequent circuit are always in the current environment required for normal operation, and maintain the stability of the circuit working state.

[0045] The first bias voltage and the second bias voltage provide fixed potentials for the gates of the first NMOS transistor and the second NMOS transistor, respectively, to set the conduction operating points of the two NMOS transistors, so that they stably work in the region suitable for current transmission and avoid abnormal working state of the transistors due to fluctuation of the gate potential.

[0046] The first NMOS transistor is stably turned on under the control of the first bias voltage, the source thereof receives the current signal of the first input terminal, and the drain thereof transmits the signal integrated with the bias current provided by the first bias current source to the first-stage filtering and current mirror unit. The second NMOS transistor is also stably turned on under the control of the second bias voltage, the source thereof receives the current signal of the second input terminal, and the drain thereof transmits the signal integrated with the bias current of the second bias current source to the first-stage filtering and current mirror unit, thereby realizing stable transmission of the differential current signal to the subsequent unit and providing reliable input for the first-stage filtering and current mirror processing.

[0047] In the embodiment 3, the T-shaped filtering subunit includes a first variable resistor R1, a second variable resistor R2 and a first capacitor C1, one end of the first variable resistor R1 is connected to the drain of the first NMOS transistor MN3, the other end of the first variable resistor R1 is connected to one end of the first capacitor C1 and one end of the second variable resistor R2 respectively, the other end of the first capacitor C1 is grounded, and the other end of the second variable resistor R2 is connected to the corresponding cascode current mirror subunit. Another T-shaped filtering subunit includes a third variable resistor R3, a fourth variable resistor R4 and a second capacitor C2, one end of the third variable resistor R3 is connected to the drain of the second NMOS transistor MN7, the other end of the third variable resistor R3 is connected to one end of the second capacitor C2 and one end of the fourth variable resistor R4 respectively, the other end of the second capacitor C2 is grounded, and the other end of the fourth variable resistor R4 is connected to the corresponding cascode current mirror subunit.

[0048] By adopting the above technical solution, the two groups of T-shaped filtering subunits are in a symmetrical structure and perform high-frequency filtering processing on the two signals output by the differential input module.

[0049] For the T-shaped filtering subunit connected to the drain of the first NMOS transistor MN3, the first variable resistor R1 receives the signal transmitted by the drain of MN3 and guides the signal to the subsequent node. The node transmits the signal in two ways: one way is to ground the signal through the first capacitor C1, because the impedance of the capacitor to the high-frequency signal is low, the high-frequency component in the signal will be filtered out through C1; the other way is to transmit the filtered signal to the corresponding cascode current mirror subunit through the second variable resistor R2. R1 cooperates with R2 and C1 to form a T-shaped filtering path, which strengthens the suppression effect on high-frequency interference.

[0050] For the T-shaped filtering subunit connected to the drain of the second NMOS transistor MN7, the working logic is consistent with the foregoing subunit: the third variable resistor R3 receives the signal of the drain of MN7, the signal is divided into two ways after passing through the resistor, one way is to ground the signal to filter out the high-frequency component through the second capacitor C2, and the other way is to transmit the signal to the corresponding cascode current mirror subunit through the fourth variable resistor R4, thereby ensuring that the filtering effects of the two ways of the differential signal are symmetrical and avoiding signal distortion.

[0051] By adjusting the resistance values of the first, second, third and fourth variable resistors, the RC time constant of the filter circuit can be changed, thereby adjusting the filtering range of high-frequency components of different frequencies, realizing flexible adjustment of the filter bandwidth, and providing a stable signal that has been preliminarily high-frequency filtered for the subsequent cascode current mirror unit.

[0052] In embodiment 4, the cascode current mirror unit includes a third NMOS tube MN1, a fourth NMOS tube MN2, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN4 and an eighth NMOS tube MN8; the drain of the third NMOS tube MN1 is connected to the first input terminal VIN, the source is grounded, and the gate is connected to the other end of the second variable resistor R2 and the π-type filter subunit; the source of the fourth NMOS tube MN2 is grounded, the gate is connected to the π-type filter subunit, and the drain is connected to the source of the seventh NMOS tube MN4; the drain of the fifth NMOS tube MN5 is connected to the second input terminal VIP, the source is grounded, and the gate is connected to the other end of the fourth variable resistor R4 and the π-type filter subunit; the source of the sixth NMOS tube MN6 is grounded, the gate is connected to the π-type filter subunit, and the drain is connected to the source of the eighth NMOS tube MN8.

[0053] By adopting the above technical scheme, the cascode current mirror unit adopts a symmetrical structure and corresponds to two paths of differential signals respectively, accurately realizes mirror transmission of current, and guarantees signal stability in cooperation with the π-type filter subunit.

[0054] For the first path of signals, the third NMOS tube MN1 serves as a reference current tube, the drain is connected to the first input terminal VIN to obtain signals, the source is grounded to form a current path, and the gate simultaneously receives filtered signals transmitted by the second variable resistor R2 and signals of the π-type filter subunit, so that the gate potential is stably controlled, thereby determining the reference current size of MN1. The fourth NMOS tube MN2 serves as a mirror tube, the source is also grounded, and the gate is only controlled by the signal of the π-type filter subunit, and the gate potential is kept in cooperation with the gate potential of MN1. Since the sources of the two tubes are grounded and the gate potentials are similar, MN2 can accurately mirror the current of MN1. The seventh NMOS tube MN4 serves as a cascode tube, the source is connected to the drain of MN2, and the mirror current of MN2 is connected, which can isolate the influence of the subsequent circuit on the drain voltage of MN2, reduce the channel modulation effect, and further improve the current mirror precision.

[0055] For the second signal, the fifth NMOS transistor MN5 and the third NMOS transistor MN1 have the same function, the drain is connected to the second input end VIP to obtain another differential signal, the source is grounded, and the gate receives the filtered signal transmitted by the fourth variable resistor R4 and the π-type filtering subunit signal to form another reference current. The sixth NMOS transistor MN6 and the fourth NMOS transistor MN2 have the same function, the source is grounded, and the gate is controlled by the π-type filtering subunit signal to accurately mirror the current of MN5. The eighth NMOS transistor MN8 is a cascode transistor of the second path, the source is connected to the drain of MN6, and the mirror current is connected and isolated from the subsequent circuit to ensure that the two differential signals are accurately mirrored and symmetrical, and to provide stable current signals for the subsequent second-stage processing.

[0056] In embodiment 5, the π-type filtering subunit includes a fifth variable resistor R5, a sixth variable resistor R6, a third capacitor C3, a fourth capacitor C4, a seventh capacitor C7, and an eighth capacitor C8; the fifth variable resistor R5 has two ends connected to the gates of the third NMOS transistor MN1 and the fourth NMOS transistor MN2, respectively; one end of the third capacitor C3 is connected to the gate of the third NMOS transistor MN1, and the other end is grounded; one end of the fourth capacitor C4 is connected to the gate of the fourth NMOS transistor MN2, and the other end is grounded; the sixth variable resistor R6 has two ends connected to the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, respectively; one end of the seventh capacitor C7 is connected to the gate of the fifth NMOS transistor MN5, and the other end is grounded; one end of the eighth capacitor C8 is connected to the gate of the sixth NMOS transistor MN6, and the other end is grounded.

[0057] By adopting the above technical scheme, the π-type filtering subunit adopts a symmetrical structure and matches the current mirror tubes of the two differential signals in the cascode current mirror subunit, and the core realizes high-frequency filtering of the gate signals of the current mirror tubes, while ensuring the symmetry and stability of the two signals.

[0058] For the first current mirror tube, the fifth variable resistor R5 connects the gates of the third NMOS transistor MN1 and the fourth NMOS transistor MN2, on the one hand to transmit signals, and on the other hand to stabilize the potential difference between the two gates, laying a potential foundation for accurate current mirroring. One end of the third capacitor C3 is connected to the gate of MN1, and the other end is grounded. By using the low impedance characteristic of the capacitor to high-frequency signals, the high-frequency components in the MN1 gate signal are filtered out through grounding; one end of the fourth capacitor C4 is connected to the gate of MN2, and the other end is grounded. Similarly, the high-frequency components in the MN2 gate signal are filtered out, ensuring that the gate signals of the two transistors only retain low-frequency effective components, avoiding high-frequency interference affecting the accuracy of current mirroring.

[0059] For the second current mirror tube, the sixth variable resistor R6 is connected to the gate of the fifth NMOS tube MN5 and the sixth NMOS tube MN6, and has the same function as the fifth variable resistor R5, which stabilizes the potential difference between the gates of MN5 and MN6 and transmits signals. One end of the seventh capacitor C7 is connected to the gate of MN5, and the other end is connected to the ground. One end of the eighth capacitor C8 is connected to the gate of MN6, and the other end is connected to the ground. The high-frequency components in the gate signals of MN5 and MN6 are filtered out respectively, and the purity of the second gate signal is ensured.

[0060] By adjusting the resistance values of the fifth and sixth variable resistors, the RC time constant of the filter circuit can be changed, and the filtering range of high-frequency components can be adjusted. In combination with the T-type filter subunit, the bandwidth of the filter can be flexibly adjusted. At the same time, the gate signal after π-type filtering is more stable, which can further improve the current mirror accuracy of the cascode current mirror subunit and reduce harmonic distortion.

[0061] In embodiment 6, the first operational amplifier AMP1 is a two-stage operational amplifier, the positive input end is connected to the first input end VIN and the second input end VIP respectively, the negative input end is connected to the source of the seventh NMOS tube MN4 and the source of the eighth NMOS tube MN8 respectively, and the output end is connected to the gate of the seventh NMOS tube MN4 and the gate of the eighth NMOS tube MN8 respectively. The first operational amplifier AMP1 clamps the drain voltages of the third NMOS tube MN1 and the fourth NMOS tube MN2, the fifth NMOS tube MN5 and the sixth NMOS tube MN6 through the positive and negative input ends, and eliminates the channel modulation effect through negative feedback.

[0062] By adopting the above technical scheme, the first operational amplifier AMP1 is a two-stage operational amplifier, which is accurately matched with the cascode current mirror subunit and the differential input module in connection, and realizes voltage clamping and negative feedback regulation, thereby ensuring the current mirror accuracy.

[0063] The positive input end of AMP1 is connected to the first input end VIN and the second input end VIP respectively, and VIN corresponds to the drain of the third NMOS tube MN1 and VIP corresponds to the drain of the fifth NMOS tube MN5. The negative input end of AMP1 is connected to the source of the seventh NMOS tube MN4 and the source of the eighth NMOS tube MN8 respectively, and the source of MN4 corresponds to the drain of the fourth NMOS tube MN2 and the source of MN8 corresponds to the drain of the sixth NMOS tube MN6. By virtue of the "virtual short" characteristic of the operational amplifier, AMP1 can clamp the drain voltages of MN1 and MN2, and the drain voltages of MN5 and MN6 to a similar level respectively, thereby avoiding the current mirror deviation caused by the difference in drain voltages.

[0064] Meanwhile, the output end of the AMP1 is connected to the gate of MN4 and MN8 respectively, forming a negative feedback loop. When the drain voltage of MN2 or MN6 changes due to external interference or circuit fluctuation, the negative input end of AMP1 will perceive the change, and then adjust the gate voltage of MN4 or MN8 through the output end, change the conduction state of MN4 or MN8, and reverse stabilize the drain voltage of MN2 or MN6, ultimately eliminating the channel modulation effect of the transistor, ensuring more accurate current mirroring between MN1 and MN2, MN5 and MN6, reducing harmonic distortion, and improving the linearity of the filter.

[0065] In the embodiment 7, the second-stage current mirror and one group of PMOS current mirror sub-units of the filter unit include a first PMOS tube MP1, a second PMOS tube MP2, and a third PMOS tube MP3. The drain of the first PMOS tube MP1 is connected to the drain and gate of the seventh NMOS tube MN4 respectively, and the source is connected to the power supply. The gate is also connected to the π-type filter sub-unit. The source of the second PMOS tube MP2 is connected to the power supply, the gate is connected to the π-type filter sub-unit, and the drain is connected to the source of the third PMOS tube MP3. Another group of PMOS current mirror sub-units includes a fourth PMOS tube MP4, a fifth PMOS tube MP5, and a sixth PMOS tube MP6. The drain of the fourth PMOS tube MP4 is connected to the drain and gate of the eighth NMOS tube MN8 respectively, and the source is connected to the power supply. The gate is also connected to the π-type filter sub-unit. The source of the fifth PMOS tube MP5 is connected to the power supply, the gate is connected to the π-type filter sub-unit, and the drain is connected to the source of the sixth PMOS tube MP6.

[0066] The π-type filter sub-unit of the second-stage current mirror and the filter unit includes a seventh variable resistor R7, an eighth variable resistor R8, a ninth capacitor C5, a tenth capacitor C6, an eleventh capacitor C9, and a twelfth capacitor C10. The two ends of the seventh variable resistor R7 are connected to the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 respectively. One end of the ninth capacitor C5 is connected to the gate of the first PMOS tube MP1, and the other end is connected to the power supply. One end of the tenth capacitor C6 is connected to the gate of the second PMOS tube MP2, and the other end is connected to the power supply. The two ends of the eighth variable resistor R8 are connected to the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5 respectively. One end of the eleventh capacitor C9 is connected to the gate of the fourth PMOS tube MP4, and the other end is connected to the power supply. One end of the twelfth capacitor C10 is connected to the gate of the fifth PMOS tube MP5, and the other end is connected to the power supply.

[0067] By adopting the technical scheme, for the first signal, the first PMOS tube MP1 is used as a reference current tube, the source electrode is connected to a power supply to obtain power supply, and the drain electrode is connected to the drain electrode of the seventh NMOS tube MN4 to receive the current transmitted by the previous stage, and is short-circuited to the gate electrode, so that the MP1 works in the saturation region to form a stable reference current; the gate electrode is connected to the π-type filtering subunit to receive the filtered control signal. The second PMOS tube MP2 is used as a mirror tube, the source electrode is also connected to the power supply, and the gate electrode is connected to the π-type filtering subunit, so that the gate electrode potential is consistent with that of the MP1; because the source electrode potentials of the two tubes are the same and the gate electrode potentials are coordinated, the MP2 can accurately mirror the reference current of the MP1; the third PMOS tube MP3 is used as a cascode tube, the source electrode is connected to the drain electrode of the MP2 to receive the mirror current of the MP2, the MP3 can isolate the influence of the subsequent output unit on the drain electrode voltage of the MP2, reduce the channel modulation effect of the PMOS tube, and further improve the current mirror precision.

[0068] For the second signal, the fourth PMOS tube MP4 has the same function as the first PMOS tube MP1, the source electrode is connected to the power supply, the drain electrode is connected to the drain electrode of the eighth NMOS tube MN8 to receive the current transmitted by the previous stage and is short-circuited to the gate electrode, to form another stable reference current, and the gate electrode is connected to the π-type filtering subunit. The fifth PMOS tube MP5 has the same function as the second PMOS tube MP2, the source electrode is connected to the power supply, and the gate electrode is connected to the π-type filtering subunit, to accurately mirror the current of the MP4. The sixth PMOS tube MP6 is used as a cascode tube for the second path, the source electrode is connected to the drain electrode of the MP5 to receive the mirror current and isolate the subsequent influence, to ensure that the current mirror of the two differential signals is symmetrical and stable.

[0069] For the first PMOS current mirror, the seventh variable resistor R7 is connected between the gate electrodes of the MP1 and the MP2, on the one hand to transmit signals, and on the other hand to stabilize the potential difference between the gate electrodes of the two tubes, to provide a stable gate electrode potential basis for accurate current mirroring; one end of the ninth capacitor C5 is connected to the gate electrode of the MP1, and the other end is connected to the power supply; one end of the tenth capacitor C6 is connected to the gate electrode of the MP2, and the other end is connected to the power supply; by using the low impedance characteristic of the capacitor to high-frequency signals, the high-frequency components in the gate electrode signals of the MP1 and the MP2 are filtered out through the power supply end, to ensure that the gate electrode signals only retain low-frequency effective components, and to avoid high-frequency interference affecting the current mirror precision.

[0070] For the second PMOS current mirror, the eighth variable resistor R8 is connected between the gate electrodes of the MP4 and the MP5, and has the same function as the seventh variable resistor R7, to stabilize the potential difference between the gate electrodes of the MP4 and the MP5 and transmit signals; one end of the eleventh capacitor C9 is connected to the gate electrode of the MP4, and the other end is connected to the power supply; one end of the twelfth capacitor C10 is connected to the gate electrode of the MP5, and the other end is connected to the power supply; the high-frequency components in the gate electrode signals of the MP4 and the MP5 are filtered out respectively, to ensure the purity of the gate electrode signals of the second path.

[0071] By adjusting the resistance values of the seventh and eighth variable resistors, the RC time constant of the π-type filtering subunit can be changed, thereby adjusting the filtering range of high-frequency components, and cooperating with the front-stage filtering unit to achieve flexible adjustment of the filter bandwidth; at the same time, the gate signal filtered by the π-type filter is more stable, which can further improve the current mirroring precision of the PMOS current mirror subunit, and provide a low-distortion current signal for the subsequent output unit.

[0072] In embodiment 8, the second operational amplifier AMP2 is a two-stage operational amplifier, the positive input ends are respectively connected to the drains of the first PMOS transistor MP1 and the fourth PMOS transistor MP4, the negative input ends are respectively connected to the drains of the second PMOS transistor MP2 and the fifth PMOS transistor MP5, and the output ends are respectively connected to the gates of the third PMOS transistor MP3 and the sixth PMOS transistor MP6; the second operational amplifier AMP2 clamps the drain voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 and the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 through the positive and negative input ends, and eliminates the channel modulation effect through negative feedback.

[0073] In embodiment 9, the output module comprises a ninth variable resistor R9 and a tenth variable resistor R10; one end of the ninth variable resistor R9 is connected to the drain of the third PMOS transistor MP3, and the other end is grounded or serves as a voltage output end; one end of the tenth variable resistor R10 is connected to the drain of the sixth PMOS transistor MP6, and the other end is grounded or serves as a voltage output end; the drain of the third PMOS transistor MP3 and the drain of the sixth PMOS transistor MP6 can also directly serve as a current output end.

[0074] By adopting the above technical solution, the output module realizes flexible output of the differential current signal processed by two stages through cooperation of the ninth variable resistor R9, the tenth variable resistor R10, the third PMOS transistor MP3 and the sixth PMOS transistor MP6, and adapts to different signal type requirements of the subsequent circuit.

[0075] The drain of the third PMOS transistor MP3 receives a mirror current transmitted by the second-stage current mirror and the filtering unit, and the current can be transmitted to the ninth variable resistor R9. When the other end of the ninth variable resistor R9 is grounded, the current flowing through the resistor generates a voltage, thereby converting the current signal into a voltage signal, and at this time, the end can serve as a voltage output end to provide a voltage signal to the subsequent circuit; if the subsequent circuit needs to directly receive a current signal, the drain of the third PMOS transistor MP3 can directly serve as a current output end to directly transmit the current signal to the subsequent stage.

[0076] The drain of the sixth PMOS transistor MP6 receives another mirrored current, and the working logic is consistent with that of the third PMOS transistor MP3: the current can be transmitted to the tenth variable resistor R10, and when the other end of the tenth variable resistor R10 is grounded, the current is converted into a voltage signal and output from the end; if a current signal is needed, the drain of the sixth PMOS transistor MP6 can be directly used as a current output end.

[0077] The two output paths are symmetrical, ensuring the output integrity of the differential signal, and through the design of the two output forms, the different needs of the subsequent circuit for current or voltage signals are met, and the adaptability of the filter is improved.

[0078] In embodiment 10, the bandwidth of the filter is adjusted by adjusting the resistance values of the first to tenth variable resistors or the capacitance values of the first to twelfth capacitors; the linearity of the filter is improved and the harmonic distortion is reduced through the clamping and negative feedback effects of the first operational amplifier and the second operational amplifier.

[0079] The bandwidth of the filter is determined by the RC time constant of the filter unit, and the RC time constant is related to the product of the resistance value and the capacitance value, which directly affects the filtering range of high-frequency components.

[0080] The first to tenth variable resistors are respectively distributed in the first-stage T-type filter subunit, the π-type filter subunit, and the second-stage π-type filter subunit, and the first to twelfth capacitors are also adapted to these filter structures. When adjusting the resistance value of the variable resistor, the impedance of the resistance branch in the filter circuit will change; when adjusting the capacitance value of the variable capacitor, the impedance characteristics of the capacitance branch to different frequency signals will change. Both adjustments can change the RC time constant of the filter unit: when the RC time constant increases, the attenuation effect of the filter circuit on high-frequency signals increases, and the bandwidth narrows; when the RC time constant decreases, the attenuation effect on high-frequency signals weakens, and the bandwidth widens, thereby realizing flexible adjustment of the filter bandwidth and adapting to the processing needs of different frequency signals.

[0081] The first operational amplifier and the second operational amplifier act on the first-stage and second-stage current mirror units, respectively, and through the double effects of clamping and negative feedback, the accuracy of the current mirror is ensured, and the linearity is improved and the harmonic distortion is reduced.

[0082] The positive and negative input terminals of the operational amplifier are respectively connected to the drain of the mirror transistors in the current mirror, the drain voltage of the mirror transistors is clamped by the "virtual short" characteristic of the operational amplifier, the drain voltages of the reference tube and the mirror tube are kept consistent, and the current mirror deviation caused by the difference in the drain voltages is avoided. Meanwhile, the output terminal of the operational amplifier is connected to the gate of the cascode tube to form a negative feedback loop: when the drain voltage of the mirror transistor changes due to circuit fluctuation, the negative input terminal of the operational amplifier senses the change, adjusts the gate voltage of the cascode tube through the output terminal, reversely stabilizes the drain voltage of the mirror transistor, eliminates the channel modulation effect of the transistor, and ensures more accurate current mirroring. The accurate current mirroring reduces the nonlinear distortion in the signal transmission process, thereby reducing the harmonic distortion and significantly improving the linearity of the filter.

[0083] The above are preferred embodiments of the present application, and do not limit the protection scope of the present application, so: any equivalent changes made according to the structure, shape, principle of the present application should be covered within the protection scope of the present application.

Claims

1. A high-linearity current-mode low-pass filter with adjustable bandwidth, characterized in that: It includes a differential input module, a first-stage filter and current mirror unit, a first-stage operational amplifier, a second-stage current mirror and filter unit, a second-stage operational amplifier, and an output unit; The first-stage filtering and current mirror unit includes symmetrically arranged T-type filtering subunits, π-type filtering subunits, and cascode current mirror unit. The T-type filtering subunits and π-type filtering subunits work together to filter high-frequency components of the input signal, and the cascode current mirror unit realizes current mirroring. The first-stage operational amplifier clamps the drain voltage of the current mirror transistor in the first-stage filter and current mirror unit through its positive and negative input terminals; The second-stage current mirror and filter unit includes a symmetrically arranged PMOS current mirror unit and a π-type filter subunit. The π-type filter subunit filters high-frequency components of the signal in a secondary manner, and the PMOS current mirror unit realizes current mirroring. The second-stage operational amplifier clamps the drain voltage of the current mirror transistor in the second-stage current mirror filter unit through its positive and negative input terminals; The output unit converts the mirrored current signal into a voltage signal for output, or directly outputs the current signal to the subsequent circuit. Both the first-stage filter and current mirror unit and the second-stage current mirror and filter unit are equipped with variable resistor-capacitor components, and the filter bandwidth can be adjusted by adjusting the parameters of the variable resistor-capacitor components. The differential input module includes a first input terminal (VIN), a second input terminal (VIP), a first bias current source (IIN), a second bias current source (IIP), a first bias voltage (VB1), a second bias voltage (VB2), a first NMOS transistor (MN3), and a second NMOS transistor (MN7). The cascode current mirror unit includes a third NMOS transistor (MN1), a fourth NMOS transistor (MN2), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN4), and an eighth NMOS transistor (MN8). The T-type filter subunit comprises a first variable resistor (R1), a second variable resistor (R2), and a first capacitor (C1). One end of the first variable resistor (R1) is connected to the drain of the first NMOS transistor (MN3), and the other end is connected to one end of the first capacitor (C1) and one end of the second variable resistor (R2). The other end of the first capacitor (C1) is grounded, and the other end of the second variable resistor (R2) is connected to the corresponding cascode current mirror unit. Another T-type filter subunit comprises a third variable resistor (R3), a fourth variable resistor (R4), and a second capacitor (C2). One end of the third variable resistor (R3) is connected to the drain of the second NMOS transistor (MN7), and the other end is connected to one end of the second capacitor (C2) and one end of the fourth variable resistor (R4). The other end of the second capacitor (C2) is grounded, and the other end of the fourth variable resistor (R4) is connected to the corresponding cascode current mirror unit. The π-type filter subunit includes a fifth variable resistor (R5), a sixth variable resistor (R6), a third capacitor (C3), a fourth capacitor (C4), a seventh capacitor (C7), and an eighth capacitor (C8). The two ends of the fifth variable resistor (R5) are respectively connected to the gate of the third NMOS transistor (MN1) and the gate of the fourth NMOS transistor (MN2). One end of the third capacitor (C3) is connected to the gate of the third NMOS transistor (MN1), and the other end is grounded. One end of the fourth capacitor (C4) is connected to the gate of the fourth NMOS transistor (MN2), and the other end is grounded. The two ends of the sixth variable resistor (R6) are respectively connected to the gate of the fifth NMOS transistor (MN5) and the gate of the sixth NMOS transistor (MN6). One end of the seventh capacitor (C7) is connected to the gate of the fifth NMOS transistor (MN5), and the other end is grounded. One end of the eighth capacitor (C8) is connected to the gate of the sixth NMOS transistor (MN6), and the other end is grounded.

2. The bandwidth-adjustable, high-linearity current-mode low-pass filter according to claim 1, characterized in that: The drain of the first NMOS transistor (MN3) is connected to the first bias current source (IIN) and the first-stage filter and current mirror unit, respectively; the gate is connected to the first bias voltage (VB1); and the source is connected to the first input terminal (VIN). The drain of the second NMOS transistor (MN7) is connected to the second bias current source (IIP) and the first-stage filter and current mirror unit, respectively; the gate is connected to the second bias voltage (VB2); and the source is connected to the second input terminal (VIP).

3. A high linearity current-mode low-pass filter with adjustable bandwidth according to claim 2, characterized in that: The drain of the third NMOS transistor (MN1) is connected to the first input terminal (VIN), the source is grounded, and the gate is connected to the other end of the second variable resistor (R2) and the π-type filter subunit, respectively. The source of the fourth NMOS transistor (MN2) is grounded, the gate is connected to the π-type filter subunit, and the drain is connected to the source of the seventh NMOS transistor (MN4). The drain of the fifth NMOS transistor (MN5) is connected to the second input terminal (VIP), the source is grounded, and the gate is connected to the other end of the fourth variable resistor (R4) and the π-type filter subunit, respectively. The source of the sixth NMOS transistor (MN6) is grounded, the gate is connected to the π-type filter subunit, and the drain is connected to the source of the eighth NMOS transistor (MN8).

4. A high-linearity current-mode low-pass filter with adjustable bandwidth according to claim 3, characterized in that: The first operational amplifier (AMP1) is a two-stage operational amplifier. Its positive input terminal is connected to the first input terminal (VIN) and the second input terminal (VIP) respectively. Its negative input terminal is connected to the source of the seventh NMOS transistor (MN4) and the source of the eighth NMOS transistor (MN8) respectively. Its output terminal is connected to the gate of the seventh NMOS transistor (MN4) and the gate of the eighth NMOS transistor (MN8) respectively. The first operational amplifier (AMP1) clamps the drain voltage of the third NMOS transistor (MN1) and the fourth NMOS transistor (MN2), and the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) through the positive and negative input terminals, and eliminates the channel modulation effect through negative feedback.

5. A high linearity current-mode low-pass filter with adjustable bandwidth according to claim 4, characterized in that: One set of PMOS current mirror units in the second-stage current mirror and filter unit includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a third PMOS transistor (MP3). The drain of the first PMOS transistor (MP1) is connected to the drain of the seventh NMOS transistor (MN4) and its own gate, respectively, and its source is connected to the power supply. Its gate is also connected to the π-type filter subunit. The source of the second PMOS transistor (MP2) is connected to the power supply, its gate is connected to the π-type filter subunit, and its drain is connected to the source of the third PMOS transistor (MP3). Another set of PMOS current mirror units includes a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), and a sixth PMOS transistor (MP6). The drain of the fourth PMOS transistor (MP4) is connected to the drain of the eighth NMOS transistor (MN8) and its own gate, respectively. The source is connected to the power supply, and the gate is also connected to the π-type filter subunit. The source of the fifth PMOS transistor (MP5) is connected to the power supply, the gate is connected to the π-type filter subunit, and the drain is connected to the source of the sixth PMOS transistor (MP6). The π-type filter subunit of the second-stage current mirror and filter unit includes a seventh variable resistor (R7), an eighth variable resistor (R8), a ninth capacitor (C5), a tenth capacitor (C6), an eleventh capacitor (C9), and a twelfth capacitor (C10). The two ends of the seventh variable resistor (R7) are respectively connected to the gate of the first PMOS transistor (MP1) and the gate of the second PMOS transistor (MP2). One end of the ninth capacitor (C5) is connected to the gate of the first PMOS transistor (MP1), and the other end is connected to the power supply. One end of the tenth capacitor (C6) is connected to the gate of the second PMOS transistor (MP2), and the other end is connected to the power supply. The two ends of the eighth variable resistor (R8) are respectively connected to the gate of the fourth PMOS transistor (MP4) and the gate of the fifth PMOS transistor (MP5). One end of the eleventh capacitor (C9) is connected to the gate of the fourth PMOS transistor (MP4), and the other end is connected to the power supply. One end of the twelfth capacitor (C10) is connected to the gate of the fifth PMOS transistor (MP5), and the other end is connected to the power supply.

6. A high-linearity current-mode low-pass filter with adjustable bandwidth according to claim 5, characterized in that: The second operational amplifier (AMP2) is a two-stage operational amplifier. Its positive input terminal is connected to the drain of the first PMOS transistor (MP1) and the drain of the fourth PMOS transistor (MP4), respectively. Its negative input terminal is connected to the drain of the second PMOS transistor (MP2) and the drain of the fifth PMOS transistor (MP5), respectively. Its output terminal is connected to the gate of the third PMOS transistor (MP3) and the gate of the sixth PMOS transistor (MP6), respectively. The second operational amplifier (AMP2) clamps the drain voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), and the fourth PMOS transistor (MP4) and the fifth PMOS transistor (MP5) through its positive and negative input terminals, and eliminates the channel modulation effect through negative feedback.

7. A bandwidth-adjustable, high-linearity current-mode low-pass filter according to claim 6, characterized in that: The output unit includes a ninth variable resistor (R9) and a tenth variable resistor (R10); one end of the ninth variable resistor (R9) is connected to the drain of the third PMOS transistor (MP3), and the other end is grounded or used as a voltage output terminal; one end of the tenth variable resistor (R10) is connected to the drain of the sixth PMOS transistor (MP6), and the other end is grounded or used as a voltage output terminal; the drains of the third PMOS transistor (MP3) and the sixth PMOS transistor (MP6) can also be directly used as current output terminals.

8. A high linearity current-mode low-pass filter with adjustable bandwidth according to claim 7, characterized in that: The filter bandwidth can be adjusted by adjusting the resistance values ​​of the first to tenth variable resistors or the capacitance values ​​of the first to twelfth capacitors; the linearity of the filter is improved and harmonic distortion is reduced by the clamping and negative feedback of the first and second operational amplifiers.

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