High-precision time synchronization method and system based on distributed airborne measurement

Abstract

The invention discloses a high-precision time synchronization method and system based on distributed airborne measurement, and the method comprises the following steps: employing a high-precision atomic clock as a system clock, transmitting the precise clock to slave devices at all levels, achieving the homology and the same frequency of the clock, and guaranteeing the time consistency of the timekeeping process of a local clock; clock and time service data are transmitted through high-speed optical fibers, independent optical fiber communication links are distributed, and the same clock and time service data receiving and transmitting module is used, so that the data transmission and receiving processing time of all levels of equipment in the time service process is fixed, and the fixed time delay can be measured through a specific means. And high-precision time synchronization is finally realized by compensating the fixed time delay. Based on the distributed design of airborne measurement, the index requirements of small design size and high synchronization precision of the master device and the slave device are met, the synchronization precision can reach 10ns, the slave device can be flexibly expanded, and the method is suitable for various distributed measurement systems or measurement and control systems with high requirements on time synchronization precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of clock synchronization, in particular to a high-precision time synchronization method and system based on distributed airborne measurement. BACKGROUND

[0002] At present, the clock synchronization method in the distributed system can be mainly divided into hardware synchronization and software synchronization. The hardware synchronization is to directly adopt a time service system such as Beidou, and the main advantage is high precision and strong anti-interference capability, but if each sub-node is configured with the module, the design cost is high and too redundant. For the pure software synchronization method, there are mainly network time protocol (NTP, Network Time Protocol) and IEEE1588 precision clock synchronization protocol (PTP, Precision Time Protocol). The NTP is to encapsulate the time information of the master clock node in the message, and then transmit it to each sub-node through the Ethernet. Since there is network delay in the transmission process, the NTP protocol can only realize the clock synchronization precision of millisecond level, and it is difficult to meet the occasions with higher requirements for clock synchronization precision. The PTP is based on the NTP protocol, and through the assistance of the hardware platform, the randomness delay of the corresponding message of the device in the Ethernet physical layer is reduced by stamping the time, the round trip time delay is reduced by using multiple message transmission and reception, and the synchronization precision is about hundred nanoseconds.

[0003] In order to obtain various test data on board, an airborne measurement system is designed to complete the data acquisition of multi-channel switching quantity signal, analog quantity signal and various airborne bus signals. Since the types and numbers of data sampled on board are large, if a single device is used to complete the sampling, the device will be large in size, and finally it is difficult to place in the limited space on board, so the practical application is limited. The distributed measurement can effectively solve the problem. By designing multiple acquisition devices to form a distributed measurement system, the size of a single device can be effectively reduced, so that it can be placed and expanded flexibly according to the space on board.

[0004] The airborne data processing software has very high requirements for the time synchronization of the airborne measurement data, so the airborne distributed measurement system must be designed with a high-precision time synchronization mechanism to solve the problem of time asynchronization caused by the distributed design. A certain airborne measurement system requires a distributed design, and the synchronization precision requirement is better than 10ns. Based on the requirement, a high-precision time synchronization method is provided to meet the index requirement. SUMMARY

[0005] The purpose of the present application is to provide a high-precision time synchronization method and system based on distributed airborne measurement, which can meet the requirement of synchronization precision.

[0006] The technical scheme adopted by the present application is: A high-precision time synchronization method based on distributed airborne measurement, comprising the following steps: Step A: distribute the devices in layers according to the order of communication, the first one is called the master device, and the following are called the first-level slave device, the second-level slave device, …, the N-level slave device. The devices at each level communicate through independent timing data optical fibers and clock data optical fibers; Step B: the master device outputs clock data from the atomic clock as the reference clock, improves the accuracy through frequency multiplication by the phase-locked loop, and then counts by the FPGA of the master device, wherein one count value represents 5ns; Step C: the master device sends the clock data output by the atomic clock to the first-level slave device, the second-level slave device, …, the N-level slave device through the corresponding optical transceiver modules and clock data optical fibers at each level, and takes this clock data as the local clock of the first-level slave device, the second-level slave device, …, the N-level slave device. The FPGA of the first-level slave device, the second-level slave device, …, the N-level slave device counts to realize local time keeping of the first-level slave device, the second-level slave device, …, the N-level slave device; Step D: the GNSS precise timing module of the master device receives and solves the Beidou satellite timing information, and solves the timing to the FPGA module of the master device to provide the reference time information T0 of the distributed measurement system. The master device uses the atomic clock to generate a 10MHz high-precision reference clock and the reference time information T0 of the GNSS precise timing module to obtain the local time of the master device, which is the system time T of the distributed measurement system sys ; Step E: the master device sends timing data to the first-level slave device through the timing data optical fiber at every whole second. After receiving the timing data from the master device, the first-level slave device updates the local time to the timing data from the master device + the time delay T delay ; at other times, the first-level slave device keeps time according to the local 200MHz clock signal; Step F: similarly, the first-level slave device sends timing data to the second-level slave device through the timing data optical fiber at every whole second. After receiving the timing data from the first-level slave device, the second-level slave device updates the local time to the timing data from the first-level slave device + the time delay T delay ; at other times, the second-level slave device keeps time according to the local 200MHz clock signal, and the process is repeated until the timing and time keeping of the N-level slave device are completed.

[0007] Step B specifically comprises the following steps: the master device accumulates and counts Cnt_1s according to the 1PPS second pulse of the GNSS precise timing module, and accumulates and counts Cnt_5ns according to the 200MHz clock signal. In the initial state, Cnt_1s is zero and Cnt_5ns is zero; Cnt_5ns starts to accumulate according to the 200MHz clock signal after the first 1PPS second pulse is received, and Cnt_1s accumulates after the second 1PPS second pulse is received, and Cnt_5ns is cleared and accumulates again according to the 200MHz clock signal; An overflow flag Flag_Overflow is set, and when Cnt_5ns accumulates to 200000000, but the 1PPS second pulse is not received, Flag_Overflow is set to 1, at this time Cnt_1s accumulates and Cnt_5ns is cleared; when the 1PPS second pulse is received when Flag_Overflow is equal to 1, Cnt_1s no longer accumulates, and only Cnt_5ns is cleared and Flag_Overflow is cleared; the purpose of setting this processing strategy is to ensure that the master device can continue to keep time according to the local clock under the abnormal state of the 1PPS second pulse signal interruption.

[0008] The atomic clock is a chip atomic clock XHTF1045 produced by Chengdu Tianao, and the frequency accuracy of the atomic clock can reach 5.0×10 -11 -10

[0009] The system time T sys of the clock data frame format: Frame header + time data identification + 10M clock state; Define the frame format of the time data: Frame header + time data identification + 10M clock state + time data A + time data B The time data frame format is compatible with the clock data frame format, and only the last 12 bytes of the data frame contain time data. The design of this frame structure can not only ensure the accurate transmission of the 10MHz precision clock data, but also meet the time delay T delay of the time data in the transmission and reception processing process. The clock data frame is triggered once to send at each rising edge and falling edge of the 10MHz clock signal, but the time data frame is sent at the 1PPS time. Since the time data frame format is compatible with the clock data frame format, the 10MHz clock signal state is also transmitted when the time data is sent.

[0010] The time delay measurement in the step E comprises the following steps: the master device and the first level slave device are both designed with a test point, which can measure the state of the input signal, and record the local time when the input signal is detected to be switched from low level to high level; the output signal is divided into two parts and sent into the test points of the master device and the first level slave device by using a signal generator, and the signal jump from low level to high level is set; the time difference value is calculated according to the local time recorded by the master device and the first level slave device when the signal jump occurs, and the difference value is the time delay T delay .

[0011] The system of the high-precision time synchronization method based on distributed airborne measurement comprises a master device and slave devices arranged in a distributed manner, wherein the master device communicates with the slave devices arranged in a hierarchical distributed manner in turn by using independent time service data optical fibers and clock data optical fibers, and further comprises a GNSS precise time service module, an atomic clock, a power supply module, an FPGA, a parallel optical transceiver module, a clock interface and a memory; wherein the FPGA, the parallel optical transceiver module, the clock interface and the memory are arranged in one-to-one correspondence with the devices, the input end of the FPGA of the master device is connected to the output end of the GNSS precise time service module and the atomic clock, and the output end of the FPGA of the master device is connected to the FPGA of the secondary device through the parallel optical transceiver module and the clock interface of the adjacent secondary device in turn.

[0012] The present application uses a high-precision atomic clock as a system clock, and transmits the precise clock to each level of slave device, so that the clock is homologous and homofrequency, thereby ensuring the time consistency of the local clock in the time keeping process; further, the clock and the time service data are transmitted by using high-speed optical fibers, and independent optical fiber communication links are allocated, the same clock and time service data transceiver module is used, so that the data transmission and reception processing time of each level of device is fixed in the time service process, and the fixed time delay can be measured by a specific means, and the high-precision time synchronization is finally realized by compensating the fixed time delay. The present application is based on the distributed design of airborne measurement, and meets the index requirements of small size and high synchronization precision of the master device and the slave device, and the synchronization precision can reach 10 ns, and the slave device can be flexibly expanded, and is suitable for various distributed measurement systems or measurement and control systems with high time synchronization precision requirements. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only show some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0014] Figure 1 It is a topological structure schematic diagram of the system of the present application. Figure 2 Allocation diagram for the optical fiber communication link of the present application; Figure 3 Deployment diagram for the clock data first launch processing module of the present application; Figure 4 Hardware architecture diagram for the master device of the present application; Figure 5 Hardware architecture diagram for the slave device of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0016] As shown in FIGS. Figure 1 , 2 and 3, the present application comprises the following steps: Step A: distribute the devices hierarchically according to the order of communication, with the first one being the master device, and the following ones being the first-level slave device, the second-level slave device,..., and the Nth-level slave device, and the devices at each level communicate with each other through independent timing data optical fibers and clock data optical fibers; Step B: the master device outputs clock data from the atomic clock as the reference clock, and through frequency multiplication by the phase-locked loop, improves the accuracy, and then counts by the FPGA of the master device, wherein one count value represents 5 ns; Step C: the master device sends the clock data output from the atomic clock to the first-level slave device, the second-level slave device,..., and the Nth-level slave device through the corresponding optical transceiver modules and clock data optical fibers at each level, and takes this clock data as the local clock of the first-level slave device, the second-level slave device,..., and the Nth-level slave device, and counts by the corresponding FPGA of the first-level slave device, the second-level slave device,..., and the Nth-level slave device, to realize local time keeping of the first-level slave device, the second-level slave device,..., and the Nth-level slave device; Step D: the GNSS precise timing module of the master device receives and solves the Beidou satellite timing information, and after solving, provides timing to the FPGA module of the master device, to serve as the reference time information T0 of the distributed measurement system; the master device uses the atomic clock to generate a 10 MHz high-precision reference clock, and combines the reference time information T0 of the GNSS precise timing module to obtain the local time of the master device, i.e., the system time T sys of the distributed measurement system. Step E: The master device sends timing data to the first-level slave device via the timing data fiber optic cable at every full second; upon receiving the timing data from the master device, the first-level slave device unconditionally updates its local time to the master device's timing data plus the delay T. delay At other times, the first-level slave devices maintain local time according to the local 200MHz clock signal; Step F: Similarly, the first-level slave device sends timing data to the second-level slave device through the timing data fiber optic cable at every whole second; after receiving the timing data from the first-level slave device, the second-level slave device unconditionally updates its local time to the timing data from the first-level slave device plus the delay T. delay At other times, the second-level slave device performs local timekeeping according to the local 200MHz clock signal, repeating until the Nth-level slave device completes time synchronization and timekeeping.

[0017] Step B specifically includes the following steps: The main device accumulates a Cnt_1s count based on the 1PPS second pulse from the GNSS precision timing module, and accumulates a Cnt_5ns count based on the 200MHz clock signal. Initially, Cnt_1s and Cnt_5ns are set to zero. After receiving the first 1PPS pulse, Cnt_5ns starts accumulating the count according to the 200MHz clock signal. After receiving the next 1PPS pulse, Cnt_1s accumulates the count, and Cnt_5ns is cleared and starts accumulating the count again according to the 200MHz clock signal. An overflow flag, Flag_Overflow, is set. When Cnt_5ns accumulates to 200000000 but no 1PPS pulse is received, Flag_Overflow is set to 1. At this time, Cnt_1s is incremented and Cnt_5ns is cleared. When Flag_Overflow equals 1 and a 1PPS pulse is received, Cnt_1s stops accumulating, and only Cnt_5ns and Flag_Overflow are cleared. The purpose of this processing strategy is to ensure that the master device can continue to keep time according to the local clock in abnormal states such as interruption of the 1PPS pulse signal.

[0018] The atomic clock used in this invention is the XHTF1045 chip atomic clock manufactured by Chengdu Tian'ao, which has a frequency accuracy of 5.0 × 10⁻⁶. -11 With an accuracy better than 0.1ns The system time T sys Clock data frame format: Frame header + timing data identifier + 10M clock status; Define the frame format for timing data: Frame header + time service data identifier + 10M clock state + time service data A + time service data B The time service data frame format is compatible with the clock data frame format, and only the last 12 bytes of the data frame contain time service data. The frame structure design can ensure accurate transmission of the 10MHz precision clock data and meet the time delay T of the time service data in the transmission and reception processing. delay Keep fixed; Clock and time service data frame field data definition; The clock data frame is triggered once per rising and falling edge of the 10MHz clock signal, but the time service data frame is sent at 1PPS time service. Since the time service data frame format is compatible with the clock data frame format, the 10MHz clock signal state is transmitted at the same time when sending the time service data. According to the clock and time service data frame length and transmission frequency calculation, the data amount on the optical fiber link is about 0.96Gbps, and the optical transceiver module transmission rate is 4.25Gbps, which can meet the data transmission requirements.

[0019] The step E delay measurement includes the following steps: the master device and the first level slave device are designed with a test point, which can measure the state of the input signal, and record the local time when the input signal is detected to switch from low level to high level; the output signal is divided into two parts and sent into the test points of the master device and the first level slave device using a signal generator, and the signal jump from low level to high level is set; according to the local time recorded by the master device and the first level slave device when the signal jump occurs, the time difference value is calculated, which is the time delay T delay .

[0020] The high-precision time synchronization system based on distributed airborne measurement includes a master device and a slave device distributedly arranged, wherein the master device communicates with the slave devices arranged in a hierarchical distribution using independent time service data optical fibers and clock data optical fibers, and further includes a GNSS precise timing module, an atomic clock, a power module, an FPGA, a parallel optical transceiver module, a clock interface and a memory; wherein the FPGA, the parallel optical transceiver module, the clock interface and the memory are matched with the number of devices and are arranged one by one, the output end of the GNSS precise timing module and the atomic clock is connected to the input end of the FPGA of the master device, and the output end of the FPGA of the master device is connected to the FPGA of the secondary device through the parallel optical transceiver module and the clock interface of the adjacent secondary device in turn.

[0021] The FPGA, as the core control chip of the main equipment, primarily implements data transmission and reception processing, clock synchronization, and other business functions. The FPGA chip used in this invention is the JFM7K325T from Shanghai Fudan Microelectronics. The JFM7K325T belongs to the JFM7 product series and is a domestically produced, high-performance FPGA chip that integrates powerful and flexibly configurable programmable resources. It can be used to implement various functions such as input / output interfaces, general-purpose digital logic, memory, digital signal processing, and clock management. The GNSS precision timing module receives and calculates BeiDou satellite timing information, and then transmits the calculated time to the main equipment FPGA module, providing the reference time information T0 for this distributed measurement system.

[0022] The atomic clock used by the main equipment generates a 10MHz high-precision reference clock. This reference clock, together with the reference time information T0 from the GNSS precision timing module, is combined to obtain the local time of the main equipment, which is the system time T of the distributed measurement system. sys The atomic clock used in this invention is the XHTF1045 chip atomic clock manufactured by Chengdu Tian'ao, which has a frequency accuracy of 5.0 × 10⁻⁶. -11 The accuracy is better than 0.1ns.

[0023] The aforementioned parallel optical transceiver module transmits system time T via optical fiber. sys Forwarded to the slave device. The optical transceiver module selected for the master device in this invention is the AVIC Optoelectronic HTG8518A optical transceiver module. The HTG8518A is a high-performance 12-channel parallel optical transceiver module (12-channel parallel optical transmission, 12-channel parallel optical reception), with a single-channel transmission rate of up to 10.3125Gbps. Other peripheral circuits mainly include power supply, clock, interface, and storage circuits, meeting the operational and application functional requirements of the master device. The slave device's hardware modules mainly include an FPGA processing module, an optical transceiver module, and other peripheral circuits. The slave device hardware architecture design is as follows: Figure 5 As shown.

[0024] The following specific examples will provide further explanation: Figure 1 This is an example of the topology of the airborne distributed measurement system designed in this invention. The master device acts as the master node, primarily responsible for receiving, summarizing, and uploading measurement data from each slave device; each slave device performs functions such as airborne data acquisition, packet assembly, and data uploading. Slave devices can be cascaded downwards as needed.

[0025] The master device uses a high-precision atomic clock as the system clock signal, and simultaneously transmits this precision clock signal to the slave devices, thus achieving clock synchronization between the master and slave devices. The master and slave devices communicate at high speed via fiber optic interfaces. The master device is designed with a certain number of optical transceiver modules to meet the requirements of the first-level slave devices. One of the key design features of this distributed airborne measurement system is the allocation of independent fiber optic channels for the clock and data signals, to avoid the impact of data signal transmission and reception delays on the accuracy and stability of the clock signal.

[0026] The allocation of fiber optic communication links between master and slave devices is as follows: Figure 2 As shown.

[0027] Based on the scale and topology of the distributed network, the number of cascaded devices at each level is designed. The master device optical transceiver module of this invention supports 12 parallel optical transceivers, and the slave device optical transceiver module supports 4 parallel optical transceivers. That is, the master device supports 6 slave devices, and each slave device supports 1 cascaded path.

[0028] The master device provides time synchronization based on the Global Navigation Satellite System (GNSS) and maintains its local clock using a local atomic clock. As the master node in the distributed system, the master device periodically synchronizes its time with the first-level slave devices. Upon receiving the time synchronization data from the master device, the first-level slave devices immediately update their time and maintain their local clock. When the system has a multi-layered architecture, it is stipulated that the higher-level device is responsible for providing time synchronization to the lower-level device.

[0029] Both the master and slave devices utilize FPGA chips for clock and timing data transmission and reception. The hardware characteristics of FPGAs enable high speed and parallel processing, meeting the real-time processing requirements of clock and timing data. To ensure consistent timing delays at each stage, each fiber optic communication link is designed with an independent timing transceiver module. The clock and timing data transmission and reception modules in this distributed system are deployed as follows: Figure 3 As shown.

[0030] Since independent optical fibers and transceiver modules are allocated between the master device and slave devices, and between slave devices and the next-level slave devices, the data transmission and reception processing time of each level of equipment during the time synchronization process is fixed, which manifests as a fixed time delay T. delay This delay can be measured and obtained through a specific method, and the time delay can be compensated when the timing data is received from the device, thereby achieving high-precision time synchronization between the upper and lower level devices.

[0031] 4.5 Time Synchronization Methods The main equipment's atomic clock outputs a 10MHz clock, which is multiplied to 200MHz via a phase-locked loop. This clock frequency accuracy can reach 1×10⁻⁶. -10The magnitude is counted by the master device FPGA, and 1 count value represents 5 ns time unit. Meanwhile, the master device sends the 10 MHz atomic clock signal to the next level slave device through the optical transceiver module as the local clock of the next level slave device, and the next level slave device FPGA counts to realize the local time keeping of the next level slave device.

[0032] When the system is a multi-layer architecture, the device with the next level slave device continues to forward the 10 MHz atomic clock, so that each level of slave device can obtain the 10 MHz clock of the atomic clock, and the local time keeping of all devices is realized.

[0033] (1) System time format The distributed system time format is defined as: Cnt_1s data range: 0x00~0xFFFFF (0~1048575); unit: second; maximum value corresponds to 291.27 hours.

[0034] Cnt_5ns data range: 0x00~0xBEBC1FF (0~199999999), unit: 5 nanoseconds.

[0035] (2) Master device time The master device counts Cnt_1s according to the 1PPS second pulse of the GNSS precise timing module, and counts Cnt_5ns according to the 200 MHz clock signal. In the initial state, Cnt_1s is zero, and Cnt_5ns is zero.

[0036] After receiving the 1PPS second pulse for the first time, Cnt_5ns starts to count according to the 200 MHz clock signal. After receiving the 1PPS second pulse again, Cnt_1s is added, Cnt_5ns is cleared and re-counted according to the 200 MHz clock signal.

[0037] Set the overflow flag Flag_Overflow, when Cnt_5ns is added to 200000000, but no 1PPS second pulse is received, Flag_Overflow is set to 1, at this time Cnt_1s is added, and Cnt_5ns is cleared. When Flag_Overflow is equal to 1, the 1PPS second pulse is received, Cnt_1s is not added, and only Cnt_5ns is cleared and Flag_Overflow is cleared. The purpose of setting this processing strategy is to ensure that the master device can continue to keep time according to the local clock under the abnormal state of 1PPS second pulse signal interruption.

[0038] (3) Slave device time The master device sends time service data to the first level slave device at every whole second. After receiving the time service data from the master device, the first level slave device unconditionally updates the local time as the time service data + delay T delay At other times, the first level slave device keeps time according to the local 200MHz clock signal.

[0039] The upper level slave device sends time service data to the lower level slave device at every whole second. After receiving the time service data from the upper level device, the lower level slave device unconditionally updates the local time as the time service data + delay T delay At other times, the slave device keeps time according to the local 200MHz clock signal.

[0040] (4) Definition of clock and time service data frame format Definition of clock data frame format: Frame header + time service data identifier + 10M clock state Definition of time service data frame format: Frame header + time service data identifier + 10M clock state + time service data A + time service data B The time service data frame format is compatible with the clock data frame format, and only the last 12 bytes of the data frame contain time service data. This frame structure design can ensure accurate transmission of 10MHz precision clock data and meet the requirement that the time delay Tdelay remains fixed during transmission and reception processing.

[0041] The data definitions of the clock and time service data frame fields are shown in Table 1.

[0042] Table 1 Data definitions of clock and time service data frame Note: 1. When only transmitting clock data, the data frame does not contain time service data A and time service data B. 2. Time service data = time service data A (seconds) + time service data B x 5 (nanoseconds).

[0043] The clock data frame is triggered once per rising and falling edge of the 10MHz clock signal, but the time service data frame is sent at 1PPS time service. Since the time service data frame format is compatible with the clock data frame format, the 10MHz clock signal state is also transmitted when sending time service data. According to the length and transmission frequency of the clock and time service data frames, the data volume on this optical fiber link is about 0.96Gbps, and the transmission rate of the optical transceiver module is 4.25Gbps, which can meet the data transmission requirements.

[0044] In actual use, the master device and the first level slave device in the embodiment are both designed with a test point, which can measure the state of the input signal and record the local time when the input signal is switched from low level to high level. The output signal is divided into two parts and sent into the test point of the master device and the first level slave device by using a signal generator, and the signal jump from low level to high level is set. According to the local time recorded by the master device and the first level slave device when the signal jump occurs, the time difference value is calculated, which is the time delay T delay .

[0045] In actual use, the clock and the time service data frame are transmitted through the independent optical fiber link, and the FPGA of each device in the distributed system adopts the same clock and time service sending module and clock and time service receiving module, so that the time delay in the time service data sending and receiving process is fixed and can be measured and compensated.

[0046] Meanwhile, the precise clock signal output by the atomic clock is used as the local clock of all devices in the distributed system, so that the local clocks of the devices are homologous and have the same frequency, and the time consistency of the local clock keeping process is ensured.

[0047] The system clock is defined as the format of second count + 5 nanosecond count, and the minimum measurement unit is 5 ns, so the measurement error of the time delay T delay in the time service data sending and receiving process is ±5 ns, which is the time error of the upper and lower level devices, i.e. the synchronization accuracy. For the distributed system with N-layer architecture, the time synchronization accuracy is (N-1) × 5 ns. The distributed measurement system involved in the application adopts a two-layer architecture, but reserves the design of cascading interface to the lower level, and the time synchronization accuracy is ±5 ns, which meets the index requirement of synchronization accuracy better than 10 ns.

[0048] The application uses a high-precision atomic clock as the system clock, and transmits the precise clock to the slave devices of each level, so that the clock is homologous and has the same frequency, thereby ensuring the time consistency of the local clock keeping process. Further, the clock and the time service data use high-speed optical fiber for data transmission, and independent optical fiber communication links are allocated, the same clock and time service data transceiver modules are used, so that the data transmission and reception processing time of the devices of each level in the time service process is fixed, and the fixed time delay can be measured by a specific means, and high-precision time synchronization is finally achieved by compensating the fixed time delay. The application is based on the distributed design of airborne measurement, and meets the index requirements of small size of the master device and the slave device and high synchronization accuracy, and the synchronization accuracy can reach 10 ns. The slave device can be flexibly expanded, and is suitable for various distributed measurement systems or measurement and control systems with high time synchronization accuracy requirements.

[0049] In the description of the application, it should be noted that for the orientation words, such as the terms "center", "transverse", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation and positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and cannot be understood as limiting the specific protection scope of the application.

[0050] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification and claims of the present application are intended to cover non-exclusive inclusion, for example, a process, method, system, product or apparatus that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatus.

[0051] Note that the above is only the preferred embodiment of the application and the application of technical principles. Those skilled in the art will understand that the application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the application. Therefore, although the application is described in more detail through the above embodiments, the application is not limited to the specific embodiments described herein, and can include more other effective embodiments without departing from the concept of the application, and the scope of the application is determined by the scope of the appended claims.

Claims

1. A high-precision time synchronization method based on distributed airborne measurement, characterized in that: It comprises the following steps: Step A: distribute the devices in a hierarchical order according to the communication sequence, the first one is called master device, the following are called first-level slave device, second-level slave device, …, N-level slave device, and the communication between each level of devices is through independent time data optical fiber and clock data optical fiber; Step B: the master device outputs clock data from the atomic clock as the reference clock, and through frequency multiplication by phase-locked loop, the accuracy is improved, and then counted by the FPGA of the master device, wherein one count value represents 5ns; Step C: the master device sends the clock data output by the atomic clock to the first-level slave device, the second-level slave device, …, the N-level slave device through the corresponding optical transceiver module and clock data optical fiber of each level, and takes this clock data as the local clock of the first-level slave device, the second-level slave device, …, the N-level slave device, and the FPGA of the first-level slave device, the second-level slave device, …, the N-level slave device respectively counts to realize the local time keeping of the first-level slave device, the second-level slave device, …, the N-level slave device; Step D: the GNSS precise timing module of the master device receives and solves the Beidou satellite timing information, and solves the timing for the master device FPGA module, which is the reference time information T0 of the distributed measurement system; the master device uses the atomic clock to generate a 10MHz high-precision reference clock and the reference time information T0 of the GNSS precise timing module to obtain the local time of the master device, that is, the system time T of the distributed measurement system sys ; Step E: the master device sends timing data to the first level slave device through the timing data optical fiber at every whole second; after receiving the timing data from the master device, the first level slave device unconditionally updates the local time to the timing data from the master device + delay T delay ; at other times, the first level slave device keeps time according to the local 200MHz clock signal; Step F: similarly, the first-level slave device sends timing data to the second-level slave device through the timing data optical fiber at each whole second moment. After the second level slave device receives the first level slave device time service data, it unconditionally updates the local time to the first level slave device time service data + time delay T delay At other times, the second level slave device keeps time according to the local 200 MHz clock signal, and repeats until the time service and time keeping of the Nth level slave device are completed.

2. The method for high-precision time synchronization based on distributed airborne measurement according to claim 1, characterized in that: Said step B specifically comprises the following steps: the master device accumulates and counts Cnt_1s according to the 1PPS second pulse of the GNSS precise timing module, and accumulates and counts Cnt_5ns according to the 200MHz clock signal.

3. In the initial state, Cnt_1s is zero, and Cnt_5ns is zero; After receiving the 1PPS second pulse for the first time, Cnt_5ns starts to accumulate and count according to the 200MHz clock signal, and after receiving the 1PPS second pulse again, Cnt_1s accumulates and counts, and Cnt_5ns is cleared and accumulates and counts again according to the 200MHz clock signal; Set the overflow flag Flag_Overflow, when Cnt_5ns accumulates to 200000000, but no 1PPS second pulse is received, Flag_Overflow is set to 1, at this time Cnt_1s accumulates and Cnt_5ns is cleared; when Flag_Overflow is equal to 1 and a 1PPS second pulse is received, Cnt_1s no longer accumulates, and only Cnt_5ns is cleared and Flag_Overflow is cleared; the purpose of setting this processing strategy is to ensure that the master device can still keep time according to the local clock under the abnormal state of 1PPS second pulse signal interruption.

4. The high-precision time synchronization method based on distributed airborne measurement according to claim 1, characterized in that: The atomic clock is a chip atomic clock XHTF1045 produced by Chengdu Tianao, and the frequency accuracy of the atomic clock can reach 5.0 x 10 -11 -6, and the accuracy is better than 0.1 ns.

5. The method for high-precision time synchronization based on distributed airborne measurement according to claim 1, characterized in that: The system time T sys Clock data frame format: Frame header + timing data identification + 10M clock state; Define the frame format of timing data: Frame header + timing data identification + 10M clock state + timing data A + timing data B The time service data frame format is compatible with the clock data frame format, and only the last 12 bytes of the data frame contain time service data. The frame structure design can ensure accurate transmission of 10 MHz precision clock data and meet the time delay T of time service data in the transmission and reception processing delay Hold fixed; The clock data frame is triggered once at each rising and falling edge of the 10MHz clock signal, but the timing data frame is sent at 1PPS timing; since the timing data frame format is compatible with the clock data frame format, the 10MHz clock signal state is also transmitted when sending the timing data.

6. The high-precision time synchronization method based on distributed airborne measurement according to claim 1, characterized in that: The time delay measurement in step E includes the following steps: the master device and the first level slave device are each designed with a test point which can measure the state of the input signal and record the local time when the input signal is detected to switch from low level to high level; a signal generator is used to send the output signal into the test points of the master device and the first level slave device, and set the signal jump from low level to high level; according to the local time recorded by the master device and the first level slave device when the signal jump occurs, the time difference value is calculated, which is the time delay T delay .

7. The system for high-precision time synchronization based on distributed airborne measurements according to any of claims 1 to 5, characterized in that: The application relates to a time server, which comprises a master device and a plurality of slave devices arranged in a distributed mode, wherein the master device communicates with the slave devices arranged in a hierarchical distributed mode in turn through independent time data optical fibers and clock data optical fibers, and further comprises a GNSS precise timing module, an atomic clock, a power module, an FPGA, a parallel optical transceiver module, a clock interface and a memory; wherein the FPGA, the parallel optical transceiver module, the clock interface and the memory are arranged in one-to-one correspondence with the devices, the input end of the FPGA of the master device is connected with the output end of the GNSS precise timing module and the atomic clock, and the output end of the FPGA of the master device is connected with the FPGA of the secondary device through the parallel optical transceiver module and the clock interface of the adjacent secondary device in turn.

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