Power-on and power-off time sequence control system, circuit and method

Abstract

The invention relates to a power-on and power-off time sequence control system, circuit and method, and the system constructs a programmable and configurable power-on and power-off time sequence management architecture by introducing a control interface, a first analysis module, a power-on / power-off time sequence configuration module and a time sequence channel mapping and starting control module. The main control device can dynamically configure a register in the time sequence channel mapping and starting control module by sending a power-on / power-off time sequence configuration instruction, control multiple groups of time sequence channels by sending a power-on / power-off control instruction, and flexibly define a power-on / power-off sequence and a time interval of each time sequence channel. According to the system, universal, fast and reliable control over the power-on and power-off time sequence of complex equipment is achieved, time sequence configuration and time sequence execution can be separated, controllability and robustness of the system are enhanced through a real-time feedback mechanism, and the technical problems that time sequence management is poor in flexibility and insufficient in monitoring capacity are effectively solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of power-on and power-off timing control, in particular to a power-on and power-off timing control system, circuit and method. BACKGROUND

[0002] In the running process of electronic devices, various computing processing units integrated in the chassis, including central processing units, graphics processing units, network interface cards and PCIe expansion interfaces and other components, all have strict and differentiated requirements for the timing sequence of power-on and power-off. These requirements are derived from the inherent characteristics of hardware architecture, for example, some devices need to be powered on first to avoid hardware damage caused by voltage fluctuations, or in the power-off stage, a certain sequence must be maintained to prevent data loss and system crash. In the current technical solution, power-on and power-off timing control relies mainly on fixed logic circuits or pre-set software scripts, which lack dynamic adaptability and are difficult to meet the diversified needs of different device models and complex system architectures. When facing a multi-chassis cluster environment, the existing method is often limited to independent control of a single chassis, and cannot achieve unified coordination management of cross-chassis devices, resulting in cumbersome configuration process, slow response speed, and easy to cause device failure or running interruption due to timing deviation. In addition, the traditional controller has deficiencies in the feedback mechanism, which cannot obtain and verify the power-on state and signal feedback of each channel in real time, reducing the system reliability and making it difficult to ensure the safe and stable operation of the chassis cluster. SUMMARY

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The main purpose of the embodiments of the present disclosure is to propose a power-on and power-off timing control system, circuit and method, which can realize general, fast and reliable control of the power-on and power-off timing of complex devices through its modular design and programmable configuration capability.

[0005] In a first aspect, the present application provides a power-on and power-off timing control system, which comprises: a plurality of timing channels, each of the timing channels comprising a plurality of timing output paths and a plurality of feedback input paths; a control interface in communication connection with a control master device, the control interface being configured to receive control instructions from the master device and upload first feedback signals and second feedback signals to the master device; The first analysis module is in communication connection with the control interface, and is configured to analyze the control instruction to obtain a first analyzed instruction, send a first power-on / off timing configuration instruction to the power-on / off timing configuration module when the first analyzed instruction is the first power-on / off timing configuration instruction, send a first power-on / off control instruction to the timing channel mapping and start control module when the first analyzed instruction is the first power-on / off control instruction, receive the first feedback signal and the second feedback signal, and upload the first feedback signal and the second feedback signal to the control interface. The power-on / off timing configuration module is in communication connection between the first analysis module and the timing channel mapping and start control module, and is configured to configure corresponding registers in the timing channel mapping and start control module according to the first power-on / off timing configuration instruction. The timing channel mapping and start control module is in communication connection with the plurality of groups of timing channels, and is configured to individually control each group of the timing channels according to the first power-on / off control instruction. The state reading module is in communication connection between the power-on / off timing configuration module and the plurality of groups of timing channels, and is configured to obtain the first feedback signal of register configuration completion of the power-on / off timing configuration module, and upload the first feedback signal to the first analysis module, and obtain the second feedback signal containing the power-on / off state of each group of the timing channels, and a plurality of feedback input paths and states of the plurality of feedback input paths of each group of the timing channels, and upload the second feedback signal to the first analysis module.

[0006] The power-on / off timing control system provided by the embodiment has at least the following beneficial effects: The system of the embodiment introduces a control interface, a first analysis module, an up / down power sequence configuration module, and a sequence channel mapping and start control module, constructs a programmable and configurable up / down power sequence management architecture, and controls the host device to dynamically configure the registers in the sequence channel mapping and start control module by sending a first up / down power sequence configuration instruction, so as to flexibly define the power-on / power-off sequence and time interval of each sequence channel. In addition, the system also integrates a state reading module for obtaining a first feedback signal and a second feedback signal. The first feedback signal is used to confirm the completion of the configuration operation, and the second feedback signal provides the real-time power-on / power-off state of each group of sequence channels and the state of the feedback input channel. This real-time state feedback mechanism enables the host device to discover and handle abnormal situations in time. Compared with the traditional scheme lacking real-time feedback, the up / down power sequence control system of the embodiment realizes general, fast and reliable control of the up / down power sequence of complex devices through the modular design and programmable configuration capability, separates the sequence configuration from the sequence execution, enhances the controllability and robustness of the system through the real-time feedback mechanism, and effectively solves the technical problems of poor flexibility and insufficient monitoring capability of the sequence management in the prior art.

[0007] In a second aspect of the present application, an up / down power sequence control circuit is provided, which comprises one or more combinations of FPGA, CPLD, other programmable logic circuits, special logic circuits or chips, and hardware circuits. The circuit is provided with the up / down power sequence control system according to the first aspect.

[0008] In a third aspect of the present application, an up / down power sequence control method is provided, which comprises: receiving a first control instruction sent by a control host device; analyzing the first control instruction to obtain an up / down power sequence configuration instruction; completing the configuration of a plurality of groups of registers according to the up / down power sequence configuration instruction; generating a first feedback signal indicating that the configuration of the plurality of groups of registers is completed, and uploading the first feedback signal to the control host device; receiving a second control instruction sent by the control host device; analyzing the second control instruction to obtain an up / down power control instruction; controlling each group of sequence channels in a plurality of groups of sequence channels according to the up / down power control instruction and the configuration of the plurality of groups of registers; each group of sequence channels comprises a plurality of feedback input channels and a plurality of feedback input channels. generating a second feedback signal comprising an up / down power state of each group of the timing channels, and a plurality of feedback input paths of each group of the timing channels and a state of the plurality of feedback input paths, and uploading the second feedback signal to the control master device.

[0009] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or related technical description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0011] Figure 1 is a structural schematic diagram of an up and down power timing control system provided by the embodiments of the present application; Figure 2 is a flow schematic diagram of an up and down power timing control method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will further describe the present application in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0013] In the description of the present application, if there is a description of first, second, etc., it is only used to distinguish technical features for the purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0014] In the description of the present application, it should be understood that the position description, such as up, down, etc., is based on the position relationship or location relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and is not used to indicate or imply that the device or element indicated must have a specific position, be constructed in a specific position and function, and therefore cannot be understood as a limitation of the present application.

[0015] In a traditional chassis system, different computing processing devices such as central processors, graphic processors, network interface cards and peripheral component interconnect express interfaces have differentiated power-on and power-off timing requirements, and meanwhile, different devices inside the same board card need to follow specific power-on and power-off sequences due to different functional requirements. At present, there is a lack of a mechanism capable of realizing general, fast and reliable power-on and power-off timing control of multiple chassis and internal devices, leading to timing conflicts in the process of starting or shutting down the devices, and further affecting the safe and stable operation of the system. Among them, the fragmentation of the timing control logic makes the control instructions unable to be accurately parsed and executed, and the integrity of the feedback signals is difficult to guarantee, thereby causing device initialization abnormalities or functional disorders.

[0016] For example, in the deployment scenario of a data center server cluster, when the control master device sends a power-on instruction to the chassis, if the power-on timing of the central processor and the graphic processor is not accurately configured, the graphic processor may start before the central processor completes initialization, causing device initialization failure.

[0017] If the above problems are not solved, the system may have technical consequences such as device functional abnormalities and data transmission interruption during operation. Further, timing errors will trigger the frequent triggering of hardware protection mechanisms, thereby causing the decline of system stability and the reduction of management efficiency, making it difficult to achieve the safe and stable operation target of the chassis cluster.

[0018] For example, in the deployment scenario of a data center server cluster, when the control master device sends a power-on instruction to the chassis, if the power-on timing of the central processor and the graphic processor is not accurately configured, the graphic processor may start before the central processor completes initialization, causing device initialization failure. Figure 1 An embodiment of the present application provides a power-on and power-off timing control system, which comprises: a plurality of timing channels, each timing channel comprising a plurality of timing output paths and a plurality of feedback input paths; a control interface in communication connection with a control master device, the control interface being configured to receive control instructions of the master device and upload first feedback signals and second feedback signals to the master device; a first parsing module in communication connection with the control interface, the first parsing module being configured to parse the control instructions to obtain first parsed instructions, send first power-on and power-off timing configuration instructions to a power-on and power-off timing configuration module in the case that the first parsed instructions are the first power-on and power-off timing configuration instructions, send first power-on and power-off control instructions to a timing channel mapping and start control module in the case that the first parsed instructions are the first power-on and power-off control instructions, and receive the first feedback signals and the second feedback signals and upload the first feedback signals and the second feedback signals to the control interface; the power-on and power-off timing configuration module being in communication connection between the first parsing module and the timing channel mapping and start control module, the power-on and power-off timing configuration module being configured to configure corresponding registers in the timing channel mapping and start control module according to the first power-on and power-off timing configuration instructions; The timing channel mapping and start control module is in communication connection with the plurality of timing channels, and is configured to control each timing channel individually according to the first power-on / off control instruction; The state reading module is in communication connection between the power-on / off timing configuration module and the plurality of timing channels, and is configured to obtain a first feedback signal of register configuration completion of the power-on / off timing configuration module, and upload the first feedback signal to the first analysis module, and obtain a second feedback signal containing the power-on / off state of each timing channel, and the plurality of feedback input channels of each timing channel and the state of the plurality of feedback input channels, and upload the second feedback signal to the first analysis module.

[0019] The power-on / off timing control system is designed to manage and coordinate the power-on and power-off sequence and time interval of multiple devices to ensure the stability and compatibility of the devices during startup and shutdown. Its main function is to provide a programmable and configurable mechanism to adapt to the specific requirements of power timing for different hardware platforms and application scenarios.

[0020] The following introduces some technical features: Timing channels are logical or physical paths in the system used to control the power-on or power-off timing of one or more groups of devices. Each timing channel is usually configured to run independently to achieve fine-grained control of different devices or device groups. Among them, the timing output channel is part of the timing channel, responsible for sending power-on or power-off control signals to the controlled devices. These signals can be voltage levels, pulse sequences or other forms of electrical signals, used to trigger or turn off the power of the devices. The feedback input channel is another part of the timing channel, used to receive the state feedback signals of the controlled devices. These feedback signals can indicate the power state of the devices (e.g., powered on, powered off, fault, etc.), allowing the control system to monitor and adjust the timing in real time.

[0021] The control interface is a bridge between the power-on / off timing control system and the external control master device. The interface is responsible for receiving instructions from the control master device and uploading the running state, configuration information and feedback signals of the system to the control master device, usually through standard communication protocols (such as SPI, I2C, UART, etc.) to realize data exchange. The control master device refers to an external processor, microcontroller or host computer, which is responsible for sending control instructions to the power-on / off timing control system and receiving and processing the feedback information uploaded by the system. The control master device is the high-level manager of the entire system, responsible for formulating and issuing specific power-on / off strategies.

[0022] The first analysis module is configured to receive control instructions from the control interface and decode and classify them. According to the type of instruction, such as power-on / off timing configuration instructions or power-on / off control instructions, the module routes the instructions to the corresponding processing unit.

[0023] The power-up / down timing configuration module is used to store and manage the configuration parameters of the power-up / down timing. According to the received configuration instructions, the module programs the registers in the timing channel mapping and start control module to define the specific working mode and timing relationship of each timing channel. The timing channel mapping and start control module is the core execution unit of the system, which performs specific power-up or power-down operations on multiple groups of timing channels according to the parameters set by the configuration module and the received control instructions.

[0024] The state reading module is configured to monitor the running state of the system in real time. The module is responsible for obtaining the first feedback signal of the register configuration completion of the power-up / down timing configuration module, and the second feedback signal of the power-up / down state of each timing channel and the state of the feedback input path. The collected state information is then sorted and uploaded to the first analysis module, and then transmitted to the control master device.

[0025] The register is a storage unit in digital circuits for storing a small amount of data. In the present system, the register is used to store timing configuration parameters, control instructions, and various status flags, which is the basis for realizing programmable control.

[0026] The first feedback signal is the state information indicating the completion of the register configuration in the power-up / down timing configuration module. The generation and upload of the signal enable the control master device to confirm the successful execution of the configuration operation. The second feedback signal is comprehensive information containing the real-time power-up / down state of each group of timing channels and the state of the feedback input path of each timing channel. The signal provides detailed monitoring data for the running state of the system, which helps the control master device to perform fault diagnosis and state management.

[0027] The present embodiment provides a power-up / down timing control system for realizing accurate management of the power-up and power-down timing of complex devices. The system includes multiple groups of timing channels, each group of timing channels including multiple timing output paths and multiple feedback input paths. The implementation of the timing channel can be through a group of independent digital I / O pins, each pin corresponding to a timing output path for controlling the power enable signal of a device. Each timing channel can also be equipped with multiple feedback input paths, for example, connected to the power state pin of the controlled device through an optocoupler or voltage comparator to monitor the actual power state of the device.

[0028] The control interface is configured to be communicatively connected with the control master device, and is used to receive control instructions from the control master device and upload the first feedback signal and the second feedback signal to the control master device. The control interface can adopt a standardized communication protocol, for example, receiving ASCII code instructions from the control master device through a UART interface and sending feedback data in the same format. Alternatively, the control interface can be a simple parallel bus interface for data exchange with the control master device through a group of data lines and control lines. For example, the control master device can send a control instruction containing a power-on sequence ID and a target device address through the interface.

[0029] The first analysis module is communicatively connected with the control interface, and is used to analyze the control instructions to obtain first analyzed instructions. In the case that the first analyzed instructions are first power-on / off timing configuration instructions, the first power-on / off timing configuration instructions are sent to the power-on / off timing configuration module. In the case that the first analyzed instructions are first power-on / off control instructions, the first power-on / off control instructions are sent to the timing channel mapping and start control module. In addition, the first analysis module also receives the first feedback signal and the second feedback signal, and uploads the first feedback signal and the second feedback signal to the control interface.

[0030] The power-on / off timing configuration module is communicatively connected between the first analysis module and the timing channel mapping and start control module, and is used to configure corresponding registers in the timing channel mapping and start control module according to the first power-on / off timing configuration instructions. The configuration module can include a group of programmable storage units, such as SRAM or EEPROM, for storing power-on / off timing parameters, such as delay time, voltage threshold, etc. When receiving the configuration instructions, the module writes the parameters in the instructions into the specified registers of the timing channel mapping and start control module. For example, a configuration instruction can specify that when a certain timing channel is started, its output path should be activated after 100 milliseconds, and the next path should be activated after 50 milliseconds after activation.

[0031] The timing channel mapping and start control module is communicatively connected with a plurality of timing channels, and is used to control each group of timing channels individually according to the first power-on / off control instructions. The module can include a timing generator and a plurality of digital switches, which accurately control the switching sequence and time interval of each timing output path according to the parameters set by the configuration module and the received control instructions. For example, when receiving a power-on control instruction, the module will activate the output paths of a specific timing channel in a predetermined timing sequence, thereby realizing the sequential power-on of a plurality of devices.

[0032] The state reading module is in communication connection with the power-on / off timing configuration module and the plurality of timing channels, and is configured to obtain a first feedback signal indicating completion of register configuration of the power-on / off timing configuration module and upload the first feedback signal to the first parsing module. In addition, the state reading module is also configured to obtain a second feedback signal including power-on / off states of each timing channel and states of a plurality of feedback input paths of each timing channel, and upload the second feedback signal to the first parsing module. The state reading module can periodically poll the feedback input paths of the timing channels and read the state registers of the configuration module. For example, the first feedback signal can be generated by monitoring a "configuration completion" flag, and the second feedback signal can be generated by reading voltage detection pins of the timing channels to indicate the actual power supply state of the device.

[0033] The system of the embodiment introduces a control interface, a first parsing module, a power-on / off timing configuration module, and a timing channel mapping and start control module to construct a programmable and configurable power-on / off timing management architecture. The control master device can dynamically configure registers in the timing channel mapping and start control module by sending a first power-on / off timing configuration instruction, thereby flexibly defining power-on / off sequences and time intervals of the timing channels. In addition, the system also integrates a state reading module to obtain a first feedback signal and a second feedback signal. The first feedback signal is used to confirm completion of the configuration operation, and the second feedback signal provides real-time power-on / off states of each timing channel and states of the feedback input paths. This real-time state feedback mechanism enables the control master device to timely discover and handle abnormal situations. Compared with traditional solutions lacking real-time feedback, the system can provide more detailed fault diagnosis capabilities and help ensure safe and stable operation of the chassis.

[0034] In summary, the power-on / off timing control system of the embodiment realizes general, fast, and reliable control of power-on / off timing of complex devices through its modular design and programmable configuration capability. The core is to separate timing configuration from timing execution and enhance controllability and robustness of the system through a real-time feedback mechanism, effectively solving the technical problems of poor flexibility and insufficient monitoring capability of timing management in the prior art.

[0035] In some embodiments of the present application, the system further comprises: a ROM module; a ROM writing module in communication connection with the first parsing module, the ROM writing module being configured to send a ROM writing instruction to the ROM reading / writing module in the case that the first parsed instruction is the ROM writing instruction; The ROM reading module is in communication connection with the first analysis module, and is configured to send the ROM reading instruction to the ROM reading / writing module when the first post-analysis instruction is a ROM reading instruction. The ROM reading / writing module is in communication connection between the ROM writing module and the ROM reading module, and is configured to write the corresponding ROM writing data into the ROM module according to the ROM writing instruction, and extract the corresponding ROM reading data from the ROM module according to the ROM reading instruction. The second analysis module is in communication connection between the ROM reading / writing module, the power-on / off timing configuration module and the timing channel mapping and starting control module, and is configured to analyze the ROM reading data to obtain a second post-analysis instruction, and send the second power-on / off control instruction to the timing channel mapping and starting control module when the second post-analysis instruction is a second power-on / off control instruction, and send the second power-on / off control instruction to the power-on / off timing configuration module when the second post-analysis instruction is a second power-on / off control instruction. The power-on / off timing configuration module is further configured to configure the corresponding register in the timing channel mapping and starting control module according to the second power-on / off control instruction. The timing channel mapping and starting control module is further configured to control each group of timing channels individually according to the second power-on / off control instruction.

[0036] The ROM module is a read-only memory for storing fixed configuration data or program code required for system startup. Its characteristics are that the data is written at the time of manufacturing, or is not easy to change after being written under certain operations, and the data will not be lost after power-off. The ROM module can be implemented in multiple technologies, for example, it can be an independent EEPROM electrically erasable programmable read-only memory chip, or a flash memory area integrated in a microcontroller.

[0037] The ROM writing module is responsible for receiving the ROM writing instruction from the first analysis module and forwarding it to the ROM reading / writing module as an intermediate transferer of control instructions, ensuring that the ROM writing operation can be correctly routed and executed. The ROM writing module can be a dedicated hardware logic circuit, such as a state machine or a simple register, for receiving and temporarily storing the writing instruction, or a software-level functional module for communicating with the ROM reading / writing module through a specific interface protocol.

[0038] The ROM reading module is responsible for receiving the ROM reading instruction from the first parsing module and forwarding it to the ROM reading and writing module. Its role is to act as an intermediate transmitter of control instructions, ensuring that the ROM reading operation can be correctly routed and executed. The ROM reading module can be a dedicated hardware logic circuit, such as a state machine or a simple register, used to receive and temporarily store reading instructions, or a software-level functional module that communicates with the ROM reading and writing module through a specific interface protocol. The ROM reading and writing module is the direct operation interface of the ROM module, which writes data into the ROM module according to the received ROM writing instruction, or extracts data from the ROM module according to the ROM reading instruction. It is responsible for handling the underlying communication protocol and timing of the ROM module, ensuring the integrity and correctness of the data. The ROM reading and writing module can be a hardware controller, such as an SPI serial peripheral interface or an I2C integrated circuit interconnection controller, used to communicate with external ROM chips, or a memory controller in an embedded system that directly accesses internal flash memory.

[0039] The second parsing module is used to parse the ROM reading data read from the ROM module to obtain the second parsed instructions required by the system. These instructions can be parameters used to configure the power-on and power-off timing, or instructions directly controlling the power-on and power-off timing. The second parsing module can be a dedicated hardware state machine that parses data streams according to a pre-set format, or a firmware program running in a microprocessor that parses data structures through software algorithms.

[0040] In addition to being configured according to the instructions of the first parsing module, the power-on and power-off timing configuration module can also be configured according to the second power-on and power-off control instructions provided by the second parsing module. This allows the system to load pre-set configuration information from the ROM and achieve autonomous configuration. Its implementation can be to add an input port to the existing configuration logic to receive instructions from the second parsing module and extend its internal state machine or control logic to handle these instructions.

[0041] In addition to controlling the timing channels according to the instructions of the first parsing module, the timing channel mapping and start control module can also control multiple groups of timing channels individually according to the second power-on and power-off control instructions provided by the second parsing module. This allows the system to load pre-set control instructions from the ROM and achieve autonomous start or operation. Its implementation can be to add an input port to the existing control logic to receive instructions from the second parsing module and extend its internal state machine or control logic to handle these instructions, thereby triggering the corresponding timing channel operation.

[0042] The embodiment can realize non-volatile storage and autonomous loading of power-on and power-off timing configuration and control instructions. This enables the system to quickly and reliably load the preset power-on and power-off timing strategy and autonomously configure and control according to the strategy in the case of being disconnected from the control master device or in the initial stage of system power-on. Therefore, the system has stronger independence and robustness, avoids startup abnormalities or function failures caused by external instruction delay, absence or system reset, significantly improves the stability and reliability of the system, and is especially suitable for scenes that need to start quickly or autonomously run in harsh environments.

[0043] In some embodiments of the present application, the system further comprises: A trusted computing module is in communication connection between the ROM writing module and the ROM reading and writing module. The trusted computing module is used for trusted computing processing of the ROM writing instruction and sending the trusted computing processed ROM writing instruction to the ROM reading and writing module.

[0044] The trusted computing module is a hardware or software module specially used for performing security-related computing tasks, aiming to ensure the integrity, authenticity and confidentiality of data. The module can be a separate hardware security module (HSM), such as a trusted platform module (TPM) chip integrated on the system mainboard, or a special logic area embedded in FPGA or CPLD, which realizes encryption, signature and other functions through hardware logic. Trusted computing processing refers to a series of security operations on data or instructions to verify their source, integrity or encryption protection, to prevent unauthorized access or tampering. The processing can be encryption of the ROM writing instruction to ensure that only the authorized ROM reading and writing module can decrypt and execute; or digital signature of the ROM writing instruction, which is verified by the ROM reading and writing module after receiving to confirm the authenticity and integrity of the instruction.

[0045] The embodiment can effectively verify the authenticity, integrity and legality of the source of the ROM writing instruction. This significantly enhances the system's defense capability against malicious tampering and unauthorized writing, ensuring the security and reliability of the configuration data and program code stored in the ROM module, thereby avoiding system function abnormalities, security vulnerabilities or unpredictable behavior caused by ROM content destruction. Compared with the scheme that only relies on the control master device to send instructions, the embodiment adds a key security verification link in the instruction transmission and processing process, providing a higher level of security protection for the entire power-on and power-off timing control system.

[0046] In some embodiments of the present application, the system further comprises: The trusted verification module is in communication connection with the ROM read-write module and the second analysis module, and is configured to perform a verification process on the trusted computing process of the ROM read instruction and send the ROM read instruction after the verification process to the second analysis module.

[0047] The trusted verification module is a functional unit specially used for verifying data integrity and authenticity. Its role is to ensure that the data read from the ROM module is authorized and has not been tampered with. This module can be implemented as a separate hardware circuit, which is specially used to execute specific verification algorithms. It can also be a firmware or software function embedded in a microcontroller or processor, which uses its computing resources to perform complex verification operations. In some cases, this module can also be combined with a hardware accelerator, such as using the encryption instruction set of the central processing unit (CPU) to accelerate the verification process. The verification process corresponding to the trusted computing process of the ROM read instruction aims to verify the integrity and authenticity of the ROM read instruction, ensuring that it matches the trusted computing process performed when writing. Specifically, if the trusted computing process is an encryption operation, the verification process can be to decrypt the read instruction and further verify whether the decrypted data conforms to the expected format or contains specific security identifiers. If the trusted computing process is digital signature authentication, the verification process can be to verify the digital signature of the read instruction using the corresponding public key. If the trusted computing process involves error correction coding, the verification process can be to decode the read instruction and check for errors, or recalculate the check code and compare it with the read check code. For custom trusted computing algorithms, the verification process is the decryption or verification process corresponding to the custom algorithm.

[0048] The embodiment further enhances the security guarantee of the system for the ROM read instruction on the basis of ensuring the trustworthiness of the ROM write instruction. The introduction of the trusted verification module enables the system to strictly verify the integrity and authenticity of the instruction read from the ROM module before processing it. This effectively avoids system running errors, configuration abnormalities, or potential security vulnerabilities caused by reading unauthorized modified or damaged instructions, significantly improves the overall reliability, stability, and security of the power-on and power-off timing control system, and ensures the accurate execution of critical timing configuration and control instructions.

[0049] In some embodiments of the present application, the trusted computing process includes any one of an encryption algorithm, a signature authentication algorithm, an error correction coding algorithm, and a custom encryption algorithm.

[0050] Among them, the encryption algorithm is used to convert the data, so that it cannot be understood without authorization, thereby protecting the confidentiality of the data. Common implementations include symmetric encryption algorithms such as Advanced Encryption Standard (AES) or asymmetric encryption algorithms such as RSA. Signature authentication algorithm is used to verify the source and integrity of the data, to ensure that the data has not been tampered with during transmission or storage. For example, a hash-based message authentication code (HMAC) or a digital signature algorithm such as Elliptic Curve Digital Signature Algorithm (ECDSA) can be used. Error correction coding algorithm is used to add redundant information in the data, so that when errors occur during data transmission or storage, these errors can be detected and corrected, thereby improving the reliability of the data. For example, cyclic redundancy check (CRC) or Reed-Solomon code can be used for this purpose. Custom encryption algorithm refers to the encryption mechanism designed and implemented according to the specific application scenario or security requirements. This can be a proprietary algorithm adopted to adapt to specific hardware resource limitations, or to increase the difficulty of cracking.

[0051] The embodiment can more effectively guarantee the security and accuracy of the key configuration and control instructions of the power-on and power-off timing control system, thereby improving the stability and reliability of the entire system, and avoiding system failure caused by unsafe or incorrect instructions.

[0052] In some embodiments of the present application, the system further comprises: The ID authentication module is in communication connection between the control interface and the first analysis module, and the ID authentication module is used for ID authentication of the control instruction, and sends the ID authenticated control instruction to the first analysis module, and ID packages the first feedback signal and the second feedback signal, and sends the ID package to the control interface.

[0053] Among them, the ID authentication module is a hardware or software unit used to perform identity verification and data integrity check. Its role is to ensure that the received control instruction comes from an authorized control master device and has not been tampered with during transmission.

[0054] ID authentication of the control instruction aims to verify the authenticity and integrity of the control instruction, and its purpose is to prevent an unauthorized entity from sending malicious instructions or tampering with legitimate instructions. The implementation can include but is not limited to: calculating a message authentication code (MAC) for the control instruction and comparing it with the expected MAC; using digital signature technology to confirm its source and integrity by verifying the digital signature of the instruction; or adopting a challenge-response mechanism to verify the identity of the control master device through an interactive protocol. The ID authenticated control instruction is sent to the first parsing module, which means that only the control instruction that passes the ID authentication will be forwarded to the first parsing module for subsequent processing, and this step ensures that the first parsing module only processes trusted instructions, thereby ensuring the security of the entire system. ID packaging of the first feedback signal and the second feedback signal aims to ensure the integrity and authenticity of the feedback signal sent by the system to the control master device, and its purpose is to prevent the feedback signal from being tampered with or forged during transmission, thereby misleading the control master device. The implementation can include but is not limited to: encrypting the feedback signal to protect its content from eavesdropping and tampering; attaching a message authentication code or digital signature to the feedback signal to verify its source and integrity; or packaging the feedback signal in a specific data packet format with a security verification mechanism. The ID packaged feedback signal is sent to the control interface, which means that only the feedback signal that has passed the ID packaging will be sent to the control interface and then uploaded to the control master device, and this step ensures that the feedback information received by the control master device is trustworthy, providing a reliable basis for the correct decision of the system.

[0055] The power-up and power-down timing control system of the present embodiment can effectively verify the legality and integrity of the instruction when receiving the control instruction, avoiding potential harm to the system caused by illegal or tampered instructions. At the same time, when uploading the feedback signal, the system can ensure the authenticity and non-tampering of the feedback information, thereby providing a reliable system state basis for the control master device. This significantly improves the security, reliability and stability of the entire power-up and power-down timing control system, effectively preventing system malfunctions or abnormal functions caused by instruction forgery or feedback tampering, and ensuring the normal operation of critical equipment.

[0056] In some embodiments of the present application, ID authentication includes any one of HMAC, MD5, SHA1, SHA256, and a custom authentication method.

[0057] By explicitly employing any one of HMAC, MD5, SHA1, SHA256, or a custom authentication method in the ID authentication module, this embodiment significantly improves the security and reliability of control command and feedback signal transmission. Compared to providing only generalized ID authentication, these specific cryptographic algorithms offer quantifiable security guarantees, effectively preventing unauthorized control commands from being executed by the system and avoiding the reception of maliciously tampered or forged feedback signals by the control master device. For example, using strong hash algorithms such as HMAC or SHA256 can effectively resist message tampering attacks and replay attacks, ensuring the integrity and authenticity of control commands and the reliability of the feedback signal source. This enables the entire power-on / off timing control system to perform power-on / off timing control and status feedback more stably and securely in complex operating environments, thereby avoiding operational errors or system failures caused by security vulnerabilities.

[0058] like Figure 2 One embodiment of this application discloses a power-on / off timing control method, the method comprising: Step S110: Receive the first control command sent by the master control device.

[0059] Step S120: Parse the first control instruction to obtain the power-on / power-off timing configuration instruction.

[0060] Step S130: Configure multiple sets of registers according to the power-on / power-off timing configuration instructions.

[0061] Step S140: Generate a first feedback signal indicating that multiple sets of registers have been configured, and upload the first feedback signal to the control master device.

[0062] Step S150: Receive the second control command sent by the master control device.

[0063] Step S160: Parse the second control command to obtain the power-on / power-off control command.

[0064] Step S170: Based on the power-on / power-off control command and the configuration of multiple sets of registers, each timing channel in the multiple timing channels is controlled individually; wherein, each timing channel includes multiple feedback input paths and multiple feedback input paths.

[0065] Step S180: Generate a second feedback signal containing the power-on / power-off status of each timing channel and the status of multiple feedback input paths for each timing channel, and upload the second feedback signal to the control master device.

[0066] It should be noted that this embodiment is based on the same inventive concept as the above system embodiment, and will not be described in detail here.

[0067] likeFigure 1 As shown for ease of understanding, the application discloses a power-on / off timing control circuit, system and method as follows: (1) Control interface; the control interface is a communication channel for realizing the exchange of control instructions and state information between the main control device (including but not limited to CPU, MCU, host computer, etc.) and the controller, including but not limited to UART, SPI, QSPI, CAN, I2C, USB, SDIO, network interface, PCIE, Aurora, SRIO, AXI, AHB, APB, etc. Various on-chip / off-chip communication interfaces capable of realizing information exchange.

[0068] (2) ROM module; the ROM module is a device or component for realizing multiple write and read of timing information without loss of power, including but not limited to flash, EEPROM, disk, optical disk, solid state disk, etc. Various storage media.

[0069] (3) Physical switch module: the physical switch is a device or component for realizing manual control operation of the controller power-on / off, reset, etc., including but not limited to various types of jog, dial, rotary, touch, relay, etc. Various physical switches.

[0070] (4) n groups of timing channels (n is a positive integer), each group of timing channels includes m timing output paths and p feedback input paths (m, p are positive integers.

[0071] (5) ID authentication module; the ID authentication module is an authorized identity authentication for the control main device, and the data sent by the unauthorized control main device is ignored. For the authorized control main device: the sent data is transmitted to the first analysis module; the state information package is sent to the authorized main device. The identity authentication method includes but is not limited to HMAC, MD5, SHA1, SHA256, and self-defined authentication method, etc. Soft / hardware method that can realize identity authentication; (6) First analysis module; the first analysis module analyzes the instructions sent by the ID authentication module, and obtains ROM write instruction, ROM read instruction, first power-on / off timing configuration instruction, first power-on / off control instruction, and sequentially transmits them to ROM write module, ROM read module, power-on / off timing configuration module and timing channel mapping and start control module; the data packet of the first feedback signal and the second feedback signal reported by the state reading module is packaged and sent to the ID authentication module; (7) State reading module; the state reading module obtains the power-on / off state of the n timing channels and the power-on / off timing configuration state, and forms the first feedback signal and the second feedback signal after arrangement and reports to the first analysis module.

[0072] (8) ROM write module, receiving the ROM write instruction sent by the first analysis module, and after necessary processing such as bit width conversion and instruction format processing, sending to the trusted computing module.

[0073] (9) ROM read module, sending the ROM read instruction to the ROM read-write module.

[0074] (10) ROM read-write module, writing the data sent by the trusted computing module into the ROM module; receiving the reset instruction sent by the ROM read module or the third analysis module, reading out the data stored in the ROM module and sending to the trusted verification module.

[0075] (11) Trusted computing module, the trusted computing module realizes the trusted computing processing of the data sent by the ROM write module, and sends the trusted data obtained to the ROM read-write module; the trusted computing can include but is not limited to encryption algorithm, signature authentication algorithm, error correction coding algorithm, and other self-defined methods that can improve the security and reliability of data storage.

[0076] (12) Trusted verification module, the trusted verification module realizes the trusted verification of the read-out data, and sends the data passed by the verification to the second analysis module; the trusted verification must correspond to the trusted computing method described in the trusted computing module.

[0077] (13) Second analysis module, realizing the instruction analysis of the data sent by the trusted verification module, obtaining the second power-on / off timing configuration instruction and the second power-on / off control instruction, and sending the second power-on / off timing configuration instruction to the power-on / off timing configuration module, and sending the second power-on / off control instruction to the timing channel mapping and start control module; (14) Power-on / off timing configuration module, used for receiving the power-on / off timing configuration instruction from the first analysis module or the second analysis module, configuring the corresponding register in the timing channel mapping and start control module, and feeding back the state signal (i.e. the first feedback signal) of the configuration completion to the state reading module after the configuration is completed.

[0078] (15) Timing channel mapping and start control module, receiving the power-on / off control instruction from the first analysis module or the second analysis module or the third analysis module, performing multi-group timing channel control, and feeding back the state signal (i.e. the second feedback signal) of the corresponding timing channel to the state reading module after the completion.

[0079] (16) Third analysis module, connected with the physical switch module. Used for generating reset instruction and power-on or power-off instruction.

[0080] The output timing branch waveform information, the input feedback branch normal reference information and the feedback delay information are configured according to the timing channel mapping configuration; a timing start control instruction is received, a timing waveform is generated and output; after the timing waveform output is completed, the corresponding feedback branch signal is read after a delay waiting, the success / failure signal of the channel power-on / power-off is obtained, and is reported to the state reading module.

[0081] The implementation mode of the power-on and power-off timing control system and method can be FPGA, CPLD, other programmable logic circuit, special logic circuit or chip, hardware circuit or combination of several or all of the above, and can be a computer device or instrument, a software method, etc. capable of millisecond-level fast power-on, logic processing calculation and data exchange.

[0082] The method comprises: (1) The control interface power-on / power-off configuration and start process comprises: Step S210: the control host device sends a control instruction (including a timing configuration data packet) to the ID authentication module through the control interface; Step S220: after receiving the data packet, the ID authentication module first performs ID authentication on the data packet, and after passing the authentication, sends the control instruction to the first analysis module; Step S230: the first analysis module analyzes the received information and obtains a first power-on / power-off timing configuration instruction, and sends the first power-on / power-off timing configuration instruction containing the configuration information to the power-on / power-off timing configuration module; Step S240: the power-on / power-off timing configuration module completes the configuration of the corresponding registers in the timing channel mapping and start control module according to the received configuration information, and feeds back a configuration completion state signal (i.e. first feedback information) to the state reading module after the configuration is completed; Step S250: after receiving the configuration completion information, the state reading module sequentially reports the configuration completion state signal, and after sequentially passing the data format conversion of the first analysis module and the ID packet of the ID authentication module, reports to the control host device through the control interface; Step S260: after receiving the state configuration completion, the control host device sends a control instruction to the ID authentication module through the control interface; Step S270: after receiving the instruction, the ID authentication module first performs ID authentication, and after passing the authentication, sends the instruction to the first analysis module; Step S280: the first analysis module analyzes the received information and obtains a first power-on / power-off control instruction, and sends the first power-on / power-off control instruction to the timing channel mapping and start control module; Step S290: After the timing channel mapping and start control module receives the first power-on / off control instruction, it starts the power-on / off timing output of specific, partial or all timing channels; and after the waveform output is completed, it collects the power-on / off completion state information (i.e. second feedback information) of each group of timing channels; Step S300: The power-on / off completion state information passes through the state reading module, the first analysis module, the ID authentication module and its internal processing in turn, and is reported to the control master device through the control interface.

[0083] (2) The control interface power-on / off configuration and power-on / off instruction writing ROM module process includes: Step S410: The control master device sends a control instruction (including a ROM writing data packet, including timing configuration and start instruction) to the ID authentication module through the control interface; Step S420: After the ID authentication module receives the instruction, it first performs ID authentication, and after passing the authentication, it issues the instruction to the first analysis module; Step S430: The first analysis module analyzes the received data to obtain the ROM writing instruction, and issues it to the ROM writing module; Step S440: The ROM writing module receives the ROM writing instruction sent by the first analysis module, and after necessary processing such as bit width conversion and instruction format processing, it sends it to the trusted computing module; Step S450: The trusted computing module performs trusted computing processing on the sent data, and sends the obtained trusted data to the ROM read / write module; Step S460: The ROM read / write module writes the data sent by the trusted computing module into the ROM module.

[0084] (3) The control interface reads the ROM to perform power-on / off control process includes: Step S510: The control master device sends a control instruction (including a ROM reading instruction packet) to the ID authentication module through the control interface; Step S520: After the ID authentication module receives the information packet, it first performs data packet ID authentication, and after passing the authentication, it issues the data to the first analysis module; Step S530: The first analysis module analyzes the received data to obtain the ROM reading instruction, and issues it to the ROM reading module; Step S540: The ROM reading module sends the ROM reading instruction (including but not limited to address, length, etc.) to the ROM read / write module; Step S550: After the ROM read / write module receives the ROM reading instruction information, it reads out the corresponding data in the ROM module and sends it to the trusted verification module; Step S560: The trusted verification module performs trusted verification on the received data, and sends the data stream that passes the verification to the second analysis module; Step S570: The second analysis module analyzes the received information and obtains a second power-on / power-off control instruction, and sends the instruction to the timing channel mapping and starting control module; Step S580: After receiving the second power-on / power-off control instruction, the timing channel mapping and starting control module starts the power-on / power-off timing output of specific, partial or all timing channels, and collects the power-on / power-off completion state information of each group of timing channels after the waveform output is completed. Step S590: The power-on / power-off completion state information passes through the state reading module, the first analysis module, the ID authentication module and its internal processing in sequence, and is reported to the control master device through the control interface.

[0085] (4) The ROM read power-on / power-off process of the controller initial power-on or physical switch reset includes: Step S610: After the controller initial power-on or physical switch generates a reset signal, a reset instruction is generated, and ROM read instruction information (including but not limited to address, length, etc.) is sent to the ROM read / write control module; Step S620: Repeat the steps in (3), which are not repeated here.

[0086] (5) The physical switch module control power-on / power-off control process includes: Step S710: The physical switch generates a power-on / power-off control signal and sends it to the third analysis module; Step S720: The third analysis module receives the signal and analyzes the power-on or power-off control instruction, and sends it to the timing channel mapping and starting control module; Step S730: After receiving the power-on or power-off control instruction, the timing channel mapping and starting control module starts the power-on / power-off timing output of specific, partial or all timing channels, and collects the power-on / power-off completion state information of each group of timing channels after the waveform output is completed. Step S740: The power-on / power-off completion information passes through the state reading module, the first analysis module, the ID authentication module and its internal processing in sequence, and is reported to the control master device through the control interface.

[0087] The embodiment has the following beneficial effects: (1) Realize n groups of independent timing channels, each group of timing channels is independently controlled; and each group has m-way timing waveform output branch and p-way feedback signal input branch, and the waveform information of each timing waveform output branch can be independently configured, and the reference information of the feedback signal can also be configured; equipped with physical switch for emergency power-on / off control. The above features ensure that the embodiment can effectively manage the power-on / off control of different chassis and different devices in the same chassis when facing the power-on / off control and management of the chassis or chassis cluster; (2) Fast power-on speed, can replace special power-on digital circuit or special chip. Because of the use of FPGA / CPLD or other devices or equipment that can be powered on in milliseconds, the embodiment can store the power-on / off control instructions in the ROM module, and in normal cases, it does not need to be controlled through the control interface or physical switch: after the system is powered on, the controller is powered on first, then reads the instruction information in the ROM, and can start the power-on / off timing waveform output of the controlled target device within milliseconds; (3) The embodiment adds an ID authentication module behind the control interface, which refuses unauthorized users to control the power-on / off of the target device or change the built-in information of the ROM module; the instruction information stored in the embodiment in the ROM is subjected to trusted processing, improving the security and reliability of data storage.

[0088] The above only describes the embodiments of the present application and does not limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A power-on / off timing control system, characterized in that, The system includes: Multiple timing channels, each of which includes multiple timing output paths and multiple feedback input paths; A control interface is communicatively connected to a master control device. The control interface is used to receive control commands from the master device and to upload a first feedback signal and a second feedback signal to the master device. The first parsing module is communicatively connected to the control interface. The first parsing module is used to parse the control command to obtain a first parsed command; when the first parsed command is a first power-on / power-off timing configuration command, the first power-on / power-off timing configuration command is sent to the power-on / power-off timing configuration module; when the first parsed command is a first power-on / power-off control command, the first power-on / power-off control command is sent to the timing channel mapping and start control module; and receive the first feedback signal and the second feedback signal, and upload the first feedback signal and the second feedback signal to the control interface. The power-on / power-off timing configuration module is communicatively connected to the first parsing module and the timing channel mapping and startup control module. The power-on / power-off timing configuration module is used to configure the corresponding registers in the timing channel mapping and startup control module according to the first power-on / power-off timing configuration instruction. The timing channel mapping and start-up control module is communicatively connected to the multiple sets of timing channels. The timing channel mapping and start-up control module is used to control each set of timing channels individually according to the first power-on / power-off control command. The status reading module is communicatively connected to the power-on / power-off timing configuration module and the multiple sets of timing channels. The status reading module is used to obtain the first feedback signal indicating that the register configuration of the power-on / power-off timing configuration module is complete, and upload the first feedback signal to the first parsing module; and to obtain the second feedback signal containing the power-on / power-off status of each set of timing channels, and the status of multiple feedback input paths of each set of timing channels, and upload the second feedback signal to the first parsing module.

2. The power-on / off timing control system according to claim 1, characterized in that, The system also includes: ROM module; The ROM writing module is communicatively connected to the first parsing module. The ROM writing module is used to send the ROM writing instruction to the ROM read / write module when the first parsed instruction is a ROM write instruction. The ROM reading module is communicatively connected to the first parsing module. The ROM reading module is used to send the ROM reading instruction to the ROM read / write module when the first parsed instruction is a ROM read instruction. The ROM read / write module is communicatively connected to the ROM write module and the ROM read module. The ROM read / write module is used to write the corresponding ROM write data into the ROM module according to the ROM write instruction and extract the corresponding ROM read data from the ROM module according to the ROM read instruction. The second parsing module is communicatively connected to the ROM read / write module, the power-on / power-off timing configuration module, and the timing channel mapping and startup control module. The second parsing module is used to parse the ROM read data to obtain a second parsed instruction. If the second parsed instruction is a second power-on / power-off control instruction, the second power-on / power-off control instruction is sent to the timing channel mapping and startup control module. If the second parsed instruction is a second power-on / power-off control instruction, the second power-on / power-off control instruction is sent to the power-on / power-off timing configuration module. The power-on / power-off timing configuration module is also used to configure the corresponding registers in the timing channel mapping and startup control module according to the second power-on / power-off control command; The timing channel mapping and start-up control module is also used to individually control each group of timing channels according to the second power-on / power-off control command.

3. The power-on / off timing control system according to claim 2, characterized in that, The system also includes: The trusted computing module is communicatively connected to the ROM writing module and the ROM read / write module. The trusted computing module is used to perform trusted computing processing on the ROM write command and send the ROM write command after trusted computing processing to the ROM read / write module.

4. The power-on / off timing control system according to claim 3, characterized in that, The system also includes: The trusted verification module is communicatively connected to the ROM read / write module and the second parsing module. The trusted verification module is used to perform verification processing on the ROM read instruction corresponding to the trusted calculation processing, and send the verified ROM read instruction to the second parsing module.

5. The power-on / off timing control system according to claim 4, characterized in that, The trusted computing process includes any one of the following: encryption algorithm, signature authentication algorithm, error correction coding algorithm, and custom encryption algorithm.

6. The power-on / off timing control system according to claim 1, characterized in that, The system also includes: The ID authentication module is communicatively connected to the control interface and the first parsing module. The ID authentication module is used to perform ID authentication on the control command, send the ID-authenticated control command to the first parsing module, and encapsulate the first feedback signal and the second feedback signal into ID packets, and send the ID packets to the control interface.

7. The power-on / off timing control system according to claim 6, characterized in that, The ID authentication includes any one of HMAC, MD5, SHA1, SHA256, and custom authentication methods.

8. The power-on / off timing control system according to claim 2, characterized in that, The system also includes: The physical switch module is used to generate physical control commands; The third parsing module is communicatively connected to the physical switch module and is used to parse the physical control command to obtain the third parsed command. If the third parsed command is a reset control command, the reset control command is sent to the ROM read / write module. If the third parsed command is a power-on or power-off control command, the power-on or power-off control command is sent to the timing channel mapping and startup control module. The ROM read / write module is also used to perform a reset after receiving the reset control command; The timing channel mapping and start control module is also used to perform corresponding power-on or power-off control on the multiple sets of timing channels after receiving the power-on or power-off control command.

9. A power-on / off timing control circuit, characterized in that, The circuit includes one or more combinations of FPGA, CPLD, other programmable logic circuits, dedicated logic circuits or chips, and hardware circuits. The circuit is equipped with a power-on / off timing control system as described in any one of claims 1 to 8.

10. A power-on / off timing control method, characterized in that, The method includes: Receive the first control command sent by the master control device; The first control command is parsed to obtain the power-on / power-off timing configuration command; Based on the power-on / power-off timing configuration instructions, complete the configuration of multiple sets of registers; Generate a first feedback signal indicating that the configuration of the multiple sets of registers is complete, and upload the first feedback signal to the control master device; Receive the second control command sent by the main control device; The second control command is parsed to obtain the power-on / power-off control command; Based on the power-on / power-off control commands and the configuration of the multiple sets of registers, each of the multiple sets of timing channels is individually controlled; wherein, each set of timing channels includes multiple feedback input paths and multiple feedback input paths. A second feedback signal is generated, which includes the power-on / power-off state of each group of timing channels, and the states of multiple feedback input paths and multiple feedback input paths of each group of timing channels. The second feedback signal is then uploaded to the control master device.

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