A memory control method, a storage device, a medium and a computer device

Abstract

The present application relates to the technical field of storage control, in particular to a memory control method, a storage device, a medium and a computer device, a three-level index structure is set, wherein only a primary root table is resident cache, bit operation is used to quickly extract index to reduce cache occupation and invalid IO overhead, the search range is reduced through the hash bucket of the three-level page table, the conflict is solved through the linked list, and the fixed structure can improve the mapping efficiency and system stability; the secondary block table and the three-level page table are loaded without blocking the CPU, so that the bandwidth is saved, the concurrent performance and the cache hit rate are improved. Through the overall scheme of three-level index, chained hash table, on-demand loading and bit operation, the whole process delay from logical address input to physical address output is significantly reduced, and the low delay requirement of the high-performance storage system is met; the three-level index structure supports flexible adjustment of the size of the root table, the block table and the page table, adapts to storage devices of different capacities, and has good scalability.

Description

TECHNICAL FIELD

[0001] The application relates to a memory control method, a storage device, a medium and a computer device, and belongs to the technical field of memory control. BACKGROUND

[0002] Nand Flash is a kind of non-volatile storage medium, which is widely used in SD, eMMC, UFS, SSD and other storage products. Due to the characteristic that NAND Flash cannot be overwritten, when data is updated, it will not be directly overwritten, but will be written to a new physical address.

[0003] In a NAND Flash storage device, FTL (Flash Translation Layer) realizes data addressing through a logical address to physical address mapping table (L2P table, Logical-to-Physical Mapping Table), and the performance directly determines the read-write efficiency of the storage device. There are mainly two paradigms in the traditional L2P mapping mechanism: one is a single-layer continuous array structure, and the other is a multi-level page table structure.

[0004] The single-layer continuous array structure sequentially stores all the mapping relationships. For a large-capacity storage device (such as a 4TB SSD), its logical address space can be as high as 1 billion entries (1e9), and if each entry occupies 8 bytes, the entire L2P table requires about 8GB of memory, which is far beyond the capacity limit of SRAM (Static Random-Access Memory) in DRAM-Less embedded devices.

[0005] To reduce memory occupation, the prior art adopts a multi-level page table mechanism to store the entire mapping table in pages in the flash memory, and only the active part is loaded into the SRAM. However, when dealing with random read-write access, this method needs to access the flash memory multiple times to load the page table level by level (for example, a four-level page table structure needs 4 flash memory accesses), resulting in a single address conversion delay of more than 120μs, which becomes the main bottleneck of system performance. In addition, the traditional index calculation method relies on division or modulo operation, which requires 10-15 clock cycles on embedded processors, and is inefficient. When the storage capacity is upgraded, the existing page table structure usually needs to be redesigned, and the scalability is poor.

[0006] The core defects of the prior art can be summarized as follows: in DRAM--less products, the contradiction between "memory occupation" and "access performance" cannot be reconciled. The single-layer mapping table occupies too much memory, and although the multi-level paging reduces the memory occupation, it introduces unacceptable performance jitter due to multiple accesses to the NAND Flash (whose access delay is more than 1,000 times that of DRAM). SUMMARY

[0007] In view of the deficiencies of the prior art, the present application aims to provide a memory control method, a storage device, a medium and a computer device.

[0008] In a first aspect, according to an embodiment of the present application, a first scheme is provided, which is a memory control method applied to a storage device comprising a non-volatile storage medium and a cache unit, the method comprising:

[0009] A three-level index structure is constructed, which comprises a first-level root table, a second-level block table and a third-level page table, wherein the first-level root table is resident in the cache unit, the second-level block table is loaded into the cache unit on demand, and the third-level page table is loaded into the cache unit on demand, and the third-level page table adopts a chained hash table structure, and each third-level page table comprises a fixed-size hash bucket array and a mapping entry node linked list.

[0010] The logical address requested by the host is obtained, and the index value of the three-level index structure is extracted through bit operation;

[0011] The root table entry in the first-level root table is located according to the root table index of the index value to obtain the block table physical page number, and if the block table is not in the cache unit, DMA is triggered to load the second-level block table from the non-volatile storage medium into the block table cache area;

[0012] The block table entry in the second-level block table is located according to the block table index of the index value to obtain the page table physical page number, and if the page table is not in the cache unit, DMA is triggered to load the third-level page table into the page table cache area;

[0013] After locating the corresponding third-level page table according to the page table index of the index value, the hash value is calculated, the hash bucket in the third-level page table is located through the hash value, the mapping entry node linked list corresponding to the hash bucket is traversed to find the mapping entry node matching the logical address, and the physical page number stored in the mapping entry node is extracted as the physical address of the actual stored data in the non-volatile storage medium, thereby completing the mapping conversion from the logical address to the physical page number.

[0014] Further, the cache unit is SRAM, and the non-volatile storage medium is NAND Flash.

[0015] Further, the first-level root table is a fixed array resident in the cache unit, the first-level root table comprises R root table entries, and each root table entry of the first-level root table points to the physical page number and valid bit of the second-level block table;

[0016] The second-level block table is an array loaded into the cache unit on demand, the second-level block table comprises B block table entries, and each block table entry of the second-level block table points to the physical page number and valid bit of the third-level page table;

[0017] Each page table of the three-level page table contains P logical page management modules, the size of the hash bucket array of the chained hash table is H, and the head insertion method is used to insert a new node in the linked list.

[0018] Further, when the valid bit of the root table entry is 1, the physical page number of the secondary block table pointed to by the root table entry is valid, and when the valid bit of the block table entry is 1, the physical page number of the three-level page table pointed to by the block table entry is valid.

[0019] Further, the primary root table adopts double-copy backup.

[0020] The primary root table has two independent copies stored in the NAND Flash, and the two copies are located in different physical blocks.

[0021] When the root table needs to be updated, one of the copies is updated first, and the writing success is verified, and then the other copy is updated.

[0022] If an abnormal power failure occurs during the updating process, the next time the power is turned on, the integrity of the two copies is checked to select the valid copy to load to the SRAM.

[0023] Further, each node of the mapping entry node linked list contains a logical address LBA, a physical page number PPN, and a pointer to the next node.

[0024] Further, the step of extracting the index value of the three-level index structure through bit operation includes:

[0025] The total logical address space bit width W of the storage device, the number R of primary root table entries, and the number B of secondary block table entries are obtained.

[0026] The right shift number S1 of the root table is calculated as S1 = W - log2(R), and the root table index is extracted through right shift operation: root_index = LBA >> S1.

[0027] The right shift number S2 of the block table is calculated as S2 = W - log2(R) - log2(B), and the block table mask M_b is determined as M_b = B - 1, and the block table index is extracted through right shift and bitwise AND operation: block_index = (LBA >> S2) & M_b.

[0028] The right shift number S3 of the page table is calculated as S3 = log2(Page_Size), where Page_Size is the logical page size of the storage device, and the page table mask M_p is determined as M_p = P - 1, where P is the number of logical page management modules, and the page table index is extracted through right shift and bitwise AND operation: page_index = (LBA >> S3) & M_p.

[0029] Further, the step of loading the secondary block table to the cache unit on demand includes:

[0030] When the valid bit of the root table entry located according to the root table index value is 1, and the corresponding secondary block table is not stored in the cache unit, DMA is triggered to load the secondary block table from the non-volatile storage medium to the block table cache area.

[0031] Further, the block table cache area uses an LRU algorithm as a cache replacement strategy, which maintains the access bit and the dirty bit of each block table. When the cache area capacity reaches a preset threshold, the longest non-dirty block table is preferentially replaced. If the block table to be replaced is in a dirty state, it is persisted to the non-volatile storage medium by an atomic write-back mechanism before replacement.

[0032] Further, it further comprises a dirty data write-back step:

[0033] The block table to be replaced is marked as dirty;

[0034] Periodic write-back and conditionally triggered write-back dirty data are combined: periodic write-back is to write back the dirty block table to the NAND Flash every preset time interval; when the number of dirty block tables reaches a threshold or cache replacement needs to replace a dirty block table, the corresponding dirty block table is written back to the NAND Flash;

[0035] After the write-back is successful, the dirty state flag of the block table is cleared.

[0036] Further, the execution step by the atomic write-back mechanism comprises:

[0037] Write the update content of the primary root table to the log area of the NAND Flash;

[0038] Verify that the content of the log area is successfully written;

[0039] Update the primary copy of the primary root table based on the log content;

[0040] If there is an abnormal power failure, the primary root table is restored to a consistent state by the content of the log area next time the power is turned on.

[0041] Further, the step of loading the tertiary page table to the cache unit on demand comprises:

[0042] When the valid bit of the block table entry located according to the block table index value is 1, and the corresponding tertiary page table is not stored in the cache unit, DMA is triggered to load the tertiary page table from the non-volatile storage medium to the page table cache area.

[0043] Further, the step of calculating the hash value and locating the hash bucket in the tertiary page table by the hash value comprises:

[0044] Obtain a preset size H of the system array in the tertiary page table;

[0045] The logical address of the host request is subjected to a modulo operation to obtain a hash value: hash = LBA % H;

[0046] According to the hash value hash, a corresponding hash bucket in the three-level page table is located.

[0047] Further, the step of searching for a mapping entry node matching the logical address in the hash bucket corresponding mapping entry node linked list includes:

[0048] Starting from the head of the mapping entry node linked list corresponding to the hash bucket, the step of searching for a mapping entry node matching the logical address in the hash bucket corresponding mapping entry node linked list includes:

[0049] Comparing the logical address stored in each node with the logical address of the host request in turn;

[0050] If a node matching the logical address of the host request is found, the node is determined to be the matching mapping entry node.

[0051] If the end of the linked list is reached and no matching node is found, it is determined that the logical address has no corresponding mapping entry node.

[0052] Further, the method further includes the steps of:

[0053] After obtaining the logical address of the host request, the number of root table entries R of the first-level root table, the number of block table entries B of the second-level block table, and the number of logical page management modules P of the third-level page table are adjusted according to the access locality of the logical address;

[0054] When the continuous access proportion exceeds the access preset value, the number of block table entries B of the second-level block table is increased to reduce the prefetch overhead;

[0055] When the hot spot area is concentrated in a small number of logical address spaces, the number of logical page management modules P of the third-level page table is reduced to improve the loading efficiency of the hot spot page table;

[0056] The adjusted granularity parameters are written atomically to the non-volatile storage medium in a log structure.

[0057] According to the embodiments of the present application, the memory control method provided in the first scheme is used, and the second scheme is provided:

[0058] In a second aspect, a storage device is used to apply the memory control method of any one of the first aspect, and the storage device includes:

[0059] a three-level index construction module, configured to construct a three-level index structure, the three-level index structure comprising a first-level root table, a second-level block table and a third-level page table, wherein the first-level root table is resident in a cache unit, the second-level block table is loaded into the cache unit on demand, the third-level page table is loaded into the cache unit on demand, and the third-level page table adopts a chained hash table structure, and the chained hash table of each third-level page table comprises a fixed-size hash bucket array and a mapping entry node linked list;

[0060] a request acquisition module, configured to acquire a logical address requested by a host, and extract an index value of the three-level index structure through bit operation;

[0061] a root table processing module, configured to locate a root table entry in the first-level root table according to a root table index of the index value to acquire a block table physical page number, and trigger DMA to load the second-level block table into a block table buffer area from a non-volatile storage medium if the block table is not in the cache unit;

[0062] a block table processing module, configured to locate a block table entry in the second-level block table according to a block table index of the index value to acquire a page table physical page number, and trigger DMA to load the third-level page table into a page table buffer area if the page table is not in the cache unit;

[0063] a page table processing module, configured to locate a corresponding third-level page table according to a page table index of the index value, calculate a hash value, locate a hash bucket in the third-level page table through the hash value, traverse a mapping entry node linked list corresponding to the hash bucket to find a mapping entry node matching the logical address, extract a physical page number stored in the mapping entry node as a physical address of actually stored data in the non-volatile storage medium, and complete mapping conversion of the logical address to the physical page number.

[0064] In a third aspect, a computer device includes a memory and a processor, the memory storing a computer program, and the computer program, when executed by the processor, causes the processor to perform the following steps:

[0065] constructing a three-level index structure, the three-level index structure comprising a first-level root table, a second-level block table and a third-level page table, wherein the first-level root table is resident in a cache unit, the second-level block table is loaded into the cache unit on demand, the third-level page table is loaded into the cache unit on demand, and the third-level page table adopts a chained hash table structure, and the chained hash table of each third-level page table comprises a fixed-size hash bucket array and a mapping entry node linked list;

[0066] acquiring a logical address requested by a host, and extracting an index value of the three-level index structure through bit operation;

[0067] locating a root table entry in the first-level root table according to a root table index of the index value to acquire a block table physical page number, and triggering DMA to load the second-level block table into a block table buffer area from a non-volatile storage medium if the block table is not in the cache unit;

[0068] The block table index according to the index value is used to locate a block table entry in the secondary block table to obtain a page table physical page number, and if the page table is not in the cache unit, DMA is triggered to load the tertiary page table into the page table cache area;

[0069] After the page table index according to the index value is located to the corresponding tertiary page table, a hash value is calculated, the hash bucket in the tertiary page table is located through the hash value, the mapping entry node chain table corresponding to the hash bucket is traversed to find the mapping entry node matching the logical address, and the physical page number stored in the mapping entry node is extracted as the physical address of the actual data stored in the non-volatile storage medium, so that the mapping conversion from the logical address to the physical page number is completed.

[0070] In a fourth aspect, a computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor executes the following steps:

[0071] A tertiary index structure is constructed, the tertiary index structure comprising a primary root table, a secondary block table and a tertiary page table, wherein the primary root table is resident in a cache unit, the secondary block table is loaded into the cache unit on demand, the tertiary page table is loaded into the cache unit on demand, and the tertiary page table adopts a chained hash table structure, and the chained hash table of each tertiary page table comprises a fixed-size hash bucket array and a mapping entry node chain table;

[0072] A logical address requested by a host is obtained, and an index value of the tertiary index structure is extracted through bit operation;

[0073] The root table index according to the index value is used to locate a root table entry in the primary root table to obtain a block table physical page number, and if the block table is not in the cache unit, DMA is triggered to load the secondary block table from the non-volatile storage medium into the block table cache area;

[0074] The block table index according to the index value is used to locate a block table entry in the secondary block table to obtain a page table physical page number, and if the page table is not in the cache unit, DMA is triggered to load the tertiary page table into the page table cache area;

[0075] After the page table index according to the index value is located to the corresponding tertiary page table, a hash value is calculated, the hash bucket in the tertiary page table is located through the hash value, the mapping entry node chain table corresponding to the hash bucket is traversed to find the mapping entry node matching the logical address, and the physical page number stored in the mapping entry node is extracted as the physical address of the actual data stored in the non-volatile storage medium, so that the mapping conversion from the logical address to the physical page number is completed.

[0076] Compared with the prior art, the technical scheme provided by the application has the beneficial effects that:

[0077] The memory control method sets a three-level index structure, wherein only a one-level root table is cached, bit operation is used to quickly extract the index to reduce cache occupation and invalid IO overhead, the three-level page table is used to reduce the search range through a hash bucket, a chain table is used to solve the conflict, and the fixed structure can improve the mapping efficiency and system stability; the two-level block table and the three-level page table are loaded without occupying the CPU, saving bandwidth, and improving the concurrent performance and cache hit rate.

[0078] The scheme balances the resource utilization and efficiency improvement as a whole, adapts to the characteristics of the storage system, and has strong scalability with parameter adjustment. DETAILED DESCRIPTION

[0079] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0080] Among them:

[0081] Figure 1 It is a flowchart of the memory control method in an embodiment;

[0082] Figure 2 It is a schematic diagram of an overview of the dynamic three-level index architecture of the L2P table in an embodiment;

[0083] Figure 3 It is a schematic diagram of index value extraction in an embodiment;

[0084] Figure 4 It is a structural block diagram of a storage device in an embodiment;

[0085] Figure 5 It is a structural block diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0086] In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0087] Embodiment one

[0088] In view of the fact that in the prior art, in the process of data addressing by a NAND Flash storage device through a logical address to physical address mapping table, the existing multi-level page table mechanism and traditional index calculation method are inefficient, have poor scalability, and have an irreconcilable contradiction between memory occupation and access performance, the existing single-layer mapping table occupies too much memory, and although multi-level paging memory occupation is small, it introduces unacceptable performance jitter due to multiple accesses to the NAND Flash, therefore, there is an urgent need for a new solution to achieve the trade-off between resource utilization and efficiency improvement of L2P table hierarchical indexing.

[0089] To solve the above technical problems, the embodiment provides a memory control method applied to a storage device containing a non-volatile storage medium and a cache unit, as shown in the figure, comprising: Figure 1

[0090] S1: Construct a three-level index structure, which includes a first-level root table, a second-level block table, and a third-level page table, wherein the first-level root table is resident in the cache unit, the second-level block table is loaded into the cache unit as needed, and the third-level page table is loaded into the cache unit as needed, and the third-level page table adopts a chained hash table structure, and the chained hash table of each third-level page table includes a fixed-size hash bucket array and a mapping entry node linked list;

[0091] S2: Obtain the logical address requested by the host, and extract the index value of the three-level index structure through bit operation;

[0092] S3: Locate the root table entry in the first-level root table according to the root table index of the index value to obtain the block table physical page number, and if the block table is not in the cache unit, trigger DMA to load the second-level block table from the non-volatile storage medium into the block table cache area;

[0093] S4: Locate the block table entry in the second-level block table according to the block table index of the index value to obtain the page table physical page number, and if the page table is not in the cache unit, trigger DMA to load the third-level page table into the page table cache area;

[0094] S5: After locating the corresponding third-level page table according to the page table index of the index value, calculate the hash value, locate the hash bucket in the third-level page table through the hash value, traverse the mapping entry node linked list corresponding to the hash bucket to find the mapping entry node matching the logical address, extract the physical page number stored in the mapping entry node as the physical address of the actual stored data in the non-volatile storage medium, and complete the mapping conversion from the logical address to the physical page number.

[0095] The above scheme constructs a three-level index structure with the first-level root table resident in the cache unit and the second-level block table and the third-level page table loaded as needed; the index value is extracted through bit operation, the root table, the block table, and the page table are located step by step, and DMA is triggered as needed to load the block table / page table not cached. ​

[0096] Only the first level root table is resident in SRAM, the second level block table and the third level page table are loaded on demand, avoiding the waste of SRAM resources caused by the traditional full load index table, and significantly improving the utilization rate of the cache; the on-demand loading mechanism only reads the block table / page table from the NANDFlash when needed, avoiding unnecessary storage medium reading and writing, reducing IO overhead, and improving the response speed of address mapping; the index value is extracted by bit operation instead of traditional arithmetic division, modulus operation and other operations, which is faster in execution and further shortens the index positioning time.

[0097] The third level page table adopts a chained hash table structure of fixed size hash bucket array + mapping entry node linked list; the hash value is used to locate the hash bucket, and the linked list is traversed to find the matching mapping entry. The hash bucket array realizes the fast hash positioning of the logical address, greatly reduces the search range, and significantly improves the efficiency compared with linear search; the mapping entry node linked list effectively solves the hash conflict problem, ensuring that the target entry can be efficiently found even if there is a conflict; the size of the hash bucket array of each third level page table is fixed, which facilitates the implementation of memory management and cache replacement strategy, and improves the system stability.

[0098] The present scheme improves the system concurrency performance and saves bandwidth through the cooperation control of on-demand loading and DMA triggering. When the second level block table / third level page table is not in the cache, DMA is triggered to load from the non-volatile storage medium to the corresponding cache area. The DMA loading method does not occupy CPU resources, and the system can still process other host requests when loading the index table, improving the concurrency performance; only the required block table / page table is loaded, avoiding invalid data transmission and saving bandwidth resources between the storage medium and the cache; on-demand loading avoids the cache overflow caused by full loading, ensuring that the cache area always stores high-frequency access index data and improving the cache hit rate.

[0099] The memory control method of the present embodiment significantly reduces the whole process delay from logical address input to physical address output through the overall scheme of three-level index, chained hash table, on-demand loading and bit operation, meeting the low delay demand of high-performance storage systems; an optimal balance is achieved among cache occupation, IO overhead and search efficiency, adapting to the characteristics of storage systems with limited SRAM resources and high IO delay of NAND Flash; the three-level index structure supports flexible adjustment of the size of the root table, block table and page table, such as R, B and P values, adapting to storage devices of different capacities and having good scalability. The pain points of the prior art are effectively solved, and efficient, low-consumption and stable memory address mapping control is realized, providing key technical support for high-performance storage systems.

[0100] Specifically, Figure 2 The overall diagram of the dynamic three-level index architecture of the L2P table is shown, which shows the architecture of the overall scheme, and illustrates the hierarchical relationship of the three-level index and the flow of data in the SRAM and the NAND Flash.

[0101] Embodiment two

[0102] This embodiment specifically illustrates the specific implementation steps of the memory control method in embodiment one.

[0103] A memory control method applied to a storage device containing a non-volatile storage medium and a cache unit, specifically, the non-volatile storage medium is a NAND Flash, and the cache unit is an SRAM.

[0104] A three-level index structure is constructed, specifically:

[0105] The first root table is a fixed array of the resident cache unit, the first root table contains R root table entries, and the root table entries of the first root table are all directed to the physical page number and the valid bit of the second block table; when the valid bit of the root table entry is 1, the physical page number of the second block table pointed to by the root table entry is valid.

[0106] The second block table is an array loaded into the cache unit on demand, the second block table contains B block table entries, and the block table entries of the second block table are all directed to the physical page number and the valid bit of the third page table; when the valid bit of the block table entry is 1, the physical page number of the third page table pointed to by the block table entry is valid.

[0107] Each page table of the third page table contains P logical page management modules, the size of the hash bucket array of the chained hash table is H, and the new node is inserted by using the head insertion method.

[0108] Further, the first root table adopts double-copy backup: the first root table has two independent copies stored in the NAND Flash, which are located in different physical blocks; when the root table needs to be updated, one of the copies is updated first and the writing success is verified, and then the other copy is updated; if an abnormal power failure occurs during the updating process, the next time the power is turned on, the integrity of the two copies is checked to select the effective copy to load into the SRAM.

[0109] This step further adopts double-copy backup in the first root table. Due to the unreliability problems of the NAND Flash such as physical block bad block and writing bit flip, if the double copies are stored in the same physical block, the bad block will cause the double copies to fail at the same time; being in different physical blocks can achieve physical isolation, avoid single point failure, and ensure that at least one copy is alive. Double-copy backup is set in the first root table, and the first root table is the entrance of the three-level index structure, and all logical address to physical address mappings depend on the root table. If the root table is lost or damaged, the entire storage system will not be able to access data, and the double-copy backup is the last line of defense for the reliability of the root table.

[0110] The core point of the scheme is sequential update. If two copies are updated at the same time, both copies may not complete writing or write errors may occur when power is off, resulting in no valid copy available. Sequential update ensures that at least one copy is in a valid state when power is off.

[0111] Data errors may occur in the NAND Flash writing process due to interference or wear. The verification of the writing success step can confirm that the current copy is written correctly, avoid synchronizing error data to another copy, and prevent error propagation.

[0112] The above mechanism solves the reliability problem of the root table at a very low cost and is the basic guarantee for stable operation of the three-level index structure.

[0113] Each node of the mapping entry node linked list contains a logical address LBA, a physical page number PPN, and a pointer to the next node.

[0114] Embodiment Three

[0115] This embodiment specifically describes how to implement fast index value extraction by bit operation. Refer to FIG. 2. Figure 3

[0116] The steps of extracting the index value of the three-level index structure by bit operation include:

[0117] Obtain the total logical address space bit width W of the storage device, the number of first-level root table entries R, and the number of second-level block table entries B;

[0118] Calculate the right shift number S1 of the root table = W - log2(R), and extract the root table index by right shift operation: root_index = LBA >> S1;

[0119] Calculate the right shift number S2 of the block table = W - log2(R) - log2(B), and determine the block table mask M_b = B-1. Extract the block table index by right shift and bitwise AND operation: block_index = (LBA >> S2) & M_b;

[0120] Calculate the right shift number S3 of the page table = log2(Page_Size), where Page_Size is the logical page size of the storage device. Determine the page table mask M_p = P-1, where P is the number of logical page management modules. Extract the page table index by right shift and bitwise AND operation: page_index = (LBA >> S3) & M_p.

[0121] The steps of loading the second-level block table into the cache unit on demand include: when the valid bit of the root table entry located according to the root table index value is 1, and the corresponding second-level block table is not stored in the cache unit, triggering DMA to load the second-level block table from the non-volatile storage medium to the block table cache area.​

[0122] Specifically, the block table cache area adopts an LRU algorithm as a cache replacement strategy, the cache replacement strategy maintains an access bit and a dirty bit of each block table, when the cache area capacity reaches a preset threshold, the longest non-dirty block table is replaced preferentially; if the block table to be replaced is in a dirty state, the block table is persisted to a non-volatile storage medium through an atomic write-back mechanism and then the replacement is performed.

[0123] Specifically, the method further comprises a dirty data write-back step: marking the block table to be replaced as dirty; combining periodic write-back and conditionally triggered write-back of dirty data: the periodic write-back writes back the dirty block table to the NAND Flash every preset time interval; when the number of dirty block tables reaches a threshold or the cache replacement needs to swap out a dirty block table, the corresponding dirty block table is written back to the NAND Flash; after the write-back is successful, the dirty state mark of the block table is cleared.

[0124] Specifically, the execution step through the atomic write-back mechanism comprises: writing the update content of the primary root table to the log area of the NAND Flash; verifying the content writing success of the log area; updating the primary copy of the primary root table based on the log content; if an abnormal power-off occurs, the primary root table is restored to a consistent state through the content of the log area at the next power-on.

[0125] Specifically, the step of loading the tertiary page table to the cache unit on demand comprises: when the valid bit of the block table entry is 1 according to the block table index value, and the corresponding tertiary page table is not stored in the cache unit, triggering DMA to load the tertiary page table from the non-volatile storage medium to the page table cache area.

[0126] In this embodiment, the total logical address space bit width W=32 bits can support a maximum of 4GB logical address space, the number of primary root table entries R=256, the number of secondary block table entries B=128, the logical page size Page_Size=4KB, the number of tertiary page table logical page management modules P=64, the block table cache area capacity threshold: 100 block tables; the dirty block table number threshold: 50; the periodic write-back interval: 10 seconds.

[0127] The step of extracting the tertiary index by bit operation is:

[0128] Calculate the displacement parameter:

[0129] The root table right shift number S1=32-8=24;

[0130] The block table right shift number S2=32-8-7=17; the block table mask M=128-1=127;

[0131] The page table right shift number S3=12; the page table mask M=64-1=63;

[0132] Extract index:

[0133] If the host requests a logical address LBA=0x12345678:

[0134] root_index = 0x12345678>>24 = 0x12;

[0135] block_index = (0x12345678>>17)&127 = (0x12345678>>17)=0x48D →&127=0x0D;

[0136] page_index = (0x12345678>>12)&63 = (0x12345678>>12)=0x12345 →&63=0x25。

[0137] The process of loading the secondary block table on demand is as follows: check the valid bit of the root table entry corresponding to root_index=0x12; if it is 1 and the block table is not in the cache, trigger DMA to load the block table from the NAND Flash to the block table cache area.

[0138] The secondary block table uses LRU replacement, and when the number of cache block tables reaches 100, the longest non-dirty block table is replaced first.

[0139] Periodic and condition-triggered write-back of dirty data achieve efficient management of dirty data. The atomic write-back mechanism ensures that there is no data loss after power failure, solving the problem of data loss caused by abnormal power failure during table updating.

[0140] Embodiment Four

[0141] Due to the large number of mapping entries in the tertiary page table, direct linear lookup of the physical page number corresponding to the logical address is extremely inefficient; hash collisions can cause lookup failure or significantly increase the delay, affecting the overall performance of address mapping.

[0142] The tertiary page table of the storage device of the embodiment adopts a chained hash table structure: the hash bucket array is preset to have a size of H=256; the host requests a logical address LBA=0x12345078.

[0143] Get the size of the hash bucket: read the system preset hash bucket array size H=256; calculate the hash value: perform modulo operation on LBA: hash = LBA % H = 305419896 %64 =78; locate the hash bucket: according to hash=78, directly locate the 78th hash bucket in the chained hash table of the tertiary page table.

[0144] Perform traversal of the linked list to quickly narrow the search range.

[0145] Further, the step of searching the mapping entry node corresponding to the logical address in the mapping entry node linked list corresponding to the hash bucket comprises: starting from the head of the mapping entry node linked list corresponding to the hash bucket; comparing the logical address stored in each node with the logical address requested by the host in sequence; if a node consistent with the logical address requested by the host is found, the node is determined to be the matching mapping entry node; if the end of the linked list is reached without finding a consistent node, it is determined that the logical address has no corresponding mapping entry node.

[0146] It should be noted that the mapping entry corresponding to the LBA is searched in the mapping entry node linked list corresponding to the hash bucket, and if it is a read request, the physical address stored in the corresponding mapping entry is returned; if it is a write request, the physical address of the entry is updated or a new node is inserted. The linked list is traversed according to the document step to avoid omission or misjudgment.

[0147] Embodiment five

[0148] Since the granularity parameters of the three-level index structure are mostly static fixed values, it is inconvenient to adapt to the dynamic changes of the host access mode.

[0149] On the basis of embodiment one, in this embodiment, after obtaining the logical address requested by the host, the number of root table entries R of the first root table, the number of block table entries B of the second block table, and the number of logical page management modules P of the third page table are adjusted according to the access locality of the logical address; when the continuous access proportion exceeds the access preset value, the number of block table entries B of the second block table is increased to reduce the prefetch overhead; when the hot region is concentrated in a small number of logical address spaces, the number of logical page management modules P of the third page table is reduced to improve the loading efficiency of the hot page table; and the adjusted granularity parameters are written atomically in the non-volatile storage medium in a log structure to ensure the consistency of the system each time it is restarted.

[0150] It should be noted that when the access mode data is obtained, the logical address access records of the host are counted in real time, and the continuous access proportion and the hot region proportion are calculated; when the continuous access proportion is greater than the first preset value, the value of B is increased; when the hot region proportion is less than the second preset value, the value of P is reduced; and the adjusted parameters are written in the NAND Flash log area, and the main configuration area is updated after the writing is verified to be successful, to ensure the consistency of the restart. By increasing the value of B, the management range of the second block table can be expanded, the number of times of prefetching the second block table can be reduced, and the NAND Flash read-write overhead can be reduced; by reducing the value of P, the management granularity of the third page table can be reduced, the hot page table can be more concentrated, and the loading efficiency can be improved.

[0151] Embodiment six

[0152] The embodiment provides a storage device, which is used for applying the memory control method of any one of the above embodiments and comprises a memory controller and a non-volatile storage medium. Figure 4 The memory controller comprises a three-level index construction module 100, a request acquisition module 200, a root table processing module 300, a block table processing module 400 and a page table processing module 500.

[0153] The three-level index construction module 100 is configured to construct a three-level index structure, the three-level index structure comprising a first-level root table, a second-level block table and a third-level page table, wherein the first-level root table is resident in a cache unit, the second-level block table is loaded into the cache unit on demand, the third-level page table is loaded into the cache unit on demand, the third-level page table adopts a chained hash table structure, and each third-level page table comprises a fixed-size hash bucket array and a mapping entry node linked list.

[0154] The request acquisition module 200 is configured to acquire a logical address requested by a host and extract an index value of the three-level index structure through bit operation.

[0155] The root table processing module 300 is configured to locate a root table entry in the first-level root table according to a root table index of the index value to acquire a block table physical page number, and if the block table is not in the cache unit, trigger DMA to load the second-level block table into a block table buffer area from the non-volatile storage medium.

[0156] The block table processing module 400 is configured to locate a block table entry in the second-level block table according to a block table index of the index value to acquire a page table physical page number, and if the page table is not in the cache unit, trigger DMA to load the third-level page table into a page table buffer area.

[0157] The page table processing module 500 is configured to locate a corresponding third-level page table according to a page table index of the index value, calculate a hash value, locate a hash bucket in the third-level page table through the hash value, traverse a mapping entry node linked list corresponding to the hash bucket to find a mapping entry node matching the logical address, extract a physical page number stored in the mapping entry node as a physical address of actually stored data in the non-volatile storage medium, and complete mapping conversion from the logical address to the physical page number.

[0158] Through the memory control method of the embodiment, the whole process delay from logical address input to physical address output is significantly reduced through the overall scheme of three-level index, chained hash table, on-demand loading and bit operation, the low-delay demand of a high-performance storage system is met, an optimal balance between cache occupancy, IO overhead and search efficiency is achieved, the storage system characteristics of limited SRAM resources and high NAND Flash IO delay are adapted, the size of the root table, the block table and the page table, such as R, B and P values, can be flexibly adjusted in the three-level index structure, different capacity storage devices are adapted, and good scalability is achieved. The pain points of the prior art are effectively solved, efficient, low-consumption and stable memory address mapping control is achieved, and key technical support is provided for a high-performance storage system.

[0159] Embodiment seven

[0160] Figure 5 An internal structural diagram of a computer device in one embodiment is shown. This computer device can specifically be a terminal or a server. Figure 5 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and may also store a computer program. When executed by the processor, this computer program enables the processor to implement memory control methods. The memory may also store a computer program, which, when executed by the processor, enables the processor to perform memory control methods. Those skilled in the art will understand that... Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0161] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to perform the following steps:

[0162] A memory control method is applied to a storage device comprising a non-volatile storage medium and a cache unit, the method comprising:

[0163] A three-level index structure is constructed, which includes a first-level root table, a second-level block table, and a third-level page table. The first-level root table resides in the cache unit, the second-level block table is loaded into the cache unit on demand, and the third-level page table is loaded into the cache unit on demand. The third-level page table adopts a chained hash table structure, and each third-level page table's chained hash table includes a fixed-size hash bucket array and a linked list of mapping entry nodes.

[0164] Obtain the logical address requested by the host, and extract the index value of the three-level index structure through bitwise operations;

[0165] The root table entry is located in the first-level root table based on the root table index of the index value to obtain the block table physical page number. If the block table is not in the cache unit, DMA is triggered to load the second-level block table from the non-volatile storage medium into the block table cache area.

[0166] The block table entry is located in the second-level block table based on the block table index of the index value to obtain the physical page number of the page table. If the page table is not in the cache unit, DMA is triggered to load the third-level page table into the page table cache area.

[0167] After locating the corresponding three-level page table according to the page table index of the index value, a hash value is calculated, the hash bucket in the three-level page table is located through the hash value, a mapping entry node matching the logical address is found by traversing the mapping entry node chain corresponding to the hash bucket, and the physical page number stored in the mapping entry node is extracted as the physical address of the actually stored data in the non-volatile storage medium, so as to complete the mapping conversion from the logical address to the physical page number.

[0168] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to enable the processor to perform the following steps:

[0169] A memory control method applied to a storage device containing a non-volatile storage medium and a cache unit, the method comprises:

[0170] A three-level index structure is constructed, which comprises a one-level root table, a two-level block table and a three-level page table, wherein the one-level root table is resident in the cache unit, the two-level block table is loaded into the cache unit on demand, the three-level page table is loaded into the cache unit on demand, and the three-level page table adopts a chained hash table structure, and the chained hash table of each three-level page table comprises a fixed-size hash bucket array and a mapping entry node chain;

[0171] The logical address requested by the host is obtained, and the index value of the three-level index structure is extracted through bit operation;

[0172] The root table entry in the one-level root table is located according to the root table index of the index value to obtain the block table physical page number, and if the block table is not in the cache unit, DMA is triggered to load the two-level block table into the block table buffer area from the non-volatile storage medium;

[0173] The block table entry in the two-level block table is located according to the block table index of the index value to obtain the page table physical page number, and if the page table is not in the cache unit, DMA is triggered to load the three-level page table into the page table buffer area;

[0174] After locating the corresponding three-level page table according to the page table index of the index value, a hash value is calculated, the hash bucket in the three-level page table is located through the hash value, a mapping entry node matching the logical address is found by traversing the mapping entry node chain corresponding to the hash bucket, and the physical page number stored in the mapping entry node is extracted as the physical address of the actually stored data in the non-volatile storage medium, so as to complete the mapping conversion from the logical address to the physical page number.

[0175] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The program can be stored in a non-volatile computer readable storage medium, and when the program is executed, the processes of the above-mentioned embodiment methods can be included. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0176] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0177] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A memory control method applied to a storage device including a nonvolatile storage medium and a cache unit, characterized by, The method comprises: a three-level index structure is constructed, the three-level index structure comprising a first-level root table, a second-level block table and a third-level page table, wherein the first-level root table is resident in a cache unit, the second-level block table is loaded into the cache unit on demand, the third-level page table is loaded into the cache unit on demand, the third-level page table adopts a chained hash table structure, and the chained hash table of each third-level page table comprises a fixed-size hash bucket array and a mapping entry node linked list; a host-requested logical address is obtained, and an index value of the three-level index structure is extracted through bit operation; a root table entry is located in the first-level root table according to a root table index of the index value to obtain a block table physical page number, and if the block table is not in the cache unit, DMA is triggered to load the second-level block table into a block table buffer area from a nonvolatile storage medium; a block table entry is located in the second-level block table according to a block table index of the index value to obtain a page table physical page number, and if the page table is not in the cache unit, DMA is triggered to load the third-level page table into a page table buffer area; after locating a corresponding third-level page table according to a page table index of the index value, a hash value is calculated, a hash bucket in the third-level page table is located through the hash value, a mapping entry node linked list corresponding to the hash bucket is traversed to find a mapping entry node matching the logical address, and a physical page number stored in the mapping entry node is extracted as a physical address of actually stored data in the nonvolatile storage medium, so as to complete mapping conversion of the logical address to the physical page number.

2. The memory control method according to claim 1, wherein, The cache unit is SRAM, and the nonvolatile storage medium is NAND Flash.

3. The memory control method according to claim 1, characterized in that: the first-level root table is a fixed array resident in the cache unit, the first-level root table comprises R root table entries, and each root table entry of the first-level root table points to a physical page number and a valid bit of the second-level block table; the second-level block table is an array loaded into the cache unit on demand, the second-level block table comprises B block table entries, and each block table entry of the second-level block table points to a physical page number and a valid bit of the third-level page table; each page table of the third-level page table comprises P logical page management modules, the hash bucket array of the chained hash table has a size of H, and a new node is inserted into the linked list by using a head insertion method.

4. The memory control method of claim 3, wherein: When the valid bit of the root table entry is 1, the physical page number of the second-level block table pointed to by the root table entry is valid, and when the valid bit of the block table entry is 1, the physical page number of the third-level page table pointed to by the block table entry is valid.

5. The memory control method of claim 3, wherein: The first-level root table adopts double-copy backup: the first-level root table has two independent copies stored in the NAND Flash, and the two copies are located in different physical blocks; when the root table needs to be updated, one of the two copies is updated first, and the other copy is updated after the writing success is verified; if abnormal power-off occurs during the updating process, the next time the power is turned on, the integrity of the two copies is checked to select the effective copy to load into the SRAM.

6. The memory control method of claim 3, wherein: Each node of the mapping entry node linked list comprises a logical address LBA, a physical page number PPN and a pointer pointing to a next node.

7. The memory control method of claim 1, wherein: The step of extracting the index value of the three-level index structure through bit operation comprises: obtaining a total logical address space bit width W of a storage device, a first-level root table entry number R and a second-level block table entry number B. Calculate the right shift number S1 = W - log2(R) of the root table, and extract the root table index by right shift operation: root_index = LBA » S1; Calculate the right shift number S2 = W - log2(R) - log2(B) of the block table, and determine the block table mask M_b = B-1, and extract the block table index by right shift and bitwise AND operation: block_index = (LBA » S2) & M_b; Calculate the right shift number S3 = log2(Page_Size) of the page table, wherein Page_Size is the logical page size of the storage device, and determine the page table mask M_p = P-1, wherein P is the number of logical page management modules, and extract the page table index by right shift and bitwise AND operation: page_index = (LBA » S3) & M_p.

8. The memory control method of claim 1, wherein, The method further comprises the step of loading the secondary block table into the cache unit on demand, which comprises: When the valid bit of the root table entry located according to the root table index value is 1, and the corresponding secondary block table is not stored in the cache unit, triggering DMA to load the secondary block table from the non-volatile storage medium to the block table cache area.

9. The memory control method of claim 8, wherein, The method further comprises that the block table cache area adopts LRU algorithm as the cache replacement policy, and the cache replacement policy maintains the access bit and the dirty bit of each block table, and when the cache area capacity reaches a preset threshold, the longest non-dirty block table is preferentially replaced; if the block table to be replaced is in a dirty state, the block table is persisted to the non-volatile storage medium by an atomic write-back mechanism before the replacement is performed.

10. The memory control method of claim 9, wherein, The method further comprises the dirty data write-back step, which comprises: Marking the block table to be replaced as dirty; Combining periodic write-back and conditionally triggered write-back of dirty data: periodic write-back is to write back the dirty block table to the NAND Flash every preset time interval; when the number of dirty block tables reaches a threshold or the cache replacement needs to replace a dirty block table, the corresponding dirty block table is written back to the NAND Flash; After the write-back is successful, the dirty state mark of the block table is cleared.

11. The memory control method of claim 9, wherein, The method comprises the execution step of the atomic write-back mechanism, which comprises: Writing the update content of the primary root table to the log area of the NAND Flash; Verifying that the content of the log area is successfully written; Updating the primary copy of the primary root table based on the log content; If abnormal power-off occurs, the primary root table is restored to a consistent state by the content of the log area next time the power is turned on.

12. The memory control method of claim 1, wherein, The step of loading the tertiary page table into the cache unit on demand comprises: When the valid bit of the block table entry located according to the block table index value is 1, and the corresponding tertiary page table is not stored in the cache unit, triggering DMA to load the tertiary page table from the non-volatile storage medium to the page table cache area.

13. The memory control method of claim 1, wherein, The step of calculating the hash value and locating the hash bucket in the tertiary page table comprises: Obtaining a preset size H of the system array in the tertiary page table; Performing modulo operation on the logical address of the host request to obtain the hash value: hash = LBA % H; Locating the corresponding hash bucket in the tertiary page table according to the hash value hash.

14. The memory control method of claim 13, wherein, The step of searching the mapping entry node matching the logical address from the mapping entry node linked list corresponding to the hash bucket comprises: Starting from the head of the mapping entry node linked list corresponding to the hash bucket; Comparing the logical address stored in each node with the logical address requested by the host in turn; If a node matching the logical address requested by the host is found, the node is determined as the matching mapping entry node; If the tail of the linked list is reached without finding a consistent node, it is determined that the logical address has no corresponding mapping entry node.

15. The memory control method of claim 1, wherein, Further comprising the steps of: After obtaining the logical address requested by the host, adjusting the root table entry number R of the first-level root table, the block table entry number B of the second-level block table and the logical page management module number P of the third-level page table according to the access locality of the logical address; When the continuous access proportion exceeds the access preset value, increasing the block table entry number B of the second-level block table to reduce the prefetch overhead; When the hot spot area is concentrated in a small number of logical address spaces, reducing the logical page management module number P of the third-level page table to improve the loading efficiency of the hot spot page table; The adjusted granularity parameters are written atomically to the non-volatile storage medium in a log structure.

16. A memory device, comprising: The storage device comprises: A three-level index construction module for constructing a three-level index structure, the three-level index structure comprising a first-level root table, a second-level block table and a third-level page table, wherein the first-level root table is resident in a cache unit, the second-level block table is loaded into the cache unit on demand, the third-level page table is loaded into the cache unit on demand, and the third-level page table adopts a chained hash table structure, each third-level page table comprising a fixed-size hash bucket array and a mapping entry node linked list; A request acquisition module for acquiring a logical address requested by a host and extracting an index value of the three-level index structure through bit operation; A root table processing module for locating a root table entry in the first-level root table according to the root table index of the index value to obtain a block table physical page number, and triggering DMA to load the second-level block table into a block table cache area from a non-volatile storage medium if the block table is not in the cache unit; A block table processing module for locating a block table entry in the second-level block table according to the block table index of the index value to obtain a page table physical page number, and triggering DMA to load the third-level page table into a page table cache area if the page table is not in the cache unit; A page table processing module for locating a corresponding third-level page table according to the page table index of the index value, calculating a hash value, locating a hash bucket in the third-level page table through the hash value, searching a mapping entry node matching the logical address from a mapping entry node linked list corresponding to the hash bucket, and extracting a physical page number stored in the mapping entry node as a physical address of actual data stored in the non-volatile storage medium, thereby completing mapping conversion from the logical address to the physical page number.

17. A computer-readable storage medium, characterized in that, A computer program is stored, and the computer program is executed by a processor to make the processor execute the steps of the method according to any one of claims 1 to 15.

18. A computer device, comprising: A memory and a processor are included, the memory stores a computer program, and the computer program is executed by the processor to make the processor execute the steps of the method according to any one of claims 1 to 15.

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