Physical layer data parallel processing method, device, medium and program product

Abstract

The present application relates to the technical field of artificial intelligence, and provides a physical layer data parallel processing method, device, medium and program product, wherein the method comprises: determining a plurality of physical layer processing modules to be executed in parallel in a communication link, and allocating hardware computing resources to each physical layer processing module; establishing a plurality of parallel execution flows, and respectively allocating data processing tasks of different time slots to different execution flows for parallel execution; wherein the data processing task of each time slot comprises a data transmission task and a computing task of each physical layer processing module. The present application allocates independent computing resources to each processing module, and establishes a plurality of parallel execution flows for data processing tasks of different time slots, thereby realizing parallel overlap of the data transmission task and the computing task between different execution flows, constructing a pipeline processing mode, and significantly reducing the physical layer end-to-end processing delay and improving the hardware resource utilization.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, and in particular to a physical layer data parallel processing method, device, medium, and program product. Background Technology

[0002] As communication technology evolves towards sixth-generation mobile communication technology (6G), in order to meet the intensive computing requirements of its physical layer algorithms, the industry has begun to use computing power chips such as graphics processing units (GPUs) and general-purpose computing on graphics processing units (GPGPUs) to accelerate communication links, replacing the less flexible application-specific integrated circuits (ASICs).

[0003] However, currently, when using GPUs, GPGPUs, and other technologies to process communication physical layer algorithms, a simple serial processing mode is typically employed. In this mode, multiple algorithm modules in the communication link are executed sequentially, and each module exclusively occupies all hardware computing resources during execution.

[0004] This serial processing method has obvious drawbacks. On the one hand, since the processing latency of the entire link is the sum of the latency of each module, modules with poor scalability can become the performance bottleneck of the entire process, resulting in excessively high total latency. On the other hand, when executing a single module, it is often impossible to fully utilize all allocated hardware resources, while other modules are in a waiting state, resulting in a serious waste of computing resources. Summary of the Invention

[0005] This invention provides a physical layer data parallel processing method, device, medium, and program product to solve the defects of high overall processing latency and low hardware resource utilization when executing communication physical layer algorithms on computing chips in related technologies.

[0006] This invention provides a physical layer data parallel processing method, comprising:

[0007] Identify the multiple physical layer processing modules to be executed in parallel in the communication link, and allocate hardware computing resources to each physical layer processing module;

[0008] Establish multiple parallel execution streams and allocate data processing tasks in different time slots to different execution streams for parallel execution;

[0009] The data processing task of each time slot comprises a data transmission task and a calculation task of each physical layer processing module, and the calculation task of each physical layer processing module is executed based on the hardware calculation resource allocated to the physical layer processing module.

[0010] According to the physical layer data parallel processing method provided by the application, the hardware calculation resource is allocated to each physical layer processing module, comprising:

[0011] The minimum hardware resource amount required by each physical layer processing module for processing unit data in a single time slot is calculated;

[0012] The minimum hardware resource amount is taken as the resource allocation benchmark of the corresponding physical layer processing module, and the hardware calculation resource is allocated to the physical layer processing module;

[0013] The sum of the hardware calculation resources allocated to each physical layer processing module is not greater than the total hardware resource amount of the device.

[0014] According to the physical layer data parallel processing method provided by the application, further comprising:

[0015] In each execution flow, the data dependency relationship between the data transmission task and the calculation task of each physical layer processing module in the current time slot is identified, and the data transmission task comprises a host-to-device input data transmission task and a device-to-host output data transmission task;

[0016] Based on the data dependency relationship, the execution order of the data transmission task and the calculation task of each physical layer processing module is determined, and each task is controlled to be executed in series according to the execution order.

[0017] According to the physical layer data parallel processing method provided by the application, the data processing tasks of different time slots are respectively allocated to different execution flows and executed in parallel, comprising:

[0018] At the same time, the multiple execution flows are controlled to be executed in time overlap, so that different execution flows execute tasks in different stages respectively;

[0019] Among them, when the first execution flow is executing the input data transmission task, the second execution flow is executing the calculation task of the physical layer processing module, and the third execution flow is executing the output data transmission task.

[0020] According to the physical layer data parallel processing method provided by the application, the data processing tasks of different time slots are respectively allocated to different execution flows and executed in parallel, comprising:

[0021] For a data processing task of any time slot, it is detected whether there is an idle execution flow in a preset flow resource pool;

[0022] If the idle execution flow exists, the data processing task of the any time slot is allocated to the idle execution flow for execution.

[0023] According to the physical layer data parallel processing method provided by the application, further comprising:

[0024] In the case that the data processing task of the any time slot is executed, the execution flow corresponding to the any time slot is put into the flow resource pool for subsequent time slot multiplexing.

[0025] According to the physical layer data parallel processing method provided by the application, the construction step of the flow resource pool comprises:

[0026] Based on the number of physical layer processing modules to be executed in parallel and the number of data transmission directions in the communication link, the pipeline depth is determined;

[0027] The execution flow object is created in an amount equal to the pipeline depth to form the flow resource pool.

[0028] The application further provides a physical layer data parallel processing device, comprising:

[0029] The resource allocation unit is configured to determine a plurality of physical layer processing modules to be executed in parallel in a communication link, and allocate hardware computing resources to each physical layer processing module;

[0030] The parallel execution unit is configured to establish a plurality of parallel execution flows, and allocate data processing tasks of different time slots to different execution flows for parallel execution.

[0031] Each time slot data processing task includes data transmission tasks and computing tasks of each physical layer processing module, and each physical layer processing module computing task is executed based on the hardware computing resources allocated to the physical layer processing module.

[0032] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the physical layer data parallel processing method as described above.

[0033] The application further provides a non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the physical layer data parallel processing method as described above.

[0034] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the physical layer data parallel processing method according to any one of the above.

[0035] The physical layer data parallel processing method, device, medium and program product provided by the application change the inefficient mode of assigning all resources to a single module by independently assigning each physical layer processing module in the communication link with the hardware computing resources required by the module. Secondly, the application establishes multiple parallel execution flows, and assigns the data processing tasks of different time slots to different execution flows for parallel execution, which converts the processing flows of different time slot data blocks that are completely separated in time into parallel task flows that can be executed in overlap. This pipeline parallel processing mechanism makes the overall throughput no longer limited by the serial execution efficiency of a single processing module, breaks the bottleneck of traditional serial processing, realizes parallel and overlap execution between data transmission tasks and computing tasks, and between different computing tasks, thereby improving the utilization of hardware resources and reducing processing delay. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Figure 1 is a flowchart of the physical layer data parallel processing method provided by the application;

[0038] Figure 2 is a schematic diagram of the physical layer communication link provided by the application;

[0039] Figure 3 is a GPGPU processing pipeline provided by the application;

[0040] Figure 4 is a structural schematic diagram of the physical layer data parallel processing device provided by the application;

[0041] Figure 5 is a structural schematic diagram of the electronic device provided by the application. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0043] With the rapid development of mobile communication technology, the sixth generation mobile communication system (6G) is gradually moving from vision to reality. The 6G network aims to provide higher data rates, lower latency, wider connectivity and intelligent services. In order to achieve this goal, the industry proposes the concept of deeply integrating artificial intelligence (Artificial Intelligence, AI) into the network, and the AI Radio Access Network (AI-RAN) emerges as one of the key directions of 6G network evolution. In the AI-RAN architecture, the physical layer needs to handle a large amount of complex signal processing and AI algorithms, which puts very high requirements on the underlying computing hardware.

[0044] In order to meet the intensive computing needs of communication physical layer algorithms, the related technology usually adopts two main hardware acceleration schemes. The first scheme is to use Application Specific Integrated Circuit (ASIC). ASIC chips tailor hardware circuits for specific communication algorithms, which can execute fixed computing tasks with very high energy efficiency. Due to the specificity of its hardware structure, the processing of different algorithm modules can be completed by different circuit units in parallel, so there is no complex hardware resource scheduling problem. However, the function of ASIC is fixed, which can only run specific algorithms, and lacks flexibility and programmability. Once the communication protocol or algorithm needs to be upgraded or iterated, it needs to be redesigned and taped out, which has a long development cycle and high cost in the AI-RAN scenario of rapid algorithm evolution, and is difficult to adapt to the needs of network intelligence and business diversification.

[0045] The second scheme is to use GPGPU, GPU and other computing chips. Taking GPGPU as an example, it has become a platform for accelerating various algorithms in communication links due to its powerful parallel computing capability and high programmability. Developers can use the versatility of GPGPU to flexibly implement and optimize different physical layer algorithm modules.

[0046] However, when GPGPU is integrated into a 6G AI-RAN system, it is found that there are some defects in its processing mode. Related technologies usually adopt a simple scheduling strategy, that is, each algorithm module in the communication link is executed in series. Specifically, the system will execute the processing task of each algorithm module in turn according to the processing order of the data stream, and when each module is executed, all GPGPU computing resources are usually allocated to it, and after the current module is executed, all resources are handed over to the next module for use.

[0047] This serial processing mode is prone to cause high processing delay. For example, some algorithm modules in the communication link may have poor scalability, that is, increasing computing resources cannot effectively shorten their processing time. In the serial mode, the total delay of the entire link is the simple addition of the delays of all modules. If a module with poor scalability itself takes a long time, even if other modules process faster, this module will become the performance bottleneck of the entire processing flow, severely restricting the overall delay performance.

[0048] In addition, when GPGPU is executing a module with low computing intensity or poor scalability, even if all hardware resources are allocated to it, most of the computing units may be idle. At the same time, due to serial execution, other modules to be processed can only wait and cannot utilize these idle resources. This results in that the hardware resources of GPGPU are not fully utilized in the time dimension during the entire processing period, causing serious resource waste.

[0049] To this end, the present application provides a physical layer data parallel processing method, which pre-allocates computing resources for different physical layer modules and parallelizes tasks in different time slots using a multi-path execution flow mechanism to build an efficient computing pipeline. This method breaks the bottleneck of traditional serial processing, realizes parallel and overlapping execution between data transmission tasks and computing tasks, and between different computing tasks, thereby greatly improving the utilization rate of GPGPU hardware resources, significantly reducing the end-to-end processing delay, and meeting the stringent real-time requirements of future communication systems such as 6G for physical layer processing.

[0050] It should be noted that the physical layer data parallel processing method provided by the present application can be executed by an electronic device or a computing system. In a typical application scenario, for example, in a 6G wireless access network (AI-RAN) base station, the execution subject can be a computing platform that includes a central processing unit (CPU) or a field programmable gate array (FPGA) as a main processor, and integrates a general-purpose graphics processor (GPGPU) as an acceleration processing unit.

[0051] In this platform, the main processor (e.g. CPU / FPGA) usually undertakes the role of control, task scheduling, communication with external systems, etc. of the whole system. The acceleration processing unit (e.g. GPGPU) is specially used to execute the computationally intensive tasks due to its strong parallel computing capability, especially in the present application, for executing various algorithm modules of the communication physical layer. Therefore, the execution process of the method of the present application is completed under the cooperative work of the main processor and the acceleration processing unit. The main processor is responsible for task decomposition, management and distribution, while the acceleration processing unit is responsible for specific parallel computation and data processing. In the following embodiments, for the convenience of description, the combination of CPU as the main processor (i.e. host side) and GPGPU as the acceleration processing unit (i.e. device side) will be described, but this does not constitute a limitation on the execution subject of the present application. Those skilled in the art can understand that any similar hardware architecture with main processing capability and parallel computing capability can be used as the execution subject of the present application.

[0052] Figure 1 is a flowchart of the physical layer data parallel processing method provided by the present application, as shown in Figure 1 , the method comprises:

[0053] Step S10, determining a plurality of physical layer processing modules to be executed in parallel in the communication link, and allocating hardware computing resources to each physical layer processing module.

[0054] Specifically, this step is the preparation stage of parallel processing. The physical layer processing module refers to a series of algorithm units with specific functions in the wireless communication physical layer processing flow. These modules may be different under different communication standards or application scenarios.

[0055] For example, in an uplink processing scenario, these modules can include channel estimation, channel equalization, demodulation, decoding, etc.; in a downlink processing scenario, they can include encoding, modulation, resource mapping, precoding, etc. Determining which modules need to be executed in parallel is usually based on the analysis of the whole communication link processing delay, and those computationally intensive and time-consuming modules are included in the GPGPU acceleration range.

[0056] Hardware computing resources refer to physical units or logical units available for executing computing tasks on parallel computing devices such as GPGPU. For example, hardware computing resources can refer to compute units (CU) in GPGPU. In GPGPU, each compute unit includes multiple computing cores, register resources, cache, etc.

[0057] In the embodiments of the present application, allocating hardware computing resources to a module means reserving or assigning a portion of computing capacity for each module planned to run on the GPGPU. For example, assuming there are four physical layer processing modules (such as module A, module B, module C, and module D) that need to be processed in the GPGPU, module A can be allocated 10% of the CU resources, module B can be allocated 15% of the CU resources, and so on. This allocation can be statically preset, that is, configured in advance according to the complexity of each module when the system is initialized, or dynamically adjusted. The purpose of the allocation is to ensure that each module has independent and sufficient resources to complete its computing task in a time unit (such as a time slot), thereby creating conditions for subsequent inter-module parallel execution.

[0058] Step S20, establishing multiple parallel execution flows, and allocating data processing tasks of different time slots to different execution flows respectively and performing in parallel;

[0059] Each data processing task of each time slot includes a data transmission task and a computing task of each physical layer processing module, and the computing task of each physical layer processing module is executed based on the hardware computing resources allocated to the physical layer processing module.

[0060] Specifically, an execution flow corresponds to a stream in the GPGPU programming model. An execution flow can be understood as a first-in first-out (FIFO) instruction queue, and multiple tasks (such as data copying, kernel function execution, etc.) submitted to the same execution flow will be executed in strict accordance with the order of submission. However, the tasks in different execution flows can be arranged by the hardware scheduler of the GPGPU to be executed in parallel or overlapped. Therefore, by creating multiple execution flows, it is equivalent to creating multiple independent channels that can execute tasks at the same time.

[0061] A time slot is a basic unit for dividing time in a communication system, representing a set of data that needs to be processed. For example, in a 5G or 6G system, a certain amount of data to be processed will be received in a time slot. The data in different time slots is logically independent.

[0062] In this step, the establishment of multiple parallel execution streams means that the program creates multiple execution stream objects. Then, the data processing tasks of different time slots are distributed. Specifically, the data processing tasks of time slot 0 (i.e., slot0) can be all submitted to execution stream 0 (i.e., stream0), the data processing tasks of time slot 1 (i.e., slot1) can be all submitted to execution stream 1 (i.e., stream1), and so on. Since these tasks are allocated to different execution streams, the scheduler of the GPGPU can recognize that there is no dependency between them, so that these tasks belonging to different execution streams can be executed in parallel as much as possible to form a pipeline effect when the hardware resources allow.

[0063] It can be understood that the complete data processing task of a time slot usually includes two main parts, i.e., a data transmission task and a calculation task of each physical layer processing module. The data transmission task mainly refers to the transmission of data between the main processor memory (such as the CPU memory) and the acceleration unit video memory (such as the GPGPU video memory), which can specifically include the host-to-device data transmission (H2D), i.e., copying the original data to be processed from the CPU or FPGA to the GPGPU, and the device-to-host data transmission (D2H), i.e., copying the result data processed by the GPGPU back to the CPU or FPGA.

[0064] The calculation task of each physical layer processing module refers to the calculation process of the kernel function of each physical layer processing module (such as module A, module B, module C, module D, etc.) on the GPGPU to execute its respective algorithm.

[0065] The key is that the calculation task of each physical layer processing module is executed based on the dedicated hardware calculation resource allocated to it in step S10. This means that when the GPGPU processes the tasks in multiple execution streams at the same time, the calculation tasks of module A (such as belonging to slot1) and module B (such as belonging to slot0) belonging to different time slots can truly run in parallel because they use different hardware calculation resources allocated to them, rather than time-sharing the same batch of resources.

[0066] Through the combination of the above steps, the embodiment of the application provides a deep pipeline parallel processing mode which can convert the original serial mode that needs to completely process the data of one time slot before processing the data of the next time slot. After the pipeline is stably running, all parts of the GPGPU are in a busy state, for example, the data copy engine can be performing the H2D operation for a new time slot, and a large number of calculation units can be simultaneously performing different module calculation tasks for multiple different time slots in different processing stages.

[0067] The method provided by the embodiment of the present application changes the inefficient mode of assigning all resources to a single module by independently assigning each physical layer processing module in the communication link with the hardware computing resources it needs. This refined resource allocation allows each module to only occupy the resources it needs, thereby effectively dividing the total hardware resources and providing a basis for the parallel operation of multiple modules, avoiding the waste caused by a single module that cannot fully utilize all resources. Secondly, the present application establishes multiple parallel execution flows and assigns the data processing tasks of different time slots to different execution flows for parallel execution. This design converts the processing flows for different time slot data blocks that are completely separated in time into parallel task flows that can be executed in parallel. This pipeline parallel processing mechanism allows the overall throughput to no longer be limited by the serial execution efficiency of a single processing module, breaking the bottleneck of traditional serial processing and achieving parallel and overlapping execution between data transmission tasks and computing tasks and between different computing tasks, thereby improving the utilization of hardware resources and reducing processing latency.

[0068] Based on the above embodiment, in step S10, the hardware computing resources are allocated to each physical layer processing module, including:

[0069] In step S11, the minimum amount of hardware resources required by each physical layer processing module to process a unit of data within a single time slot is calculated.

[0070] In step S12, the minimum amount of hardware resources is used as the resource allocation reference for the corresponding physical layer processing module, and the hardware computing resources are allocated to the physical layer processing module.

[0071] The sum of the hardware computing resources allocated to each physical layer processing module is not greater than the total amount of hardware resources of the device.

[0072] It should be noted that in the above embodiment, multiple physical layer processing modules that need to be executed in parallel on the GPGPU are determined, such as module A, module B, module C, and module D. In order to achieve their parallelism in different execution flows, appropriate hardware computing resources need to be allocated to them. If the allocation is improper, for example, a module is insufficient in resources, it will become a bottleneck of the entire pipeline; and if a module has excess resources, it will cause waste and reduce the total number of parallel modules. The embodiment of the present application aims to accurately meet the performance requirements of each module, thereby maximizing the overall parallelism and resource utilization.

[0073] In particular, when allocating hardware computing resources to each physical layer processing module, first, the minimum amount of hardware resources each physical layer processing module needs to process a unit of data in a single time slot can be calculated. Here, a unit of data usually refers to a data block that needs to be processed in a time slot. For example, in a wireless communication system, a time slot can correspond to one or more transport blocks, and the amount of data is determined.

[0074] The minimum amount of hardware resources is a key performance indicator, which refers to the minimum amount of hardware computing resources (e.g., the minimum number of computing units) that a certain physical layer processing module needs to occupy in order to complete the processing of a unit of data in the duration of a time slot (e.g., 1 millisecond). This value is usually determined through empirical testing and benchmarking.

[0075] For example, taking module A as an example, different amounts of hardware resources (e.g., 2 CUs, 4 CUs, 6 CUs,...) can be allocated to it in a separate test environment, and it is allowed to process a unit of data while its execution time is recorded. It can be observed that as the amount of allocated resources increases, the execution time decreases. When the execution time is first less than or equal to the duration of a time slot, the amount of resources allocated at that time can be considered as the minimum amount of hardware resources required by the module. For example, if it is found through testing that module A takes 1.1 ms when allocated 4 CUs, but takes 0.9 ms when allocated 6 CUs, and the length of a time slot is 1 ms, then the minimum amount of hardware resources required by module A is 6 CUs.

[0076] It can be understood that for some modules with poor scalability of communication algorithms, blindly increasing resources cannot effectively reduce the latency. By calculating the minimum amount of hardware resources, the most cost-effective resource configuration point can be accurately found, avoiding wasting valuable computing resources on modules that cannot bring significant performance improvement.

[0077] After determining the minimum amount of hardware resources for each module, the actual resource allocation is based on this benchmark. The resource allocation benchmark means that the final resource allocation is based on this value. In the simplest case, the calculated minimum amount of hardware resources can be directly used as the final allocation amount for the module. For example, if the minimum amount of hardware resources required by module A, module B, module C, and module D are 6 CUs, 10 CUs, 8 CUs, and 12 CUs, respectively, they can be directly allocated these amounts of resources.

[0078] In some more complex implementations, a small amount of redundancy (e.g., 5% or 10%) can be added to the benchmark as a safety margin to cope with some sudden computing fluctuations and ensure the robustness of the system. However, regardless of how, the fundamental basis for allocation is the calculated minimum amount of resources.

[0079] Finally, it is necessary to ensure that the sum of the hardware computing resources allocated to all physical layer processing modules is not greater than the total amount of hardware resources of the device. This is a feasibility constraint condition. After completing the resource allocation of all parallel modules, the resource allocation amounts of them need to be summed up and compared with the total amount of hardware resources possessed by the GPGPU device.

[0080] For example, assume that a GPGPU has 60 available CUs. According to the above criteria, module A, module B, module C, and module D require 6, 10, 8, and 12 SMs respectively, and the total is 36 CUs. Because 36 < 60, this parallel scheme is feasible, and the GPGPU has enough resources to allow the four modules to run simultaneously in different execution streams. If the total is greater than 60, it means that the current GPGPU cannot support the parallel running of all these modules at the same time, and the scheme needs to be adjusted, for example, the number of parallel modules is reduced, or the algorithm of some modules is optimized to reduce its resource demand.

[0081] The embodiment of the application achieves fine management and efficient use of hardware computing resources by calculating the minimum resource requirement of each module. This not only ensures that each processing stage in the pipeline will not become a performance bottleneck, but also avoids waste caused by excessive allocation of resources, so that the maximum degree of parallel processing can be achieved under the limited total resources, further improving the throughput and real-time performance of the entire physical layer data processing flow.

[0082] Based on any of the above embodiments, the method further comprises:

[0083] Within each of the execution streams, a data dependency relationship between the data transmission tasks and the computing tasks of the physical layer processing modules in the current time slot is identified, the data transmission tasks including host-to-device input data transmission tasks and device-to-host output data transmission tasks;

[0084] Based on the data dependency relationship, the execution order of the data transmission tasks and the computing tasks of the physical layer processing modules is determined, and each task is controlled to be executed in series according to the execution order.

[0085] It should be noted that, on the basis of the above parallel processing framework, the embodiment of the application further elaborates how to ensure that the data processing tasks of a time slot can be correctly and orderly completed within a single execution stream. The core of the foregoing embodiments is to build a parallel pipeline between tasks of different time slots, and the core of the embodiment of the application is to ensure the serial correctness within a single time slot task.

[0086] Specifically, after all data processing tasks of one time slot (e.g. time slot N) are assigned to one independent execution stream, there naturally exists a logical order in the processing procedure, which is determined by the data dependency. Here, the data dependency refers to that the execution of a task must wait for the completion of the previous task or tasks it depends on, because it needs to use the data generated by the previous task as input. If the dependency is violated, it will lead to processing errors (e.g. processing incomplete or outdated data) or program crashes.

[0087] Figure 2 is a schematic diagram of the physical layer communication link provided by the present application. As shown in Figure 2 the dependency chain of the data of a single time slot is as follows: the computation task of the physical layer processing module A needs to wait for the original data to be transmitted from the host processor (e.g. CPU, FPGA, etc.) to the GPGPU memory before it can start. Therefore, the computation task of module A depends on the completion of the host-to-device data transmission task (H2D). The computation task of the physical layer processing module B needs to use the result data processed by module A as input, therefore, the computation task of module B depends on the completion of the computation task of module A. Similarly, module C depends on module B, and module D depends on module C, forming a serial dependency chain, i.e. module A→module B→module C→module D. Finally, when all computation tasks are completed, the final result data needs to be transmitted from the GPGPU memory back to the host processor, therefore, the device-to-host data transmission task (D2H) depends on the completion of the computation task of the last physical layer processing module (i.e. module D).

[0088] For the above-mentioned single time slot, the complete data dependency chain of all tasks inside it is identified as: H2D task→module A computation task→module B computation task→module C computation task→module D computation task→D2H task. After the data dependency is identified, the execution order is naturally determined, i.e. it needs to be executed in the order of the dependency chain.

[0089] In the embodiment of the present application, the control of the task execution order is realized by using the internal working mechanism of the execution stream. All tasks submitted to the same execution stream will be strictly executed in series according to the order of submission by the GPGPU driver and hardware. Therefore, in order to realize the above-mentioned determined execution order, the control logic of the application program (usually running on the CPU) will submit each task to the same execution stream object in the order of the determined execution order.

[0090] Taking an execution stream 0 (stream0) processing slot0 data as an example, the control process is as follows: first, a GPGPU programming interface is called to submit a H2D task to the stream0 to copy the original data of the slot0 from the host memory to the device memory in an asynchronous manner. Then, a kernel start interface is immediately called to submit the calculation task of the module A to the stream0. Then, the calculation task of the module B is continuously submitted to the stream0, and the calculation tasks of the module C and the module D are sequentially submitted to the stream0. Finally, after all the calculation tasks are submitted, a corresponding interface is called to submit a D2H task to the stream0 to copy the output result of the module D from the device memory back to the host memory.

[0091] Since all the tasks are submitted to the same execution stream stream0, the GPGPU ensures that they are executed in strict accordance with the order of submission, that is, the calculation of the module A must start after the H2D is completed, the calculation of the module B must start after the calculation of the module A is completed, and so on, until the D2H task starts after all the calculations are completed, so that the data dependency between the tasks can be guaranteed to be correct. In addition, each time slot can ensure that new data is received from the host processor and processed data is returned to the outside, avoiding data congestion in the GPGPU and causing packet loss, thereby enhancing the stability of the 6G AI-RAN system.

[0092] The embodiments of the present application ensure the logical correctness and data integrity when processing the data of a single time slot by identifying and following the data dependency relationship between the tasks in a time slot and using the inherent serial execution characteristics of the execution stream to enforce the order, so that the overall processing capacity and efficiency can be maximized when the serial execution inside the execution stream is combined with the multi-way parallel execution between the execution streams.

[0093] Based on any of the above embodiments, in step S20, the data processing tasks of different time slots are respectively distributed to different execution streams for parallel execution, including:

[0094] At the same time, the multiple execution streams are controlled to be executed in time overlap, so that different execution streams execute tasks in different stages respectively;

[0095] Among them, when the first execution stream is executing the input data transmission task, the second execution stream is executing the calculation task of the physical layer processing module, and the third execution stream is executing the output data transmission task.

[0096] It should be noted that the above embodiments describe that the tasks within a single execution stream are executed in series according to the business logic. However, if the system has to wait for all the tasks of the previous execution stream to be completed before starting the next execution stream, the processing is essentially still in series, and most of the hardware resources of the GPGPU are still idle at any time. For example, when the H2D task is executed, the computing unit is idle; when the computing task is executed, the data copy engine is idle.

[0097] The embodiments of the present application are exactly to solve this problem, and the core is that at the same time, multiple execution streams are controlled to execute in time overlap, so that different execution streams execute tasks in different stages respectively.

[0098] Here, the control does not mean that the CPU needs to micro-manage each GPGPU hardware unit, but means that by asynchronously submitting tasks to different and independent execution streams, the hardware scheduler of the GPGPU can autonomously find and execute these tasks that can be parallel. Since there is no dependency between different execution streams, the scheduler can arrange the data copy task in one execution stream and the computing task in another execution stream to be executed at the same time on different hardware units (such as data copy engine and computing unit) of the GPGPU. This process will eventually form a deep pipeline.

[0099] Figure 3 is a schematic diagram of the GPGPU processing pipeline provided by the present application, as shown in Figure 3 Different time slot data processing tasks are assigned to different execution streams for execution, for example, the data processing task of slot0 is assigned to stream0 for execution, the data processing task of slot1 is assigned to stream1 for execution, and so on. After the system runs stably for a period of time, multiple execution streams will be in a stable state of time overlap execution. Take the time t=5 shown in the black bold dashed box in Figure 3 as an example, at this time, the processing state of the GPGPU fully embodies the parallel mechanism described in the embodiments of the present application.

[0100] Specifically, at time t=5, the first execution stream (e.g., stream5) just starts to process the latest data slot slot5, and the task it is executing is an input data transfer task (i.e., H2D task) to copy the raw data of slot5 from the CPU memory to the GPGPU memory, which mainly occupies the data copy engine of the GPGPU. At the same time, the second execution stream (e.g., stream4, stream3, stream2, stream1) is executing the calculation tasks of the respective physical layer processing modules, for example, stream4 is executing the calculation of module A, stream3 is executing the calculation of module B, stream2 is executing the calculation of module C, and stream1 is executing the calculation of module D. These calculation tasks mainly occupy the calculation units (e.g., CUs) of the GPGPU. Since independent calculation resources have been allocated to each module, these calculation tasks can be executed in parallel on the respective resources.

[0101] At the same time (i.e., at time t=5), the third execution stream (e.g., stream0) has completed all the calculation tasks on slot0 and enters the last stage of the processing flow. The task it is executing is an output data transfer task (i.e., D2H task) to copy the final processing result of slot0 from the GPGPU memory back to the CPU memory. This task also mainly occupies the data copy engine of the GPGPU.

[0102] At this time point t=5, the input copy engine, the multiple calculation units, and the output copy engine of the GPGPU are all in working states, serving different execution streams (i.e., different data slots). This forms a pipeline operation scenario, and the hardware resources are fully utilized.

[0103] The embodiment of the present application successfully overlaps the originally separate data transfer and calculation processes, and the calculation processes in different stages in time by utilizing the multi-execution stream mechanism and the internal hardware scheduling capability of the GPGPU. It converts the linear and discrete task sequence into a continuous and multi-stage parallel processing pipeline. This way maximizes the parallelism of different functional hardware units inside the GPGPU, thereby improving the overall throughput and hardware utilization efficiency of the system, and is the key to realizing low-latency and high-efficiency physical layer data processing.

[0104] Based on any of the above embodiments, in the above embodiments, an independent execution stream is allocated for each new data slot. However, in a real-time communication system that needs to process thousands of slots per second, creating new execution stream objects without limitation will bring an unacceptable system overhead. Although the creation and destruction overhead of a single execution stream is not large, the cumulative operation at a high frequency will become a performance bottleneck of the host end, causing system jitter and affecting the stability of the processing flow.

[0105] To solve this problem, embodiments of the present application introduce a resource pool based execution flow management and reuse mechanism. This mechanism covers the whole life cycle management of execution flow creation, allocation and recycling, which will be introduced in detail as follows.

[0106] Firstly, before system initialization or processing flow starts, a fixed size execution flow pool, i.e. flow resource pool, needs to be created and maintained in advance. The size of this pool is not set randomly, but calculated according to the intrinsic requirements of processing flow. The specific construction steps of flow resource pool are as follows:

[0107] determine a pipeline depth based on a number of physical layer processing modules to be executed in parallel and a number of data transmission directions in the communication link;

[0108] create execution flow objects in a number equal to the pipeline depth to form the flow resource pool.

[0109] Specifically, the pipeline depth refers to the total number of independent processing stages that need to exist in parallel at the same time in order to make the processing pipeline of GPGPU saturated (i.e. all hardware units are fully utilized). This depth is determined by two factors, i.e. the number of physical layer processing modules to be executed in parallel and the number of data transmission directions.

[0110] Here, the number of physical layer processing modules to be executed in parallel refers to the number of computing tasks determined to be executed on GPGPU. For example, as shown in FIG. 1, assuming there are four modules A, B, C and D. The number of data transmission directions usually includes input data transmission (H2D) and output data transmission (D2H) directions. Therefore, the pipeline depth can be equal to the sum of the number of physical layer processing modules and the number of data transmission directions. Figure 2

[0111] For example, in the above example, the number of physical layer processing modules to be executed in parallel is 4, and the number of data transmission directions is 2, so the pipeline depth is 6. This means that in order to make the entire processing flow run like a pipeline, ideally 6 independent execution flows are needed to carry tasks in 6 different processing stages, as shown in the state at t=5 in FIG. 2. Figure 3

[0112] After determining the pipeline depth, the system will call the GPGPU programming interface to create execution flow objects in a number equal to the depth. In the above example, i.e. 6 execution flow objects are created. These created execution flow objects collectively constitute the flow resource pool. In the initial state, all execution flows in this pool are in an idle state and can be taken at any time. This resource pool can be managed by a queue, list or any other collection type data structure. ​​

[0113] Secondly, when the system needs to process a new data slot (e.g. slotN), it does not create a new execution stream, but requests an available execution stream from the preset stream resource pool. That is, in step S20, the data processing tasks of different time slots are respectively allocated to different execution streams for parallel execution, including:

[0114] In step S21, for the data processing task of any time slot, it is detected whether there is an idle execution stream in the preset stream resource pool;

[0115] In step S22, if the idle execution stream exists, the data processing task of the any time slot is allocated to the idle execution stream for execution.

[0116] Specifically, the control logic checks the stream resource pool. If the pool is not empty, it means that there is one or more execution streams that have completed previous tasks, are in an idle waiting state, etc. If it is detected that there is an idle execution stream, the system takes one from the pool (e.g. pops an execution stream object from the head of the queue), and allocates all data processing tasks (including H2D, module calculation, D2H) of the current time slot (slotN) to this taken execution stream. Then, the system asynchronously submits these tasks to the execution stream in sequence for execution.

[0117] Finally, an execution stream, after being allocated and executing all the tasks it carries, is not destroyed, but recycled into the resource pool, so that it can be reused by subsequent new data slots. Specifically, the method further includes:

[0118] In the case that the data processing task of the any time slot is executed, the execution stream corresponding to the any time slot is put into the stream resource pool for subsequent time slot reuse.

[0119] Specifically, the system needs a mechanism to determine whether all the tasks on an execution stream have been completed. This can usually be achieved through the event or synchronization API of the GPGPU. When the last task (usually the D2H task) submitted to the execution stream is reported completed by the GPGPU, it is considered that the execution stream has completed all the tasks for the current time slot.

[0120] After confirming the completion of the task, the control logic re-puts the execution stream object back into the stream resource pool (e.g. pushes it to the tail of the queue), so that its state changes from busy to idle. In this way, it can be acquired and reused by the subsequent incoming data slots. For example, as Figure 3As shown, slot6 reuses the stream0 which has been idle, when the stream0 of slot0 has finished all its tasks, it is recycled to the resource pool. Then, when slot6 comes and needs to allocate an execution stream, it gets this just released stream0 from the resource pool.

[0121] The embodiment of the present application avoids creating and destroying execution stream objects in real-time processing flow by constructing a fixed-size stream resource pool and implementing the reuse strategy of acquisition, use and return. This significantly reduces the management overhead of the host end and the system jitter caused by memory allocation and release, making the entire processing system more stable and efficient. At the same time, since the size of the resource pool is calculated according to the pipeline depth, it ensures that there are enough execution streams to maintain full-load operation of the pipeline, and it does not cause unnecessary resource waste.

[0122] Based on any of the above embodiments, the embodiment of the present application provides a method suitable for GPGPU accelerated 6G AI-RAN physical layer algorithm. By utilizing the principle of GPGPU multi-context parallelism and the stream mechanism, a certain amount of hardware computing resources are allocated to each physical layer processing module, so that each module runs in parallel on the GPGPU. The following will take a specific scene as an example for introduction. The processing link and running state of this scene are shown in Figure 2 and Figure 3 .

[0123] Step S1, system initialization and resource pool construction.

[0124] First, determine the processing link and resource requirement. According to the communication link diagram shown in Figure 2 , it is determined that the physical layer processing link that needs to be accelerated by GPGPU this time includes four computationally intensive physical layer processing modules, namely module A, module B, module C and module D. The entire processing flow starts from the main processor (i.e. the host end, such as CPU or FPGA), data enters the GPGPU through H2D (host to device) transmission, and is processed in turn through the four modules, and the final result is transmitted back to the main processor (CPU) through D2H (device to host).

[0125] Second, calculate the resource allocation. The system will perform performance profiling on module A, module B, module C and module D, and calculate the minimum amount of hardware resources required for each module to complete data processing in a single time slot. Then, the system will allocate a certain amount of computing resources (such as a certain number of CUs) to each module as a benchmark for static allocation of dedicated computing resources on the GPGPU. This step ensures that the four modules can truly run in parallel in the subsequent steps, and the total resource consumption does not exceed the carrying capacity of the GPGPU.

[0126] Finally, the system needs to build a fixed-size execution stream resource pool. The size of the stream resource pool is determined by the pipeline depth. According to Figure 2 the communication link diagram shown in FIG. 2, the pipeline depth is equal to the sum of the number of physical layer processing modules and the number of data transmission directions (i.e., 4+2=6). Therefore, the system creates 6 execution stream objects (i.e., stream0 to stream5) in the initialization stage and puts them into an idle queue to form a stream resource pool for subsequent use.

[0127] Step S2, pipeline establishment and stable operation.

[0128] After the system initialization is completed, the system starts to receive and process the continuously incoming data slots. The following will describe how the pipeline is filled and reaches a stable state with reference to the GPGPU processing pipeline diagram shown in FIG. 3. Figure 3

[0129] At t=0, the first data slot slot0 arrives. The system obtains an idle execution stream, i.e., stream0, from the stream resource pool, and then submits the first task H2D of slot0 to stream0 to start execution.

[0130] At t=1, the second data slot slot1 arrives. The system obtains the next idle execution stream, i.e., stream1, from the resource pool, and submits the H2D task of slot1 to stream1. At the same time, the H2D task of slot0 has been completed, and the GPGPU scheduler starts to execute the computing task of module A on the computing resource allocated to module A according to the task queue of stream0. At this moment, the data copy engine and part of the computing units of the GPGPU have started to work in parallel.

[0131] At t=2 to t=4, the pipeline is gradually filled in this way. Each new slot arrives, a new execution stream is obtained from the resource pool, and the H2D task thereof is started. The earlier slots enter the next processing stage (such as modules B, C, etc.) in order in the respective execution streams.

[0132] When the system runs to Figure 3 ​At time t=5, the processing pipeline reaches a full, efficient, and stable state. At this moment, the GPGPU is in the following state: stream5 is processing the newest data slot5, which is a H2D task, occupying the data copy engine of the GPGPU to transfer data from the host. stream4 is processing slot4, which is a computation task of module A, occupying the computation resource allocated to module A. stream3 is processing slot3, which is a computation task of module B, occupying the computation resource allocated to module B. stream2 is processing slot2, which is a computation task of module C, occupying the computation resource allocated to module C. stream1 is processing slot1, which is a computation task of module D, occupying the computation resource allocated to module D. stream0 is processing the earliest slot0, which has finished all computations and is performing the last D2H task, occupying the data copy engine of the GPGPU to transfer the result back to the host.

[0133] At this moment, the input copy engine of the GPGPU, all allocated computation units, and the output copy engine are almost in active state, serving different processing stages of 6 different data slots. This achieves deep overlap and parallelism between data transfer and computation, and between different computation tasks, reaching the ideal state of full GPGPU resource.

[0134] Step S3, recycling and reuse of the execution stream.

[0135] The pipeline continues to move forward, and after time t=5, when stream0 finishes the D2H task of slot0, all tasks of this slot carried by stream0 have been executed. The system detects this completion state and recycles stream0, putting it back to the free queue of the stream resource pool.

[0136] When the next data slot slot6 arrives, the system needs to allocate an execution stream for it. At this time, the system detects that stream0 just recycled is in the free state from the stream resource pool, and then allocates it to slot6. As shown in FIG. 6, slot6 starts to reuse stream0 to execute its H2D task. Figure 3

[0137] For subsequent slotN, the system adopts a cyclic allocation strategy, such as taking modulo operation (N%6) to select an available stream from the resource pool containing 6 execution streams. This reuse mechanism avoids the overhead of creating a new stream for each slot, ensuring the stability and efficiency of long-term system operation.

[0138] ​The embodiment of the present application successfully maps a complex, multi-stage physical layer processing task into a software pipeline running efficiently on a GPGPU by the complete logical flow described above. It comprehensively uses a variety of technical means such as fine-grained resource pre-allocation, in-stream serialization based on data dependency, inter-stream parallelism based on multi-stream mechanism, and execution stream multiplexing based on resource pool, and finally realizes the goal of maximizing hardware resource utilization and significantly reducing processing delay under the premise of ensuring the correctness of processing logic.

[0139] The physical layer data parallel processing device provided by the present application is described below, and the physical layer data parallel processing device described below can be referred to each other corresponding to the physical layer data parallel processing method described above.

[0140] Based on any of the above embodiments, Figure 4 is a structural schematic diagram of the physical layer data parallel processing device provided by the present application, as Figure 4 indicated, the device comprises:

[0141] The resource allocation unit 410 is configured to determine a plurality of physical layer processing modules to be executed in parallel in the communication link, and allocate hardware computing resources to each physical layer processing module.

[0142] The parallel execution unit 420 is configured to establish a plurality of parallel execution streams, and distribute data processing tasks of different time slots to different execution streams for parallel execution.

[0143] Each of the data processing tasks of each time slot comprises a data transmission task and a computing task of each of the physical layer processing modules, and the computing task of each of the physical layer processing modules is executed based on the hardware computing resources allocated to the physical layer processing module.

[0144] The device provided by the embodiment of the present application changes the inefficient mode of assigning all resources to a single module by independently assigning each physical layer processing module in the communication link with the hardware computing resources it needs. This fine resource allocation allows each module to only occupy the resources it needs, thereby effectively dividing the total hardware resources and providing a basis for the parallel operation of multiple modules, avoiding the waste caused by a single module not being able to fully utilize all resources. Secondly, the present application establishes multiple parallel execution flows and assigns the data processing tasks of different time slots to different execution flows for parallel execution. This design converts the processing flows of different time slot data blocks that are completely separated in time into parallel task flows that can be executed in parallel. This pipeline parallel processing mechanism allows the overall throughput to no longer be limited by the serial execution efficiency of a single processing module, breaking the bottleneck of traditional serial processing and achieving parallel and overlapping execution between data transmission tasks and computing tasks and between different computing tasks, thereby improving the utilization of hardware resources and reducing processing latency.

[0145] According to any one of the above embodiments, the resource allocation unit is specifically configured to:

[0146] calculate the minimum amount of hardware resources required by each physical layer processing module to process a unit of data within a single time slot;

[0147] use the minimum amount of hardware resources as the resource allocation benchmark for the corresponding physical layer processing module, and allocate hardware computing resources to the physical layer processing module;

[0148] wherein the sum of the hardware computing resources allocated to the physical layer processing modules is not greater than the total amount of hardware resources of the device.

[0149] According to any one of the above embodiments, the device further comprises a serial execution unit, which is configured to:

[0150] identify the data dependency relationship between the data transmission tasks and the computing tasks of the physical layer processing modules within each execution flow, the data transmission tasks including host-to-device input data transmission tasks and device-to-host output data transmission tasks;

[0151] determine the execution order of the data transmission tasks and the computing tasks of the physical layer processing modules based on the data dependency relationship, and control the tasks to be executed in series according to the execution order.

[0152] According to any one of the above embodiments, the parallel execution unit is specifically configured to:

[0153] At the same moment, the plurality of execution flows are controlled to be executed in time overlap, so that different execution flows execute tasks at different stages respectively;

[0154] Wherein, when the first execution flow is executing the input data transmission task, the second execution flow is executing the calculation task of the physical layer processing module, and the third execution flow is executing the output data transmission task.

[0155] Based on any of the above embodiments, the parallel execution unit is specifically used for:

[0156] For a data processing task of any time slot, it is detected whether there is an idle execution flow in the preset flow resource pool;

[0157] If the idle execution flow exists, the data processing task of the any time slot is allocated to the idle execution flow for execution.

[0158] Based on any of the above embodiments, the device further comprises a resource multiplexing unit, and the resource multiplexing unit is used for:

[0159] In the case that the data processing task of the any time slot is executed, the execution flow corresponding to the any time slot is put into the flow resource pool for subsequent time slot multiplexing.

[0160] Based on any of the above embodiments, the device further comprises a resource pool construction unit, and the resource pool construction unit is used for:

[0161] Based on the number of physical layer processing modules to be executed in parallel and the number of data transmission directions in the communication link, the pipeline depth is determined;

[0162] An execution flow object with a number equal to the pipeline depth is created to form the flow resource pool.

[0163] Figure 5 An example of an entity structure diagram of an electronic device is shown in FIG. 1. Figure 5As shown, the electronic device can include a processor 510, a communication interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communication interface 520, and the memory 530 complete mutual communication through the communication bus 540. The processor 510 can invoke the logical instructions in the memory 530 to execute the physical layer data parallel processing method, which includes determining a plurality of physical layer processing modules to be executed in parallel in a communication link, and allocating hardware computing resources to each physical layer processing module; establishing a plurality of parallel execution flows, and respectively assigning data processing tasks of different time slots to different execution flows for parallel execution; wherein the data processing task of each time slot includes a data transmission task and a computing task of each physical layer processing module, and the computing task of each physical layer processing module is executed based on the hardware computing resources allocated to the physical layer processing module.

[0164] In addition, the logical instructions in the memory 530 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that contribute to the related art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0165] On the other hand, the present application also provides a computer program product, which includes a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the physical layer data parallel processing method provided by the above-mentioned methods, which includes: determining a plurality of physical layer processing modules to be executed in parallel in a communication link, and allocating hardware computing resources to each physical layer processing module; establishing a plurality of parallel execution flows, and respectively assigning data processing tasks of different time slots to different execution flows for parallel execution; wherein the data processing task of each time slot includes a data transmission task and a computing task of each physical layer processing module, and the computing task of each physical layer processing module is executed based on the hardware computing resources allocated to the physical layer processing module.

[0166] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the physical layer data parallel processing method provided by any of the above methods, and the method comprises: determining a plurality of physical layer processing modules to be executed in parallel in a communication link, and allocating hardware computing resources to each physical layer processing module; establishing a plurality of parallel execution flows, and allocating data processing tasks of different time slots to different execution flows respectively for parallel execution; wherein the data processing task of each time slot comprises a data transmission task and a computing task of each physical layer processing module, and the computing task of each physical layer processing module is executed based on the hardware computing resources allocated to the physical layer processing module.

[0167] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0168] From the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software plus a necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0169] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for physical layer data parallel processing, the method comprising: The method comprises: determining a plurality of physical layer processing modules to be executed in parallel in a communication link, and allocating hardware computing resources to each physical layer processing module; establishing a plurality of parallel execution flows, and allocating data processing tasks of different time slots to different execution flows for parallel execution; wherein the data processing task of each time slot comprises a data transmission task and a computing task of each physical layer processing module, and the computing task of each physical layer processing module is executed based on the hardware computing resources allocated to the physical layer processing module.

2. The physical layer data parallel processing method of claim 1, wherein, The allocation of hardware computing resources to each physical layer processing module comprises: calculating the minimum amount of hardware resources required by each physical layer processing module to process a unit of data within a single time slot; using the minimum amount of hardware resources as a resource allocation benchmark for the corresponding physical layer processing module, and allocating hardware computing resources to the physical layer processing module; wherein the sum of the hardware computing resources allocated to each physical layer processing module is not greater than the total amount of hardware resources of the device.

3. The physical layer data parallel processing method of claim 1, wherein, The method further comprises: within each execution flow, identifying a data dependency relationship between the data transmission task and the computing task of each physical layer processing module of the current time slot, the data transmission task comprising a host-to-device input data transmission task and a device-to-host output data transmission task; based on the data dependency relationship, determining the execution order of the data transmission task and the computing task of each physical layer processing module, and controlling the serial execution of each task according to the execution order.

4. The physical layer data parallel processing method of claim 3, wherein, The allocation of data processing tasks of different time slots to different execution flows for parallel execution comprises: controlling a plurality of execution flows to execute in time overlap at the same time, so that different execution flows execute tasks in different stages respectively; wherein when the first execution flow is executing the input data transmission task, the second execution flow is executing the computing task of the physical layer processing module, and the third execution flow is executing the output data transmission task.

5. The physical layer data parallel processing method according to any one of claims 1 to 4, characterized in that, The allocation of data processing tasks of different time slots to different execution flows for parallel execution comprises: for the data processing task of any time slot, detecting whether there is an idle execution flow in a preset flow resource pool; if there is an idle execution flow, then allocating the data processing task of the any time slot to the idle execution flow for execution.

6. The physical layer data parallel processing method of claim 5, wherein, The method further comprises: in the case where the data processing task of the any time slot is executed, putting the execution flow corresponding to the any time slot into the flow resource pool for reuse in subsequent time slots.

7. The physical layer data parallel processing method of claim 5, wherein, The construction of the flow resource pool comprises: determining the pipeline depth based on the number of physical layer processing modules to be executed in parallel in the communication link and the number of data transmission directions; creating execution flow objects in a number equal to the pipeline depth to form the flow resource pool.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The processor executes the computer program to implement the physical layer data parallel processing method according to any one of claims 1 to 7. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the physical layer data parallel processing method according to any one of claims 1 to 7.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the physical layer data parallel processing method according to any one of claims 1 to 7.

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