Adaptive data anti-lost method for 1553B bus RT equipment

Abstract

A self-adaptive data anti-lost method for a 1553B bus RT device comprises the steps that a processor initializes a 1553B protocol chip, the 1553B protocol chip working mode, a device sub-address, a receiving and sending sub-address interrupt mode, a sub-address data cache type and a sub-address cache address are set, an interrupt information list is initialized, and a user callback function is registered; after the processor receives interrupt information sent by the 1553B protocol chip, the processor enters an interrupt service processing flow, including closing interrupt of the 1553B protocol chip, reading the number n of interrupt logs in the 1553B protocol chip, entering an interrupt log processing flow to process the interrupt information when the number n of the interrupt logs is greater than 1, and entering an interrupt service processing flow when the number n of the interrupt logs is 1. Entering a direct interrupt processing flow to process interrupt information; and after the user callback function is executed, judging the number of times that the interrupt data with the status bit being 1 and the effective bit being 0 in the interrupt information list are not used, if the number of times is greater than 3, shielding the interrupt data as an interrupt source of the 1553B protocol chip, and starting the interrupt of the 1553B protocol chip.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of MIL-STD-1553B bus interrupt processing design, and particularly relates to a method for adaptive data loss prevention of a 1553B bus RT device. BACKGROUND

[0002] MIL-STD-1553B bus is used as an avionics aviation data bus, has bidirectional transmission characteristics, high real-time and reliability, and is widely applied to aircraft and radar, and is also widely applied to the bus in space systems.

[0003] MIL-STD-1553B bus mainly comprises a bus controller BC, a remote terminal RT and an optional bus monitor MT device. The BC device is used for executing and starting data transmission, the RT device extracts received data or sends data under the control of the BC device, and the MT device is used for monitoring data transmission on the bus, and recording and analyzing data sources on the bus. One BC device, at most 30 RT devices or one MT device are included on a MIL-STD-1553B bus.

[0004] Data transmission and reception of the RT device is performed by a 1553B protocol chip and a processor. The 1553B protocol chip receives mode control and data sent by the BC device on the 1553B bus, and notifies the processor of the received mode control and data through a parallel bus, such as a 16-bit wide local bus, or a serial bus, such as an SPI bus. The data sent by the user to the BC device is also sent to the 1553B protocol chip buffer through a parallel bus or a serial bus, and is read by the BC device. The notification mechanism between the 1553B protocol chip and the processor is an interrupt. When the 1553B protocol chip receives a command or data on the bus, it will actively trigger an interrupt to notify the processor. The interrupt service function will obtain the command or data information on the bus, such as data type, data sub-address, data length, etc., and notify the user. The user decides whether to receive data or send data to a specific sub-address on the bus according to the demand in the task thread.

[0005] The command or data transmission and reception type on the 1553B bus includes broadcast data and non-broadcast data. Each type of data contains 30 received data sub-addresses, 30 sent data sub-addresses, 32 sent mode control words, and 32 received mode control words. Each received or sent sub-address can receive 1-32 bytes. When the commonly used 1553B protocol chip transmits and receives data, all the mode control instruction / data transmission and reception type interrupts are enabled. When the 1553B protocol chip receives non-broadcast data and broadcast data with the same device sub-address, it will directly trigger the processor interrupt and enter the interrupt service program. The processing mode of enabling all mode control instruction and data transmission and reception type interrupts has the following disadvantages:

[0006] (1) An RT device in the system only needs to process specific non-broadcast data and specific broadcast data, enabling all mode control instructions and data transceiver type interrupt processing mode, which will process a large number of useless mode control words and useless data in interrupt processing, increasing the interrupt service processing load;

[0007] (2) The interrupt triggered by a large number of useless mode control words and useless data will frequently preempt the processor interrupt resource, causing the processor to be unable to respond to other interrupts in time, affecting the real-time performance of the processor in processing data;

[0008] (3) The interrupt triggered by a large number of useless mode control words and useless data will frequently preempt the processor's task thread, causing the task processing time to be lengthened, affecting the task processing progress, and even causing the task to cross frames and cause system abnormalities.

[0009] Generally, when a 1553B protocol chip performs interrupt processing with a processor through a serial bus such as an SPI bus, the interrupt type and data type are directly determined by reading the interrupt status word and command word register. Since the SPI bus needs to go through the steps of selecting a memory address pointer, sending a write operation instruction code, sending an operation address, and sending a read-write operation instruction to read the interrupt status word data and command word data when accessing the 1553B protocol chip, the 1553 data is parsed according to the interrupt status word and command word data information, and the following disadvantages exist in the direct reading of the interrupt status word and the command word in the middle-end processing mode:

[0010] (1) 1 useful register reading needs other 5 read-write operations, the SPI bus reading process is time-consuming, and the interrupt status and command word information triggered during the reading process may be covered by the next 1553B bus command or data due to the failure to read in time, causing the loss of interrupt data;

[0011] (2) Other interrupt sources occupy the processor interrupt controller, causing the loss of interrupt data;

[0012] (3) The lost interrupt information cannot be reacquired.

[0013] In view of the existence of the above technical defects, the present application is proposed. SUMMARY

[0014] The purpose of the present application is to provide a 1553B bus RT device adaptive data loss prevention method, which is a MIL-STD-1553B bus remote terminal RT device adaptive data loss prevention method, to overcome or alleviate at least one aspect of the known technical defects.

[0015] The technical solution of the present application is:

[0016] A 1553B bus RT device adaptive data loss prevention method, comprising:

[0017] The processor initializes the 1553B protocol chip, including setting the working mode of the 1553B protocol chip, the device sub-address, the transceiving sub-address interrupt mode, the sub-address data cache type, the sub-address cache address, and initializing the interrupt information list and registering the user callback function;

[0018] When the processor receives the interrupt information sent by the 1553B protocol chip, the interrupt service processing flow is entered, including closing the interrupt of the 1553B protocol chip, reading the interrupt log quantity n of the 1553B protocol chip, when the interrupt log quantity n is greater than 1, the interrupt log processing flow is entered to process the interrupt information, and when the interrupt log quantity n is 1, the direct interrupt processing flow is entered to process the interrupt information;

[0019] The interrupt log processing flow is specifically:

[0020] The interrupt log information in the interrupt log cache is obtained according to the interrupt log quantity and the interrupt log address;

[0021] The interrupt identification information and the interrupt address information are parsed from the interrupt log information, the interrupt type is identified according to the interrupt identification information, it is identified whether the interrupt type is sending or receiving according to the interrupt address information, it is identified whether the data type is broadcast data or non-broadcast data, the transceiving data sub-address and the corresponding sub-address description list are parsed according to the interrupt address information, and the data storage position and the data length are obtained according to the control word information in the description list;

[0022] All the interrupt data information in the interrupt log is updated into the interrupt information list;

[0023] The interrupt log quantity n is read again, when n is 0, the user callback function is executed, and if n is not 0, the interrupt log processing flow is executed again;

[0024] The direct interrupt processing flow is specifically:

[0025] The interrupt state, the current command and the control word address are directly read;

[0026] The interrupt log quantity n is read again, when n is 0, the interrupt information is parsed, the data sub-address, the data type and the data length are parsed, the interrupt information list is updated, the interrupt information is informed to the user through the user callback function, and if n is not 0, the interrupt log processing flow is jumped to;

[0027] After the user callback function is executed, it is judged whether the number of times that the interrupt data with the state bit being 1 and the valid bit being 0 in the interrupt information list is unused is greater than 3, if yes, the interrupt enable bit corresponding to the interrupt data in the description list is set to 0, the interrupt data is shielded as the 1553B protocol chip interrupt source, and the 1553B protocol chip interrupt is enabled, if no, the 1553B protocol chip interrupt is enabled directly.

[0028] According to at least one embodiment of the present application, in the method for adaptive data loss prevention of the 1553B bus RT device, the 1553B protocol chip is initialized and configured, specifically as follows:

[0029] The working mode of the 1553B protocol chip is set to the RT mode;

[0030] The RT device address is set according to the user's use demand;

[0031] The transceiving subaddress interrupt mode is set, including three modes of the receiving interrupt, the broadcast interrupt and the sending interrupt, the address range of the broadcast and non-broadcast transceiving subaddress is 0-31, and there are 128 kinds of message interrupt trigger types, the interrupt invalidation or validation is realized by setting the corresponding bit in the control word in the description list of the 1553B protocol chip, when the interrupt enable broadcast and non-broadcast bit in the corresponding command descriptor list is 0, the 1553B protocol chip will not generate the interrupt when receiving the command or data;

[0032] The transceiving subaddress buffer mode is set, including the single buffer mode, the double buffer mode and the cyclic buffer mode;

[0033] The transceiving subaddress buffer address is set, and a unique buffer address is allocated for each transceiving subaddress, which is used for transceiving the bus data;

[0034] The interrupt information list is initialized, and the list has 128 items, each item includes a state bit, a valid bit and an unused count variable, and all the list is set to 0.

[0035] According to at least one embodiment of the present application, in the method for adaptive data loss prevention of the 1553B bus RT device, the user callback function notifies the user of each interrupt information, and the user knows the data type, the data subaddress and the data length in the interrupt data.

[0036] According to at least one embodiment of the present application, in the method for adaptive data loss prevention of the 1553B bus RT device, the interrupt information list is updated, specifically as follows:

[0037] Convert the interrupt data into an index, which is equal to the combination of Bd, TR and Sa, wherein Bd is a broadcast / non-broadcast flag bit, with a bit width of 1 Bit, the broadcast data is 0, and the non-broadcast data is 1, TR is a read-write flag bit, with a bit width of 1 Bit, wherein the read data is 0, and the write data bit is 1, and Sa is a sub-address, with a bit width of 5 Bit, wherein 0 or 31 indicates a mode control instruction, and 1-30 indicates a data instruction;

[0038] According to the index, find the state bit of the corresponding interrupt in the interrupt information list, if the state is 0, set the state to 1, according to the index, find the valid bit of the corresponding interrupt in the interrupt information list, if the valid bit is 1, end the flow, and when the valid bit is 0, add 1 to the unused parameter.

[0039] According to at least one embodiment of the present application, in the above-mentioned 1553B bus RT device adaptive data loss prevention method, when the user performs a send data operation, data is written to a specific sub-address, and then control instruction code 16 is written to the corresponding vector word, the send data sub-address interrupt state is updated, the state bit in the list item corresponding to the write data sub-address in the interrupt information list is set to 1, the valid bit is set to 1, the control instruction code 16 corresponding interrupt information list is updated, the state bit in the list item corresponding to the write control instruction code 16 in the interrupt information list is set to 1, and the valid bit is set to 1.

[0040] When the user performs a receive data operation, data on the data sub-address to be received is read, and then the data sub-address corresponding interrupt information list is updated, the state bit in the list item corresponding to the data sub-address in the interrupt information list is set to 1, and the valid bit is set to 1.

[0041] According to at least one embodiment of the present application, in the above-mentioned 1553B bus RT device adaptive data loss prevention method, when the user adds a data interrupt source, first set the interrupt enable bit of the control word corresponding to the data sub-address in the description list on the 1553B protocol chip, and then update the data sub-address interrupt state, set the state bit in the list item corresponding to the data sub-address in the interrupt information list to 1, and set the valid bit to 1.

[0042] When the user deletes a data interrupt source, first clear the interrupt enable bit of the control word corresponding to the data sub-address in the description list on the 1553B protocol chip, and then set the state bit in the list item corresponding to the data sub-address in the interrupt information list to 0, and set the valid bit to 0.

[0043] The present application has at least the following beneficial technical effects:

[0044] A 1553B bus RT device adaptive data loss prevention method is provided, which has the following advantages:

[0045] The mode control word and data type required by the user can be accurately identified, and a large number of useless mode control words and useless data triggered interrupts can be automatically shielded, so that the number of interrupt services is reduced, the interrupt processing load of the processor is reduced, the system response timeliness is improved, and the communication reliability is improved.

[0046] The interrupt log mode is used to avoid the loss of interrupt data caused by the complex SPI bus reading timing, improve the communication reliability, and avoid the loss of 1553B interrupt data caused by the processor processing other interrupts.

[0047] The mode control word and data type required by the user can be automatically identified according to the user demand, and the universality of the driver in different use scenarios is improved.

[0048] The user can be provided with a user entry to modify the user mode control word and data type demand, and the use flexibility is improved.

[0049] The interrupt source information is directly read, and the interrupt source is indirectly obtained by analyzing the interrupt log, so that the interrupt source information is not lost, and the interrupt source rate is improved. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is a 1553B bus RT device adaptive data loss prevention principle block diagram provided by the embodiment of the application;

[0051] Figure 2 is a flowchart of initializing a 1553B protocol chip provided by the embodiment of the application;

[0052] Figure 3 is a flowchart of interrupt service processing provided by the embodiment of the application;

[0053] Figure 4 is a flowchart of automatically obtaining useful interrupt information provided by the embodiment of the application;

[0054] Figure 5 is a flowchart of updating the interrupt information list provided by the embodiment of the application.

[0055] In order to better illustrate the embodiment, some contents of the drawings may be omitted, enlarged or reduced, and are only used for exemplary description, and cannot be understood as a limitation on the application. DETAILED DESCRIPTION

[0056] In order to make the technical solutions of the present application and their advantages clearer, the technical solutions of the present application will be further clearly and completely described in the following with reference to the drawings. It should be understood that the specific embodiments described herein are only some embodiments of the present application, which are used to explain the present application, but not to limit the present application. It should be noted that, for the convenience of description, only parts related to the present application are shown in the drawings, and other related parts can be referred to the general design.

[0057] In addition, unless otherwise defined, the technical terms or scientific terms used in the description of the present application should be the general meanings understood by the general skilled person in the field to which the present application belongs. In the description of the present application, "comprising" indicates that the concept appearing before the word covers the concepts listed after the word and their equivalents, and does not exclude other associated concepts.

[0058] A method for adaptive data loss prevention of a 1553B bus RT device, which can automatically shield the 1553B data type useless to the user by combining the interrupt log information and the user read-write behavior, in order to prevent the data loss of the 1553B caused by the processor processing not in time, on the one hand, it can only process the data type needed by the user, and automatically shield the data type useless to the user by combining the interrupt log information and the user read-write behavior, reduce the number of 1553B interrupts, and reduce the interrupt service load of the system, on the other hand, it can adapt to low-speed interfaces such as SPI interfaces, and prevent the interrupt data loss caused by the slow read-write rate of the low-speed interface or the interrupt processing not in time.

[0059] The implementation principle block diagram of the method for adaptive data loss prevention of a 1553B bus RT device can be seen from Figure 1 , Figure 1 The design in (a) is mainly divided into a processor and a 1553B protocol chip, Figure 1 The design in (b) is mainly divided into a processor, a 1553B protocol chip, and an FPGA with an SRIO / PCIE to SPI interface IP core.

[0060] The processor can be a PowerPC processor, an ARM processor, including domestic processors such as Ft series processors, fmql series Zynq processors, or DSP processors, with a PCIe controller or an SRIO controller or an SPI controller or a parallel bus LBC controller, an interrupt controller. The 1553B protocol chip acts as the function of the RT device on the 1553B bus, can receive data or mode control instructions on the 1553B bus, respond to data transmission instructions on the bus, has an interrupt log function, and is internally provided with an isolation transformer to realize isolation with the external 1553B bus. The FPGA with an SRIO / PCIE to SPI interface IP core realizes the conversion of the SRIO / PCIE bus interface on the processor to the SPI interface bus.

[0061] The processor initializes the 1553B protocol chip, including setting the chip's operating mode, device sub-address, transmit / receive sub-address interrupt mode, sub-address data buffer type, and sub-address buffer address. It also initializes the interrupt information list, registers user callback functions, and receives and processes interrupt information from the 1553B chip. It obtains interrupt source information either directly by reading the interrupt status register or indirectly through the interrupt log. The processor then submits the parsed command and control information and transmit / receive data information, including sub-address information and data length, to the user through the user callback function. Furthermore, based on the user's operation data type, it automatically identifies the necessary command and control information and transmit / receive data information, including sub-address information and data length, as well as other useful interrupt source information. Its workflow is as follows: Figure 4 As shown, useless interrupt source information is automatically masked, and interrupt log information is used to determine whether there are any interrupt sources that have not been processed in a timely manner and report them.

[0062] Perform initial configuration of the 1553B protocol chip, such as... Figure 2 As shown, it includes:

[0063] Set the 1553B protocol chip to RT mode;

[0064] Configure the RT device address according to user needs;

[0065] The interrupt mode for the transmit and receive sub-addresses can be set, including three modes: receive interrupt, broadcast interrupt, and transmit interrupt. The address range of the transmit and receive sub-addresses for both broadcast and non-broadcast is 0-31, with a total of 128 message interrupt triggering types. The interrupt is enabled or disabled by setting the corresponding bit of the control word in the description list of the 1553B protocol chip. When the interrupt enable broadcast and non-broadcast bit in the corresponding command descriptor list is 0, the 1553B protocol chip will not generate an interrupt when it receives the command or data.

[0066] Configure the send and receive sub-address caching mode, including single-buffer mode, double-buffer mode, and circular buffer mode;

[0067] Configure the transmit and receive sub-address cache address, and assign a unique cache address to each transmit and receive sub-address for transmitting and receiving bus data;

[0068] Initialize the interrupt information list, which contains 128 items. Each item includes a status bit, a valid bit, and an unused counter variable. Set the entire list to 0.

[0069] Callback function for registered users.

[0070] When the processor receives the interrupt information sent by the 1553B protocol chip, the processor enters the interrupt service routine, such as... Figure 3As shown, it includes closing 1553B protocol chip interrupt, reading 1553B protocol chip interrupt log number n, when the interrupt log number n is greater than 1, it indicates that the data information triggering the interrupt is covered by other 1553B data information, entering the interrupt log processing flow to process the interrupt information, when the interrupt log number n is 1, it indicates that the data information triggering the interrupt is not covered by other 1553B data information, entering the direct interrupt processing flow to process the interrupt information.

[0071] The interrupt log processing flow is specifically as follows:

[0072] According to the interrupt log number and the interrupt log address, the interrupt log information in the interrupt log buffer is obtained.

[0073] The interrupt identification information and the interrupt address information are parsed from the interrupt log information, the interrupt type is identified according to the interrupt identification information, whether the interrupt type is sending or receiving is identified according to the interrupt address information, whether the data type is broadcast data or non-broadcast data is identified, the transceiving data sub-address and the corresponding sub-address description list are parsed from the interrupt address information by the driver, and the data storage position and the data length are obtained according to the control word information in the description list.

[0074] All the interrupt data information in the interrupt log is updated into the interrupt information list.

[0075] The interrupt log number n is read again, when n is 0, it indicates that no new interrupt information enters during the interrupt log processing, the user callback function is executed, if n is not 0, it indicates that new interrupt information appears during the interrupt log processing, the interrupt log processing flow is executed again.

[0076] The user callback function notifies the user of each interrupt information, the user knows the data type (broadcast receiving data, broadcast sending data, non-broadcast receiving data, non-broadcast sending data), the data sub-address (mode control instruction or data) and the data length in the interrupt data.

[0077] The update to the interrupt information list is as shown in the following table: Figure 5 The update to the interrupt information list is as shown in the following table:

[0078] The interrupt data is converted into an index, the index is equal to the combination of Bd, TR and Sa, wherein Bd is a broadcast / non-broadcast flag bit, the bit width is 1 Bit, the broadcast data is 0, the non-broadcast data is 1, TR is a read-write flag bit, the bit width is 1 Bit, wherein the read data is 0 and the write data is 1, Sa is a sub-address, the bit width is 5 Bit, wherein 0 or 31 indicates a mode control instruction, 1-30 indicates a data instruction.

[0079] According to the index, the state bit of the corresponding interrupt in the interrupt information list is found. If the state is 0, it indicates that the interrupt information type has not been received before, and the state is set to 1. If the state is 1, jump to the next step;

[0080] According to the index, the valid bit of the corresponding interrupt in the interrupt information list is found. If the valid bit is 1, it indicates that the interrupt information type is used by the user, and the process ends. When the valid bit is 0, it indicates that the interrupt information type has not been used before, and the unused parameter needs to be increased by 1.

[0081] Direct interrupt processing flow, please refer to the following:

[0082] Directly read the interrupt state, current command and control word address;

[0083] Read the interrupt log number n again. When n is 0, it indicates that the obtained interrupt information is correct and not contaminated by other interrupt data. Analyze the current interrupt information, analyze the data sub-address, data type and data length, and update the interrupt information list. Inform the user of the interrupt information through the user callback function. The user knows the data type in the interrupt data (broadcast receiving data, broadcast sending data, non-broadcast receiving data, non-broadcast sending data), data sub-address (mode control instruction or data) and data length. If n is not 0, it indicates that the interrupt information is contaminated, and jump to the interrupt log processing flow. At this time, the number of interrupt data to be processed is n+1.

[0084] After executing the user callback function, judge the number of times the interrupt data with state bit 1 and valid bit 0 in the interrupt information list is not used. If the number of times is greater than 3, it indicates that the interrupt data is not needed by the user. Set the interrupt enable bit corresponding to the interrupt data in the description list to 0, and shield the interrupt data as the 1553B protocol chip interrupt source. Finally, enable the 1553B protocol chip interrupt. If the number of times is less than or equal to 3, directly enable the 1553B protocol chip interrupt.

[0085] The user updates the interrupt information list through read and write operations. When the user performs a send data operation, data is written to a specific sub-address, and then control instruction code 16 is written to the corresponding vector word. Update the send data sub-address interrupt state. Set the state bit to 1 in the list item corresponding to the write data sub-address in the interrupt information list, and set the valid bit to 1. Update the control instruction code 16 corresponding interrupt information list. Set the state bit to 1 in the list item corresponding to the write control instruction code 16 in the interrupt information list, and set the valid bit to 1, as shown in Figure 4 (a). When the user performs a receive data operation, read the data on the data sub-address to be received, and then update the data sub-address corresponding interrupt information list. Set the state bit to 1 in the list item corresponding to the data sub-address in the interrupt information list, and set the valid bit to 1, as shown in Figure 4 (b).

[0086] When the user needs to customize the modification of the data interrupt source, it can be realized by adding and deleting the interrupt source function. When the user needs to add the interrupt source function, first set the interrupt enable bit of the control word corresponding to the data sub-address in the 1553B protocol chip description list, and then update the data sub-address interrupt state, set the state bit to 1 and the valid bit to 1 in the list item corresponding to the data sub-address in the interrupt information list. When the user needs to delete the data interrupt source, first clear the interrupt enable bit of the control word corresponding to the data sub-address in the 1553B protocol chip description list, and then set the state bit to 0 and the valid bit to 0 in the list item corresponding to the data sub-address in the interrupt information list.

[0087] The above-mentioned 1553B bus RT device adaptive data loss prevention method adopts device useful mode control word and data type automatic collection technology, automatically acquires useful information such as useful control word and data sub-address according to user receiving and sending data parameters in this scene, adopts interrupt log acquisition and analysis technology, acquires the number of interrupt logs and interrupt log addresses of the 1553B protocol chip, analyzes the message type, data length and other information of each interrupt according to the interrupt log information, adopts useless mode control word and data type interrupt source shielding technology, shields the broadcast / non-broadcast mode control word receiving and transmitting sub-address, broadcast / non-broadcast receiving and transmitting data sub-address and other interrupt sources that the user does not need, and no longer triggers the processor interrupt, and adopts interrupt source acquisition mode automatic switching technology to realize direct acquisition of interrupt source information and indirect automatic switching through interrupt log analysis mode in the process of acquiring interrupt source information.

[0088] The above-mentioned 1553B bus RT device adaptive data loss prevention method can automatically shield a large number of useless broadcast / non-broadcast mode control words and useless broadcast / non-broadcast data triggered interrupts, reduce the number of interrupt services, reduce the processor interrupt processing load, improve the system response timeliness, judge whether the interrupt source information has an overlap problem in the interrupt log mode, avoid the interrupt data loss caused by the complex SPI bus reading timing or the processor not responding in time due to processing other transactions, improve the communication reliability, automatically identify the mode control word and data type required by the user according to the user's needs, improve the universality of the driver program in different use scenarios, and automatically convert between direct reading mode and indirect interrupt source acquisition mode through interrupt log analysis mode, which can ensure that the interrupt source information is not lost and improve the interrupt processing rate.

[0089] The technical scheme of the present application has been described in combination with the preferred embodiments shown in the drawings, and it should be understood by those skilled in the art that the protection scope of the present application is obviously not limited to these specific embodiments, and those skilled in the art can make equivalent changes or replacements to the related technical features without departing from the principles of the present application, and the technical schemes after the changes or replacements will fall within the protection scope of the present application.

Claims

1. A method for 1553B bus RT device adaptive data loss prevention, characterized in that, Comprise: The processor initializes the 1553B protocol chip, including setting the 1553B protocol chip working mode, device sub-address, transceiver sub-address interrupt mode, sub-address data buffer type, sub-address buffer address, and initializing the interrupt information list, and registering the user callback function; When the processor receives the interrupt information sent by the 1553B protocol chip, enter the interrupt service processing flow, including closing the 1553B protocol chip interrupt, reading the interrupt log number n, when the interrupt log number n is greater than 1, enter the interrupt log processing flow to process the interrupt information, when the interrupt log number n is 1, enter the direct interrupt processing flow to process the interrupt information; The interrupt log processing flow is specifically: According to the interrupt log number and the interrupt log address, obtain the interrupt log information in the interrupt log buffer; From the interrupt log information, parse out the interrupt identification information and the interrupt address information, identify the interrupt type according to the interrupt identification information, identify whether the interrupt type is sending or receiving according to the interrupt address information, identify whether the data type is broadcast data or non-broadcast data, parse out the transceiver data sub-address and the corresponding sub-address description list according to the interrupt address information, and obtain the data storage position and the data length according to the control word information in the description list; Update all the interrupt data information in the interrupt log to the interrupt information list; Read the interrupt log number n again, when n is 0, execute the user callback function, if n is not 0, re-execute the interrupt log processing flow; The direct interrupt processing flow is specifically: Directly read the interrupt state, the current command and the control word address; Read the interrupt log number n again, when n is 0, parse the interrupt information, parse out the data sub-address, the data type and the data length, update the interrupt information list, inform the user of the interrupt information through the user callback function, if n is not 0, jump to the interrupt log processing flow; After executing the user callback function, judge the number of times that the interrupt data with state bit 1 and valid bit 0 in the interrupt information list is not used, if the number of times is greater than 3, set the interrupt enable bit corresponding to the interrupt data in the description list to 0, shield the interrupt data as the 1553B protocol chip interrupt source, turn on the 1553B protocol chip interrupt, if the number of times is less than or equal to 3, turn on the 1553B protocol chip interrupt.

2. The method for 1553B bus RT device adaptive data loss prevention according to claim 1, characterized in that, Initialize and configure the 1553B protocol chip, specifically: Set the 1553B protocol chip working mode to RT mode; Set the RT device address according to the user's needs; Set the transceiver sub-address interrupt mode, including three modes of receiving interrupt, broadcast interrupt and sending interrupt, the address range of broadcast and non-broadcast receiving and transmitting sub-address is 0-31, a total of 128 message interrupt trigger types, set the interrupt invalid or valid is realized by setting the corresponding bit of the control word in the 1553B protocol chip description list, when the interrupt enable broadcast and non-broadcast bit in the corresponding command descriptor list is 0, the 1553B protocol chip will not generate interrupt when receiving the command or data; Set the transceiver sub-address buffer mode, including single buffer mode, double buffer mode and circular buffer mode; Setting the transceiver sub-address cache address, allocating a unique cache address for each receiving and transmitting sub-address, used for receiving and transmitting bus data; Initializing the interrupt information list, which contains 128 items, each item including a status bit, a valid bit and an unused count variable, setting all items to 0.

3. The method for 1553B bus RT device adaptive data loss prevention according to claim 2, characterized in that, The user callback function informs the user of each interrupt information, and the user learns the data type, data sub-address and data length in the interrupt data.

4. The method for 1553B bus RT device adaptive data loss prevention of claim 3, wherein, Updating the interrupt information list, specifically: Converting the interrupt data into an index, which is equal to the combination of Bd, TR and Sa, where Bd is the broadcast / non-broadcast flag bit, 1 bit wide, broadcast data is 0 and non-broadcast data is 1, TR is the read-write flag bit, 1 bit wide, where read data is 0 and write data is 1, and Sa is the sub-address, 5 bits wide, where 0 or 31 represents the mode control instruction, and 1-30 represents the data instruction; According to the index, find the status bit of the corresponding interrupt in the interrupt information list, if the status is 0, set it to 1, according to the index, find the valid bit of the corresponding interrupt in the interrupt information list, if the valid bit is 1, end the process, when the valid bit is 0, add 1 to the unused parameter.

5. The method for 1553B bus RT device adaptive data loss prevention according to claim 4, characterized in that, When the user performs a send data operation, write data to a specific sub-address, then write control instruction code 16 to the corresponding vector word, update the send data sub-address interrupt status, set the status bit to 1 in the list item corresponding to the write data sub-address in the interrupt information list, set the valid bit to 1, update the interrupt information list corresponding to control instruction code 16, set the status bit to 1 in the list item corresponding to control instruction code 16 in the interrupt information list, set the valid bit to 1. When the user performs a receive data operation, read the data on the data sub-address to be received, then update the data sub-address interrupt information list, set the status bit to 1 in the list item corresponding to the data sub-address in the interrupt information list, set the valid bit to 1.

6. The method for 1553B bus RT device adaptive data loss prevention according to claim 5, characterized in that, When the user adds a data interrupt source, first set the interrupt enable bit of the control word corresponding to the data sub-address in the description list on the 1553B protocol chip, then update the data sub-address interrupt status, set the status bit to 1 in the list item corresponding to the data sub-address in the interrupt information list, set the valid bit to 1. When the user deletes a data interrupt source, first clear the interrupt enable bit of the control word corresponding to the data sub-address in the description list on the 1553B protocol chip, then set the status bit to 0 in the list item corresponding to the data sub-address in the interrupt information list, set the valid bit to 0.

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