GAA and FinFET heterogeneous process PDK construction method, device and equipment

Abstract

The invention discloses a GAA and FinFET heterogeneous process PDK construction method, device and equipment, relates to the technical field of integrated circuit design automation, and is used for solving the problems of poor compatibility, inflexible physical verification mechanism and inaccurate MIV parasitic parameter modeling during cross-process node design of a three-dimensional PDK in the prior art. Comprising the following steps: constructing a three-dimensional heterogeneous PDK integrated framework; on the basis of a three-dimensional heterogeneous PDK integrated framework, a dynamically configurable cross-layer physical verification mechanism is set, and a global control variable is introduced; based on a three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, aiming at a key interconnection structure in three-dimensional integration, constructing a lumped model; and integrating the lumped model into a three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integrated framework. According to the technical scheme provided by the invention, compatibility, verification flexibility and model precision in collaborative design of GAA and FinFET heterogeneous processes can be ensured, and good expansibility is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design automation, and in particular to a GAA and FinFET heterogeneous process PDK construction method, device and equipment. BACKGROUND

[0002] With the continuous scaling of CMOS process nodes, technical challenges are increasing, and power consumption and integration density problems are particularly prominent. M3D technology realizes high-density interconnection by sequentially integrating multiple device layers, and exhibits excellent power consumption characteristics. At the device level, FinFET effectively enhances the gate control capability and suppresses the leakage current by virtue of its three-dimensional fin structure and mature process; and the gate all-around (GAA) structure can provide more accurate current control at more advanced nodes. Three-dimensional integration technology is expected to combine the process maturity of FinFET and the performance advantages of GAA at the scaling node, thereby optimizing the power, performance and area of the chip.

[0003] PDK is a key bridge connecting integrated circuit manufacturing process and design, and usually includes process files, device models, physical verification rule files and parameterized cells and other components. Efficient and accurate process design kit is essential to improve design efficiency.

[0004] In the prior art, the PDK framework for monolithic three-dimensional integration is not perfect. The typical solution is to simply combine two two-dimensional PDKs based on the same process node, and the device models and metal layer characteristics are used as the two-dimensional PDK data, which fails to solve the inherent compatibility problem when integrating different device structures (such as GAA and FinFET). The framework directly introduces physical verification rule files in the PDK components, and uses a fixed value assumption for the parasitic RC parameters of MIV. This assumption is based on the simulation extraction results of the ideal three-dimensional physical structure of MIV, and fails to fully consider the process fluctuations in the size parameters (such as height and width) and shape of MIV in the actual manufacturing process, lacks analysis of the impact of process fluctuations, and ignores the parasitic effects under high-frequency operating conditions.

[0005] Therefore, there is an urgent need to provide a more reliable GAA and FinFET heterogeneous process PDK construction scheme. SUMMARY

[0006] The present application aims to provide a GAA and FinFET heterogeneous process PDK construction method, device and equipment, which solves the problems of poor compatibility, inflexible physical verification mechanism and inaccurate MIV parasitic parameter modeling of the three-dimensional PDK in the prior art when designing across process nodes.

[0007] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions: In a first aspect, the present application provides a GAA and FinFET heterogeneous process PDK construction method, which comprises: constructing a three-dimensional heterogeneous PDK integration framework; the three-dimensional heterogeneous PDK integration framework at least comprises three-dimensional process files, three-dimensional device models, three-dimensional physical verification rules, three-dimensional parasitic parameter extraction files and PCell units; on the basis of the three-dimensional heterogeneous PDK integration framework, setting a dynamically configurable cross-layer physical verification mechanism, and introducing global control variables; based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, constructing a lumped model for the key interconnection structure in three-dimensional integration; integrate the lumped model into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework.

[0008] Optionally, the three-dimensional heterogeneous PDK integration framework supports the integration of GAA and FinFET heterogeneous processes, and at least includes restructured process files and unified layer naming rules to realize the compatibility of layer definition under different process nodes; the three-dimensional heterogeneous PDK integration framework at least comprises: obtaining basic PDK components; the basic PDK components at least include GAA device PDK based on normal temperature manufacturing process and FinFET device PDK based on low heat budget manufacturing process; fuse and restructure the process files corresponding to the GAA device PDK and the FinFET device PDK to construct three-dimensional process files; based on the GAA device PDK and the FinFET device PDK, the device model is temperature compensated to obtain a three-dimensional device model for the interlayer temperature gradient caused by three-dimensional stacking structure; set three-dimensional parasitic parameter extraction rules; based on the three-dimensional process files and the three-dimensional device model, restructure to obtain PCell units.

[0009] Optionally, on the basis of the three-dimensional heterogeneous PDK integration framework, a dynamically configurable cross-layer physical verification mechanism is set, and global control variables are introduced, which comprises: set global control variables in the verification rules, and perform configurable switching between single-layer mode and multi-layer mode in DRC rules and LVS rules, and integrate cross-verification rules; the cross-verification rules at least include interlayer alignment rules, three-dimensional density and three-dimensional antenna effect rules; the global control variables are set in the verification rules, and the configurable switching between single-layer mode and multi-layer mode is performed in the DRC rules and the LVS rules, and the cross-verification rules are integrated, which comprises: Adding interlayer alignment rules in the DRC rule file, dynamically switching the physical verification file through a global control variable; In the LVS rule, the device identification logic is reconstructed based on the layer number, supporting independent or joint extraction of the FinFET device PDK at the bottom and the GAA device PDK at the top; When the global control variable is a preset specific value, the system executes the cross-verification rule in parallel to generate a comprehensive verification report.

[0010] Optionally, the global control variable is set in the verification rule, and the single-layer mode and multi-layer mode are configured to switch in the DRC rule and the LVS rule, and the cross-verification rule is integrated, including: Input the process temperature variation, material thermal expansion coefficient and initial length corresponding to the GAA device PDK and the FinFET device PDK; According to the expansion formula: ΔL =α·ΔT·L0 Calculate the size change caused by temperature change, and adjust the DRC interlayer alignment rule according to the size change, and merge the DRC rule file corresponding to the GAA device PDK and the FinFET device PDK; wherein ΔT represents the process temperature variation corresponding to the GAA device PDK and the FinFET device PDK, α represents the material thermal expansion coefficient, and L0 represents the initial length; Merge and modify the LVS rule file corresponding to the GAA device PDK and the FinFET device PDK; the layer name and layer number are compatible and consistent, and the layer number corresponds to the transistor device located at different layers; In the standard verification rule format, the verification mode is switched according to the value of the global control variable through a preset condition compilation instruction; the verification mode includes single-layer mode and multi-layer mode; the single-layer mode includes only verifying GAA layer and only verifying FinFET layer; the multi-layer mode means loading two-layer rules in parallel, activating cross-layer verification, and outputting a comprehensive verification report.

[0011] Optionally, based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for the key interconnection structure in three-dimensional integration, including: According to the geometric structure size and material physical properties of the key interconnection structure in the three-dimensional integration, the electrical parameters of the key interconnection structure are calculated respectively by using analytical formula; the electrical parameters at least include parasitic resistance, parasitic inductance, parasitic conductance and parasitic capacitance; The skin effect is introduced to dynamically reflect the change of resistance with frequency, and a lumped model is constructed.

[0012] Optionally, the step of calculating the electrical parameters of the key interconnect structures using analytical formulas based on the geometric dimensions and material physical properties of the key interconnect structures in the three-dimensional integration includes: Input the geometric dimensions, material physical properties, and process parameters of the key interconnect structure; Based on the geometric dimensions, material physical properties, and process parameters of the key interconnect structure, the following formula is used: Calculate the DC resistance; where ρ represents the resistivity of the conductive material, L represents the length, and r represents the resistance. MIV Indicates radius; Furthermore, a skin effect model is introduced to dynamically calculate parasitic resistance, which is expressed as: Among them, R MIV Denotes parasitic resistance, δ represents skin depth, and K p The correction coefficient representing the skin effect; Formula used: Calculate the parasitic capacitance, where C MIV C represents parasitic capacitance. ox Indicates the capacitance of the insulating layer, C dep Indicates the depletion layer capacitance; Based on the current loop approximation model: Calculate the parasitic inductance; where L MIV Indicates parasitic inductance; Using a coaxial cable model: Calculate the parasitic conductance, where G MIV Indicates parasitic conductance, t ox h represents the thickness of the insulating layer. Si ρ represents the height of the silicon layer. SiO2 This indicates the resistivity of silicon dioxide, an insulating material.

[0013] Optionally, to address the interlayer temperature gradient caused by the three-dimensional stacked structure, the step of obtaining a three-dimensional device model by performing temperature compensation on the device model based on the GAA device PDK and the FinFET device PDK includes: Input the specific temperature parameters of the GAA device PDK and the FinFET device PDK; The specific temperature parameters are applied to the corresponding device model, and the compensated three-dimensional device model that adapts to the temperature distribution of heterogeneous processes is output by calling the device model temperature compensation function.

[0014] Optionally, the reconstructing the PCell unit based on the three-dimensional process file and the three-dimensional device model comprises: updating a parameter list in a component description format file, and adding a three-dimensional related variable; the three-dimensional related variable at least comprises a number of the key interconnection structures; modifying a netlist generation module of the PCell based on the added three-dimensional related variable; the modified netlist generation module of the PCell calls the bottom GAA device, the top FinFET device and the specified number of key interconnection structures; recompiling the PCell library to generate the PCell unit supporting the three-dimensional heterogeneous circuit design.

[0015] Compared with the prior art, the application provides a GAA and FinFET heterogeneous process PDK construction method. A three-dimensional heterogeneous PDK integration framework is constructed; a dynamically configurable cross-layer physical verification mechanism is set based on the three-dimensional heterogeneous PDK integration framework, and a global control variable is introduced; a lumped model is constructed for the key interconnection structure in the three-dimensional integration based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism; and the lumped model is integrated into a three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework. The three core problems of compatibility, verification flexibility and model accuracy in the collaborative design of the GAA and FinFET heterogeneous process are effectively solved; wherein the dynamically configurable cross-layer physical verification mechanism is set, and the global control variable is introduced to realize seamless switching between single-layer and multi-layer modes, which significantly improves the verification comprehensiveness and reduces the design risk; based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for the key interconnection structure in the three-dimensional integration, which greatly improves the reliability of circuit post-simulation; at the same time, the application has good expansibility and provides strong technical support for high-density integration of more layers of stacking and emerging semiconductor processes. The application supports collaborative design across process nodes and has the expansion capability of heterogeneous integration of carbon nanotubes, two-dimensional materials and silicon semiconductor materials, which helps to promote the industrialization application of high-density integrated circuits.

[0016] In the second aspect, the application provides a GAA and FinFET heterogeneous process PDK construction device, which is applied to the GAA and FinFET heterogeneous process PDK construction method provided in the first aspect, and the device comprises: a three-dimensional heterogeneous PDK integration framework construction module configured to construct a three-dimensional heterogeneous PDK integration framework; the three-dimensional heterogeneous PDK integration framework at least comprises a three-dimensional process file, a three-dimensional device model, a three-dimensional physical verification rule, a three-dimensional parasitic parameter extraction file and a PCell unit; The cross-layer physical verification mechanism determination module is configured to set a dynamically configurable cross-layer physical verification mechanism and introduce a global control variable based on the three-dimensional heterogeneous PDK integration framework. The lumped model construction module is configured to construct a lumped model for a key interconnection structure in three-dimensional integration based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism. The lumped model integration module is configured to integrate the lumped model into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework.

[0017] In a third aspect, the present application provides a GAA and FinFET heterogeneous process PDK construction device, which comprises: A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program executable by the processor; and the processor executes the computer program to perform the GAA and FinFET heterogeneous process PDK construction method.

[0018] The device scheme provided in the second aspect and the equipment scheme provided in the third aspect achieve the same technical effects as the method scheme provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the present application, form a part of the present application and illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings: Figure 1 A GAA and FinFET heterogeneous process PDK construction method flowchart provided by the present application; Figure 2 A three-dimensional heterogeneous PDK integration framework construction process schematic diagram provided by the present application; Figure 3 A three-dimensional heterogeneous process DRC / LVS multi-layer verification method flowchart provided by the present application; Figure 4 A single-chip interlayer via accurate modeling flowchart in a three-dimensional parasitic parameter extraction implementation method provided by the present application; Figure 5 A GAA and FinFET heterogeneous process PDK construction device module structure schematic diagram provided by the present application; Figure 6 A GAA and FinFET heterogeneous process PDK construction device structure schematic diagram provided by the present application. DETAILED DESCRIPTION

[0020] For the convenience of clearly describing the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", etc. are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish different thresholds, and the order is not limited. Those skilled in the art can understand that the terms of "first", "second", etc. do not limit the quantity and execution order, and the terms of "first", "second", etc. also do not necessarily mean different.

[0021] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0022] In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0023] First, the part of the abbreviations and key terms used in the embodiments of the present specification are defined in the form of a table: In the prior art, the three-dimensional PDK scheme has the following main technical problems: 1) Poor compatibility: When directly merging PDK components of different process nodes (especially different device structures, such as GAA and FinFET), there are conflicts in process layer definition, device naming rules, etc.

[0024] 2) Inflexible verification mechanism: DRC / LVS verification rules are difficult to switch flexibly between single-layer design and multi-layer collaborative design modes.

[0025] 3) MIV modeling is not accurate: the parasitic parameter modeling of the key interconnection structure MIV is too simplified, and the key process parameters such as height, radius and interlayer dielectric thickness are not combined to extract the accurate parasitic parameters, resulting in insufficient accuracy of the MIV model.

[0026] The above problems jointly restrict the efficiency and accuracy of cross-process node three-dimensional collaborative design. Therefore, the present application aims to build a three-dimensional PDK integration framework suitable for GAA and FinFET heterogeneous processes to solve the technical problems of compatibility, verification flexibility and MIV model accuracy, and support efficient collaborative design across process nodes. Specifically, the present application provides a GAA and FinFET heterogeneous process PDK construction method, device and equipment, which solves the technical problems of poor compatibility, inflexible physical verification mechanism and inaccurate MIV parasitic parameter modeling of existing three-dimensional PDK in cross-process node design. The PDK includes process files, device models, physical verification rules and PCell unit core components, and the method of the present application constructs a unified three-dimensional PDK framework that supports heterogeneous process integration.

[0027] It should be emphasized that: although the embodiments of the present application mainly describe two-layer stacking as the main object, the three-dimensional PDK integration framework construction method of the present application is also applicable to three-layer, four-layer or more device layer stacking structures. Only by integrating the process files, device models and verification rules of the newly added device layer according to the layer naming unification, model compatibility processing and verification rule expansion method described in the present application can it be realized. The device structure used in the technical solution is not limited to GAA and FinFET, and the principles and methods are also applicable to other types of devices, including but not limited to traditional silicon-based planar CMOS devices, carbon nanotube transistors, and two-dimensional material transistors and other new semiconductor material devices.

[0028] Next, first, the method provided by the embodiments of the present application will be described mainly with two-layer stacking as the main object: As shown in Figure 1 , the method flow can include the following steps: Step 110: Construct a three-dimensional heterogeneous PDK integration framework; the three-dimensional heterogeneous PDK integration framework includes at least three-dimensional process files, three-dimensional device models, three-dimensional physical verification rules, three-dimensional parasitic parameter extraction files and PCell units.

[0029] The above steps construct a three-dimensional heterogeneous PDK integration framework, which integrates a three-dimensional process file, a three-dimensional device model, a three-dimensional physical verification rule, a three-dimensional parasitic parameter extraction file, and a PCell unit; wherein the three-dimensional process file can define a three-dimensional structure manufacturing process, the three-dimensional device model can describe the three-dimensional structure and electrical characteristics of the device, the three-dimensional physical verification rule can be used to verify whether the design process conforms to the relevant rules, the three-dimensional parasitic parameter extraction file can be used to extract three-dimensional structure parasitic parameters, and the PCell unit can be a parameterized device unit for quickly generating different configuration devices.

[0030] Further, this step can achieve compatibility of layer definition under different process nodes by reconstructing the process file and unifying the layer naming rules, and ensure the accuracy of device electrical characteristics in a heterogeneous integration environment by applying a temperature gradient compensation to the device SPICE model to adapt to the temperature difference existing in the three-dimensional stacked structure.

[0031] It should be noted that the three-dimensional heterogeneous PDK integration framework supports the integration of GAA and FinFET heterogeneous processes, and at least includes reconstructing the process file, unifying the layer naming rules, and achieving compatibility of layer definition under different process nodes.

[0032] Step 120: Based on the three-dimensional heterogeneous PDK integration framework, a dynamically configurable cross-layer physical verification mechanism is set, and a global control variable is introduced.

[0033] The cross-layer physical verification mechanism realizes flexible switching between single-layer verification mode and multi-layer (or cross-layer) verification mode through the global control variable, so as to cope with the complex interlayer relationship in three-dimensional design, improve the verification efficiency, and ensure that the design conforms to the manufacturing specification under different verification scenarios.

[0034] Specifically, a global control variable MULTI_TIER can be introduced in the physical verification rule, and the flexible switching between DRC and LVS verification rules in single-layer mode and cross-layer mode can be realized by changing the value of the global control variable. For example, when MULTI_TIER is set to a specific value 3, the system loads the verification rules of the GAA layer and the FinFET layer in parallel, activates the cross-verification rules (interlayer alignment rules, three-dimensional density rules, three-dimensional antenna effect, etc.), and generates a comprehensive verification report, which significantly improves the verification efficiency and comprehensiveness.

[0035] Step 130: Based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for the key interconnection structure in three-dimensional integration.

[0036] Step 130 mainly illustrates the accurate modeling of MIV parasitic parameters based on an analytical method, specifically, for the key interconnection structure MIV in three-dimensional integration, the traditional fixed RC value assumption is abandoned, and according to the actual cylindrical geometric structure and material physical properties, the closed-form analytical formula is used to calculate the parasitic resistance, inductance, conductance and capacitance. The model further introduces the skin effect to dynamically reflect the change of resistance with frequency, and builds a lumped model.

[0037] Step 140: integrate the lumped model into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework.

[0038] The integration of the lumped model into the three-dimensional parasitic parameter extraction rule file enables the three-dimensional heterogeneous PDK constructed to solve the problems of poor compatibility, inflexible physical verification mechanism and inaccurate MIV parasitic parameter modeling in the prior art three-dimensional PDK when designing across process nodes, thereby significantly improving the accuracy of circuit post-simulation.

[0039] Figure 1 The method in the method, by constructing a three-dimensional heterogeneous PDK integration framework; on the basis of the three-dimensional heterogeneous PDK integration framework, a dynamically configurable cross-layer physical verification mechanism is set, and a global control variable is introduced; based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for the key interconnection structure in three-dimensional integration; and the lumped model is integrated into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework. Effectively solve the three core problems of compatibility, verification flexibility and model accuracy in GAA and FinFET heterogeneous process collaborative design; wherein the dynamically configurable cross-layer physical verification mechanism is set, and the global control variable is introduced to realize seamless switching between single-layer and multi-layer modes, which significantly improves the verification comprehensiveness and reduces the design risk; based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for the key interconnection structure in three-dimensional integration, which greatly improves the reliability of circuit post-simulation; at the same time, the present application has good expansibility, and provides strong technical support for future more layer stacking and emerging semiconductor process high-density integration. Support collaborative design across process nodes, and have the expansion ability of heterogeneous integration of carbon nanotube, two-dimensional material and silicon semiconductor materials, which helps to promote the industrialization application of high-density integrated circuits.

[0040] Again, the above method is not only suitable for the heterogeneous integration of GAA and FinFET, but also has good expansibility in architecture and process design, which can support more layers of device layer stacking, and can adapt to emerging semiconductor processes such as carbon nanotube transistors and two-dimensional material devices, providing a technical basis for future high-density, heterogeneous integrated circuit design.

[0041] Based onFigure 1 The method is provided by the embodiments of the present disclosure, and some specific implementations of the method are also provided, which are described below.

[0042] As one of the embodiments, in step 110, the three-dimensional heterogeneous PDK integration framework is constructed, which at least includes: obtaining a basic PDK component; the basic PDK component at least includes a GAA device PDK based on a normal-temperature manufacturing process and a FinFET device PDK based on a low-thermal-budget manufacturing process.

[0043] fusing and reconstructing process files corresponding to the GAA device PDK and the FinFET device PDK to obtain a three-dimensional process file.

[0044] based on the GAA device PDK and the FinFET device PDK, performing temperature compensation on a device model to obtain a three-dimensional device model; setting a three-dimensional parasitic parameter extraction rule.

[0045] based on the three-dimensional process file and the three-dimensional device model, reconstructing a PCell unit.

[0046] The above steps can be further refined in combination with Figure 2 The above steps can be further refined in combination with Step 201: obtaining or determining a GAA device PDK based on a normal-temperature manufacturing process and a FinFET device PDK based on a low-thermal-budget manufacturing process.

[0047] This step is a step of providing a basic PDK component. Specifically, a GAA device PDK based on a normal-temperature manufacturing process and a FinFET device PDK based on a low-thermal-budget manufacturing process, referred to as “GAA device PDK” and “FinFET device PDK” for short, can be obtained or determined respectively. These two independent two-dimensional PDKs will serve as the input basis of the three-dimensional integration framework, which should include complete process files, device SPICE models, DRC / LVS physical verification rules, three-dimensional parasitic parameter extraction files, and PCell units.

[0048] Step 202: 3D heterogeneous process file fusion: merging the process files of GAA and FinFET; defining MIV layers; adopting a unified layer naming rule to ensure cross-layer compatibility.

[0049] This step is to construct a three-dimensional process file, specifically, the process files of the GAA device PDK and the FinFET device PDK can be fused and reconstructed to eliminate layer definition conflicts and ensure cross-layer consistency. In specific implementation, the layers of the bottom GAA device PDK are assigned unique layer numbers and appended with a suffix “_B”, and the layers of the top FinFET device PDK are assigned unique layer numbers and appended with a suffix “_T”. In addition, a dedicated process layer needs to be defined for identifying and drawing the monolithic interlayer via MIV, which will serve as a key basis for interlayer electrical connection and physical verification. This unified naming and definition method is the basis for subsequent cross-layer data processing and verification.

[0050] Step 203: 3D device Spice model determination: merging the device Spice models of each layer and ensuring uniqueness; applying a temperature compensation function to output a compensated device model adapted to the temperature gradient of the heterogeneous process.

[0051] Step 203 is a step for determining a three-dimensional device model. Specifically, for the interlayer temperature gradient caused by the three-dimensional stacked structure, the device model is temperature compensated to ensure the accuracy of the electrical characteristics. Specifically, the specific temperature parameters of the bottom GAA device PDK and the top FinFET device PDK are input and applied to the corresponding compact device model. By calling the device model temperature compensation function, a compensated device model adapted to the temperature distribution of the heterogeneous process is output, which will be used for subsequent circuit simulation.

[0052] Step 204: 3D heterogeneous process DRC / LVS multi-layer collaborative verification mechanism: merging and reconstructing the physical verification files of the two layers; setting the MULTI_TIER variable to select single / multi-layer verification.

[0053] Step 204 is a step for determining a three-dimensional physical verification rule. Specifically, interlayer alignment rules can be added in the DRC rule file, and dynamic switching of the verification mode is realized through a global control variable MULTI_TIER. In the LVS rule, the device recognition logic is reconstructed based on the layer number, supporting independent or joint extraction of the bottom FinFET device PDK and the top GAA device PDK. When MULTI_TIER is set to a specific value 3, the system loads the two-layer verification rules such as interlayer alignment, three-dimensional density, and antenna effect checking in parallel and performs cross-verification to generate a comprehensive verification report.

[0054] Step 205: 3D parasitic parameter extraction file determination: MIV accurate modeling, integrated into the 3D parasitic parameter extraction file.

[0055] Step 205 is a step of determining a three-dimensional parasitic parameter extraction rule, specifically, integrating the MIV parasitic parameter model based on the analytical method into the parasitic parameter extraction rule file. The model considers the (diameter, height) and material physical properties (resistivity, dielectric constant) of MIV, uses a closed-form analytical formula to calculate the resistance, capacitance, inductance and conductance parameters, and supports frequency-dependent skin effect.

[0056] Step 206: 3D device PCell reconstruction: based on the merged 3D process file, combined with the 3D device model, modify the CDF parameters and netlist, add new MIV quantity variables, and recompile the PCell unit of the room temperature layer-low thermal budget layer.

[0057] This step is a step of determining a three-dimensional PCell unit. Based on the three-dimensional process file generated in step 202 and the compensated device model obtained in step 203, the PCell unit is reconstructed. Specifically, it includes updating the parameter list in the CDF, adding three-dimensional related variables such as "MIV quantity", modifying the netlist generation module of PCell, so that it can call the bottom GAA device, the top FinFET device and the specified number of MIV, and finally recompile the PCell library to generate a parameterized unit supporting three-dimensional heterogeneous circuit design.

[0058] Step 207: 3D PDK release.

[0059] Specifically, all components generated by the foregoing steps, including three-dimensional process files, three-dimensional device model libraries, three-dimensional physical verification rules, three-dimensional parasitic parameter extraction rule files, and three-dimensional PCells, are integrated to form a complete three-dimensional PDK, which is provided to integrated circuit designers for use.

[0060] As an optional embodiment, a dynamically configurable cross-layer physical verification mechanism is set based on the three-dimensional heterogeneous PDK integration framework, and a global control variable is introduced, which can include: A global control variable is set in the verification rule, and the single-layer mode and multi-layer mode are configured to switch in the DRC rule and the LVS rule, and the cross-verification rule is integrated; the cross-verification rule at least includes interlayer alignment rule, three-dimensional density and three-dimensional antenna effect rule; The global control variable is set in the verification rule, and the single-layer mode and multi-layer mode are configured to switch in the DRC rule and the LVS rule, and the cross-verification rule is integrated, which includes: An interlayer alignment rule is added in the DRC rule file, and the global control variable is used for dynamic switching of the physical verification file; In the LVS rule, the device identification logic is reconstructed based on the layer number, supporting independent or joint extraction of the FinFET device PDK at the bottom layer and the GAA device PDK at the top layer; When the global control variable is a preset specific value, the system executes the cross-validation rules in parallel to generate a comprehensive validation report.

[0061] Furthermore, the step of setting global control variables in the verification rules, enabling configurable switching between single-layer and multi-layer modes in DRC and LVS rules, and integrating cross-validation rules may include: Input the process temperature change, material thermal expansion coefficient, and initial length corresponding to the GAA device PDK and the FinFET device PDK; The dimensional changes caused by temperature variations are calculated based on the expansion formula, and the DRC interlayer alignment rules are adjusted according to the dimensional changes. The DRC rule files corresponding to the GAA device PDK and the FinFET device PDK are then merged. Merge and modify the LVS rule files corresponding to the GAA device PDK and the FinFET device PDK; ensure that the layer names and layer numbers are compatible and consistent, and that the layer numbers correspond to transistor devices located on different layers. In the standard verification rule format, the verification mode is switched according to the value of the global control variable by using preset conditional compilation instructions. The verification mode includes single-layer mode and multi-layer mode. The single-layer mode includes verifying only the GAA layer and verifying only the FinFET layer. The multi-layer mode means loading two layers of rules in parallel, activating cross-layer verification, and outputting a comprehensive verification report.

[0062] It should be noted that the above method uses an analytical approach based on physical formulas to extract MIV parasitic parameters, as it strikes a good balance between accuracy and computational efficiency. However, its modeling concept can also be implemented through other numerical or algorithmic methods, including but not limited to the finite element method, convolutional neural networks, or multi-scale order reduction models.

[0063] The steps corresponding to the above-mentioned three-dimensional heterogeneous process DRC / LVS multilayer verification method can be combined with Figure 3 Explanation: like Figure 3 As shown, the steps corresponding to the three-dimensional heterogeneous process DRC / LVS multilayer verification method may include: Step 301: Input data: Input the process temperature change ΔT of the GAA layer and FinFET layer, the material thermal expansion coefficient α, and the initial length L0.

[0064] Step 302: Calculate the length change based on the linear thermal expansion formula and adjust the DRC interlayer alignment rules.

[0065] Step 302 belongs to the step of enhancing DRC rules, specifically, the expansion formula can be used, such as formula (1): ΔL =α·ΔT·L0 (1) Calculate the size change caused by temperature change, and adjust the DRC interlayer alignment rule (such as offset tolerance) according to the size change, merge the DRC rule files corresponding to the GAA device PDK and the FinFET device PDK; wherein ΔT represents the process temperature change corresponding to the GAA device PDK and the FinFET device PDK, α represents the thermal expansion coefficient of the material, L0 represents the initial length, and the DRC rule files of GAA and FinFET are merged to ensure the uniqueness of the layer name and layer number.

[0066] Step 303: Modify the LVS rule file to enable the tool to independently identify the transistor located in different layers. This step belongs to the step of reconstructing the LVS rule, and the LVS rule files of GAA and FinFET can be merged and modified to ensure the compatibility of the layer name and layer number, so that the verification tool can independently identify the transistor devices located in different layers based on the layer number.

[0067] Step 304: Set the MULTI_TIER parameter (1 / 2 / 3). This step belongs to the step of implementing dynamic verification mode switching. In the standard verification rule format (SVRF), the verification mode is switched according to the value of MULTI_TIER through conditional compilation instructions (IFDEF-ENDIF): when MULTI_TIER=1, load the GAA definition, write the GAA verification rule, and generate the GAA verification report, that is, only verify the GAA layer; when MULTI_TIER=2, load the FinFET definition, write the FinFET verification rule, and generate the FinFET verification report, that is, only verify the FinFET layer; when MULTI_TIER=3, load the GAA and FinFET definitions, write the GAA and FinFET independent verification rules, write the cross-layer verification rules, and generate the comprehensive verification report, that is, load the two-layer rules in parallel, activate the cross-layer verification (including DRC interlayer alignment, three-dimensional density, three-dimensional antenna effect rules, and MIV identification and global netlist comparison in LVS), and output the comprehensive verification report.

[0068] Step 305: Complete the DRC / LVS physical verification rule.

[0069] As an optional embodiment, based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for the key interconnection structure in three-dimensional integration, which can include: According to the geometric size and material physical property of the key interconnection structure in the three-dimensional integration, an analytical formula is used to calculate electrical parameters of the key interconnection structure respectively; the electrical parameters at least include parasitic resistance, parasitic inductance, parasitic conductance and parasitic capacitance; The skin effect is introduced to dynamically reflect the change of resistance with frequency, and a lumped model is constructed.

[0070] As shown in Figure 4 The MIV accurate modeling step integrated into the parasitic parameter extraction file can include: Step 401: input the geometric size, material physical property and process parameter of the key interconnection structure.

[0071] Specifically, the geometric size (diameter, height) of MIV, the material physical property (resistivity of MIV filling material ρ, dielectric constant of silicon dioxide ε) and the process parameter (insulation layer thickness) can be input.

[0072] Step 402: MIV parasitic resistance: calculate DC resistance + skin effect correction. Specifically, according to the geometric size, material physical property and process parameter of the key interconnection structure, formula (2) is used: (2) Calculate DC resistance; wherein, ρ represents the resistivity of conductive material, L represents length, r MIV represents radius; And introduce the skin effect model to dynamically calculate the parasitic resistance, which is represented as formula (3): (3) Wherein, R MIV represents parasitic resistance, δ represents skin depth, K p represents the correction coefficient of skin effect.

[0073] Step 403: MIV parasitic capacitance: calculate according to insulation layer capacitance and depletion layer capacitance, specifically, formula (4) is used: (4) Calculate parasitic capacitance, wherein, C MIV represents parasitic capacitance, C ox represents insulation layer capacitance, C dep represents depletion layer capacitance.

[0074] Step 404: MIV parasitic inductance: based on current loop approximation model, specifically, based on current loop approximation model, formula (5) is used: (5) Calculate parasitic inductance; wherein, LMIV Indicates parasitic inductance; Step 405: MIV parasitic conductance: Calculated using a coaxial cable model, specifically, as shown in formula (6): (6) Calculate the parasitic conductance, where G MIV Indicates parasitic conductance, t ox h represents the thickness of the insulating layer. Si ρ represents the height of the silicon layer. SiO2 This indicates the resistivity of silicon dioxide, an insulating material.

[0075] Step 406: Integrate the MIV model into the 3D PEX file. Specifically, the RLGC parameters mentioned above are constructed into a lumped model and integrated into the 3D parasitic parameter extraction rule file to ensure that all interlayer parasitic effects are accurately captured.

[0076] As an optional embodiment, the step of obtaining a three-dimensional device model by performing temperature compensation on the device model based on the GAA device PDK and the FinFET device PDK may include: Input the specific temperature parameters of the GAA device PDK and the FinFET device PDK; The specific temperature parameters are applied to the corresponding device model, and the compensated three-dimensional device model that adapts to the temperature distribution of heterogeneous processes is output by calling the device model temperature compensation function.

[0077] As an optional embodiment, the process of reconstructing the PCell unit based on the three-dimensional process file and the three-dimensional device model may include: Update the parameter list in the component description format file and add three-dimensional related variables; the three-dimensional related variables include at least the number of the key interconnect structures. The netlist generation module of PCell is modified based on the newly added 3D related variables; the modified netlist generation module of PCell calls the underlying GAA device, the top FinFET device, and a specified number of key interconnect structures. Recompile the PCell library to generate PCell cells that support 3D heterogeneous circuit design.

[0078] The application provides the above technical scheme, and the GAA and FinFET heterogeneous process PDK construction method can comprise: fusing and reconstructing GAA and FinFET process files, unifying layer naming rules and device model temperature gradient compensation, and realizing cross-process node and temperature condition collaborative design compatibility; dynamic physical verification can be realized by setting a global control variable MULTI_TIER in the verification rule, realizing configurable switching of single-layer mode and multi-layer mode in the DRC / LVS verification rule, and integrating cross-verification rules such as interlayer alignment, three-dimensional density and three-dimensional antenna effect; MIV parasitic parameter modeling can calculate the parasitic RLGC parameters of MIV based on the geometric structure size and material physical properties of MIV, and construct a lumped model integrated into a three-dimensional parasitic parameter extraction file. By constructing a unified three-dimensional PDK integration framework, the three core problems of compatibility, verification flexibility and model accuracy in the collaborative design of GAA and FinFET heterogeneous processes are effectively solved: the unified process file and temperature compensation model ensure the accuracy and efficiency of cross-process node design; the configurable physical verification mechanism realizes seamless switching of single-layer and multi-layer modes, significantly improves verification comprehensiveness and reduces design risk; the MIV accurate parasitic model based on the analytical method greatly improves the reliability of circuit post-simulation; at the same time, the framework has good expansibility and provides strong technical support for high-density integration of more layer stacks and emerging semiconductor process technologies.

[0079] Moreover, the technical scheme provided by the application supports three-layer or more-layer device stacking, and the integration method has expansibility and can adapt to emerging semiconductor process technologies such as carbon nanotubes and two-dimensional materials.

[0080] Based on the same idea, the application also provides a GAA and FinFET heterogeneous process PDK construction device, as shown in Figure 5 The device can comprise: The three-dimensional heterogeneous PDK integration framework construction module 510 is configured to construct a three-dimensional heterogeneous PDK integration framework; the three-dimensional heterogeneous PDK integration framework comprises at least a three-dimensional process file, a three-dimensional device model, a three-dimensional physical verification rule, a three-dimensional parasitic parameter extraction file and a PCell unit; The cross-layer physical verification mechanism determination module 520 is configured to set a dynamically configurable cross-layer physical verification mechanism on the basis of the three-dimensional heterogeneous PDK integration framework, and introduce a global control variable; The lumped model construction module 530 is configured to construct a lumped model for key interconnection structures in three-dimensional integration based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism; The lumped model integration module 540 is configured to integrate the lumped model into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework.

[0081] based on Figure 5 The device in the method can further include some specific implementation units: Optionally, the three-dimensional heterogeneous PDK integration framework supports GAA and FinFET heterogeneous process integration, and at least includes the following: reconstructing process files, unifying layer naming rules, and realizing compatibility of layer definition under different process nodes; The three-dimensional heterogeneous PDK integration framework modeling module 510 can at least include: A basic PDK component acquisition unit is configured to acquire a basic PDK component; the basic PDK component at least includes a GAA device PDK based on a normal-temperature manufacturing process and a FinFET device PDK based on a low-thermal-budget manufacturing process; A three-dimensional process file construction unit is configured to fuse and reconstruct process files corresponding to the GAA device PDK and the FinFET device PDK, and construct a three-dimensional process file; A three-dimensional device model determination unit is configured to, based on the GAA device PDK and the FinFET device PDK, perform temperature compensation on a device model to obtain a three-dimensional device model, in view of an interlayer temperature gradient caused by a three-dimensional stacked structure; A three-dimensional parasitic parameter extraction rule setting unit is configured to set a three-dimensional parasitic parameter extraction rule; A PCell unit reconstruction unit is configured to reconstruct a PCell unit based on the three-dimensional process file and the three-dimensional device model.

[0082] Optionally, the cross-layer physical verification mechanism determination module 520 can include: A global control variable setting unit is configured to set a global control variable in a verification rule, perform configurable switching between single-layer mode and multi-layer mode in DRC rules and LVS rules, and integrate cross-verification rules; the cross-verification rules at least include interlayer alignment rules, three-dimensional density, and three-dimensional antenna effect rules; The global control variable setting unit can be specifically configured to: Add interlayer alignment rules in the DRC rule file, and perform dynamic switching of a physical verification file through a global control variable; In the LVS rules, reconstruct device identification logic based on layer numbers, and support independent or joint extraction of the FinFET device PDK at the bottom layer and the GAA device PDK at the top layer; When the global control variable is a preset specific value, the system executes the cross-verification rules in parallel, and generates a comprehensive verification report.

[0083] Optionally, the global control variable setting unit can be specifically configured to: Input the process temperature variation, material thermal expansion coefficient and initial length corresponding to the GAA device PDK and the FinFET device PDK; According to the expansion formula: ΔL =α·ΔT·L0 Calculate the size variation caused by temperature variation, and adjust the DRC interlayer alignment rule according to the size variation, and merge the DRC rule files corresponding to the GAA device PDK and the FinFET device PDK; wherein ΔT represents the process temperature variation corresponding to the GAA device PDK and the FinFET device PDK, α represents the material thermal expansion coefficient, and L0 represents the initial length; Merge and modify the LVS rule files corresponding to the GAA device PDK and the FinFET device PDK; the layer name and layer number are compatible and consistent, and the layer number corresponds to the transistor device located in different layers; In the standard verification rule format, the verification mode is switched according to the value of the global control variable through the preset condition compilation instruction; the verification mode includes a single-layer mode and a multi-layer mode; the single-layer mode includes only verifying the GAA layer and only verifying the FinFET layer; the multi-layer mode means loading two layers of rules in parallel, activating cross-layer verification, and outputting a comprehensive verification report.

[0084] Optionally, the lumped model construction module 530 can include: An electrical parameter calculation unit configured to calculate electrical parameters of the key interconnection structure in the three-dimensional integration according to geometric structure sizes and material physical properties of the key interconnection structure, and using analytical formulas; the electrical parameters at least include parasitic resistance, parasitic inductance, parasitic conductance and parasitic capacitance; A lumped model construction unit configured to introduce a skin effect to dynamically reflect changes of resistance with frequency, and to construct a lumped model.

[0085] Optionally, the electrical parameter calculation unit can be specifically configured to: Input the geometric structure sizes, material physical properties and process parameters of the key interconnection structure; According to the geometric structure sizes, material physical properties and process parameters of the key interconnection structure, use the formula: Calculate the DC resistance; wherein ρ represents the resistivity of the conductive material, L represents the length, r MIV represents the radius; And introduce a skin effect model to dynamically calculate the parasitic resistance, which is represented as: Wherein, R MIVrepresents a parasitic resistance, δ represents a skin depth, K p represents a correction coefficient of the skin effect; The formula is: The parasitic capacitance is calculated, wherein, C MIV represents a parasitic capacitance, C ox represents an insulating layer capacitance, C dep represents a depletion layer capacitance; Based on the current loop approximation model: The parasitic inductance is calculated; wherein, L MIV represents a parasitic inductance; The coaxial cable model is adopted: The parasitic conductance is calculated, wherein, G MIV represents a parasitic conductance, t ox represents the thickness of the insulating layer, h Si represents the height of the silicon layer, ρ SiO2 represents the resistivity of the insulating material silicon dioxide.

[0086] Optionally, a three-dimensional device model determination unit, specifically for: Input the specific temperature parameters of the GAA device PDK and the FinFET device PDK; Apply the specific temperature parameters to the corresponding device model, and output the compensated three-dimensional device model adapted to the temperature distribution of the heterogeneous process by calling the device model temperature compensation function.

[0087] Optionally, a PCell unit reconstruction unit specifically for: Update the parameter list in the component description format file, and add three-dimensional related variables; the three-dimensional related variables at least include the number of key interconnection structures; Modify the netlist generation module of the PCell based on the added three-dimensional related variables; the modified netlist generation module of the PCell calls the bottom GAA device, the top FinFET device, and the specified number of key interconnection structures; Recompile the PCell library to generate a PCell unit supporting three-dimensional heterogeneous circuit design.

[0088] The technical scheme provided by the application comprises three-dimensional heterogeneous process file fusion, three-dimensional device model compatibility processing, multi-layer DRC and LVS verification mechanism cooperation, MIV fast and accurate modeling based on an analytic method, and three-dimensional PCell reconstruction. The application supports cross-process node collaborative design, has extension capability of heterogeneous integration to semiconductor materials such as carbon nanotubes, two-dimensional materials and silicon, and helps to promote the industrial application of high-density integrated circuits.

[0089] Based on the same idea, the present specification also provides a GAA and FinFET heterogeneous process PDK construction device. As shown in the figure, Figure 6 The device comprises: a memory, a processor and a communication interface coupled with the processor; the memory stores a computer program executable by the processor; and the processor executes the computer program to perform the GAA and FinFET heterogeneous process PDK construction method.

[0090] As shown in the figure, Figure 6 The processor can be a general central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs of the present application. The communication interface can be one or more. The communication interface can use any transceiver device to communicate with other devices or communication networks.

[0091] As shown in the figure, Figure 6 The terminal device can further comprise a communication line. The communication line can comprise a channel for transmitting information between the components.

[0092] Optionally, as shown in the figure, Figure 6 The terminal device can further comprise a memory. The memory stores a computer program executable by the processor; and the processor executes the computer program to implement the method provided by the present application.

[0093] As shown in the figure, Figure 6As shown, the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to this. The memory can exist independently, and be connected to the processor through a communication line. The memory can also be integrated with the processor.

[0094] Optionally, the computer-executed instructions in the embodiments of the present application can also be referred to as application program codes, and the embodiments of the present application are not limited in this regard.

[0095] In a specific implementation, as an example, as shown in Figure 6 The processor can include one or more CPUs, such as CPU0 and CPU1 in Figure 6 .

[0096] In a specific implementation, as an example, as shown in Figure 6 The terminal device can include a plurality of processors, such as the processors in Figure 6 . Each of the processors can be a single-core processor or a multi-core processor.

[0097] The above mainly introduces the scheme provided by the embodiments of the present application from the perspective of the interaction between the modules. It can be understood that each module includes a hardware structure and / or a software unit for executing the corresponding functions in order to achieve the above functions. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the examples described in the embodiments disclosed in the present text, the present application can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0098] The embodiments of the present application can be divided into functional modules according to the above method examples, for example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be realized in the form of hardware or in the form of a software functional module. It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division, and another division mode can be used in actual implementation.

[0099] The processor in the specification can also have the function of a memory. The memory is used to store computer execution instructions for executing the scheme of the present application, and is controlled by the processor to execute. The processor is used to execute the computer execution instructions stored in the memory, so as to realize the method provided by the embodiments of the present application.

[0100] The memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, an optical disk storage (including a compact disk, a laser disk, an optical disk, a digital versatile disk, a Blu-ray disk, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a communication line. The memory can also be integrated with the processor.

[0101] Optionally, the computer execution instructions in the embodiments of the present application can also be referred to as application program codes, which are not limited in the embodiments of the present application.

[0102] The method disclosed by the embodiments of the present application can be applied to a processor or implemented by the processor. The processor can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the method can be completed by using an integrated logic circuit or an instruction in the form of software in the processor. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application can be implemented or executed by the processor. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware code executed by the processor, or a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or other mature storage media in the art. The memory is located in the storage device, and the processor reads information in the memory and combines the hardware to complete the steps of the above method.

[0103] Although the present application is described in conjunction with the specific embodiments, one skilled in the art will understand and appreciate that other changes and modifications can be made to the application without departing from the scope of the application. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0104] Although the present application is described in conjunction with the specific embodiments, one skilled in the art will understand and appreciate that other changes and modifications can be made to the application without departing from the scope of the application. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0104] Although the present application is described in conjunction with the specific embodiments, one skilled in the art will understand and appreciate that other changes and modifications can be made to the application without departing from the scope of the application. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method for constructing a GAA and FinFET heterogeneous process PDK, characterized in that, The method comprises: constructing a three-dimensional heterogeneous PDK integration framework; the three-dimensional heterogeneous PDK integration framework at least comprises three-dimensional process files, three-dimensional device models, three-dimensional physical verification rules, three-dimensional parasitic parameter extraction files and PCell units; on the basis of the three-dimensional heterogeneous PDK integration framework, setting a dynamically configurable cross-layer physical verification mechanism, and introducing global control variables; based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, for the key interconnection structure in three-dimensional integration, a lumped model is constructed; the lumped model is integrated into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework.

2. The method of claim 1, wherein, The three-dimensional heterogeneous PDK integration framework supports the fusion of GAA and FinFET heterogeneous processes, at least includes restructured process files and unified layer naming rules, and realizes the compatibility of layer definition under different process nodes; the three-dimensional heterogeneous PDK integration framework at least comprises: obtaining basic PDK components; the basic PDK components at least include GAA device PDK based on normal temperature manufacturing process and FinFET device PDK based on low heat budget manufacturing process; fusing and restructuring the process files corresponding to the GAA device PDK and the FinFET device PDK to obtain three-dimensional process files; based on the GAA device PDK and the FinFET device PDK, the device model is temperature compensated to obtain a three-dimensional device model for the interlayer temperature gradient caused by three-dimensional stacking structure; setting three-dimensional parasitic parameter extraction rules; based on the three-dimensional process files and the three-dimensional device model, the PCell unit is restructured.

3. The method of claim 2, wherein, on the basis of the three-dimensional heterogeneous PDK integration framework, setting a dynamically configurable cross-layer physical verification mechanism, and introducing global control variables, comprising: setting global control variables in the verification rules, performing configurable switching of single-layer mode and multi-layer mode in DRC rules and LVS rules, and integrating cross-verification rules; the cross-verification rules at least include interlayer alignment rules, three-dimensional density and three-dimensional antenna effect rules; setting global control variables in the verification rules, performing configurable switching of single-layer mode and multi-layer mode in DRC rules and LVS rules, and integrating cross-verification rules, comprising: adding interlayer alignment rules in the DRC rule file, and dynamically switching physical verification files through global control variables; in the LVS rule, based on the layer number reconstructor, the device identification logic is supported, and the FinFET device PDK of the bottom layer and the GAA device PDK of the top layer are independently or jointly extracted; when the global control variable is a preset specific value, the system executes the cross-verification rules in parallel, and generates a comprehensive verification report.

4. The method of claim 3, wherein, setting global control variables in the verification rules, performing configurable switching of single-layer mode and multi-layer mode in DRC rules and LVS rules, and integrating cross-verification rules, comprising: input the process temperature variation, material thermal expansion coefficient and initial length corresponding to the GAA device PDK and the FinFET device PDK; according to the expansion formula: AL = a * AT * L0 calculating a size change caused by a temperature change, and adjusting a DRC interlayer alignment rule according to the size change, merging DRC rule files corresponding to the GAA device PDK and the FinFET device PDK; wherein AT represents a process temperature change corresponding to the GAA device PDK and the FinFET device PDK, a represents a material thermal expansion coefficient, and L0 represents an initial length; merging and modifying LVS rule files corresponding to the GAA device PDK and the FinFET device PDK; layer names and layer numbers are compatible and consistent, and the layer numbers correspond to transistor devices located at different layers; in a standard verification rule format, switching verification modes according to values of the global control variables through preset condition compilation instructions; the verification modes include a single-layer mode and a multi-layer mode; the single-layer mode includes only verifying a GAA layer and only verifying a FinFET layer; and the multi-layer mode represents loading two-layer rules in parallel, activating cross-layer verification, and outputting a comprehensive verification report.

5. The method of claim 3, wherein, Based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism, a lumped model is constructed for a key interconnection structure in three-dimensional integration, including: According to the geometric structure size and material physical properties of the key interconnection structure in the three-dimensional integration, the electrical parameters of the key interconnection structure are calculated respectively by using analytical formulas; the electrical parameters at least include parasitic resistance, parasitic inductance, parasitic conductance and parasitic capacitance; The skin effect is introduced to dynamically reflect the change of resistance with frequency, and a lumped model is constructed.

6. The method of claim 5, wherein, According to the geometric structure size and material physical properties of the key interconnection structure in the three-dimensional integration, the electrical parameters of the key interconnection structure are calculated respectively by using analytical formulas, including: Input the geometric structure size, material physical properties and process parameters of the key interconnection structure; According to the geometric structure size, material physical properties and process parameters of the key interconnection structure, the formula is used: The DC resistance is calculated; wherein p represents the resistivity of the conductive material, L represents the length, r MIV represents the radius; And the skin effect model is introduced to dynamically calculate the parasitic resistance, which is represented as: wherein R MIV represents a parasitic resistance, δ represents a skin depth, K p represents a correction factor for the skin effect; The formula is used: Calculate the parasitic capacitance, where C MIV represents the parasitic capacitance, C ox represents the insulating layer capacitance, C dep represents the depletion layer capacitance; Based on the current loop approximation model: calculating parasitic inductance; wherein, L MIV represents parasitic inductance; The coaxial cable model is used: The parasitic conductance is calculated, where G MIV represents the parasitic conductance, t ox represents the thickness of the insulating layer, h Si represents the height of the silicon layer, p SiO2 represents the resistivity of the insulating material, silicon dioxide.

7. The method of claim 2, wherein, For the interlayer temperature gradient caused by the three-dimensional stacked structure, based on the GAA device PDK and the FinFET device PDK, a three-dimensional device model is obtained by temperature compensation of the device model, including: Input the specific temperature parameters of the GAA device PDK and the FinFET device PDK; Apply the specific temperature parameters to the corresponding device model, and output the compensated three-dimensional device model adapted to the heterogeneous process temperature distribution by calling the device model temperature compensation function.

8. The method of claim 2, wherein, Based on the three-dimensional process file and the three-dimensional device model, a PCell unit is reconstructed, including: Updating the parameter list in the component description format file, and adding three-dimensional related variables; the three-dimensional related variables at least include the number of key interconnection structures; a netlist generation module of a PCell is modified based on the newly added three-dimensional related variables; the modified netlist generation module of the PCell calls the underlying GAA device, the top FinFET device and a specified number of key interconnection structures; a PCell library is recompiled to generate PCell units supporting three-dimensional heterogeneous circuit design.

9. A GAA and FinFET heterogeneous process PDK construction apparatus, comprising: The device is applied to the GAA and FinFET heterogeneous process PDK construction method in any one of claims 1-8, and the device comprises: a three-dimensional heterogeneous PDK integration framework construction module configured to construct a three-dimensional heterogeneous PDK integration framework; the three-dimensional heterogeneous PDK integration framework at least includes a three-dimensional process file, a three-dimensional device model, a three-dimensional physical verification rule, a three-dimensional parasitic parameter extraction file and a PCell unit; a cross-layer physical verification mechanism determination module configured to set a dynamically configurable cross-layer physical verification mechanism on the basis of the three-dimensional heterogeneous PDK integration framework, and introduce a global control variable; a lumped model construction module configured to construct a lumped model for key interconnection structures in three-dimensional integration based on the three-dimensional heterogeneous PDK integration framework and the cross-layer physical verification mechanism; a lumped model integration module configured to integrate the lumped model into the three-dimensional parasitic parameter extraction file in the three-dimensional heterogeneous PDK integration framework.

10. A PDK fabrication device for GAA and FinFET heterogeneous processes, characterized in that the device... comprise: a memory, a processor and a communication interface coupled to the processor; the memory has a computer program stored thereon, which can be run by the processor; the processor runs the computer program, and executes the GAA and FinFET heterogeneous process PDK construction method in any one of claims 1-8.

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