Verification method and system thereof, equipment, storage medium and computer program product

Abstract

A verification method and system, device, storage medium and computer program product, the verification method comprising: at least obtaining a layout in any one of a first state and a second state, the layout comprising a device pattern, the device pattern comprising a port having a preset connection relationship, in the layout of the first state, the device pattern comprising a port having a preset connection relationship; in the layout in the first state, the preset connection relation is that the ports are disconnected mutually, and in the layout in the second state, the preset connection relation is that the ports are short-circuited mutually through preset connection layer graphs; design rule checking is conducted on the connection relation between the ports in the layout of any state through a design rule checking file, a checking result is obtained, and connection rules of the ports and the preset connection layer graph are defined in the design rule checking file; and verifying the design rule check file according to the check result. According to the invention, the verification efficiency and verification quality of the design rule check file are improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a verification method and system, device, storage medium and computer program product. BACKGROUND

[0002] In the field of integrated circuits, it is often necessary to perform design rule checking (DRC) on a layout, through which portions of the layout that do not meet the requirements of the manufacturing process (e.g., minimum line width, minimum spacing, etc.) can be found, thereby enabling potential manufacturing problems to be avoided.

[0003] Currently, after each process platform completes development of a design rule checking file, rigorous verification work needs to be performed, and the duration of the verification work is usually measured in weeks. Verification of each portion of the design rule checking file is performed independently, and checking of the connectivity relationship of the front end of line (FEOL) portion is a very important part. In order to ensure that each device is relatively independent and can form a network (Net) through a plug (CT) and a metal (Metal) layer without undesired open and short circuit conditions, verification of this portion is particularly important.

[0004] However, the efficiency and quality of verification of the design rule checking file still need to be improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a verification method and system, device, storage medium and computer program product, which improve the efficiency and quality of verification of the design rule checking file.

[0006] To solve the above problem, an embodiment of the present application provides a verification method for a design rule checking file, comprising: obtaining at least a layout in any one of a first state and a second state, the layout comprising a device pattern, the device pattern comprising ports having a preset connectivity relationship, in the layout in the first state, the preset connectivity relationship is that the ports are mutually open, and in the layout in the second state, the preset connectivity relationship is that the ports are mutually short-circuited through a preset connection layer pattern; performing design rule checking on the connectivity relationship between the ports in the layout in any one state by a design rule checking file, obtaining a checking result about the connectivity relationship, the design rule checking file defining a connection rule of the ports and the preset connection layer pattern; verifying the design rule checking file according to the checking result, and determining that the definition of the connection rule of the ports and the preset connection layer pattern in the design rule checking file is incorrect when the checking result does not match the preset connectivity relationship of the corresponding state.

[0007] Correspondingly, the embodiment of the present application also provides a verification system of a design rule checking file, comprising: a graphic acquisition module, configured to acquire at least a layout in any one of a first state and a second state, wherein the layout comprises a device graphic, and the device graphic comprises ports having a preset connectivity relationship; in the layout in the first state, the preset connectivity relationship is that the ports are disconnected from each other; in the layout in the second state, the preset connectivity relationship is that the ports are short-circuited from each other through a preset connection layer graphic; an inspection module, configured to perform design rule checking on a connectivity relationship between the ports in the layout in any one of the states by using a design rule checking file, to obtain an inspection result about the connectivity relationship, wherein the design rule checking file defines a connection rule of the ports and the preset connection layer graphic; and a verification module, configured to verify the design rule checking file according to the inspection result, and determine that the definition of the connection rule of the ports and the preset connection layer graphic in the design rule checking file is incorrect when the inspection result does not match the preset connectivity relationship of the corresponding state.

[0008] Correspondingly, the embodiment of the present application also provides a device, comprising at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the verification method of the design rule checking file provided by any one of the embodiments of the present application.

[0009] Correspondingly, the embodiment of the present application also provides a storage medium, wherein the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the verification method of the design rule checking file provided by any one of the embodiments of the present application.

[0010] Correspondingly, the embodiment of the present application also provides a computer program product, comprising computer instructions, and the computer instructions are executed by a processor to implement the verification method of the design rule checking file provided by any one of the embodiments of the present application.

[0011] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0012] The method for verifying a design rule checking file provided by the embodiment of the present application comprises: obtaining a layout in any one of a first state and a second state, the layout comprising device graphics, the device graphics comprising ports having a preset connectivity relationship, in the layout in the first state, the preset connectivity relationship being that the ports are mutually disconnected, in the layout in the second state, the preset connectivity relationship being that the ports are mutually short-circuited through a preset connection layer graphic, performing design rule checking on the connectivity relationship between the ports in the layout in any one of the states through a design rule checking file, obtaining a checking result about the connectivity relationship, defining the connection rule of the ports and the preset connection layer graphic in the design rule checking file, and verifying the design rule checking file according to the checking result; wherein the connectivity relationship between the ports in any one of the first state and the second state is known in advance, the checking result about the connectivity relationship is obtained by performing the design rule checking, and thus whether the definition of the connection rule in the design rule checking file is correct can be verified by judging whether the checking result meets the expectation, meanwhile, the preset connectivity relationship is that all the ports are mutually disconnected or mutually short-circuited, and the preset connectivity relationship corresponding to the layout in each state is single, which facilitates fast and accurate verification of the design rule checking file, and thus the verification efficiency and verification quality of the design rule checking file are improved.

[0013] The system for verifying a design rule checking file provided by the embodiment of the present application comprises: a graphic obtaining module, which obtains a layout in any one of a first state and a second state, the layout comprising device graphics, the device graphics comprising ports having a preset connectivity relationship, in the layout in the first state, the preset connectivity relationship being that the ports are mutually disconnected, in the layout in the second state, the preset connectivity relationship being that the ports are mutually short-circuited through a preset connection layer graphic; an checking module, which performs design rule checking on the connectivity relationship between the ports in the layout in any one of the states through a design rule checking file, obtains a checking result about the connectivity relationship, and defines the connection rule of the ports and the preset connection layer graphic in the design rule checking file; and a verifying module, which verifies the design rule checking file according to the checking result; wherein the connectivity relationship between the ports in any one of the first state and the second state is known in advance, the checking result about the connectivity relationship is obtained by performing the design rule checking, and thus whether the definition of the connection rule in the design rule checking file is correct can be verified by judging whether the checking result meets the expectation, meanwhile, the preset connectivity relationship is that all the ports are mutually disconnected or mutually short-circuited, and the preset connectivity relationship corresponding to the layout in each state is single, which facilitates fast and accurate verification of the design rule checking file, and thus the verification efficiency and verification quality of the design rule checking file are improved. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a flowchart of a verification method of a design rule check file according to an embodiment of the present application;

[0015] Figure 2 is Figure 1 is a flowchart of steps S1, S2 and S3 in the method according to an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of a verification system of a design rule check file according to an embodiment of the present application;

[0017] Figure 4 is a hardware structure diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] As known from the background art, the check of the connectivity relationship of the preceding section is very important, but as for the connectivity relationship of the preceding section, the verification efficiency and verification quality of the design rule check file still need to be improved.

[0019] As for the verification of the connectivity relationship of the preceding section, currently, the verification is mainly performed in a manual checking manner. However, with the increase of the number of devices, the workload of the manual checking increases accordingly, which wastes a lot of manpower and time cost. Moreover, too much manual intervention also increases the risk of errors.

[0020] To solve the technical problem, an embodiment of the present application provides a verification method of a design rule check file. Figure 1 , a flowchart of a verification method of a design rule check file according to an embodiment of the present application is shown. The verification method of the design rule check file according to an embodiment of the present application includes the following basic steps:

[0021] Step S1: at least a layout in any one of a first state and a second state is acquired, the layout includes a device pattern, the device pattern includes ports having a preset connectivity relationship, in the layout in the first state, the preset connectivity relationship is that the ports are disconnected from each other, in the layout in the second state, the preset connectivity relationship is that the ports are short-circuited from each other through a preset connection layer pattern;

[0022] Step S2: a design rule check file is used to perform a design rule check on the connectivity relationship between the ports in the layout in the any one state, an inspection result about the connectivity relationship is obtained, the design rule check file defines a connection rule of the ports and the preset connection layer pattern;

[0023] Step S3: verifying the design rule checking file according to the checking result, and determining that the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is incorrect when the checking result does not conform to the preset connection relationship of the corresponding state.

[0024] The verification method of the embodiment of the present application can realize the verification of the connection relationship of the preceding stage device in the design rule checking file. For the layout in any one of the first state and the second state, the connection relationship between the ports is known in advance, and the checking result of the connection relationship is obtained by performing the design rule checking. Therefore, whether the definition of the connection rule in the design rule checking file is correct can be verified by judging whether the checking result conforms to the expectation. Meanwhile, the preset connection relationship is that all the ports are disconnected or all the ports are short-circuited. The preset connection relationship corresponding to the layout of each state is single, which facilitates the fast and accurate verification of the design rule checking file, thereby improving the verification efficiency and verification quality of the design rule checking file.

[0025] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0026] Reference is made to Figure 1 and Figure 2 , Figure 1 is a flowchart of an embodiment of the verification method of the design rule checking file, Figure 2 is Figure 1 the flowchart of an embodiment of each step in steps S1, S2 and S3, step S1 is performed, and at least the layout in any one of the first state and the second state is obtained. The layout includes a device pattern, the device pattern includes ports having a preset connection relationship, in the layout of the first state, the preset connection relationship is that the ports are disconnected from each other, and in the layout of the second state, the preset connection relationship is that the ports are short-circuited through a preset connection layer pattern.

[0027] The verification method of the embodiment is used to verify whether the connection relationship of the preceding stage in the design rule checking is defined accurately. Therefore, the layout containing the device pattern is obtained, which prepares for the subsequent design rule checking.

[0028] It can be understood that the device pattern belongs to the preceding stage. In the embodiment, the ports of the device pattern include gate ports, source ports and drain ports.

[0029] In the layout in the first state, the preset connectivity relationship is that the ports are disconnected from each other, and in the layout in the second state, the preset connectivity relationship is that the ports are short-circuited from each other through the preset connection layer pattern. For the layout in any one of the first state and the second state, the connectivity relationship between the ports is known in advance. Therefore, at least one state of the layout is obtained, and after a design rule check is performed on the layout in any one state, if the actual check result does not match the preset connectivity relationship corresponding to the state, it is determined that the definition of the connection rule of the port and the preset connection layer pattern in the design rule check file is incorrect.

[0030] In this embodiment, the layout in the first state and the second state is obtained respectively, and subsequently, the connectivity relationship between the ports in the layouts in the two states is checked according to the design rule, so as to verify the design rule check file by combining the first check result obtained based on the layout in the first state and the second check result obtained based on the layout in the second state, thereby further improving the verification quality.

[0031] In the step of obtaining the layout in the first state, the layout in the first state does not contain the preset connection layer pattern.

[0032] Subsequently, the connectivity relationship between the ports is checked according to the design rule check file, and the design rule check file defines the connection rule of the port and the preset connection layer pattern, so that the layout in the first state does not contain the preset connection layer pattern, and the ports in the layout in the first state are disconnected from each other.

[0033] In the step of obtaining the layout in the first state, the port of the device pattern has a plug pattern.

[0034] The port of the device pattern has a plug pattern, which facilitates subsequent covering of all plug patterns by the preset connection layer pattern, so that the ports are short-circuited from each other through the preset connection layer pattern.

[0035] Specifically, as shown in FIG. 1, in the step (step S1) of obtaining at least one state of the layout in the first state and the second state, the step of obtaining the layout in the first state includes the following steps. Figure 2

[0036] ​After the cell pattern is called, the cell pattern usually includes interconnection patterns, and the ports can be connected through the interconnection patterns, so at least the preset connection layer pattern is deleted to disconnect the ports.

[0037] In particular, the step of deleting at least the preset connection layer pattern includes deleting at least the interconnection pattern, which facilitates ensuring that the ports are disconnected.

[0038] It should be noted that the interconnection pattern refers to a back-end (BEOL) pattern.

[0039] In other embodiments, for the purpose of disconnection, only the preset connection layer pattern in the interconnection pattern can be deleted, and other interconnection patterns except the preset connection layer pattern are retained, for example, other metal layer patterns and via patterns except the preset connection layer pattern are retained.

[0040] In this embodiment, the step of obtaining the original layout includes obtaining a plurality of parameterized cells (Pcells) to obtain a plurality of cell patterns, and placing the cell patterns in the same original layout.

[0041] The parameterized cell is mounted in the electronic design automation (EDA) software and is a core part of the PDK, and a programming language is usually used to automatically generate the cell pattern (for example, skill language programming is used).

[0042] Through the parameterized cell, a plurality of cell patterns can be placed in a layout file in batches, improving the efficiency of obtaining the original layout and correspondingly improving the efficiency of obtaining the first state layout.

[0043] As an example, the cell patterns can be placed in an array in a layout file in batches through a script.

[0044] In this embodiment, deleting the interconnection pattern includes deleting the first metal layer (M1) pattern and all metal layer patterns and via patterns above the first metal layer (M1) pattern.

[0045] In the step of deleting at least the preset connection layer pattern, the plug pattern is retained.

[0046] Retaining the plug pattern facilitates obtaining a second state layout based on the first state layout, reduces the complexity of obtaining the second state layout, and thus improves the verification efficiency.

[0047] As an example, the interconnection pattern can be deleted through a script.

[0048] As Figure 2 shown in the embodiment, in the step of acquiring the layout in the second state (step S1), the layout in the second state is acquired by performing step S13, after acquiring the layout in the first state, connecting all the ports in the layout in the first state by using the preset connection layer pattern, so as to short-circuit all the ports by the preset connection layer pattern.

[0049] Adding the preset connection layer pattern on the basis of the layout in the first state to obtain the layout in the second state reduces the complexity of acquiring the layout in the second state.

[0050] It should be noted that in other embodiments, in the step of deleting at least the interconnection pattern, the plug pattern can also be deleted to further ensure that the ports are disconnected from each other. Correspondingly, the step of acquiring the layout in the second state after acquiring the layout in the first state and before connecting all the ports in the layout in the first state by using the preset connection layer pattern further includes: restoring the deleted plug pattern so that the ports of the device pattern have the plug pattern.

[0051] In the embodiment, the preset connection layer pattern is a first metal layer pattern, so that the device can be divided into the two cases of being connected and being disconnected by physical connection, and the disconnection and the short-circuit can be realized by the first metal layer pattern, thereby reducing the complexity of verification.

[0052] In the embodiment, connecting all the ports in the layout in the first state by using the preset connection layer pattern includes: extracting the frame of all the device patterns in the layout in the first state; obtaining a maximum coverage area based on the extracted frame; and covering the preset connection layer pattern on the maximum coverage area.

[0053] The maximum coverage area is obtained by extracting the frame of all the layers of the device pattern in the layout in the first state, and the preset connection layer pattern covers the maximum coverage area, so as to ensure that the preset connection layer pattern can cover all the device patterns. Moreover, the preset connection layer pattern adopts the full coverage manner, which also reduces the complexity of connecting all the ports in the layout in the first state.

[0054] Specifically, the ports in the layout in the first state have the plug pattern, so that in the step of connecting all the ports in the layout in the first state by using the preset connection layer pattern, the preset connection layer pattern covers all the plug patterns.

[0055] The preset connection layer pattern covers the plug-in patterns, and the ports are connected through the plug-in patterns and the preset connection layer pattern above the plug-in patterns, and the preset connection layer pattern covers all the plug-in patterns, and all the ports are short-circuited through the preset connection layer pattern.

[0056] In the embodiment, the device patterns are arranged in an array in the layout, so that when the preset connection layer pattern is added to the layout in the first state, the preset connection layer pattern is easily made to cover all the ports, and the difficulty of obtaining the layout in the second state is reduced. Moreover, the device patterns are arranged in an array in the layout, and the regularity of the layout of the device patterns is improved, and the complexity of obtaining the layout is reduced.

[0057] With reference to Figure 1 and Figure 2 , a step S2 is performed, in which the connectivity relationship between the ports in the layout in any state is checked according to a design rule checking file, and a checking result about the connectivity relationship is obtained, and the design rule checking file defines the connection rule of the ports and the preset connection layer pattern.

[0058] The design rule checking file defines the connection rule of the ports and the preset connection layer pattern, and the ports in the device pattern have the preset connectivity relationship, so that whether the definition of the connection rule of the ports and the preset connection layer pattern in the design rule checking file is correct can be verified by subsequently judging whether the actual checking result is consistent with the preset connectivity relationship.

[0059] As an example, the design rule checking file is a design rule checking script.

[0060] As an example, in the step of checking the connectivity between the ports according to the design rule, the connection rule of the ports and the preset connection layer pattern includes that the ports are connected through plug-in patterns and the preset connection layer pattern.

[0061] In the embodiment, the connectivity relationship between the ports in the layout in any state is checked according to the design rule checking file, and a checking result about the connectivity relationship is obtained, including that a network statistics operation is performed to obtain the network identifier (Net ID) of all the ports in the layout in the corresponding state.

[0062] As an example, the network statistics instruction is run to perform network statistics to obtain the network identifier of all the ports.

[0063] The ports in short circuit belong to the same network, and thus the ports in short circuit theoretically have the same network identifier. The ports in open circuit do not belong to the same network, and thus the ports in open circuit theoretically have different network identifiers. The ports in the layout have a preset connectivity relationship. In the layout in the first state, the preset connectivity relationship is that the ports are in open circuit. In the layout in the second state, the preset connectivity relationship is that the ports are in short circuit through the preset connection layer pattern. Therefore, the network identifiers of all the ports in the layout in the corresponding state are obtained as the checking result and output, so as to facilitate judging whether the actual checking result is consistent with the preset connectivity relationship in the corresponding state, and reduce the complexity of the judging mode.

[0064] As an example, in the step of obtaining the network identifiers of all the ports in the layout in the corresponding state, a network identifier list (Net ID list) is obtained.

[0065] In this embodiment, after the layout in the first state is obtained, the connectivity relationship between the ports in the layout in the first state is checked by using the design rule checking file, and a first checking result about the connectivity relationship is obtained.

[0066] As shown in Figure 2 That is, the step (i.e., step S2) of checking the connectivity relationship between the ports in the layout in any state by using the design rule checking file includes: performing step S21, checking the connectivity relationship between the ports in the layout in the first state by using the design rule checking file, and obtaining a first checking result about the connectivity relationship.

[0067] Correspondingly, in this embodiment, the first checking result is the network identifiers of all the ports in the layout in the first state.

[0068] Since the preset connectivity relationship is that the ports are in open circuit in the layout in the first state, in the first checking result, theoretically, each port corresponds to one network identifier, and the network identifiers are different.

[0069] In this embodiment, the layout in the first state does not contain the preset connection layer pattern. Therefore, when the connectivity relationship between the ports is checked by using the design rule checking file, since the preset connection layer pattern cannot be recognized, each port has an independent network identifier.

[0070] For example, the first state of the layout includes four device patterns, and each device pattern includes three ports of a gate port, a source port and a drain port, and in the first checking result, there are twelve network identifiers, for example, the network identifiers of the twelve ports are Net1, Net2, Net3, …, Net11 and Net12.

[0071] In this embodiment, after obtaining the layout in the second state, the connectivity relationship between the ports in the layout in the second state is checked according to the design rule checking file to obtain a second checking result about the connectivity relationship.

[0072] As shown in Figure 2 That is, the step (i.e., step S2) of checking the connectivity relationship between the ports in the layout in any state according to the design rule checking file includes: performing step S22, checking the connectivity relationship between the ports in the layout in the second state according to the design rule checking file to obtain a second checking result about the connectivity relationship.

[0073] Correspondingly, in this embodiment, the second checking result is the network identifiers of all the ports in the layout in the second state.

[0074] Since in the layout in the second state, the preset connectivity relationship is that the ports are short-circuited to each other through the preset connection layer pattern, in the second checking result, theoretically, the network identifiers of all the ports are the same.

[0075] For example, the second state of the layout includes four device patterns, and each device pattern includes three ports of a gate port, a source port and a drain port, and in the second checking result, there is only one network identifier, for example, the network identifiers of the twelve ports are all Net1.

[0076] In this embodiment, after obtaining the first checking result about the connectivity relationship, the layout in the second state is obtained.

[0077] The preset connectivity relationship corresponding to the layout in the second state is that the ports are short-circuited to each other through the preset connection layer pattern, and therefore, after the layout in the first state is checked according to the design rule, the preset connection layer pattern is added to the layout in the first state, so that the layout in the second state is obtained, which is beneficial to reduce the complexity of obtaining layouts in different states.

[0078] It should be noted that in other embodiments, the layout in the first state can also be obtained after obtaining the second checking result of the connectivity relationship. For example, after obtaining the layout in the first state, all ports in the layout in the first state are connected by using the preset connection layer pattern to obtain a layout in a second state, and the connectivity relationship between the ports in the layout in the second state is checked according to the design rules to obtain a second checking result, and then the layout in the first state is reobtained, and the connectivity relationship between the ports in the layout in the first state is checked according to the design rules.

[0079] With reference to the foregoing Figure 1 and Figure 2 , step S3 is performed, and the design rule checking file is verified according to the checking result. When the checking result does not conform to the preset connectivity relationship of the corresponding state, it is determined that the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is incorrect.

[0080] For the layout in any one of the first state and the second state, the connectivity relationship between the ports is known in advance, and the checking result of the connectivity relationship is obtained by performing the design rule checking, so that whether the definition of the connection rule in the design rule checking file is correct can be verified by judging whether the actual checking result conforms to the expectation; meanwhile, the preset connectivity relationship corresponding to the layout in the first state is that the ports are disconnected from each other, and the preset connectivity relationship corresponding to the layout in the second state is that the ports are short-circuited from each other, and the preset connectivity relationship corresponding to the layout in any one state is single, which facilitates rapid and accurate verification of the design rule checking file, thereby improving the verification efficiency and verification quality of the design rule checking file. In addition, by the above-mentioned manner, whether the front connection relationship of the device is perfect and error-free can be intelligently verified, which can avoid the problem of increasing the risk of errors due to too much manual intervention, thereby improving the verification quality.

[0081] Taking the layout in the first state as an example, since the connection rule of the port and the preset connection layer pattern is defined in the design rule checking file, and in the layout in the first state, the preset connectivity relationship is that the ports are disconnected from each other, in other words, each port in the layout in the first state is not connected by using the same preset connection layer pattern. Assuming that the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is correct, then after performing the design rule checking on the connectivity relationship between the ports in the layout in the first state, in theory, the checking result represents that each port is disconnected from each other. Therefore, by judging whether the actual checking result corresponding to the layout in the first state conforms to the expectation, whether the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is correct can be determined.

[0082] Similarly, taking the layout in the second state as an example, in the layout of the second state, the preset connectivity relationship is that the ports are short-circuited to each other through a preset connection layer graphic. Assuming that the definition of the connection rules between the ports and the preset connection layer graphic in the design rule check file is correct, then theoretically, after performing a design rule check on the connectivity relationship between the ports in the layout of the second state, the check result indicates that each port is short-circuited to each other. Therefore, by judging whether the actual check result corresponding to the layout of the second state meets expectations, it is possible to determine whether the definition of the connection rules between the ports and the preset connection layer graphic in the design rule check file is correct.

[0083] like Figure 2 As shown, in this embodiment, the step of verifying the design rule check file based on the check results (i.e., step S3) includes: executing step S3', verifying the design rule check file based on the first check result and the second check result, and determining that the definition of the connection rule between the port and the preset connection layer graphic in the design rule check file is incorrect when either the first check result or the second check result does not match the preset connectivity relationship of the corresponding state.

[0084] Therefore, this embodiment places all device patterns in one layout and establishes the short-circuit and open-circuit relationships of devices through preset connection layer patterns. That is, it divides all device patterns into two cases, connected and disconnected, through physical connection, thereby analyzing the front-end connection relationship. Moreover, the design rule check document is verified by combining the first check result and the second check result. Not only are the verification results obtained under the case of device open circuit, but also the verification results under the case of device short circuit. By combining the two cases of device open circuit and device short circuit, the front-end connection relationship of the device is verified to be complete and error-free, further improving the verification quality.

[0085] Specifically, the step of verifying the design rule check file based on the check results includes: determining whether the check results match the preset connectivity relationship of the corresponding state based on the network identifier.

[0086] Ports that are short-circuited to each other theoretically have the same network identifier, while ports that are open-circuited to each other theoretically have different network identifiers. Therefore, the accuracy of the inspection results can be judged by the network identifier, and the judgment method is simple.

[0087] As an example, in the case of performing a design rule check on the connectivity relationship between ports in the first state layout, verifying the design rule check file according to the check result includes: judging whether the network identifiers in the first check result are all independent; when the network identifiers in the first check result are not all independent, determining that the definition of the connection rule of the ports and the preset connectivity layer graph in the design rule check file is incorrect.

[0088] The ports in the first state layout are disconnected with each other, so that each port theoretically has an independent network identifier, that is, the ports and the network identifiers are one-to-one corresponding, and the network identifiers are all different from each other; if the same network identifier exists in the first check result, it is indicated that the definition of the connection rule is incorrect.

[0089] As another example, in the case of performing a design rule check on the connectivity relationship between ports in the second state layout, verifying the design rule check file according to the check result includes: judging whether the network identifiers in the second check result are all the same; when the network identifiers in the second check result are not all the same, determining that the definition of the connection rule of the ports and the preset connectivity layer graph in the design rule check file is incorrect.

[0090] The ports in the second state layout are short-circuited with each other, so that all the ports are theoretically the same network identifier; if different network identifiers exist in the second check result, it is indicated that the definition of the connection rule is incorrect.

[0091] As an example, when it is determined that the definition of the connection rule is incorrect, the specific reason needs to be further analyzed and modified by referring to a design rule manual.

[0092] In the embodiment, when the check result is consistent with the preset connectivity relationship of the corresponding state, it is determined that the definition of the connection rule of the ports and the preset connectivity layer graph is correct.

[0093] Specifically, when the first check result and the second check result are both consistent with the preset connectivity relationship of the corresponding state, it is proved that the definition of the front-end connectivity relationship of the device is correct, and can be used for design rule check.

[0094] Correspondingly, the embodiment of the present application also provides a verification system of a design rule check file. Figure 3 , Figure 3 is a schematic diagram of a verification system of a design rule check file according to an embodiment of the present application.

[0095] In the embodiment, the verification system of the design rule checking file comprises: a graphic acquisition module 10 configured to acquire at least a layout in any one of a first state and a second state, the layout comprising device graphics, the device graphics comprising ports having a preset connectivity relationship, in the layout in the first state, the preset connectivity relationship is that the ports are disconnected from each other, and in the layout in the second state, the preset connectivity relationship is that the ports are short-circuited from each other through a preset connection layer graphic; a checking module 20 configured to perform design rule checking on the connectivity relationship between the ports in the layout in any one of the states by using a design rule checking file, to obtain a checking result about the connectivity relationship, the design rule checking file defining a connection rule of the ports and the preset connection layer graphic; and a verification module 30 configured to verify the design rule checking file according to the checking result, and determining that the definition of the connection rule of the ports and the preset connection layer graphic in the design rule checking file is incorrect when the checking result does not match the preset connectivity relationship corresponding to the state.

[0096] For the layout in any one of the first state and the second state, the connectivity relationship between the ports is known in advance, and the checking result about the connectivity relationship is obtained by performing the design rule checking, so that whether the definition of the connection rule in the design rule checking file is correct can be verified by judging whether the actual checking result matches the expected result; meanwhile, the preset connectivity relationship corresponding to the layout in the first state is that the ports are disconnected from each other, the preset connectivity relationship corresponding to the layout in the second state is that the ports are short-circuited from each other, and the preset connectivity relationship corresponding to the layout in any one of the states is single, which facilitates fast and accurate verification of the design rule checking file, thereby improving the verification efficiency and the verification quality of the design rule checking file. In addition, by the above method, whether the front connection relationship of the device is perfect and correct can be verified intelligently, and the problem of increasing the risk of errors due to too much manual intervention can be avoided, thereby improving the verification quality.

[0097] With the layout in the first state as an example, since the connection rule of the port and the preset connection layer pattern is defined in the design rule checking file, and in the layout in the first state, the preset connection relationship is that the ports are disconnected with each other, in other words, the ports in the layout in the first state are not connected through the same preset connection layer pattern, assuming that the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is correct, after the design rule checking is performed on the connection relationship between the ports in the layout in the first state, theoretically, the checking result represents that the ports are disconnected with each other. Therefore, by judging whether the actual checking result corresponding to the layout in the first state is consistent with the expectation, whether the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is correct can be determined.

[0098] Similarly, with the layout in the second state as an example, in the layout in the second state, the preset connection relationship is that the ports are short-circuited with each other through the preset connection layer pattern, assuming that the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is correct, after the design rule checking is performed on the connection relationship between the ports in the layout in the second state, theoretically, the checking result represents that the ports are short-circuited with each other. Therefore, by judging whether the actual checking result corresponding to the layout in the second state is consistent with the expectation, whether the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is correct can be determined.

[0099] The verification system of the embodiment is used for verifying whether the connection relationship in the front stage is defined accurately in the design rule checking, therefore, the layout containing the device pattern is acquired by the pattern acquisition module 10, so as to prepare for the subsequent design rule checking.

[0100] In the embodiment, the port of the device pattern includes a gate port, a source port and a drain port.

[0101] In the layout in the first state, the preset connection relationship is that the ports are disconnected with each other, and in the layout in the second state, the preset connection relationship is that the ports are short-circuited with each other through the preset connection layer pattern. For the layout in any one of the first state and the second state, the connection relationship between the ports is known in advance, therefore, at least the layout in one state is acquired, after the design rule checking is performed on the layout in any one state, if the actual checking result is inconsistent with the preset connection relationship corresponding to the state, it can be determined that the definition of the connection rule of the port and the preset connection layer pattern in the design rule checking file is incorrect.

[0102] In the embodiment, the pattern acquisition module 10 acquires the layout in the first state and the layout in the second state respectively, and then performs design rule check on the connectivity between the ports in the layouts in the two states respectively, so as to verify the design rule check file by combining the first check result obtained based on the layout in the first state and the second check result obtained based on the layout in the second state, thereby further improving the verification quality.

[0103] In the embodiment, the layout in the first state does not contain the preset connection layer pattern.

[0104] The design rule check file is used to perform design rule check on the connectivity between the ports, and the design rule check file defines the connection rule of the port and the preset connection layer pattern, the layout in the first state does not contain the preset connection layer pattern, and the ports in the layout in the first state are ensured to be disconnected with each other.

[0105] In the embodiment, the port of the device pattern has the plug pattern in the layout in the first state.

[0106] The port of the device pattern has the plug pattern, which facilitates subsequent covering of all plug patterns by the preset connection layer pattern, so that the ports are short-circuited with each other through the preset connection layer pattern.

[0107] In the embodiment, the pattern acquisition module 10 includes a first pattern acquisition module (not shown in the figure) configured to acquire the layout in the first state.

[0108] Specifically, the first pattern acquisition module includes an original layout acquisition unit (not shown in the figure) configured to acquire an original layout, the original layout including a plurality of unit patterns, each unit pattern including a device pattern, a plug pattern on a port of the device pattern, and an interconnection pattern on the plug pattern, the interconnection pattern including the preset connection layer pattern; and a first pattern processing unit configured to delete at least the preset connection layer pattern, and the remaining unit pattern as a device pattern.

[0109] After the unit pattern is called, the unit pattern usually includes the interconnection pattern, and the ports can be connected through the interconnection pattern, so that at least the preset connection layer pattern is deleted to ensure that the ports are disconnected with each other.

[0110] Specifically, the first pattern processing unit deletes at least the interconnection pattern, which is beneficial to ensure that the ports are disconnected with each other.

[0111] It should be noted that the interconnection pattern refers to a back-end pattern.

[0112] In other embodiments, for the purpose of breaking the circuit, only the preset connection layer pattern in the interconnection pattern can be deleted, and other interconnection patterns, such as other metal layer patterns and via hole patterns, except the preset connection layer pattern, can be reserved.

[0113] In the embodiment, the original layout acquisition unit is configured to acquire a plurality of parameterized units, obtain a plurality of unit patterns, and place the unit patterns in the same original layout.

[0114] As an example, the original layout acquisition unit places the unit patterns in an array in a layout file in batches through a script.

[0115] In the embodiment, the first pattern processing unit is configured to delete the first metal layer pattern and all metal layer patterns and via hole patterns above the first metal layer pattern.

[0116] In the embodiment, when the first pattern processing unit deletes at least the preset connection layer pattern, the plug-in pattern is reserved.

[0117] The plug-in pattern is reserved to facilitate obtaining a second state layout based on the first state layout, reduce the complexity of obtaining the second state layout, and improve the verification efficiency.

[0118] As an example, the first pattern processing unit deletes the interconnection pattern through a script.

[0119] In the embodiment, the pattern acquisition module 10 comprises a second pattern acquisition module (not shown in the figure), configured to acquire a layout in a second state.

[0120] Specifically, the second pattern acquisition module is configured to connect all ports in the first state layout by using a preset connection layer pattern, so that all the ports are short-circuited to each other through the preset connection layer pattern.

[0121] The preset connection layer pattern is added to the first state layout to obtain a second state layout, which reduces the complexity of obtaining the second state layout.

[0122] In the embodiment, the preset connection layer pattern is a first metal layer pattern, so that the devices can be divided into two cases of being connected to each other and being disconnected from each other through physical connection, and the breaking and short-circuiting can be realized through the first metal layer pattern, thereby reducing the complexity of verification.

[0123] In the embodiment, the second pattern acquisition module is configured to extract the frame of all device patterns in the first state layout, obtain a maximum coverage area based on the extracted frame, and make the preset connection layer pattern cover the maximum coverage area.

[0124] The maximum coverage area is obtained by extracting the frame of all layers of the device pattern in the first state layout, and the preset connection layer pattern covers the maximum coverage area, so as to ensure that the preset connection layer pattern can cover all the device patterns. Moreover, the preset connection layer pattern adopts the full coverage manner, and the complexity of connecting all the ports in the first state layout is reduced.

[0125] Specifically, the ports in the first state layout have plug-in patterns thereon, and thus the second pattern acquisition module covers all the plug-in patterns with the preset connection layer pattern.

[0126] The ports are connected with the preset connection layer pattern through the plug-in patterns thereon, and the preset connection layer pattern covers all the plug-in patterns, so that all the ports are short-circuited with each other through the preset connection layer pattern.

[0127] In this embodiment, the device patterns are arranged in an array in the layout, so that when the preset connection layer pattern is added on the basis of the first state layout, the preset connection layer pattern is easy to cover all the ports, and the difficulty of obtaining the second state layout is reduced. Moreover, the device patterns arranged in an array in the layout also improve the regularity of the layout of the device patterns, and correspondingly reduce the complexity of obtaining the layout.

[0128] The checking module 20 is configured to perform design rule checking on the connectivity relationship between the ports in any state layout by using a design rule checking file, and obtain a checking result about the connectivity relationship.

[0129] The design rule checking file defines the connection rule of the ports and the preset connection layer pattern, and the ports in the device pattern have a preset connectivity relationship, so that whether the actual checking result is consistent with the preset connectivity relationship is judged, and it is verified whether the definition of the connection rule of the ports and the preset connection layer pattern in the design rule checking file is correct.

[0130] As an example, the design rule checking file is a design rule checking script.

[0131] As an example, the connection rule of the ports and the preset connection layer pattern includes that the ports are connected with the preset connection layer pattern through plug-in patterns.

[0132] In this embodiment, the checking module 20 is configured to perform network statistics to obtain the network identifiers of all the ports in the corresponding state layout. As an example, a network identifier list is obtained.

[0133] As an example, the network statistics are performed by running a network statistics instruction to obtain the network identifiers of all the ports.

[0134] The ports short-circuited to each other belong to the same network, and thus the ports short-circuited to each other theoretically have the same network identifier. The ports open-circuited to each other do not belong to the same network, and thus the ports open-circuited to each other theoretically have different network identifiers. The ports have a preset connectivity relationship. In the layout in the first state, the preset connectivity relationship is that the ports are open-circuited to each other. In the layout in the second state, the preset connectivity relationship is that the ports are short-circuited to each other through the preset connection layer pattern. Therefore, the network identifiers of all the ports in the layout in the corresponding state are obtained as the checking result and output, so as to facilitate judging whether the actual checking result is consistent with the preset connectivity relationship in the corresponding state.

[0135] In this embodiment, after the checking module 20 obtains the layout in the first state, the checking module 20 performs design rule checking on the connectivity relationship between the ports in the layout in the first state through the design rule checking file, and obtains a first checking result about the connectivity relationship.

[0136] Correspondingly, the first checking result is the network identifiers of all the ports in the layout in the first state.

[0137] Since the preset connectivity relationship is that the ports are open-circuited to each other in the layout in the first state, in the first checking result, theoretically, each port corresponds to a network identifier, and the network identifiers are different from each other.

[0138] In this embodiment, the layout in the first state does not contain the preset connection layer pattern. Therefore, when the design rule checking is performed on the connectivity relationship between the ports, since the preset connection layer pattern cannot be recognized, each port has an independent network identifier.

[0139] In this embodiment, after the checking module 20 obtains the layout in the second state, the checking module 20 performs design rule checking on the connectivity relationship between the ports in the layout in the second state through the design rule checking file, and obtains a second checking result about the connectivity relationship.

[0140] Correspondingly, the second checking result is the network identifiers of all the ports in the layout in the second state.

[0141] Since the preset connectivity relationship is that the ports are short-circuited to each other through the preset connection layer pattern in the layout in the second state, in the second checking result, theoretically, the network identifiers of all the ports are the same.

[0142] In this embodiment, after the checking module 20 obtains the first checking result about the connectivity relationship, the layout in the second state is obtained through the second pattern obtaining module in the pattern obtaining module 10.

[0143] The preset connectivity relationship corresponding to the second state layout is that the ports are short-circuited through the preset connection layer pattern, and thus, the design rule check is performed on the first state layout, and after the check is completed, the preset connection layer pattern is added to the first state layout, so that the second state layout is obtained, which is beneficial to reducing the complexity of obtaining the layout in different states.

[0144] It should be noted that in other embodiments, the layout in the first state can also be obtained after the second check result about the connectivity relationship is obtained. For example, after the layout in the first state is obtained, all the ports in the first state layout are connected through the preset connection layer pattern to obtain the second state layout, and the connectivity relationship between the ports in the second state layout is checked according to the design rule to obtain the second check result, and then the first state layout is obtained again, and the connectivity relationship between the ports in the first state layout is checked according to the design rule.

[0145] In this embodiment, the verification module 30 verifies the design rule check file according to the first check result and the second check result, and when any one of the first check result and the second check result is inconsistent with the preset connectivity relationship of the corresponding state, it is determined that the definition of the connection rule of the port and the preset connection layer pattern in the design rule check file is incorrect.

[0146] As can be seen, in this embodiment, all device patterns are placed in one layout, the short-circuit and open-circuit relationship of the devices is established through the preset connection layer pattern, that is, all device patterns are divided into two cases of connection and disconnection through physical connection, so that the front-stage connection relationship is analyzed, and the design rule check file is verified in combination with the first check result and the second check result, so that the verification result in the case of device open circuit is obtained, and the verification result in the case of device short circuit is also obtained, and the front-stage connection relationship of the device is verified in combination with the two cases of device open circuit and device short circuit, so that the verification quality is further improved.

[0147] Specifically, the verification module 30 determines whether the check result is consistent with the preset connectivity relationship of the corresponding state according to the network identifier.

[0148] Theoretically, the ports that are short-circuited have the same network identifier, and the ports that are open-circuited have different network identifiers, and thus the accuracy of the check result can be determined through the network identifier, and the determination method is simple.

[0149] As an example, in the case of performing design rule checking on the connectivity relationship between ports in the first state layout, the verification module 30 judges whether the network identifiers in the first checking result are all independent; when the network identifiers in the first checking result are not all independent, it is determined that the definition of the connection rule of the port and the preset connectivity layer graph in the design rule checking file is incorrect.

[0150] The ports in the first state layout are mutually disconnected, so that each port theoretically has an independent network identifier, that is, the port and the network identifier are one-to-one corresponding, and the network identifiers are all different from each other; if there are the same network identifiers in the first checking result, it is indicated that the definition of the connection rule is incorrect.

[0151] As another example, in the case of performing design rule checking on the connectivity relationship between ports in the second state layout, the verification module 30 judges whether the network identifiers in the second checking result are all the same; when the network identifiers in the second checking result are not all the same, it is determined that the definition of the connection rule of the port and the preset connectivity layer graph in the design rule checking file is incorrect.

[0152] The ports in the second state layout are mutually short-circuited, so that all the ports are theoretically the same network identifier; if there are different network identifiers in the second checking result, it is indicated that the definition of the connection rule is incorrect.

[0153] As an example, when it is determined that the definition of the connection rule is incorrect, the specific reason needs to be further analyzed and modified by referring to the design rule manual.

[0154] In the embodiment, when the checking result is consistent with the preset connectivity relationship of the corresponding state, it is determined that the definition of the connection rule of the port and the preset connectivity layer graph is correct.

[0155] Specifically, when the first checking result and the second checking result are both consistent with the preset connectivity relationship of the corresponding state, it is proved that the definition of the front connection relationship of the device is correct, and can be used for design rule checking.

[0156] It should be noted that the verification system of the design rule checking file in the embodiment of the application can be used to execute the verification method of the design rule checking file as described above, or other verification systems can be used to execute the verification method of the design rule checking file as described above. For the verification system of the design rule checking file in the embodiment of the application, please refer to the detailed description in the verification method of the design rule checking file as described above, which will not be repeated here.

[0157] Correspondingly, the embodiment of the present application also provides an electronic device, which can verify the design rule checking file in the form of a loaded program to implement the design rule checking file verification method provided by the embodiment of the present application.

[0158] Reference Figure 4 Fig. 1 shows a hardware structure diagram of an electronic device provided by an embodiment of the present application. The device of the embodiment comprises at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0159] In the embodiment, the number of the processor 01, the communication interface 02, the memory 03 and the communication bus 04 is at least one, and the processor 01, the communication interface 02 and the memory 03 complete mutual communication through the communication bus 04.

[0160] The communication interface 02 can be an interface of a communication module for network communication, for example, an interface of a GSM module.

[0161] The processor 01 can be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the design rule checking file verification method of the embodiment.

[0162] The memory 03 can contain a high-speed RAM memory, and can also include a non-volatile memory, for example, at least one disk memory. The memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the design rule checking file verification method provided by the foregoing embodiment.

[0163] It should be noted that the above-mentioned electronic device can also include other devices (not shown) which can not be necessary for the disclosure of the embodiment of the present application; since these other devices can not be necessary for understanding the disclosure of the embodiment of the present application, the embodiment of the present application does not introduce them one by one.

[0164] The embodiment of the present application also provides a storage medium, which stores one or more computer instructions, and the one or more computer instructions are used to implement the design rule checking file verification method provided by the foregoing embodiment.

[0165] The embodiment of the present application also provides a computer program product, which comprises computer instructions, and the computer instructions are executed by a processor to implement the design rule checking file verification method provided by the foregoing embodiment.

[0166] The above-described embodiments of the application are combinations of elements and features of the applications. The elements or features can be applied to one another only in combinations, unless otherwise indicated. Each individual element or feature can be replaced by alternative elements or features serving the same, equivalent or similar purpose, unless otherwise stated. The numerous individual features or elements can be combined or integrated in other combinations or arrangements, unless otherwise indicated. Other combinations and modifications of the application will occur to those skilled in the art upon reading this description.

[0167] Embodiments of the present application can be implemented in various means, for example, hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to an exemplary embodiment of the present application can be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, etc.

[0168] In a firmware or software configuration, the embodiments of the present application can be implemented in the form of modules, procedures, functions, and so on. Software code can be stored in a memory unit and executed by a processor. The memory unit is located at the interior or exterior of the processor and can deliver data to and receive data from the processor via various known means.

[0169] The above description of disclosed embodiments is merely intended to illustrate the general principles of the application. Various modifications in form and details can be made to the described embodiments without departing from the spirit of the application. Accordingly, the scope of the application should be determined not by the embodiments illustrated, but by the claims and their equivalents.

[0170] While the application has been disclosed in connection with the embodiments presented, it should be understood that modifications and / or additions can be made thereto without departing from the spirit and scope of the application. Accordingly, this application is intended to be governed solely by the spirit and scope of the claims, including all equivalents thereof.

Claims

1. A method of verifying a design rule check file, characterized by, The method comprises the following steps: acquiring a layout in either of a first state and a second state, the layout comprising a device pattern, the device pattern comprising ports having a preset connectivity relationship, in the layout in the first state, the preset connectivity relationship being that the ports are mutually disconnected, and in the layout in the second state, the preset connectivity relationship being that the ports are mutually short-circuited through a preset connection layer pattern; performing design rule checking on the connectivity relationship between the ports in the layout in either state by using a design rule checking file, the design rule checking file defining connection rules of the ports and the preset connection layer pattern, and obtaining checking results about the connectivity relationship; verifying the design rule checking file according to the checking results, and determining that the definition of the connection rules of the ports and the preset connection layer pattern in the design rule checking file is incorrect when the checking results do not match the preset connectivity relationship of the corresponding state.

2. The method of verifying a design rule check file according to claim 1, wherein, determining that the definition of the connection rules of the ports and the preset connection layer pattern is correct when the checking results match the preset connectivity relationship of the corresponding state.

3. The method of claim 1, wherein the design rule check file is verified by: acquiring layouts in the first state and the second state respectively; performing design rule checking on the connectivity relationship between the ports in the layout in the first state by using a design rule checking file, and obtaining first checking results about the connectivity relationship; performing design rule checking on the connectivity relationship between the ports in the layout in the second state by using a design rule checking file, and obtaining second checking results about the connectivity relationship; verifying the design rule checking file according to the first checking results and the second checking results, and determining that the definition of the connection rules of the ports and the preset connection layer pattern in the design rule checking file is incorrect when any one of the first checking results and the second checking results does not match the preset connectivity relationship of the corresponding state.

4. The method of verifying a design rule check file according to claim 3, wherein, acquiring the layout in the second state after obtaining the first checking results about the connectivity relationship.

5. The method of verifying a design rule check file according to any one of claims 1 to 4, wherein, performing design rule checking on the connectivity relationship between the ports in the layout in either state by using a design rule checking file, and obtaining checking results about the connectivity relationship, which comprises performing a network statistics operation to obtain network identifiers of all the ports in the layout in the corresponding state; the step of verifying the design rule checking file according to the checking results comprises judging whether the checking results match the preset connectivity relationship of the corresponding state according to the network identifiers.

6. The method of verifying a design rule check file according to claim 5, wherein, acquiring a layout in the first state, performing design rule checking on the connectivity relationship between the ports in the layout in the first state by using a design rule checking file, and obtaining first checking results about the connectivity relationship; verifying the design rule checking file according to the checking results, which comprises judging whether the network identifiers in the first checking results are all independent; determining that the definition of the connection rules of the ports and the preset connection layer pattern in the design rule checking file is incorrect when the network identifiers in the first checking results are not all independent.

7. The method of verifying a design rule check file according to claim 5, wherein, After the layout in the second state is obtained, connectivity between the ports in the layout in the second state is checked according to a design rule checking file, and a second checking result about the connectivity is obtained; According to the checking result, the design rule checking file is verified, including: judging whether the network identifiers in the second checking result are all the same; When the network identifiers in the second checking result are not all the same, it is determined that the definition of the connection rule of the ports and the preset connection layer pattern in the design rule checking file is incorrect.

8. The method of verifying a design rule check file of claim 1, wherein, After the layout in the first state is obtained, all the ports in the layout in the first state are connected by using a preset connection layer pattern, so that all the ports are short-circuited through the preset connection layer pattern, and the layout in the first state does not contain the preset connection layer pattern.

9. The method of verifying a design rule check file according to claim 8, wherein, After the layout in the first state is obtained, all the ports in the layout in the first state are connected by using a preset connection layer pattern, so that all the ports are short-circuited through the preset connection layer pattern, and the layout in the first state does not contain the preset connection layer pattern.

10. The method of claim 8, wherein the design rule check file is verified by checking whether the design rule check file is identical to the design rule check file stored in the memory. In the step of checking the connectivity between the ports according to the design rule checking file, the connection rule of the ports and the preset connection layer pattern defined in the design rule checking file includes that the ports are connected with the preset connection layer pattern through a plug-in pattern; In the step of obtaining the layout in the first state, the port of the device pattern has a plug-in pattern; In the step of connecting all the ports in the layout in the first state by using the preset connection layer pattern, all the plug-in patterns are covered by using the preset connection layer pattern.

11. The method of verifying a design rule check file of claim 1, wherein, The preset connection layer pattern is a first metal layer pattern.

12. The method of verifying a design rule check file according to any one of claims 1 to 4, wherein, The device patterns are arranged in an array in the layout.

13. The method of verifying a design rule check file according to any one of claims 1 to 4, wherein, The step of obtaining the layout in the first state includes: Obtaining an original layout, the original layout including a plurality of unit patterns, each of the unit patterns including a device pattern, a plug-in pattern on a port of the device pattern, and an interconnection pattern on the plug-in pattern, the interconnection pattern including the preset connection layer pattern; At least deleting the preset connection layer pattern, and the remaining unit patterns serving as device patterns.

14. The method of verifying a design rule check file according to claim 13, wherein, The step of at least deleting the preset connection layer pattern includes at least deleting the interconnection pattern.

15. The method of verifying a design rule check file of claim 13, wherein, In the step of at least deleting the preset connection layer pattern, the plug-in pattern is retained.

16. The method of verifying a design rule check file of claim 13, wherein, The step of obtaining the original layout includes obtaining a plurality of parameterized units, obtaining a plurality of unit patterns, and placing the unit patterns into the same original layout.

17. The method of verifying a design rule check file according to any one of claims 1 to 4, wherein, The port of the device pattern includes a gate port, a source port and a drain port.

18. A verification system for design rule check files, characterized by, The method includes: A pattern obtaining module is configured to obtain at least a layout in any one of a first state and a second state, the layout including a device pattern, the device pattern including a port having a preset connectivity, in the layout in the first state, the preset connectivity being that the ports are disconnected from each other, and in the layout in the second state, the preset connectivity being that the ports are short-circuited through a preset connection layer pattern; The checking module is configured to perform design rule checking on a connectivity relationship between ports in the layout of any of the states by using a design rule checking file, and obtain a checking result about the connectivity relationship, wherein the design rule checking file defines a connection rule of the ports and a preset connection layer pattern; The verification module is configured to verify the design rule checking file according to the checking result, and determine that a definition of the connection rule of the ports and the preset connection layer pattern in the design rule checking file is incorrect when the checking result does not match a preset connectivity relationship of a corresponding state.

19. An apparatus, comprising: The apparatus includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method for verifying the design rule checking file according to any one of claims 1-17.

20. A storage medium, characterized by The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the method for verifying the design rule checking file according to any one of claims 1-17.

21. A computer program product, characterised in that, The computer instructions are executed by the processor to implement the method for verifying the design rule checking file according to any one of claims 1-17.

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