Reader-writer

Abstract

The invention discloses a reader-writer which comprises a demodulation circuit used for extracting an envelope signal of a radio frequency signal emitted by an electronic tag, a pulse shaping circuit connected with the demodulation circuit and used for outputting a modulation ending pulse signal or a modulation starting pulse signal based on the envelope signal output by the demodulation circuit; the counter is connected with the demodulation circuit, and the counter is used for counting in response to the change of the amplitude of the envelope signal output by the demodulation circuit; the symbol detection circuit is connected with the counter and the pulse shaping circuit, and the symbol detection circuit is used for responding to the modulation starting pulse signal, controlling the counter to be zero and starting to count; controlling a stop counting of the counter in response to the end modulation pulse signal; and carrying out symbol detection and demodulation based on the count value of the counter to obtain original data information. Therefore, through the combination of the demodulation circuit, the pulse shaping circuit and the symbol detection circuit, the reliability of reading information recorded in the electronic tag can be improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a reader-writer. BACKGROUND

[0002] With the continuous promotion of the construction of new power systems, the intelligent management of power equipment is facing multi-dimensional challenges. The monitoring data generated by power equipment has real-time, dynamic and massive characteristics. In order to effectively manage the power equipment, an electronic tag is generally used to record the relevant information of the power equipment. The staff can identify and extract the information recorded in the electronic tag through the reader-writer to obtain the relevant information of the power equipment.

[0003] However, the traditional reader-writer has the problems of unstable signal identification and easy interference in a complex electromagnetic environment, resulting in low reliability of the information recorded in the electronic tag read by the reader-writer. SUMMARY

[0004] The embodiments of the application provide a reader-writer which can improve the reliability of reading the information recorded in the electronic tag.

[0005] In a first aspect, the embodiments of the application provide a reader-writer, comprising:

[0006] A demodulation circuit, the demodulation circuit is used for extracting an envelope signal of a radio frequency signal emitted by an electronic tag, and the envelope signal comprises original data information of the electronic tag;

[0007] A pulse shaping circuit, the pulse shaping circuit is connected with the demodulation circuit, and the pulse shaping circuit is used for outputting an end modulation pulse signal or a start modulation pulse signal based on the envelope signal output by the demodulation circuit;

[0008] A counter, the counter is connected with the demodulation circuit, and the counter is used for counting in response to a change in the amplitude of the envelope signal output by the demodulation circuit;

[0009] A symbol detection circuit, the symbol detection circuit is connected with the counter and the pulse shaping circuit, and the symbol detection circuit is used for controlling the counter to be zero and start counting in response to the start modulation pulse signal, controlling the counter to stop counting in response to the end modulation pulse signal, and performing symbol detection and demodulation based on the count value of the counter to obtain the original data information.

[0010] In some embodiments, the demodulation circuit comprises a low-pass filter circuit, and the low-pass filter circuit is connected with the pulse shaping circuit and the counter.

[0011] In some embodiments, the low-pass filter circuit comprises:

[0012] a first resistor, one end of the first resistor inputting the radio frequency signal;

[0013] a first transistor, a gate of the first transistor being connected with the other end of the first resistor;

[0014] a second resistor, one end of the second resistor being connected with a source of the first transistor, and the other end being grounded;

[0015] a second transistor, a gate of the second transistor being connected with a source of the first transistor, a source of the second transistor being grounded, and a drain of the second transistor being connected with the pulse shaping circuit and the counter;

[0016] a third resistor, one end of the third resistor being connected with a drain of the first transistor, and the other end being connected with a drain of the second transistor.

[0017] In some embodiments, the demodulation circuit further comprises:

[0018] a third transistor, a gate of the third transistor being connected with the low pass filter circuit, and a source of the third transistor being grounded;

[0019] a high pass filter circuit, a first end of the high pass filter circuit being connected with a drain of the first transistor, a second end of the high pass filter circuit being connected with a drain of the third transistor, and a third end of the high pass filter circuit being connected with the pulse shaping circuit and the counter.

[0020] In some embodiments, the high pass filter circuit comprises:

[0021] a fourth resistor, one end of the fourth resistor being connected with a drain of the first transistor, and the other end being connected with a drain of the third transistor;

[0022] a first capacitor, one end of the first capacitor being connected with the other end of the fourth resistor, and the other end of the first capacitor being connected with the pulse shaping circuit and the counter;

[0023] a fifth resistor, one end of the fifth resistor being connected with the other end of the first capacitor, and the other end being grounded.

[0024] In some embodiments, the demodulation circuit further comprises:

[0025] a fourth transistor, a drain of the fourth transistor being connected with the other end of the first capacitor, and a source and a gate of the fourth transistor being grounded.

[0026] In some embodiments, the pulse shaping circuit comprises:

[0027] a fifth transistor, a gate of the fifth transistor being connected with the adjusting circuit, and a source of the fifth transistor being grounded.

[0028] a sixth transistor, a drain of the sixth transistor being connected with the drain of the fifth transistor, a source of the sixth transistor being connected with the source of the fifth transistor;

[0029] a sixth resistor, one end of the sixth resistor being connected with the drain of the fifth transistor;

[0030] a power supply circuit, the power supply circuit being used for supplying power to the fifth transistor and the sixth transistor, a first end of the power supply circuit being connected with the other end of the sixth resistor, a second end of the power supply circuit being grounded;

[0031] a time constant circuit, the time constant circuit being used for determining a pulse width of the pulse shaping circuit, a first end of the time constant circuit being connected with the drain of the fifth transistor, a second end of the time constant circuit being connected with a third end of the power supply circuit;

[0032] a seventh transistor, a gate of the seventh transistor being connected with the third end of the time constant circuit, a source of the seventh transistor being connected with the source of the sixth transistor, a drain of the seventh transistor being connected with the second end of the time constant circuit;

[0033] a push-pull circuit, the push-pull circuit being used for buffering a signal outputted by the seventh transistor, a first end of the push-pull circuit being connected with the drain of the seventh transistor, a second end of the push-pull circuit being connected with the source of the seventh transistor, a third end of the push-pull circuit being connected with the drain of the seventh transistor, a fourth end of the push-pull circuit being connected with the gate of the sixth transistor, a fifth end of the push-pull circuit being connected with the sign detection circuit.

[0034] In some embodiments, the power supply circuit comprises:

[0035] a second capacitor, one end of the second capacitor being connected with the other end of the sixth resistor, the other end of the second capacitor being grounded;

[0036] an eighth transistor, a source of the eighth transistor being connected with one end of the second capacitor, a drain of the eighth transistor being connected with the second end of the time constant circuit.

[0037] In some embodiments, the time constant circuit comprises:

[0038] a third capacitor, one end of the third capacitor being connected with the drain of the fifth transistor, the other end of the third capacitor being connected with the gate of the seventh transistor;

[0039] a seventh resistor, one end of the seventh resistor being connected with the other end of the third capacitor, the other end of the seventh resistor being connected with the drain of the eighth transistor and the drain of the seventh transistor.

[0040] In some embodiments, the push-pull circuit comprises:

[0041] a ninth transistor, a gate of the ninth transistor being connected with a drain of the seventh transistor, a source of the ninth transistor being connected with a source of the seventh transistor, a drain of the ninth transistor being connected with a drain of the seventh transistor;

[0042] a tenth transistor, a source of the tenth transistor being connected with a source of the ninth transistor, a gate of the tenth transistor being connected with a drain of the ninth transistor, a drain of the tenth transistor being connected with the symbol detection circuit;

[0043] an eleventh transistor, a gate of the eleventh transistor being connected with a gate of the sixth transistor, a source of the eleventh transistor being connected with a drain of the tenth transistor, a drain of the eleventh transistor being connected with a drain of the ninth transistor.

[0044] In a second aspect, the embodiments of the present application provide an electronic device, the device comprising the reader / writer of the first aspect.

[0045] The reader / writer and the electronic device of the embodiments of the present application can be responsible for extracting the envelope signal in the radio frequency signal through the demodulation circuit, effectively filtering out the carrier frequency and its harmonics, and only retaining the modulation information of the signal, i.e., the envelope signal. Since the envelope signal contains the actual transmitted data information, and high-frequency noise and interference are usually located near the carrier frequency, by extracting the envelope signal, the influence of these noise and interference on the signal can be significantly reduced. The pulse shaping circuit generates the start and end modulation pulses based on the envelope signal, further optimizes the shape of the signal, can enhance the edge definition of the signal, reduce the misjudgment caused by the fuzzy signal edge, and make it more suitable for subsequent symbol detection; the symbol detection circuit controls the counter to zero after receiving the start modulation pulse signal, and starts counting the amplitude change of the envelope signal. When the end modulation pulse signal is received, the counting is stopped. This counting method based on accurate synchronization signal can ensure the accuracy of the counting, thereby improving the accuracy of the symbol detection. In this way, the accuracy and anti-interference ability of signal processing are improved, the technical problems of unstable signal recognition and easy interference of the traditional reader / writer in a complex electromagnetic environment are solved, and the data processing ability and reliability of the system are enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced below. Those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0047] Figure 1is a structural schematic diagram of a reader-writer provided by an embodiment of the present application;

[0048] Figure 2 is a circuit schematic diagram of a first embodiment of a demodulation circuit provided by an embodiment of the present application;

[0049] Figure 3 is a circuit schematic diagram of a second embodiment of a demodulation circuit provided by an embodiment of the present application;

[0050] Figure 4 is a schematic diagram of a pulse shaping circuit provided by an embodiment of the present application;

[0051] Figure 5 is a schematic diagram of a symbol detection circuit provided by an embodiment of the present application;

[0052] Figure 6 is a circuit schematic diagram of an electronic tag provided by an embodiment of the present application;

[0053] Figure 7 is a schematic diagram of a square patch antenna provided by an embodiment of the present application. DETAILED DESCRIPTION

[0054] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the drawings. To make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of the specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0055] It should be noted that, in this document, relational terms such as first and second and the like can only be used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations exist in any such actual relationship or order. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements does not only include those elements, but also includes other elements not explicitly listed or other elements inherent to such process, method, article or apparatus. Without more limitations, an element defined by the statement "comprising" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0056] To solve the related art problems, an embodiment of the present application provides a reader-writer. First, the reader-writer provided by an embodiment of the present application will be introduced.

[0057] This reader can be used to read information from electronic tags.

[0058] Figure 1 A schematic diagram of the reader / writer provided in an embodiment of this application is shown. Figure 1 As shown, the reader includes a demodulation circuit, a pulse shaping circuit, a counter, and a symbol detection circuit.

[0059] The demodulation circuit is used to extract the envelope signal (Env_out signal) of the radio frequency signal emitted by the electronic tag. The envelope signal includes the original data information of the electronic tag.

[0060] The pulse shaping circuit is connected to the demodulation circuit, and the pulse shaping circuit is used to output an end-modulation pulse signal or an start-modulation pulse signal based on the envelope signal output by the demodulation circuit.

[0061] The counter is connected to the demodulation circuit and is used to count in response to changes in the amplitude of the envelope signal output by the demodulation circuit.

[0062] The symbol detection circuit is connected to the counter and the pulse shaping circuit. The symbol detection circuit is used to control the counter to be reset to zero and start counting in response to the start modulation pulse signal; to control the counter to stop counting in response to the end modulation pulse signal; and to perform symbol detection and demodulation based on the counter count value to obtain the original data information.

[0063] Specifically, refer to Figure 2 , Figure 2 A circuit diagram of a first embodiment of the demodulation circuit provided in this application.

[0064] The main function of the demodulation circuit (AM demodulation circuit) is to extract the envelope of the AM modulated signal from the radio frequency (RF) signal, which is the Env_out signal.

[0065] like Figure 2 As shown, the demodulation circuit may include a low-pass filter circuit, which is connected to a pulse shaping circuit and a counter. The low-pass filter circuit is used to attenuate the input radio frequency signal (RF signal) to obtain the Env_out signal, and outputs the Env_out signal to the pulse shaping circuit and the counter, as shown. Figure 2 The green line in the diagram indicates the signal path, and the output signal is Env_out.

[0066] In some embodiments, the low-pass filter circuit may include a first resistor R. in First transistor M1, second resistor R c The second transistor M2 and the third resistor R DM2.

[0067] wherein one end of the first resistor R in inputs the radio frequency signal; the other end of the first resistor R in is connected to the gate of the first transistor M1; one end of the second resistor R c is connected to the source of the first transistor M1, and the other end is grounded; the gate of the second transistor M2 is connected to the source of the first transistor M1, the source of the second transistor M2 is grounded, and the drain of the second transistor M2 is connected to the pulse shaping circuit and the counter; one end of the third resistor R DM2 is connected to the drain of the first transistor M1, and the other end is connected to the drain of the second transistor M1.

[0068] The RF signal is first attenuated by a low-pass filter network (low-pass filter circuit) composed of R in , R c and the gate-source capacitance C GS of M1, and the capacitance C GS of M2 in parallel, M1 works as a voltage follower, making the upper half of the sine wave of the RF signal work in the saturation region and the lower half enter the cutoff region, and the C GS of M2 and R DM2 jointly determine the discharge time constant required to obtain the AM envelope of the RF signal (i.e. the Env_out signal).

[0069] In some embodiments, as shown in Figure 3 , the circuit schematic diagram of a second embodiment of the demodulation circuit provided by the embodiments of the present application is shown in Figure 3 . The above demodulation circuit can further include a third transistor M3 and a high-pass filter circuit.

[0070] wherein the gate of the third transistor is connected to the low-pass filter circuit, and the source of the third transistor is grounded; the first end of the high-pass filter circuit is connected to the drain of the first transistor M1, the second end is connected to the drain of the third transistor M3, and the third end is connected to the pulse shaping circuit and the counter.

[0071] In some embodiments, the high-pass filter circuit can include a fourth resistor R DM3 , a first capacitor C HP , and a fifth resistor R HP .

[0072] wherein one end of the fourth resistor R DM3 is connected to the drain of the first transistor M1, and the other end is connected to the drain of the third transistor M3; one end of the first capacitor C HP is connected to the other end of the fourth resistor R DM3 , and the other end is connected to the pulse shaping circuit and the counter; one end of the fifth resistor R HP is connected to the first capacitor CHP The other end is connected to the ground.

[0073] As Figure 3 shown in the blue line in the figure is the signal direction, and the output Env_out signal.

[0074] In order to improve the slew rate of the envelope edge, the Env_out signal from the drain of M2 is sent to the gate of the second stage (M3), and finally through the high-pass RC filter (high-pass filter circuit) composed of C HP , R DM3 and R HP . In this way, a short positive pulse is generated each time the RF carrier reappears. These pulses are used to generate the Endmod signal, which is crucial for the timing control of the tag.

[0075] In some embodiments, the demodulation circuit can also include a fourth transistor M4, the drain (D) of which is connected to the other end of the first capacitor C HP , and the source (S) and gate (G) of the fourth transistor M4 are grounded.

[0076] In some embodiments, the above-mentioned transistors can be NPN transistors or PNP transistors, etc.

[0077] For example, as shown in Figure 3 or Figure 2 , the 13.56 MHZ f c signal first passes through an RC filter network composed of a 170-kilohm (170kΩ) resistor R in , an 11fF C GS capacitor in the NPN transistor M1, and a 2-megohm (2MΩ) resistor R c and the C GS capacitor of the NPN transistor M2 are connected in parallel. The C GS capacitor of M2 is designed to be high, and by selecting a high width-to-length ratio, high instantaneous gain is achieved, effectively filtering out the radio frequency carrier frequency and extracting the desired AM envelope signal. The M1 transistor acts as a voltage follower, allowing the upper half of the RF sinusoidal wave to operate in the saturation region and the lower half to be in the cutoff region. The C GS capacitor of M2 and the R c resistor together determine the discharge time constant of the AM envelope signal of the RF signal, ensuring stable extraction of the envelope signal.

[0078] As shown in Figure 3 , the Env_out signal from the drain of M2 is first transmitted to the gate of the second stage M3, and then through the high-pass RC filter (high-pass filter circuit) composed of C HP capacitor, R DM3 resistor, and RHP The high-pass RC filter composed of resistors generates short positive pulses each time the radio frequency carrier is recovered, and these pulses are used to generate the Endmod signal which is essential for the timing control of the tag. Figure 3 The C of M3 GS = 75 fF, R DM2 = 1.5 MΩ are taken as examples.

[0079] In some embodiments, referring to Figure 4 , Figure 4 The schematic diagram of the pulse shaping circuit provided by the embodiments of the present application is shown.

[0080] The pulse shaping circuit (i.e. Eccles-Jordan circuit) adopts an improved monostable circuit, and the function thereof is to generate the Endmod signal (end modulation pulse signal) and the Startmod signal (start modulation pulse signal).

[0081] As shown in Figure 4 , the pulse shaping circuit can include a fifth transistor M5, a sixth transistor M6, a sixth resistor R D , a power supply circuit, a time constant circuit, a seventh transistor M7, and a push-pull circuit. The power supply circuit is used to supply power to the fifth transistor M5 and the sixth transistor M6, the time constant circuit is used to determine the pulse width generated by the pulse shaping circuit, and the push-pull circuit is used to buffer the signal output by the seventh transistor.

[0082] Among them, the gate (G) of the fifth transistor M5 is connected to the adjusting circuit, and the source (S) of the fifth transistor M5 is grounded; the drain (D) of the sixth transistor M6 is connected to the drain (D) of the fifth transistor M5, and the source (S) of the sixth transistor M6 is connected to the source (S) of the fifth transistor M5; one end of the sixth resistor R D is connected to the drain (D) of the fifth transistor M5; the first end of the power supply circuit is connected to the other end of the sixth resistor R D , and the second end of the power supply circuit is grounded; the first end of the time constant circuit is connected to the drain (D) of the fifth transistor M5, and the second end of the time constant circuit is connected to the third end of the power supply circuit; the gate (G) of the seventh transistor M7 is connected to the third end of the time constant circuit, the source (S) of the seventh transistor M7 is connected to the source (S) of the sixth transistor M6, and the drain (D) of the seventh transistor M7 is connected to the second end of the time constant circuit; the first end of the push-pull circuit is connected to the drain (D) of the seventh transistor M7, the second end of the push-pull circuit is connected to the source (S) of the seventh transistor M7, the third end of the push-pull circuit is connected to the drain (D) of the seventh transistor M7, the fourth end of the push-pull circuit is connected to the gate of the sixth transistor M6, and the fifth end of the push-pull circuit is connected to the symbol detection circuit.

[0083] In some embodiments, the power supply circuit can include a second capacitor C B and an eighth transistor M D .

[0084] wherein one end of the second capacitor C B is connected to the other end of the sixth resistor R D , the other end of the second capacitor is grounded; the source of the eighth transistor M D is connected to one end of the second capacitor C B , and the drain of the eighth transistor M D is connected to the second end of the time constant circuit.

[0085] In some embodiments, the time constant circuit can include a third capacitor C EC and a seventh resistor R EC .

[0086] wherein one end of the third capacitor C EC is connected to the drain (D) of the fifth transistor M5, the other end of the third capacitor C EC is connected to the gate of the seventh transistor M7; one end of the seventh resistor R EC is connected to the other end of the third capacitor C EC , the other end of the seventh resistor R EC is connected to the drain of the eighth transistor M D , the drain of the seventh transistor M7.

[0087] In some embodiments, the push-pull circuit can include a ninth transistor M8, a tenth transistor M 10 and an eleventh transistor M9.

[0088] wherein the gate of the ninth transistor M8 is connected to the drain of the seventh transistor M7, the source of the ninth transistor M8 is connected to the source of the seventh transistor M7, and the drain of the ninth transistor M8 is connected to the drain of the seventh transistor M7; the source of the tenth transistor M 10 is connected to the source of the ninth transistor M8, the gate of the tenth transistor M 10 is connected to the drain of the ninth transistor M8, and the drain of the tenth transistor M 10 is connected to the symbol detection circuit; the gate of the eleventh transistor M9 is connected to the gate of the sixth transistor M6, the source of the eleventh transistor M9 is connected to the drain of the tenth transistor M 10 , and the drain of the eleventh transistor M9 is connected to the drain of the ninth transistor M8.

[0089] In some embodiments, the pulse shaping circuit can further include an eighth resistor R MD7 , one end of the eighth resistor R MD7 is connected to the drain of the seventh transistor M7, and the other end of the eighth resistor RMD7 The other end of the eighth resistor R MD7 The other end of the eighth resistor R EC The other end of the eighth resistor R

[0090] In some embodiments, the pulse shaping circuit can further include a ninth resistor R MD8 The other end of the ninth resistor R MD8 The one end of the ninth resistor R MD8 The one end of the ninth resistor R MD8 The other end of the ninth resistor R

[0091] In some embodiments, in the case that the pulse shaping circuit can further include an eighth resistor R MD7 The other end of the ninth resistor R MD7 The other end of the eighth resistor R

[0092] The drain and the gate of the seventh transistor M7 are connected with a system voltage source V harv .

[0093] In some embodiments, the pulse shaping circuit further includes a twelfth transistor M 12 , a thirteenth transistor M 13 and a fourteenth transistor M 14 .

[0094] The gate and the source of the twelfth transistor M 12 are connected with the source of the sixth transistor M6, the drain of the twelfth transistor M 12 is connected with the gate and the source of the thirteenth transistor M 13 , the drain of the thirteenth transistor M 13 is connected with the other end of the third capacitor C EC , the source and the gate of the fourteenth transistor M 14 are connected with the drain of the thirteenth transistor M 13 , and the drain of the fourteenth transistor M 14 is connected with a reference voltage source Vref.

[0095] In some embodiments, the pulse shaping circuit can further include a tenth resistor R MD10 The one end of the tenth resistor R MD10 is connected with the drain of the tenth transistor M 10 , and the other end of the tenth resistor R MD10 is connected with the drain of the eleventh transistor M9.

[0096] Specifically, the E-C circuit is triggered by a positive pulse at the gate of transistor M5. The drain resistance of transistor M5 and the first stage of the E-C circuit (i.e., M6) are connected by C. B Bypass capacitor and M D The transistor (used as a diode) is used for power supply. This method ensures that the drain voltage of M5 and M6 is unaffected by V. harv The effect of fluctuations. Therefore, the pulse width generated by the E-C circuit depends only on C. EC and R EC The time constant is determined to ensure that the Endmod and Startmod pulse signals are immune to changes in RF field strength. To ensure C EC Under stable charging conditions, the maximum gate voltage of the second stage (M7) of the EC circuit is limited to a value determined by the tag's internal reference voltage source (V). ref =1.1V) and M L The threshold voltage U of the transistor t (used as a diode to limit C) EC Within the range of the sum of voltages. To maintain a high switching rate for the Endmod and Startmod pulse signals, the second stage of the E-C circuit uses an RTL inverter (utilizing M8) and is connected by M9 and M... 10 A push-pull circuit composed of transistors is used for buffering to maintain the high slew rate characteristics of the Endmod pulse signal and the Startmod pulse signal, ensuring stable and fast signal transmission.

[0097] In some embodiments, refer to Figure 5 , Figure 5 This is a schematic diagram of a symbol detection circuit provided in an embodiment of this application.

[0098] The symbol detection circuit may include a pseudo-CMOS inverter, a counter, a first D flip-flop DFF1, a second D flip-flop DFF2, and a detection and demodulation circuit. The detection and demodulation circuit is used to perform symbol detection and demodulation based on the counter value to obtain the original data information. The bistable synchronous circuit includes a pair of D flip-flops.

[0099] In this circuit, the first terminal of the pseudo-CMOS inverter is connected to the pulse shaping circuit, the first terminal of the counter is connected to the demodulation circuit, the second terminal of the counter is connected to the second terminal of the pseudo-CMOS inverter, the first terminal of the first D flip-flop DFF1 is connected to the third terminal of the pseudo-CMOS inverter, the second terminal of the first D flip-flop DFF1 is connected to the third terminal of the counter, the first terminal of the second D flip-flop DFF2 is connected to the first terminal of the first D flip-flop DFF1, the second terminal of the second D flip-flop DFF2 is connected to the fourth terminal of the counter, one terminal of the detection and demodulation circuit is connected to the third terminals of the first D flip-flop DFF1 and the second D flip-flop DFF2, and the other terminal of the detection and demodulation circuit outputs the original data information.

[0100] Specifically, the pseudo CMOS inverter can include a plurality of unipolar transistors, such as Figure 5 as shown, Figure 5 Taking the pseudo CMOS inverter including 5 unipolar transistors as an example.

[0101] The one end of the i-th unipolar transistor FET i is connected with the pulse shaping circuit, the one end of the i+1-th unipolar transistor FET i+1 is connected with the other end of the i-th unipolar transistor FET i , i takes a value from 1 to N-1, N is the number of unipolar transistors included in the plurality of unipolar transistors, the one end of the N-th unipolar transistor FET N is connected with the one end of the N-1-th unipolar transistor FET N-1 , the other end of the N-1-th unipolar transistor FET N-1 is connected with the second end of the counter, and the other end of the N-th unipolar transistor FET N is connected with the first end of the first D flip-flop DFF1.

[0102] The counter can include a plurality of D flip-flops, such as Figure 5 as shown, Figure 5 Taking the counter including 4 D flip-flops as an example.

[0103] The first end of the third D flip-flop DFF3 is connected with the demodulation circuit and the clock, the first end of the i+1-th D flip-flop DFF i+1 is connected with the second end D of the i-th D flip-flop DFF i , the third end of the i-th D flip-flop DFF i is connected, the fourth end R of the i+1-th D flip-flop DFF i+1 is connected with the fourth end R of the i-th D flip-flop DFF i , i takes a value from 3 to 3+M, M is the number of D flip-flops included in the plurality of D flip-flops, the fourth end R of the 3+M-th D flip-flop DFF 3+M is connected with the other end of the N-1-th unipolar transistor FET N-1 , the first end of the 3+M-th D flip-flop DFF 3+M is connected with the second end D of the first D flip-flop DFF1, and the third end of the 3+M-th D flip-flop DFF 3+M is connected with the second end D of the second D flip-flop DFF2.

[0104] The counter can be a 4-bit ripple counter composed of cascaded D flip-flops, rather than a synchronous counter sharing a common clock signal, to reduce the fan-out load from the carrier divider master clock node. When OOK modulation is enabled, the ripple counter is initialized by the Startmod pulse signal. After completing the interval measurement, the counter high-bit output is buffered and synchronized by a pair of D flip-flops triggered by the Startmod signal delayed by a four-stage pseudo-CMOS inverter.

[0105] Further, in order to facilitate understanding, the following describes the signal flow process of the above reader:

[0106] The AM demodulation circuit first extracts the envelope (Env_out) from the 13.56 MHz RF signal, and generates Startmod and Endmod pulses to mark the start and end of modulation through a pulse shaping circuit; then, after the pulses are optimized by the pulse shaping circuit to ensure their fixed width and immunity to voltage fluctuations, they are transmitted to the symbol detection circuit. The symbol detection circuit uses the Startmod pulse to trigger a four-bit ripple counter to measure the modulation interval, thereby distinguishing different commands such as the detection request signal SENS_REQ or the read data channel signal RID.

[0107] With the continuous advancement of new power system construction, the intelligent management of power equipment is facing multi-dimensional challenges. The monitoring data generated by power equipment has real-time, dynamic and massive characteristics. Traditional paper labels have been difficult to meet the needs of modern power systems for power equipment management, which is manifested in the following aspects: first, traditional power equipment labels rely on paper work order systems, resulting in scattered data storage and low retrieval efficiency; second, power equipment inspection operations are easily affected by extreme environmental and climate conditions, resulting in insufficient monitoring continuity; third, manual recording methods lack multi-dimensional data analysis capabilities and are difficult to support intelligent evaluation of equipment status.

[0108] Although traditional RFID (Radio Frequency Identification) electronic tags have been widely used in some industries, they cannot meet the actual needs of the special environment of smart grid power equipment, which is manifested in:

[0109] 1) Lack of flexibility. The form of smart grid power equipment is diverse (such as transformers and cable joints), and the size of traditional RFID tags is difficult to fit into narrow spaces;

[0110] 2) Insufficient transmission rate and poor monitoring real-time performance. Due to the limitations of communication protocol standards, traditional RFID tags cannot meet the transmission rate requirements of smart grid scenarios;

[0111] 3) Security is not enough. The security encryption of traditional RFID tags does not meet the security requirements of sensitive data transmission equipment in smart grids, and the vulnerabilities of traditional encryption methods pose a major threat to data integrity, grid reliability and physical device security.

[0112] To solve the above related problems, the embodiment provides an electronic tag, which refers to Figure 6 , Figure 6 The circuit schematic diagram of the electronic tag provided by the embodiment is shown in Figure 6 The electronic tag includes an electronic tag chip U1, an antenna and a peripheral circuit, the peripheral circuit is connected with a preset pin of the electronic tag chip, and the antenna is connected with a preset pin of the electronic tag chip.

[0113] In an implementation manner, the electronic tag chip can adopt an integrated circuit chip based on near field communication technology. In a specific implementation, the integrated circuit chip based on near field communication technology can adopt a PN532 chip, Figure 6 The electronic tag chip U1 takes the PN532 chip as an example. The reason for selecting the PN532 chip is that it has the following advantages:

[0114] 1) Performance: Since there are large-scale electronic devices in the power system, the reading speed is the core index of the NFC control chip. The PN532 chip adopted in the embodiment can reach a maximum communication rate of 424 kbit / s under the support of the ISO1443B protocol, which is much higher than the commonly used NFC chips on the market, such as ST ST25R3916, TI RF430FRL152H and NXP PN65T, etc. The PN532 chip can greatly shorten the time for the reader to read the electronic tag on the power equipment and save the time cost. Moreover, the PN532 chip has superior stability, reliability and energy saving, and is very suitable for electronic tags on electronic devices which need to work stably for a long time and do not need to replace the battery frequently.

[0115] 2) Compatibility: The PN532 chip adopted in the embodiment supports multiple standards including ISO14443A / B(Type2 / Type 4), ISO15693, FeliCa and NFC Forum Type1 to Type 4 tags, covering more than 90% of the scenarios. In addition, the PN532 chip also has a wide frequency adaptation capability and can work stably in different frequency ranges.

[0116] 3) Security and privacy: PN532 chip has built-in AES-128 encryption algorithm, which is easy to implement and develop, and can be widely used in new power system construction. PN532 chip supports data encryption transmission and supports multiple identity verification mechanisms, which can effectively prevent unauthorized access and protect user privacy and data security. It is very suitable for power equipment with high security requirements and can ensure that the electronic tag on it cannot be read by a stranger reader, causing loss of the power system.

[0117] 4) Interface flexibility: PN532 chip supports SPI, I2C, UART and other interfaces, which can easily adapt to mainstream master chips such as Arduino, Raspberry Pi, STM32, etc. In addition, PN532 chip provides diversified interface options, so it can be easily integrated into the electronic tag required by the power system and will not be limited by the device.

[0118] The antenna can be a square patch antenna.

[0119] Referring to Figure 7 , Figure 7 A square patch antenna provided by the embodiment of the present application is shown in the figure. The square patch antenna can use a small-volume square patch antenna, which includes a radiation patch 1, a dielectric layer 2, and a ground layer 3. Through the application of microstrip line technology and high-frequency materials, the square small-volume patch antenna can achieve high-efficiency communication performance.

[0120] The above design has the following advantages: the square antenna can provide good gain and directivity in limited space, which can meet the demand of high-speed data transmission required by the electronic tag on the power equipment for real-time monitoring and fast response; secondly, the small-volume patch antenna has strong flexibility, and the small occupied volume makes the electronic tag proposed in the embodiment applicable to most power equipment.

[0121] In some embodiments, the peripheral circuit can include a power supply circuit, a reset circuit, a crystal oscillator circuit, and a communication interface circuit.

[0122] The power supply circuit supplies working voltage to the electronic tag chip through the VCC and GND pins.

[0123] In a specific embodiment, the power supply circuit can supply 3.3v working voltage to the chip through the VCC and GND pins, wherein the 110nF decoupling capacitor C3 is used to filter out power supply noise, smooth voltage fluctuations, effectively suppress power supply ripple, and reduce electromagnetic interference, which can ensure the stability of the power supply voltage.

[0124] In an embodiment, one end of the reset circuit is connected to a preset pin of the electronic tag chip, and the other end is connected to a preset voltage source. The reset circuit can include a diode D1, a resistor R1, and a capacitor C1, wherein the negative electrode of the diode D1 is connected to the preset pin of the electronic tag chip, one end of the resistor R1 is connected to the positive electrode of the diode D1, the other end of the resistor R1 is connected to the preset voltage source, one end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the capacitor C1 is connected to the other end of the resistor R1.

[0125] Specifically, as shown in Figure 6 , the reset circuit adopts a power-on reset circuit composed of a diode D1, a 1k-ohm resistor R1 (it should be noted that the resistance value units of the resistors involved in Figure 1 are ohms), and a 10-microfarad capacitor C1. During the charging and discharging of the capacitor, the RC delay circuit generates a reset pulse, controls the speed of the current flowing through the capacitor through the resistor, and thus controls the speed of voltage change. This can effectively eliminate power supply noise and transient interference, ensure that the microcontroller starts working only after the power voltage is stable, and avoid abnormal start caused by voltage fluctuations.

[0126] In an embodiment, the diode D1 can be a light-emitting diode LED1 to constitute an LED indicator circuit. The LED is connected to the I / O pin of the microcontroller through a current-limiting resistor, and can be controlled by the program to be turned on or off. The LED indicator circuit can directly show the user the system running state or be used as a debugging tool. The LED indicator circuit can directly show the user the running state of the device through the lamp language design.

[0127] In an embodiment, the first end and the second end of the crystal oscillator circuit are connected to preset pins of the electronic tag chip, and the third end of the crystal oscillator circuit is grounded. The crystal oscillator circuit can include a crystal oscillator X1, a capacitor C14, and a capacitor C15. The two ends of the crystal oscillator X1 are respectively connected to different preset pins of the electronic tag chip. One end of the capacitor C14 is connected to one end of the crystal oscillator X1, the other end of the capacitor C14 is grounded, one end of the capacitor C15 is connected to the other end of the crystal oscillator X1, and the other end of the capacitor C15 is connected to the other end of the capacitor C14.

[0128] In a specific implementation, the crystal oscillator circuit can adopt a Pierce oscillation circuit, wherein the input pin of the electronic tag chip is connected to one end of the crystal oscillator X1, the output pin is connected to the other end of the crystal oscillator X1, and the crystal oscillator X1 is respectively connected in parallel with the first capacitor and the second capacitor to form a π-type network structure.

[0129] Specifically, as shown in Figure 6 , the crystal oscillator circuit adopted is composed of a 27.12MHZ crystal oscillator and two 22-picofarad capacitors C 14 , C15 OSCIN pin is connected to one end of X1, receives signals from the crystal oscillator, and forms an oscillation feedback path through the internal inverting amplifier; the OSCOUT pin is connected to the other end of the crystal oscillator, and feeds back the output signal of the internal inverting amplifier to the crystal oscillator, together constituting a Pierce oscillator, which ensures that the system can obtain a high-precision, low-drift clock signal, and guarantees the timing synchronization and stable operation of the microcontroller kernel, peripheral modules and communication modules.

[0130] In some embodiments, the communication interface circuit described above includes resistors R3, R4, R5, R6, R7, R9, capacitors C4, C5, C6, C7, C8, C9, C12, C13, inductors L1, L2 and a pin connector.

[0131] One end of the inductor L1 is connected to a preset pin of the electronic tag chip, one end of the capacitor C6 is connected to the other end of the inductor L1, the other end of the capacitor C6 is grounded, one end of the capacitor C4 is connected to one end of the capacitor C6, one end of the capacitor C5 is connected to the other end of the capacitor C4, the other end of the capacitor C5 is connected to the other end of the capacitor C6, one end of the resistor R4 is connected to one end of the capacitor C5, the other end of the resistor R4 is connected to the other end of the capacitor C5, one end of the resistor R3 is connected to one end of the resistor R4, the first end of the pin connector is connected to the other end of the resistor R3, the second end of the pin connector is connected to the other end of the resistor R4, one end of the capacitor C6 is connected to the third end of the pin connector, one end of the resistor R5 is connected to the other end of the capacitor C6, the other end of the resistor R5 is connected to the second end of the pin connector, one end of the capacitor C7 is connected to one end of the resistor R5, the other end of the capacitor C7 is connected to the second end of the pin connector, one end of the capacitor C9 is connected to one end of the capacitor C7, one end of the capacitor C8 is connected to the other end of the capacitor C9, the other end of the capacitor C8 is connected to the other end of the capacitor C6, one end of the inductor L2 is connected to one end of the capacitor C8, the other end of the inductor L2 is connected to the preset pin of the electronic tag chip, one end of the resistor R7 is connected to one end of the capacitor C8, one end of the capacitor C12 is connected to the other end of the resistor R7, one end of the resistor R9 is connected to the other end of the capacitor C12, the other end of the resistor R9 is connected to the preset pin of the electronic tag chip, one end of the capacitor C13 is connected to one end of the resistor R9, the other end of the resistor R9 and the preset pin of the electronic tag chip respectively, the other end of the capacitor C13 is grounded.

[0132] The filter circuit is composed of C4-C9, R2, R3 and inductor L, which is used to realize impedance matching, ensure signal integrity and suppress noise and interference, thereby improving the data precision of ADC sampling.

[0133] Figure 6 The part marked as ANT is a pin connector for connecting an antenna, which accesses the circuit through the pin connector.

[0134] In a specific embodiment, the communication interface circuit is composed of a UART (Universal Asynchronous Receiver-Transmitter) interface and two 560 nanohenry inductors, the TX (transmit) and RX (receive) pins of the UART interface are used for serial data transmission, L1 and L2 act as common-mode chokes, which suppress common-mode noise through high impedance while maintaining the integrity of differential-mode signals, reducing the impact of electromagnetic interference on communication.

[0135] wherein, Figure 6 The part marked as Header in the figure also refers to a pin connector, which is used for electrical connection of other modules or external devices, for debugging and functional expansion.

[0136] In some embodiments, the above-mentioned peripheral circuit can further include a capacitor C3, two ends of the capacitor C3 are connected to different preset pins of the electronic tag chip, respectively.

[0137] In some embodiments, the above-mentioned peripheral circuit can further include a capacitor C2 and a resistor R2, one end of the resistor R2 is connected to a preset pin of the electronic tag chip, one end of the capacitor C2 is connected to the other end of the resistor R2, and the other end of the capacitor C2 is grounded.

[0138] In some embodiments, the above-mentioned peripheral circuit can further include a patch button KEY1, one end of the patch button KEY1 is connected to a preset pin of the electronic tag chip and a cathode of a diode D1, and the other end is grounded.

[0139] In some embodiments, the above-mentioned peripheral circuit can further include a key input circuit, which is realized by an 8-bit key matrix and its peripheral circuit. The 8-bit key matrix is connected to the corresponding pin, supports users to input instructions or control functions through keys, and each key can correspond to different functions, greatly enhancing the flexibility of the system and user experience.

[0140] In Figure 6 R3=33kΩ, R6=33kΩ, R4=10kΩ, R5=10kΩ, C5=56pF, C7=56pF, C4=16pF, C9=18pF, C6=220pF, C8=220pF, R7=2.7kΩ, R9=1kΩ, C 12 =100nF, C 13 =100nF, L1=560nH, L2=560nH, C3=100nF, C2=100nF, R2=10kΩ, C 14 =22pF, C 15= 22 pF, Y1 = 27.12 M, R1 = 1 kΩ, C1 = 100 μF are examples.

[0141] The scheme of the embodiment provides a near field communication system, including the electronic tag and the NFC reader described above, at the hardware design level, the electronic tag takes the PN532 chip as the core, and high-precision timing control is realized through the improved E-C monostable circuit. The circuit structure between the antenna and the chip can effectively reduce signal reflection, signal loss and distortion in the transmission process through this design, ensure the signal transmission efficiency and signal integrity between the antenna and the chip, in addition, the impedance matching network can also play a filtering role, suppress external noise and interference, improve the anti-interference ability of the system, through the design of the reader tag demodulation circuit, pulse shaping circuit and symbol detector, the accurate decoding and interval measurement of the OOK modulated signal are realized, and stable communication under the fluctuation of the radio frequency field intensity is ensured.

[0142] The embodiment of the application further provides an electronic device, the electronic device includes the reader described above.

[0143] In all examples shown and described above, any specific values should be interpreted as merely exemplary and not as a limitation, and thus other examples of the example embodiments can have different values.

[0144] It should be noted that: similar labels and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0145] The above-described embodiments only express several implementation manners of the application, the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the application. It should be pointed out that, for ordinary skilled in the art, without departing from the concept of the application, several modifications and improvements can be made, which all belong to the protection scope of the application.

[0146] The above is only a specific embodiment of the application, but the protection scope of the application is not limited to this, any skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered in the protection scope of the application.

Claims

1. A reader / writer characterized by comprising: The demodulation circuit comprises: a demodulation circuit for extracting an envelope signal of a radio frequency signal emitted by an electronic tag, the envelope signal comprising original data information of the electronic tag; a pulse shaping circuit connected with the demodulation circuit, and the pulse shaping circuit is used for outputting an end modulation pulse signal or a start modulation pulse signal based on the envelope signal output by the demodulation circuit; a counter connected with the demodulation circuit, and the counter is used for counting in response to a change in amplitude of the envelope signal output by the demodulation circuit; a symbol detection circuit connected with the counter and the pulse shaping circuit, and the symbol detection circuit is used for controlling the counter to be zeroed and start counting in response to the start modulation pulse signal; controlling the counter to stop counting in response to the end modulation pulse signal; and based on a count value of the counter, symbol detection and demodulation are performed to obtain the original data information.

2. The reader / writer of claim 1, wherein, The demodulation circuit comprises a low-pass filter circuit connected with the pulse shaping circuit and the counter.

3. The reader / writer of claim 2, wherein, The low-pass filter circuit comprises: a first resistor, one end of the first resistor inputting the radio frequency signal; a first transistor, a gate of the first transistor connected with the other end of the first resistor; a second resistor, one end of the second resistor connected with a source of the first transistor, and the other end grounded; a second transistor, a gate of the second transistor connected with the source of the first transistor, a source of the second transistor grounded, and a drain of the second transistor connected with the pulse shaping circuit and the counter; a third resistor, one end of the third resistor connected with a drain of the first transistor, and the other end connected with a drain of the second transistor.

4. The read-write device of claim 3, wherein, The demodulation circuit further comprises: a third transistor, a gate of the third transistor connected with the low-pass filter circuit, and a source of the third transistor grounded; a high-pass filter circuit, a first end of the high-pass filter circuit connected with the drain of the first transistor, a second end of the high-pass filter circuit connected with a drain of the third transistor, and a third end of the high-pass filter circuit connected with the pulse shaping circuit and the counter.

5. The read-write device of claim 4, wherein, The high-pass filter circuit comprises: a fourth resistor, one end of the fourth resistor connected with the drain of the first transistor, and the other end connected with the drain of the third transistor; a first capacitor, one end of the first capacitor connected with the other end of the fourth resistor, and the other end connected with the pulse shaping circuit and the counter; a fifth resistor, one end of the fifth resistor connected with the other end of the first capacitor, and the other end grounded.

6. The read-write device of claim 5, wherein, The demodulation circuit further comprises: a fourth transistor, a drain of the fourth transistor connected with the other end of the first capacitor, and a source and a gate of the fourth transistor grounded.

7. The reader / writer of claim 1, wherein, The pulse shaping circuit comprises: a fifth transistor, a gate of the fifth transistor connected with the demodulation circuit, and a source of the fifth transistor grounded; a sixth transistor, a drain of the sixth transistor connected with a drain of the fifth transistor, and a source of the sixth transistor connected with a source of the fifth transistor; a sixth resistor, one end of the sixth resistor is connected with the drain of the fifth transistor; a power supply circuit, the power supply circuit is used for supplying power for the fifth transistor and the sixth transistor, a first end of the power supply circuit is connected with the other end of the sixth resistor, and a second end of the power supply circuit is grounded; a time constant circuit, the time constant circuit is used for determining the pulse width generated by the pulse shaping circuit, a first end of the time constant circuit is connected with the drain of the fifth transistor, and a second end of the time constant circuit is connected with a third end of the power supply circuit; a seventh transistor, a gate of the seventh transistor is connected with the third end of the time constant circuit, a source of the seventh transistor is connected with a source of the sixth transistor, and a drain of the seventh transistor is connected with the second end of the time constant circuit; a push-pull circuit, the push-pull circuit is used for buffering the signal output by the seventh transistor, a first end of the push-pull circuit is connected with the drain of the seventh transistor, a second end of the push-pull circuit is connected with the source of the seventh transistor, a third end of the push-pull circuit is connected with the drain of the seventh transistor, a fourth end of the push-pull circuit is connected with the gate of the sixth transistor, and a fifth end of the push-pull circuit is connected with the sign detection circuit.

8. The reader / writer of claim 1, wherein, the power supply circuit comprises: a second capacitor, one end of the second capacitor is connected with the other end of the sixth resistor, and the other end of the second capacitor is grounded; an eighth transistor, a source of the eighth transistor is connected with one end of the second capacitor, and a drain of the eighth transistor is connected with the second end of the time constant circuit.

9. The read-write device of claim 8, wherein, the time constant circuit comprises: a third capacitor, one end of the third capacitor is connected with the drain of the fifth transistor, and the other end of the third capacitor is connected with the gate of the seventh transistor; a seventh resistor, one end of the seventh resistor is connected with the other end of the third capacitor, and the other end of the seventh resistor is connected with the drain of the eighth transistor and the drain of the seventh transistor.

10. The read-write device of claim 9, wherein, the push-pull circuit comprises: a ninth transistor, a gate of the ninth transistor is connected with the drain of the seventh transistor, a source of the ninth transistor is connected with the source of the seventh transistor, and a drain of the ninth transistor is connected with the drain of the seventh transistor; a tenth transistor, a source of the tenth transistor is connected with the source of the ninth transistor, a gate of the tenth transistor is connected with the drain of the ninth transistor, and a drain of the tenth transistor is connected with the sign detection circuit; an eleventh transistor, a gate of the eleventh transistor is connected with the gate of the sixth transistor, a source of the eleventh transistor is connected with the drain of the tenth transistor, and a drain of the eleventh transistor is connected with the drain of the ninth transistor.

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