Controller with duty ratio calculation function and duty ratio identification method thereof

Abstract

The invention discloses a controller with a duty ratio calculation function and a duty ratio calculation method thereof. The controller comprises a first capture pin, a second capture pin, a timing module and a processing module. The first capture pin receives a pulse width modulation signal in a rising edge trigger mode. The second capture pin receives a pulse width modulation signal in a falling edge trigger mode. The timing module executes a counting program, and detects a first count value of a rising edge of the pulse width modulation signal captured by the first capture pin for the first time, a second count value of a falling edge of the pulse width modulation signal captured by the second capture pin, and a third count value of the rising edge of the pulse width modulation signal captured by the first capture pin for the second time. The processing module calculates the duty ratio of the pulse width modulation signal according to the first count value, the second count value and the third count value.

Description

TECHNICAL FIELD

[0001] The present application relates to a controller, in particular, a controller with a duty cycle calculation function. The present application also relates to a duty cycle calculation method of the controller. BACKGROUND

[0002] Lighting devices with adjustable brightness and color temperature have been widely used in various buildings due to their convenience. The brightness and color temperature of the lighting devices are mainly controlled by a pulse width modulation (PWM) signal. A user can adjust the brightness and color temperature of the lighting devices by adjusting the duty cycle of the PWM signal.

[0003] However, the microcontroller of the existing lighting device has poor performance, and the interrupt processing time of the duty cycle measurement mechanism thereof is long. Therefore, the existing lighting device cannot detect the waveform of the PWM signal with a low duty cycle. As a result, the error of the duty cycle detection mechanism of the existing lighting device is large, and the anti-interference ability thereof is poor. If a high-performance microcontroller is used, the cost and power consumption of the lighting device will be greatly increased. SUMMARY

[0004] According to an embodiment of the present application, a controller with a duty cycle calculation function is provided. The controller includes a first capture pin, a second capture pin, a timing module, and a processing module. The first capture pin receives a pulse width modulation (PWM) signal in a rising edge trigger mode. The second capture pin receives the PWM signal in a falling edge trigger mode. The timing module performs a counting procedure and detects a first count value of a first rising edge of the PWM signal captured by the first capture pin, a second count value of a falling edge of the PWM signal captured by the second capture pin, and a third count value of a second rising edge of the PWM signal captured by the first capture pin. The processing module calculates a duty cycle of the PWM signal according to the first count value, the second count value, and the third count value.

[0005] In an embodiment, the timing module operates in a continuous counting mode.

[0006] In an embodiment, when no overflow occurs in the counting mode, the processing module subtracts the first count value from the third count value to obtain a period of the PWM signal, subtracts the first count value from the second count value to obtain a high time of the PWM signal, and calculates the duty cycle of the PWM signal according to a ratio of the high time to the period.

[0007] In an embodiment, when an overflow occurs in the counting mode, the processing module subtracts the first count value from a product of an overflow value and an overflow number to obtain a difference, subtracts the difference from the third count value to obtain the period of the PWM signal, subtracts the difference from the second count value to obtain the high time of the PWM signal, and calculates the duty cycle of the PWM signal according to a ratio of the high time to the period.

[0008] In one embodiment, the timing module is a timer.

[0009] According to another embodiment of the present application, a duty cycle calculation method is also provided, which comprises the following steps: receiving a pulse width modulation signal by a first capture pin in a rising edge trigger mode; receiving the pulse width modulation signal by a second capture pin in a falling edge trigger mode; performing a counting procedure by a timing module and detecting a first count value of a first rising edge of the pulse width modulation signal captured by the first capture pin, a second count value of a falling edge of the pulse width modulation signal captured by the second capture pin, and a third count value of a second rising edge of the pulse width modulation signal captured by the first capture pin; and calculating a duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value by a processing module.

[0010] In one embodiment, the timing module operates in a continuous counting mode.

[0011] In one embodiment, the step of calculating the duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value by the processing module further comprises: subtracting the first count value from the third count value to obtain a period of the pulse width modulation signal by the processing module when the counting mode does not overflow; subtracting the first count value from the second count value to obtain a high time of the pulse width modulation signal by the processing module; and calculating the duty cycle of the pulse width modulation signal according to a ratio of the high time to the period by the processing module.

[0012] In one embodiment, the step of calculating the duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value by the processing module further comprises: subtracting the first count value from a product of an overflow value and an overflow times to obtain a difference value by the processing module when the counting mode overflows; subtracting the difference value from the third count value to obtain a period of the pulse width modulation signal by the processing module; subtracting the difference value from the second count value to obtain a high time of the pulse width modulation signal by the processing module; and calculating the duty cycle of the pulse width modulation signal according to a ratio of the high time to the period by the processing module.

[0013] In one embodiment, the timing module is a timer.

[0014] According to the above, the controller with a duty cycle calculation function and the duty cycle calculation method thereof according to the embodiments of the present application can have one or more of the following advantages:

[0015] (1) In an embodiment of the present application, the controller includes a first capture pin, a second capture pin, a timing module and a processing module. The first capture pin receives the PWM signal in a rising edge trigger mode. The second capture pin receives the PWM signal in a falling edge trigger mode. The timing module performs a counting procedure and detects a first count value of a first rising edge of the PWM signal captured by the first capture pin, a second count value of a falling edge of the PWM signal captured by the second capture pin and a third count value of a second rising edge of the PWM signal captured by the first capture pin. The processing module calculates the duty cycle of the PWM signal according to the first count value, the second count value and the third count value. As described above, the controller can obtain the count values of the rising edges of two PWM signals and the count value of the falling edge of one PWM signal through the first capture pin in the rising edge trigger mode and the second capture pin in the falling edge trigger mode, and calculate the duty cycle of the PWM signal according to the count values. The signal capture mechanism described above can accurately calculate the duty cycle of the PWM signal without being affected by the interrupt processing time, so that the signal capture mechanism can detect the PWM signal with extremely low duty cycle. In this way, the controller can meet the requirements of different applications.

[0016] (2) In an embodiment of the present application, the controller has a special signal capture mechanism which can accurately calculate the duty cycle of the PWM signal without being affected by the interrupt processing time, so that the signal capture mechanism can detect the PWM signal with extremely low duty cycle. In this way, the lighting device using the controller can accurately calculate the duty cycle of the PWM signal, and does not need to use a high-performance microcontroller, so that the lighting device can correctly perform the brightness adjustment function and the color temperature adjustment function. Therefore, the cost and power consumption of the lighting device can be reduced, and the lighting device still has accurate brightness adjustment function and color temperature adjustment function.

[0017] (3) In an embodiment of the present application, the processing module subtracts the first count value from the third count value to obtain the period of the PWM signal when the counting mode does not overflow, subtracts the first count value from the second count value to obtain the high level time of the PWM signal, and calculates the duty cycle of the PWM signal according to the ratio of the high level time to the period. When the counting mode overflows, the processing module subtracts the first count value from the product of the overflow value and the overflow times to obtain a difference value, subtracts the difference value from the third count value to obtain the period of the PWM signal, and subtracts the difference value from the second count value to obtain the high level time of the PWM signal, and calculates the duty cycle of the PWM signal according to the ratio of the high level time to the period. Through the duty cycle calculator described above, the processing module can accurately calculate the duty cycle of the PWM signal when the counting mode overflows or does not overflow. Therefore, the controller can meet the requirements of actual applications.

[0018] (4) In an embodiment of the present application, the controller integrates a special signal capture mechanism and a duty cycle calculator, so that it can detect a pulse width modulation signal with extremely low duty cycle and accurately calculate the duty cycle of the pulse width modulation signal. Therefore, the controller can be applied to various different lighting devices, and can actually implement various different intelligent functions. Therefore, the controller can meet the future development trend.

[0019] (5) In an embodiment of the present application, the controller is simple in design, so that the desired functions can be achieved without significantly increasing the cost. Therefore, the controller not only has high practicality, but also can meet the needs of different applications. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A block diagram of the circuit structure of the controller with duty cycle calculation function in an embodiment of the present application.

[0021] Figure 2 A schematic diagram of the operation state of the controller with duty cycle calculation function in an embodiment of the present application.

[0022] Figure 3 A first schematic diagram of the duty cycle calculator of the controller with duty cycle calculation function in an embodiment of the present application.

[0023] Figure 4 A second schematic diagram of the duty cycle calculator of the controller with duty cycle calculation function in an embodiment of the present application.

[0024] Figure 5 A third schematic diagram of the duty cycle calculator of the controller with duty cycle calculation function in an embodiment of the present application.

[0025] Figure 6 A flowchart of the duty cycle calculation method in another embodiment of the present application.

[0026] Figure 7 A flowchart of the duty cycle calculation method in another embodiment of the present application.

[0027] REFERENCE SIGNS:

[0028] 1 - controller; 11 - processing module; 12 - timing module; P1 - first capture pin; P2 - second capture pin; Ms - pulse width modulation signal; T1 - first count value; T2 - second count value; T3 - third count value; N - overflow number; S60-S63, S71-S78 - step flow.

[0029] The present application will become fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration and are not intended to limit the present application. DETAILED DESCRIPTION

[0030] Embodiments of a controller with duty cycle calculation function and a duty cycle calculation method thereof according to the present application will be described below with reference to the drawings. For the purpose of clarity and convenience, the components in the drawings can be exaggerated or reduced in size and proportion. In the following description and / or claims, when referring to a component being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component or intervening components can be present. When referring to a component being "directly connected" or "directly coupled" to another component, no intervening components are present for describing the relationship between the components or layers. For the purpose of convenience, the same components in the following embodiments are denoted by the same reference numerals.

[0031] Referring to Figure 1 which is a block diagram of a circuit structure of a controller with duty cycle calculation function according to an embodiment of the present application. As shown in the figure, the controller 1 includes a first capture pin P1, a second capture pin P2, a timing module 12 and a processing module 11. In this embodiment, the controller 1 is a microcontroller (MCU). In another embodiment, the processing module 11 can be an application specific integrated circuit chip (ASIC), a field programmable gate array (FPGA) or other similar components.

[0032] The first capture pin P1 and the second capture pin P2 are connected to the timing module 12. In an embodiment, the first capture pin P1 can be TIMx_CH1 or other pins with similar functions; the second capture pin P2 can be TIMx_CH2 or other pins with similar functions. In an embodiment, the timing module 12 can be a timer (e.g. a 16-bit timer or a timer with other different counting lengths).

[0033] The processing module 11 is connected to the timing module 12. In an embodiment, the processing module 11 can be a processing unit (CPU) in a microcontroller.

[0034] Of course, this embodiment is only used for illustration and is not intended to limit the scope of the present application. Equivalent modifications or changes to the controller 1 with duty cycle calculation function according to this embodiment should still be included in the patent scope of the present application.

[0035] Referring to Figure 2Fig. 2 is a schematic diagram of the operation state of the controller with duty cycle calculation function according to an embodiment of the present application. As shown in the figure, the first capture pin P1 receives the pulse width modulation signal Ms in the rising edge trigger mode. The second capture pin P2 receives the pulse width modulation signal Ms in the falling edge trigger mode.

[0036] Then, the timing module 12 operates in the continuous counting mode and executes the counting procedure. In the counting procedure, the timing module 12 detects the first counting value of the rising edge of the pulse width modulation signal Ms captured by the first capture pin P1 for the first time, the second counting value of the falling edge of the pulse width modulation signal Ms captured by the second capture pin P2, and the third counting value of the rising edge of the pulse width modulation signal Ms captured by the first capture pin P1 for the second time. Each capture channel of the timing module 12 has a capture register. The timing module 12 stores the first counting value, the second counting value, and the third counting value into the corresponding capture registers. The first counting value, the second counting value, and the third counting value trigger the interrupt procedure when they are obtained, so that the data can be processed as necessary.

[0037] Next, the calculation procedure is triggered, and the processing module 11 obtains the first counting value, the second counting value, and the third counting value by reading the above-mentioned capture registers, and calculates the duty cycle of the pulse width modulation signal Ms according to the first counting value, the second counting value, and the third counting value.

[0038] Through the above-mentioned mechanism, the controller 1 can detect the pulse width modulation signal Ms with a duty cycle of 0.1% or less, and the error is less than ±0.02%, which greatly improves the accuracy.

[0039] As described above, in the present embodiment, the controller 1 can obtain the counting value of the rising edge of two pulse width modulation signals Ms and the counting value of the falling edge of one pulse width modulation signal Ms through the first capture pin P1 in the rising edge trigger mode and the second capture pin P2 in the falling edge trigger mode, and calculate the duty cycle of the pulse width modulation signal Ms according to the counting values. The above-mentioned signal capture mechanism can accurately calculate the duty cycle of the pulse width modulation signal Ms without being affected by the interrupt processing time, so that the signal capture mechanism can detect the pulse width modulation signal Ms with an extremely low duty cycle. In this way, the controller 1 can meet the requirements of different applications.

[0040] In addition, in the present embodiment, the controller 1 has a special signal capture mechanism that can accurately calculate the duty cycle of the pulse width modulation signal Ms without being affected by the interrupt processing time, so that the signal capture mechanism can detect the pulse width modulation signal Ms with an extremely low duty cycle. In this way, the lighting device using the controller 1 can accurately calculate the duty cycle of the pulse width modulation signal Ms, without using a high-performance microcontroller, so that the lighting device can correctly perform the brightness adjustment function and the color temperature adjustment function. Therefore, the cost and power consumption of the lighting device can be reduced, and the lighting device still has accurate brightness adjustment function and color temperature adjustment function.

[0041] Of course, the present embodiment is only used for illustration and not limit the scope of the present application, and equivalent modifications or changes made according to the controller 1 with duty cycle calculation function of the present embodiment should still be included in the patent scope of the present application.

[0042] Please refer to Figure 3 , which is a first schematic diagram of the duty cycle calculator of the controller with duty cycle calculation function of an embodiment of the present application. As shown in the figure, the timing module 12 detects the first count value T1 of the first capture pin P1 capturing the rising edge of the pulse width modulation signal Ms for the first time, the second count value T2 of the second capture pin P2 capturing the falling edge of the pulse width modulation signal Ms, and the third count value T3 of the first capture pin P1 capturing the rising edge of the pulse width modulation signal Ms for the second time.

[0043] Then, the calculation program is triggered, and the processing module 11 calculates the duty cycle of the pulse width modulation signal Ms according to the first count value, the second count value and the third count value. Since the count mode does not overflow, the processing module 11 subtracts the first count value T2 from the third count value T3 to obtain the period of the pulse width modulation signal Ms, as shown in the following formula (1):

[0044] Pd = T3 - T1 …………………… (1)

[0045] Where Pd represents the period of the pulse width modulation signal Ms.

[0046] Then, the processing module 11 subtracts the first count value T1 from the second count value T2 to obtain the high level time of the pulse width modulation signal Ms, as shown in the following formula (2):

[0047] Ht = T2 - T1 …………………… (2)

[0048] Where Ht represents the high level time of the pulse width modulation signal Ms.

[0049] Then, the processing module 11 can calculate the duty cycle of the pulse width modulation signal Ms according to the ratio of the high level time to the period, as shown in the following formula (3):

[0050] Cy = (Ht / Pd) x 100% (3)

[0051] wherein Ht represents the duty cycle of the pulse width modulation signal Ms.

[0052] Of course, the present embodiment is only for illustration and not for limiting the scope of the present application, and equivalent modifications or changes made to the controller 1 with the duty cycle calculation function according to the present embodiment should still be included in the patent scope of the present application.

[0053] Referring to Figure 4 , which is a second schematic diagram of the duty cycle calculator of the controller with the duty cycle calculation function according to an embodiment of the present application. As shown in the figure, the timing module 12 detects a first count value T1 of the first capture pin P1 capturing the rising edge of the pulse width modulation signal Ms for the first time, a second count value T2 of the second capture pin P2 capturing the falling edge of the pulse width modulation signal Ms, and a third count value T3 of the first capture pin P1 capturing the rising edge of the pulse width modulation signal Ms for the second time.

[0054] Then, the calculation program is triggered, and the processing module 11 calculates the duty cycle of the pulse width modulation signal Ms according to the first count value, the second count value, and the third count value. Since the count mode has overflowed, the processing module 11 will subtract the product of the overflow value and the overflow times from the first count value to obtain a difference value, and subtract the difference value from the third count value to obtain the period of the pulse width modulation signal, as shown in the following formula (4):

[0055] Pd = T3 - (K x N - T1) (4)

[0056] wherein K represents the overflow value; N represents the overflow times (as can be seen from the figure, the overflow times are 1). In the present embodiment, the timing module 12 is a 16-bit timer, and the overflow value is equal to the maximum value of the timing module 12 (65535); the overflow value can be adjusted according to actual needs, and is not limited thereto.

[0057] Then, the processing module 11 subtracts the difference value from the second count value T2 to obtain the high level time of the pulse width modulation signal Ms, as shown in the following formula (5):

[0058] Ht = T2 - (K x N - T1) (5)

[0059] Then, the processing module 11 can calculate the duty cycle of the pulse width modulation signal Ms according to the ratio of the high level time to the period, as shown in the above formula (3).

[0060] As mentioned above, the controller 1 integrates a special signal capture mechanism and a duty cycle calculator mechanism, so that it can detect a PWM signal Ms with a very low duty cycle and accurately calculate the duty cycle of the PWM signal Ms. The controller 1 can detect a PWM signal Ms with a duty cycle of 0.1% or less, and the error is less than ±0.02%, which greatly improves the accuracy.

[0061] Of course, the present embodiment is only used for illustration and not limit the scope of the present application, equivalent modifications or changes made according to the controller 1 with a duty cycle calculation function of the present embodiment should still be included in the patent scope of the present application.

[0062] Please refer to Figure 5 , which is a third schematic diagram of the duty cycle calculator mechanism of the controller with a duty cycle calculation function of an embodiment of the present application. As shown in the figure, the overflow number of the counting mode is 2. Therefore, the processing module 11 can still calculate the duty cycle of the PWM signal Ms according to formula (4), formula (5) and formula (3).

[0063] As mentioned above, through the above-mentioned duty cycle calculator mechanism, the processing module 11 can accurately calculate the duty cycle of the PWM signal Ms when the counting mode overflows or does not overflow. Therefore, the controller 1 can meet the needs of practical applications.

[0064] In addition, in the present embodiment, the controller 1 integrates a special signal capture mechanism and a duty cycle calculator mechanism, so that it can detect a PWM signal Ms with a very low duty cycle and accurately calculate the duty cycle of the PWM signal Ms. Therefore, the controller 1 can be applied to various different lighting devices, and can actually have various different intelligent functions. Therefore, the controller 1 can meet the trend of future development.

[0065] Of course, the present embodiment is only used for illustration and not limit the scope of the present application, equivalent modifications or changes made according to the controller 1 with a duty cycle calculation function of the present embodiment should still be included in the patent scope of the present application.

[0066] It is worth mentioning that the microcontroller of the existing lighting device cannot detect the waveform of the pulse width modulation signal with low duty cycle because of its poor performance and long interruption processing time of the duty cycle measurement mechanism. Therefore, the error of the duty cycle detection mechanism of the existing lighting device is large, and the anti-interference ability is poor. If a high-performance microcontroller is used, the cost of the lighting device will be greatly increased, and the power consumption of the lighting device will be increased. According to the embodiments of the present application, the controller includes a first capture pin, a second capture pin, a timing module and a processing module. The first capture pin receives the pulse width modulation signal in the rising edge trigger mode. The second capture pin receives the pulse width modulation signal in the falling edge trigger mode. The timing module executes a counting program and detects a first count value of the first capture pin capturing the rising edge of the pulse width modulation signal for the first time, a second count value of the second capture pin capturing the falling edge of the pulse width modulation signal, and a third count value of the first capture pin capturing the rising edge of the pulse width modulation signal for the second time. The processing module calculates the duty cycle of the pulse width modulation signal according to the first count value, the second count value and the third count value. As can be seen from the above, the controller can obtain the count values of the rising edges of two pulse width modulation signals and the count value of the falling edge of one pulse width modulation signal through the first capture pin in the rising edge trigger mode and the second capture pin in the falling edge trigger mode, and calculate the duty cycle of the pulse width modulation signal according to these count values. The above signal capture mechanism can accurately calculate the duty cycle of the pulse width modulation signal without being affected by the interruption processing time, so that this signal capture mechanism can detect the pulse width modulation signal with extremely low duty cycle. In this way, the controller can meet the needs of different applications.

[0067] In addition, according to the embodiments of the present application, the controller has a special signal capture mechanism that can accurately calculate the duty cycle of the pulse width modulation signal without being affected by the interruption processing time, so that this signal capture mechanism can detect the pulse width modulation signal with extremely low duty cycle. In this way, the lighting device using this controller can accurately calculate the duty cycle of the pulse width modulation signal, without using a high-performance microcontroller, so that the lighting device can correctly perform the brightness adjustment function and the color temperature adjustment function. Therefore, the cost and power consumption of the lighting device can be reduced, and the lighting device still has accurate brightness adjustment function and color temperature adjustment function.

[0068] In addition, according to the embodiments of the present application, the processing module subtracts the first count value from the third count value to obtain a period of the pulse width modulation signal when the count mode does not overflow, and subtracts the first count value from the second count value to obtain a high level time of the pulse width modulation signal, and then calculates a duty cycle of the pulse width modulation signal according to a ratio of the high level time to the period. The processing module subtracts the first count value from a product of the overflow value and the overflow times to obtain a difference value when the count mode overflows, and subtracts the difference value from the third count value to obtain a period of the pulse width modulation signal, and subtracts the difference value from the second count value to obtain a high level time of the pulse width modulation signal, and then calculates a duty cycle of the pulse width modulation signal according to a ratio of the high level time to the period. Through the above-mentioned duty cycle calculation method, the processing module can accurately calculate the duty cycle of the pulse width modulation signal when the count mode overflows or does not overflow. Therefore, the controller can meet the requirements of practical applications.

[0069] In addition, according to the embodiments of the present application, the controller integrates a special signal capture mechanism and a duty cycle calculation method, so that it can detect a pulse width modulation signal with an extremely low duty cycle and accurately calculate the duty cycle of the pulse width modulation signal. Therefore, the controller can be applied to various different lighting devices and can actually have various different intelligent functions. Therefore, the controller can meet the trend of future development.

[0070] Furthermore, according to the embodiments of the present application, the controller is simple in design, so that the desired effects can be achieved without significantly increasing the cost. Therefore, the controller not only has high practicality, but also can meet the requirements of different applications. As described above, the controller with a duty cycle calculation function according to the embodiments of the present application can indeed achieve excellent technical effects.

[0071] Please refer to Figure 6 which is a flowchart of a duty cycle calculation method of another embodiment of the present application. As shown in the figure, the duty cycle calculation method of the present embodiment includes the following steps:

[0072] Step S60: receiving the pulse width modulation signal by the first capture pin in a rising edge trigger mode.

[0073] Step S61: receiving the pulse width modulation signal by the second capture pin in a falling edge trigger mode.

[0074] Step S62: executing a count program by the timing module, and detecting a first count value of a first rising edge of the pulse width modulation signal captured by the first capture pin, a second count value of a falling edge of the pulse width modulation signal captured by the second capture pin, and a third count value of a second rising edge of the pulse width modulation signal captured by the first capture pin.

[0075] Step S63: calculating a duty cycle of the pulse width modulation signal by the processing module according to the first count value, the second count value, and the third count value.

[0076] Of course, the present embodiment is only used for illustration and not to limit the scope of the present application, equivalent modifications or changes made according to the duty cycle calculation method of the present embodiment should still be included in the patent scope of the present application.

[0077] Referring to Figure 7 , which is a flowchart of a duty cycle calculation method of another embodiment of the present application. As shown, the duty cycle calculation method of the present embodiment includes the following steps:

[0078] Step S71: receiving the pulse width modulation signal by the first capture pin in the rising edge trigger mode.

[0079] Step S72: receiving the pulse width modulation signal by the second capture pin in the falling edge trigger mode.

[0080] Step S73: performing a counting procedure via the timing module and detecting a first count value of the first capture pin capturing the rising edge of the pulse width modulation signal for the first time, a second count value of the second capture pin capturing the falling edge of the pulse width modulation signal, and a third count value of the first capture pin capturing the rising edge of the pulse width modulation signal for the second time.

[0081] Step S74: subtracting the first count value from the third count value to obtain the period of the pulse width modulation signal by the processing module when the counting mode does not overflow.

[0082] Step S75: subtracting the first count value from the second count value to obtain the high level time of the pulse width modulation signal by the processing module, and calculating the duty cycle of the pulse width modulation signal according to the ratio of the high level time to the period.

[0083] Step S76: subtracting the first count value from the product of the overflow value and the overflow times to obtain a difference value by the processing module when the counting mode overflows.

[0084] Step S77: subtracting the difference value from the third count value to obtain the period of the pulse width modulation signal by the processing module.

[0085] Step S78: subtracting the difference value from the second count value to obtain the high level time of the pulse width modulation signal by the processing module, and calculating the duty cycle of the pulse width modulation signal according to the ratio of the high level time to the period.

[0086] Of course, the present embodiment is only used for illustration and not to limit the scope of the present application, equivalent modifications or changes made according to the duty cycle calculation method of the present embodiment should still be included in the patent scope of the present application.

[0087] Although the steps of the methods described herein are shown and described in a particular order, the order of the steps of each method can be altered, certain steps can be performed in reverse order, or certain steps can be performed at the same time as other steps. In another embodiment, not all steps are performed.

[0088] In summary, according to embodiments of the present application, the controller includes a first capture pin, a second capture pin, a timing module and a processing module. The first capture pin receives the PWM signal in a rising edge trigger mode. The second capture pin receives the PWM signal in a falling edge trigger mode. The timing module performs a counting procedure and detects a first count value of a first rising edge of the PWM signal captured by the first capture pin, a second count value of a falling edge of the PWM signal captured by the second capture pin and a third count value of a second rising edge of the PWM signal captured by the first capture pin. The processing module calculates the duty cycle of the PWM signal according to the first count value, the second count value and the third count value. As can be seen from the above, the controller can obtain the count values of the rising edges of two PWM signals and the count value of the falling edge of one PWM signal by the first capture pin in the rising edge trigger mode and the second capture pin in the falling edge trigger mode, and calculate the duty cycle of the PWM signal according to the count values. The signal capture mechanism described above can accurately calculate the duty cycle of the PWM signal without being affected by the interrupt processing time, so that the signal capture mechanism can detect the PWM signal with extremely low duty cycle. Thus, the controller can meet the requirements of different applications.

[0089] In addition, according to embodiments of the present application, the controller has a special signal capture mechanism which can accurately calculate the duty cycle of the PWM signal without being affected by the interrupt processing time, so that the signal capture mechanism can detect the PWM signal with extremely low duty cycle. Thus, the lighting device using the controller can accurately calculate the duty cycle of the PWM signal, and does not need to use a high-performance microcontroller, so that the lighting device can correctly perform the brightness adjustment function and the color temperature adjustment function. Therefore, the cost and power consumption of the lighting device can be reduced, and the lighting device still has accurate brightness adjustment function and color temperature adjustment function.

[0090] In addition, according to the embodiments of the present application, the processing module subtracts the first count value from the third count value to obtain a period of the pulse width modulation signal when the count mode does not overflow, and subtracts the first count value from the second count value to obtain a high level time of the pulse width modulation signal, and then calculates a duty cycle of the pulse width modulation signal according to a ratio of the high level time to the period. The processing module subtracts the first count value from a product of the overflow value and the overflow times to obtain a difference value when the count mode overflows, and subtracts the difference value from the third count value to obtain a period of the pulse width modulation signal, and subtracts the difference value from the second count value to obtain a high level time of the pulse width modulation signal, and then calculates a duty cycle of the pulse width modulation signal according to a ratio of the high level time to the period. Through the above duty cycle calculator, the processing module can accurately calculate the duty cycle of the pulse width modulation signal when the count mode overflows or does not overflow. Therefore, the controller can meet the requirements of practical applications.

[0091] In addition, according to the embodiments of the present application, the controller integrates a special signal capture mechanism and a duty cycle calculator, so that it can detect a pulse width modulation signal with a very low duty cycle and accurately calculate the duty cycle of the pulse width modulation signal. Therefore, the controller can be applied to various different lighting devices, and can actually have various different intelligent functions. Therefore, the controller can meet the trends of future development.

[0092] Furthermore, according to the embodiments of the present application, the controller is simple in design, so that the desired effects can be achieved without significantly increasing the cost. Therefore, the controller not only has high practicality, but also can meet the requirements of different applications.

[0093] It should be noted that although the above embodiments have been described in the present text, the patent protection scope of the present application is not limited thereby. Therefore, based on the innovative idea of the present application, changes and modifications to the embodiments described in the present text, or equivalent structures or equivalent process transformations made using the content of the present application specification and drawings, direct or indirect application of the above technical solutions to other related technical fields, are all included in the protection scope of the present application patent.

Claims

1. A controller having a duty ratio calculation function, characterized by comprising: Comprising: a first capture pin for receiving a pulse width modulation signal in a rising edge trigger mode; a second capture pin for receiving the pulse width modulation signal in a falling edge trigger mode; a timing module for performing a counting procedure and detecting a first count value of a first rising edge of the pulse width modulation signal captured by the first capture pin, a second count value of a falling edge of the pulse width modulation signal captured by the second capture pin, and a third count value of a second rising edge of the pulse width modulation signal captured by the first capture pin; and a processing module for calculating a duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value. The timing module operates in a continuous counting mode.

2. The controller with a duty cycle calculation function according to claim 1, wherein, The processing module is configured to subtract the first count value from the third count value to obtain a period of the pulse width modulation signal when no overflow occurs in the counting procedure, subtract the first count value from the second count value to obtain a high time of the pulse width modulation signal, and calculate the duty cycle of the pulse width modulation signal according to a ratio of the high time to the period.

3. The controller with a duty cycle calculation function according to claim 1, wherein The processing module is configured to subtract a product of an overflow value and an overflow count from the first count value to obtain a difference value when an overflow occurs in the counting procedure, subtract the difference value from the third count value to obtain the period of the pulse width modulation signal, subtract the difference value from the second count value to obtain the high time of the pulse width modulation signal, and calculate the duty cycle of the pulse width modulation signal according to the ratio of the high time to the period.

4. The controller with a duty cycle calculation function according to claim 1, wherein The timing module is a timer.

5. The controller with a duty cycle calculation function according to claim 1, wherein Comprising:

6. A duty cycle calculation method characterized by, receiving a pulse width modulation signal by a first capture pin in a rising edge trigger mode; receiving the pulse width modulation signal by a second capture pin in a falling edge trigger mode; performing a counting procedure by a timing module and detecting a first count value of a first rising edge of the pulse width modulation signal captured by the first capture pin, a second count value of a falling edge of the pulse width modulation signal captured by the second capture pin, and a third count value of a second rising edge of the pulse width modulation signal captured by the first capture pin; and calculating a duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value by a processing module. The timing module operates in a continuous counting mode.

7. The duty cycle calculation method of claim 6, wherein, The step of calculating the duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value by the processing module further comprises:

8. The duty cycle calculation method of claim 6, wherein, subtracting the first count value from the third count value to obtain a period of the pulse width modulation signal by the processing module when no overflow occurs in the counting procedure; subtracting the first count value from the second count value to obtain a high time of the pulse width modulation signal by the processing module; and calculating the duty cycle of the pulse width modulation signal according to a ratio of the high time to the period by the processing module. The step of calculating the duty cycle of the pulse width modulation signal according to the first count value, the second count value, and the third count value by the processing module further comprises:

9. The duty cycle calculation method of claim 6, wherein, ​ When an overflow occurs in the counting mode, the processing module subtracts the first count value from the product of the overflow value and the number of overflows to obtain the difference. The processing module subtracts the difference from the third count value to obtain the period of the pulse width modulation signal; The processing module subtracts the difference from the second count value to obtain the high-level time of the pulse width modulation signal; and The processing module calculates the duty cycle of the pulse width modulation signal based on the ratio of the high-level time to the period.

10. The duty cycle calculation method of claim 6, wherein, The timing module is a timer.

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