Phase inverter capable of simultaneously resisting total dose and single event effect

Abstract

The invention discloses a phase inverter capable of simultaneously resisting total dose and single event effect, which adopts the structural design that a main phase inverter and an auxiliary phase inverter are combined, and the main phase inverter is composed of two PMOS (P-channel Metal Oxide Semiconductor) tubes connected in series and an NMOS (N-channel Metal Oxide Semiconductor) tube. On the basis of a mode that an auxiliary phase inverter provides a level compensation signal at the NMOS source end of a main phase inverter, the high level output by the phase inverter under the total dose effect is prevented from being reduced, and transient upset of the output level of the phase inverter from high to low under the single event effect of an NMOS tube is avoided; on the basis of a double PMOS structure design mode, transient upset of the output level of the inverter from low to high caused by conduction of a PMOS tube under a single event effect is avoided. And finally, stable output of the inverter under the total dose and single-particle system effect can be realized.

Description

Technical Field

[0001] This invention belongs to the field of radiation-hardened analog integrated circuits, specifically relating to an inverter that is simultaneously resistant to total dose and single-event effects. Background Technology

[0002] Particles in the natural space radiation environment can cause ionizing damage to semiconductor devices operating within it, inducing ionizing radiation effects, specifically including total dose effects (mainly electrons and protons) and single-event effects. The total dose effect refers to the cumulative radiation effect that causes performance degradation in circuits or devices operating continuously in a radiation environment, mainly manifested as a decrease in threshold voltage and an increase in leakage current in NMOS transistors. The single-event effect refers to the phenomenon where, when a reverse-biased PN junction region of a device or circuit is bombarded by high-energy particles, a large number of electron-hole pairs generated along the particle's incident trajectory are collected by the electric field of that region, resulting in a current pulse that causes circuit malfunction or performance degradation. The source of the single-event effect is protons, neutrons, and heavy ions in the natural space radiation environment. Based on its impact on electronic components, the single-event effect can be divided into hard errors (permanent damage) and soft errors (non-permanent damage). Hard errors include single-event gate breakdown (SEGR), single-event burnout (SEB), and partial single-event latchup. Soft errors include Single Event Upset (SEU), Single Event Transient (SET), Single Event Function Interrupt (SEFI), and another type of Single Event Latch. Inverter circuits are combinational logic circuits, and their single-event effects are primarily considered in relation to SET.

[0003] Traditional inverters such as Figure 1 As shown, it consists of one PMOS transistor and one NMOS transistor. Under the total dose effect, as the total irradiation dose accumulates, the threshold voltage reduction value ΔVtn of the NMOS transistor gradually increases. When the input signal Vin gradually increases and the output signal Vout gradually decreases, the turn-on voltage V01 of the inverter output signal Vout from high level to low level is Vtn - ΔVtn, that is, the turn-on voltage V01 of the inverter low-level input will become smaller and smaller (the low-level threshold voltage of the inverter decreases), which will cause the output characteristic curve to shift to the left. In addition, as the total irradiation dose accumulates, due to the accumulation of oxide charge in the gate oxide, the leakage current I of the NMOS transistor increases. NMOS漏 Increase, according to Kirchhoff's laws, I NMOS漏 =I PMOS漏Because the conducting PMOS transistor has a parasitic resistance R PMOS When the inverter is in a low-level input state, the output voltage Vout = VDD - I PMOS漏 *R PMOS With I PMOS漏 The increase will gradually decrease, affecting the inverter's voltage switching effect.

[0004] Under the single-event effect, when the single-event effect acts on the inverter unit circuit, the bombardment of high-energy particles may cause a transient voltage disturbance, resulting in a transient jump from low to high output voltage or a transient jump from high to low output voltage. This transient disturbance will propagate along the circuit and may be stored as erroneous data in the timing circuit, ultimately leading to circuit malfunction.

[0005] Inverters are an important structure in radiation hardening, and their performance in resisting total dose (TND) and single-event effects (SEE) is of great value to integrated circuit design in radiation-related fields. However, currently, there are no inverter designs in China that simultaneously achieve resistance to TND and SEE. Patent CN214378450U proposes a SEE-hardened inverter based on polycrystalline resistors, but the size of the polycrystalline resistors needs to be adjusted according to the specific process node and it cannot achieve resistance to TND. Patent CN206353779U proposes an inverter with anti-parameter drift, which can effectively solve the parameter drift problems caused by external factors such as TND, such as reduced low-level noise margin, decreased output high-level, and transmission characteristic curve of inverters, but it cannot achieve resistance to SEE. Patent CN114975596A proposes four novel circuit structures that can... While achieving circuit functionality and strengthening against total dose and single-event lockout when the source of an NMOS transistor is not connected to a substrate, it cannot resist single-event upset effects. Patent CN107196636A proposes an inverter that suppresses single-event transient effects, which can further reduce the interference of single-event transient effects on the inverter, while the circuit driving capability and circuit operating frequency are not affected, but it cannot resist total dose effects. Patent CN214378450U proposes to connect a polysilicon resistor to the circuit sensitive node to strengthen against single-event effects, but it cannot resist total dose effects. Summary of the Invention

[0006] In view of this, the present invention proposes an inverter that is simultaneously resistant to total dose and single event effect. By designing a main inverter, an auxiliary inverter, and dual MOS devices, the inverter threshold voltage can be reduced, the output characteristic curve can be shifted to the left, and the output transient disturbance can be suppressed under total dose and single event effect.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] The inverter simultaneously resisting total dose and single particle effect comprises a main inverter and an auxiliary inverter; the main inverter has an input end Vin and an output end Vout and is composed of two serial PMOS tubes P11 and P12 and an NMOS tube N11; the input end of the auxiliary inverter is connected with the input end Vin of the main inverter and the output end is connected with the source end of the NMOS tube N11.

[0009] Preferably, the main inverter is composed of two serial PMOS tubes P21 and P22 and two serial NMOS tubes N21 and N22; the output end of the auxiliary inverter is used to provide a level signal to compensate the parameter drift of the inverter caused by external factors.

[0010] Preferably, the auxiliary inverter is composed of a PMOS tube P13 and an NMOS tube N13; the source end of the PMOS tube P13 is connected with a power supply VDD, the gate end is connected with the input end Vin and the drain end is connected with the drain end of the NMOS tube N13; the gate end of the NMOS tube N13 is connected with the input end Vin and the source end is connected with a ground end GND.

[0011] Preferably, the auxiliary inverter is composed of two serial PMOS tubes P23 and P24 and two serial NMOS tubes N23 and N24; the source end of the PMOS tube P23 is connected with a power supply VDD, the gate end is connected with the input end Vin and the drain end is connected with the source end of the PMOS tube P24; the gate end of the PMOS tube P24 is connected with the input end Vin and the drain end is connected with the drain end of the NMOS tube N23; the gate end of the NMOS tube N23 is connected with the input end Vin and the source end is connected with the drain end of the NMOS tube N24; the gate end of the NMOS tube N24 is connected with the input end Vin and the source end is connected with a ground end GND.

[0012] Preferably, the junction area of the NMOS tubes N23 and N24 is greater than or equal to the junction area of the NMOS tube in the main inverter.

[0013] The technical scheme of the present application provides an inverter circuit structure simultaneously resisting total dose and single particle effect, through the structural design of the main inverter double PMOS tube and the auxiliary inverter voltage compensation, the output voltage of the inverter unit circuit can be kept stable under the total dose effect, single particle effect or the synergistic effect of the total dose effect and the single particle effect. The present application has important application value in the field of radiation hardening integrated circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 Conventional inverter unit circuit structure;

[0015] Figure 2 One embodiment of the inverter simultaneously resisting total dose and single particle effect of the present application;

[0016] Figure 3 Another embodiment of the inverter resistant to both total dose and single event effects. DETAILED DESCRIPTION

[0017] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application.

[0018] As shown in Figure 2 An inverter resistant to both total dose and single event effects comprises a main inverter and an auxiliary inverter. The main inverter has an input terminal Vin and an output terminal Vout and is composed of two PMOS transistors P11 and P12 and an NMOS transistor N11 connected in series. The source of the PMOS transistor P11 is connected to a power supply VDD, the gate is connected to the input terminal Vin, and the drain is connected to the source of the PMOS transistor P12. The gate of the PMOS transistor P12 is connected to the input terminal Vin, the drain is connected to the drain of the NMOS transistor N11, and the gate of the NMOS transistor N11 is connected to the input terminal Vin. The input terminal of the auxiliary inverter is connected to the input terminal Vin of the main inverter, and the output terminal is connected to the source of the NMOS transistor N11, for providing a voltage Vm at the source of the NMOS transistor N11 to compensate for parameter drift of the inverter caused by external factors.

[0019] Under the effect of total dose, the threshold voltage of the NMOS transistor decreases by ΔVtn relative to the original Vtn, and the auxiliary inverter provides the voltage Vm at the source of the NMOS transistor. When the input signal Vin gradually increases and the output gradually decreases, the turn-on voltage V01 of the main inverter at the low level input is Vtn-ΔVtn+Vm. Therefore, the presence of Vm can compensate for ΔVtn and ensure the stability of the turn-on voltage of the main inverter, inhibit the decrease of the threshold voltage at the low level of the inverter, and effectively solve the problem of leftward shift of the output characteristic curve of the inverter. At the same time, the inverter can also effectively solve the problem of decrease of the output high level caused by the leakage current of total dose effect. When the input of the inverter is at the low level, Vm and the output Vout are both at the high level, and Vm raises the voltage at the source of the NMOS transistor of the main inverter to the high level, which can effectively reduce the voltage difference between the drain and the source of the NMOS transistor and in turn reduce the leakage current, thereby eliminating the phenomenon of decrease of the output high level caused by the leakage current.

[0020] Under the action of single event effect, for the main inverter, when the input Vin is high level and the output signal Vout is low level, the main inverter P11 transistor and P12 transistor are off, and the N11 transistor is on. When the single event effect acts on the P11 or P12 transistor in the off state, the P11 or P12 transistor is momentarily on, but the other PMOS transistor in series is still in the off state. The output signal Vout is still isolated by the PMOS transistor in the off state, and the output signal Vout will not appear from low to high instantaneous jump. When the input Vin is low level and the output signal Vout is high level, the main inverter P11 transistor and P12 transistor are on, and the N11 transistor is off. When the single event effect acts on the N11 transistor, the N11 transistor is momentarily on, but the level signal Vm output by the auxiliary inverter is also high level, so that there is no voltage difference across the N11 transistor, and the output signal Vout will not appear from high to low instantaneous jump.

[0021] In addition, based on the above-mentioned double MOS structure of the main inverter and the level compensation design of the auxiliary inverter, when the total dose effect and the single particle appear simultaneously, the inverter can still work normally.

[0022] In another embodiment, the main inverter is composed of two PMOS tubes P21 and P22 in series and two NMOS tubes N21 and N22 in series; the auxiliary inverter output is used to provide a level signal at the source end of the NMOS tube N22 to compensate for the parameter drift of the inverter caused by external factors, which can further improve the single particle effect resistance of the main inverter.

[0023] Further preferably, the auxiliary inverter is composed of a PMOS tube P13 and an NMOS tube N13; the source electrode of the PMOS tube P13 is connected to the power supply VDD, the gate electrode is connected to the input Vin, and the drain electrode is connected to the drain electrode of the NMOS tube N13; the gate electrode of the NMOS tube N13 is connected to the input Vin, and the source electrode is connected to the ground end GND.

[0024] In another preferred embodiment, as shown in Figure 3 the auxiliary inverter is composed of two PMOS tubes P23 and P24 in series and two NMOS tubes N23 and N24 in series; the source electrode of the PMOS tube P23 is connected to the power supply VDD, the gate electrode is connected to the input Vin, and the drain electrode is connected to the source electrode of the P24; the gate electrode of the PMOS tube P24 is connected to the input Vin, and the drain electrode is connected to the drain electrode of the NMOS tube N23; the gate electrode of the NMOS tube N23 is connected to the input Vin, and the source electrode is connected to the drain electrode of the NMOS tube N24; the gate electrode of the NMOS tube N24 is connected to the input Vin, and the source electrode is connected to the ground end GND.

[0025] When the input end Vin is high, the auxiliary inverter output signal Vm is low, at this time, the PMOS tubes P23 and P24 are turned off, and the NMOS tubes N23 and N24 are turned on, when the single particle effect acts on the P23 or P24 transistor in the off state, the P23 or P24 transistor is turned on instantaneously, but the other transistor in series with it is still in the off state, the output signal Vm is still isolated from the transistor in the off state, and the output signal Vm will not jump from low to high instantaneously; when the input end Vin is low, the auxiliary inverter output signal Vm is high, at this time, the auxiliary inverter PMOS tubes P23 and P24 are turned on, and the NMOS tubes N23 and N24 are turned off, when the single particle effect acts on the N23 or N24 transistor, the N23 or N24 transistor is turned on instantaneously, but the transistor in series with it is still in the off state, the output signal Vm is still isolated from the transistor in the off state, and the output signal Vm will not jump from high to low instantaneously, thereby realizing the anti-single particle effect performance of the auxiliary inverter. Through the design, the stability of the inverter under the synergistic action of the total dose effect and the single particle effect can be further improved.

[0026] Preferably, the junction area of the NMOS tubes N23 and N24 is greater than or equal to the junction area of the NMOS tubes in the main inverter, so as to ensure the voltage pull-down capability of the inverter.

[0027] The present application is not limited to the above specific embodiments, and various transformations made by the skilled in the art without creative labor, based on the above ideas, all fall within the protection scope of the present application.

Claims

1. An inverter simultaneously resistant to total dose and single event effects, characterized in that, The auxiliary inverter is composed of a PMOS tube P13 and an NMOS tube N13; the source of the PMOS tube P13 is connected to the power supply VDD, the gate is connected to the input end Vin, and the drain is connected to the drain of the NMOS tube N13; the gate of the NMOS tube N13 is connected to the input end Vin, and the source is connected to the ground end GND.

2. The simultaneous anti-total dose and single event effect inverter of claim 1, wherein, The auxiliary inverter is composed of a PMOS tube P13 and an NMOS tube N13; the source of the PMOS tube P13 is connected to the power supply VDD, the gate is connected to the input end Vin, and the drain is connected to the drain of the NMOS tube N13; the gate of the NMOS tube N13 is connected to the input end Vin, and the source is connected to the ground end GND.

3. The simultaneous anti-total dose and single event effect inverter of claim 1 or 2, wherein, The auxiliary inverter is composed of a PMOS tube P13 and an NMOS tube N13; the source of the PMOS tube P13 is connected to the power supply VDD, the gate is connected to the input end Vin, and the drain is connected to the drain of the NMOS tube N13; the gate of the NMOS tube N13 is connected to the input end Vin, and the source is connected to the ground end GND.

4. The simultaneous anti-total dose and single event effect inverter of claim 1 or 2, wherein, The auxiliary inverter is composed of a PMOS tube P13 and an NMOS tube N13; the source of the PMOS tube P13 is connected to the power supply VDD, the gate is connected to the input end Vin, and the drain is connected to the drain of the NMOS tube N13; the gate of the NMOS tube N13 is connected to the input end Vin, and the source is connected to the ground end GND.

5. The simultaneous anti-total dose and single event effect inverter of claim 4, wherein, The junction area of the NMOS tubes N23 and N24 is greater than or equal to the junction area of the NMOS tube in the main inverter.

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