Electronic component packaging structure, radar sensor and electronic equipment

Abstract

The embodiment of the invention relates to the technical field of signal processing, and discloses an electronic component packaging structure, a radar sensor and electronic equipment, and the electronic component packaging structure comprises at least one rewiring layer, a dielectric layer and a parasitic antenna layer which are sequentially arranged. The electronic component couples a radio frequency signal to the parasitic antenna layer through the at least one rewiring layer; and / or, the parasitic antenna layer couples a received space radiation signal to the at least one rewiring layer and then transmits the space radiation signal to the electronic component; wherein the dielectric constant of the dielectric layer is less than or equal to 0.02 method / meter. According to the scheme, the wafer-level packaging is adopted to replace the traditional bumping and substrate-single packaging process, so that the packaging process without introducing the substrate is realized, the packaging cost can be greatly reduced, and the processing period is shortened.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to an electronic component packaging structure, a radar sensor and an electronic device. BACKGROUND

[0002] Antenna-in-Package (AiP) integrates an antenna and a chip in a package by using a packaging material and process, and provides an antenna solution for emerging wireless system-on-chip or single-chip radio. Currently, the AiP structure introduces a substrate in the packaging process by using a bumping process, and the bumps (for example, gold pillars, copper pillars, etc.) formed by the bumping process are connected to the solder on pads (SOP) on the surface of the substrate. However, the processing cost of the substrate is high, and the processing cycle is long, which seriously affects the overall packaging cost and production efficiency of the antenna-in-package. SUMMARY

[0003] Embodiments of the present application aim to provide an electronic component packaging structure, a radar sensor and an electronic device, which uses wafer-level packaging to replace the traditional bumping and substrate-single-chip packaging process, so as to realize a packaging process without introducing a substrate, thereby greatly reducing the packaging cost and shortening the processing cycle.

[0004] To solve the above technical problems, an electronic component packaging structure is provided in an embodiment of the present application, which comprises: at least one redistribution layer, a dielectric layer and a parasitic antenna layer arranged in sequence; the electronic component couples a radio frequency signal to the parasitic antenna layer through the at least one redistribution layer; and / or the parasitic antenna layer couples a received spatial radiation signal to the at least one redistribution layer and then transmits the spatial radiation signal to the electronic component; wherein the dielectric constant of the dielectric layer is less than or equal to 0.02 F / m.

[0005] Compared with the related art, in the electronic component packaging structure of the present application, at least one redistribution layer, a dielectric layer and a parasitic antenna layer are arranged in sequence; the electronic component couples a radio frequency signal to the parasitic antenna layer through the at least one redistribution layer; and / or the parasitic antenna layer couples a received spatial radiation signal to the at least one redistribution layer and then transmits the spatial radiation signal to the electronic component, so as to realize that the dielectric layer replaces the traditional substrate and the separate redistribution layer replaces the metal trace arranged in the substrate, thereby eliminating the processing cost and processing cycle of the substrate, greatly reducing the overall packaging cost, and shortening the processing cycle; at the same time, the dielectric constant of the dielectric layer is less than or equal to 0.02 F / m, which can effectively reduce the loss of the radio frequency signal caused by the dielectric layer during the transmission of the radio frequency signal, and improve the transmission speed of the signal.

[0006] In some embodiments, further comprising a plastic encapsulation layer, the plastic encapsulation layer is arranged in contact with the at least one redistribution layer. The plastic encapsulation layer can work together with the dielectric layer to replace the traditional substrate to support the overall packaging structure.

[0007] In some embodiments, the plastic encapsulation layer is arranged in contact with the redistribution layer farthest from the dielectric layer, the electronic component is located inside the plastic encapsulation layer, and the electronic component is connected to the redistribution layer through at least one bump. By arranging the electronic component inside the plastic encapsulation layer, the plastic encapsulation layer can encapsulate the electronic component; and the connection between the electronic component and the redistribution layer is realized through the bump.

[0008] In some embodiments, further comprising a plurality of solder balls and a plurality of metal columns penetrating through the plastic encapsulation layer, the plurality of solder balls are located on a side of the plastic encapsulation layer away from the dielectric layer, and the at least one redistribution layer is connected to the solder balls through the metal columns. By arranging the metal columns in the plastic encapsulation layer, the connection between the redistribution layers on both sides of the plastic encapsulation layer and the solder balls is realized.

[0009] In some embodiments, further comprising a solder mask layer, the solder mask layer is located on a surface of the redistribution layer farthest from the dielectric layer, and the electronic component is connected to the redistribution layer through the solder mask layer. By arranging the solder mask layer on the surface of the outermost redistribution layer away from the dielectric layer, the connection between the electronic component and the redistribution layer is realized.

[0010] In some embodiments, the at least one redistribution layer is connected to the solder balls through the solder mask layer. The connection between the redistribution layer and the solder ball can also be realized by using the solder mask layer.

[0011] In some embodiments, the plastic encapsulation layer is located between two adjacent redistribution layers, and the plastic encapsulation layer is internally provided with metal traces for connecting the redistribution layers on both sides of the plastic encapsulation layer. By flexibly arranging the plastic encapsulation layer between two adjacent redistribution layers and connecting the redistribution layers on both sides of the plastic encapsulation layer through the metal traces penetrating through the plastic encapsulation layer, a structure is formed in which the plastic encapsulation layer replaces the substrate to allow the metal traces to penetrate through to realize the interconnection of the redistribution layers. Compared with the structure in which the metal traces penetrate through the traditional substrate, the structure has a smaller thickness size, and the pitch and width of the metal traces can be further reduced.

[0012] In some embodiments, the electronic component is located outside the plastic encapsulation layer. By flexibly arranging the relative position between the electronic component and the plastic encapsulation layer, more abundant packaging structures are provided.

[0013] In some embodiments, the material of the plastic encapsulation layer is plastic or glass.

[0014] In some embodiments, the material of the dielectric layer is silicon or glass.

[0015] In another aspect, the application provides an electronic component packaging structure, comprising: a first electronic device, a second electronic device, and a first insulating layer, a plastic encapsulation layer, a second insulating layer, a dielectric layer, and a parasitic antenna layer arranged in sequence; the first electronic device and the second electronic device are arranged in a stack inside the plastic encapsulation layer, the first insulating layer, the second insulating layer, and the plastic encapsulation layer are each provided with metal traces connected to each other; the first electronic device is electrically connected to the metal traces through bumps and connected to solder balls on the surface of the first insulating layer through the metal traces, and the first electronic device couples radio frequency signals to the parasitic antenna layer through the metal traces; the second electronic device is electrically connected to the metal traces through bumps and connected to solder balls on the surface of the first insulating layer through the metal traces, and the second electronic device couples radio frequency signals to the parasitic antenna layer through the metal traces; and the dielectric layer has a dielectric constant less than or equal to 0.02 F / m.

[0016] Compared with related technologies, in the electronic component packaging structure of the application, the first insulating layer, the plastic encapsulation layer, the second insulating layer, the dielectric layer, and the parasitic antenna layer are arranged in sequence, the first electronic device and the second electronic device are arranged in a stack inside the plastic encapsulation layer, the first insulating layer, the second insulating layer, and the plastic encapsulation layer are each provided with metal traces connected to each other, so that the dielectric layer is used to replace the traditional substrate, and the metal traces pass through the dielectric layer and the insulating layer to realize multi-layer interconnection, thereby eliminating the processing cost and processing period of the substrate, greatly reducing the overall packaging cost, and shortening the processing period; the first electronic device and the second electronic device are respectively electrically connected to the metal traces through bumps and connected to solder balls on the surface of the first insulating layer through the metal traces, the first electronic device and the second electronic device couple radio frequency signals to the parasitic antenna layer through the metal traces to realize radio frequency signal transmission; and the dielectric layer has a dielectric constant less than or equal to 0.02 F / m, which can effectively reduce the loss of the dielectric layer to the radio frequency signals and improve the transmission speed of the signals during the transmission of the radio frequency signals.

[0017] In another aspect, the application provides a method for manufacturing an electronic component packaging structure, comprising:

[0018] providing a carrier plate, and forming a parasitic antenna layer, a dielectric layer, and at least one redistribution layer on the first surface of the carrier plate in sequence;

[0019] electrically connecting electronic components to the redistribution layer through bumps;

[0020] filling the electronic components with packaging material to form a plastic encapsulation layer;

[0021] A plurality of metal columns are formed between the upper and lower surfaces of the plastic sealing layer, and the redistribution layer is connected with the solder balls on the surface of the plastic sealing layer through the metal columns.

[0022] The carrier plate is removed.

[0023] The dielectric constant of the medium layer is less than or equal to 0.02 F / m.

[0024] In another aspect, the application provides a chip packaged by the electronic component packaging structure according to any one of the above embodiments.

[0025] In another aspect, the application provides a radar sensor comprising the chip according to the above.

[0026] In another aspect, the application provides an electronic device comprising the chip according to the above or the radar sensor according to the above. BRIEF DESCRIPTION OF DRAWINGS

[0027] One or more embodiments are illustrated by way of example in the figures that form a part of this patent document. These example are not intended to limit the application, but to clarify and explain the principles of the at least one embodiment. The accompanying drawings incorporated in and forming a part of the specification, illustrate several aspects of the present application. It is stressed that the principles of the present application can be employed in various and numerous embodiments without departing from the scope of the application. The drawings are in simplified form and are not to precise scale. For purposes of clarity, not every component is called out in the drawings. In the drawings:

[0028] Figure 1 is a schematic diagram of a substrate-based AiP packaging structure;

[0029] Figure 2 is a cross-sectional view of an electronic component packaging structure according to an embodiment of the application;

[0030] Figure 3 is a cross-sectional view of an electronic component packaging structure according to another embodiment of the application;

[0031] Figure 4 is a cross-sectional view of an electronic component packaging structure according to yet another embodiment of the application;

[0032] Figure 5 is a cross-sectional view of an electronic component packaging structure according to yet another embodiment of the application;

[0033] Figure 6 is a flowchart of a method for manufacturing an electronic component packaging structure according to an embodiment of the application;

[0034] Figure 7a is a flowchart of a process for forming a parasitic antenna layer and a medium layer according to an embodiment of the application;

[0035] Figure 7bis a flow chart of a process for forming a redistribution layer according to an embodiment of the present application;

[0036] Figure 7c is a flow chart of a process for flip-chip connection and molding layer formation of an electronic component according to an embodiment of the present application;

[0037] Figure 7d is a flow chart of a process for metal pillar interconnection and removal of a carrier substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the various embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the various embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the following various embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and the various embodiments can be combined with each other and cited to each other without contradiction.

[0039] Figure 1 An exemplary AiP structure is shown, the substrate of the AiP structure mainly includes an antenna layer L1, a feed line layer L2, a metal ground layer L3, and a wiring layer L4, wherein the antenna layer L1 and the feed line layer L2 include a Pre-preg Material 02 therebetween, the feed line layer L2 and the metal ground layer L3 include a Core Material 01 therebetween, and the metal ground layer L3 and the wiring layer L4 include a Pre-preg Material 02 therebetween; the wafer 03 is connected to the pads on the surface of the substrate through the bumps 04 after bumping processing.

[0040] In the AiP packaging process, the introduction of the substrate results in a large overall packaging structure size, and the processing cost is high and the processing period is long. In the embodiments of the present application, the dielectric layer is provided instead of the substrate, and the redistribution layer (RDL) provided separately from the dielectric layer is used to realize signal transmission between the electronic component and the antenna layer and connection between the electronic component and the solder balls. The RDL replaces the Cu wiring of the substrate, can realize shorter interconnection and smaller pitch, improve the redundancy of the wiring, reduce the packaging size, and the RDL process can also increase the wiring area available for the chip, fully utilize the effective area of the chip, and achieve the purpose of reducing the cost.

[0041] An embodiment of the present application relates to an electronic component packaging structure, such as Figure 2As shown, the electronic component packaging structure includes at least one redistribution layer, a dielectric layer 11, and a parasitic antenna layer 12 arranged sequentially.

[0042] The number of redistribution layers can be as follows: Figure 2 As shown in, but not limited to, the embodiments of this application, there are three redistribution layers M1 to M3, where M1 to M3 can be, sequentially, a trace layer M1, a feed line M2, and an active antenna layer M3. An insulating layer is provided between adjacent layers, and the material of the insulating layer can be, but is not limited to, polyimide or glass. The trace layer M1 is mainly used to connect with electronic components and solder balls to achieve overall interconnection between the redistribution layer and other electronic components or structures. The feed line layer M2 is used to feed the active antenna layer M3. Since this embodiment uses a separate redistribution layer, unlike the method of setting metal traces through mechanical drilling on the substrate, the metal traces are completed through photolithography and electroplating, resulting in a smaller trace size; that is, the minimum linewidth and line spacing in the redistribution layer can be 5 to 10 micrometers, respectively. The dielectric layer 11 separates adjacent redistribution layers (such as the feed line layer M3) and the parasitic antenna layer 12, so that the two are not directly interconnected through traces but are coupled to achieve radio frequency signal transmission. The dielectric layer 11 also provides support for the overall package structure. Among them, dielectric layer 11 is a material with a very low dielectric constant. The material with a very low dielectric constant is mainly obtained through D. k / D f To describe, where D k D is the dielectric constant. f This refers to dielectric loss. For example, in the embodiments of this application, the dielectric constant of the dielectric layer 11 material is less than or equal to 0.02 F / m. The embodiments of this application can be, but are not limited to, silicon or glass. A lower dielectric constant can effectively reduce the loss of radio frequency signals caused by the dielectric layer during the transmission of radio frequency signals through coupling between the redistribution layer and the parasitic antenna layer 12, thereby improving the signal transmission speed.

[0043] The electronic component couples the radio frequency signal to the parasitic antenna layer 12 through at least one redistribution layer; and / or, the parasitic antenna layer 12 couples the received spatial radiation signal to the at least one redistribution layer and then transmits it to the electronic component.

[0044] In the embodiment, the electronic component can be a wafer die. The electronic component can be connected to the trace layer M1 in the redistribution layer, and then the radio frequency signal is coupled to the parasitic antenna layer 12 through the feed line layer M2 and the active antenna layer M3, and / or the received spatial radiation signal is coupled to the active antenna layer M3 in the redistribution layer by the parasitic antenna layer 12, and then transmitted to the electronic component through the feed line layer M2 and the trace layer M1, so as to realize the radio frequency signal transmission between the electronic component and the parasitic antenna layer 12. In the embodiment, the relative position of the electronic component and the redistribution layer, and the specific connection mode are not limited. The electronic component can be located outside the overall structure of all redistribution layers, or can be located between any two redistribution layers, such as the insulating layer between the adjacent two redistribution layers.

[0045] In the electronic component packaging structure in the embodiment, the dielectric layer is used instead of the traditional substrate, and the separate redistribution layer is used instead of the metal trace arranged in the substrate. The processing cost and processing period of the substrate are saved, so that the overall packaging cost is greatly reduced, and the processing period is shortened. Meanwhile, the dielectric constant of the dielectric layer is less than or equal to 0.02 F / m. In the process of transmitting the radio frequency signal, the dielectric layer can effectively reduce the loss of the radio frequency signal caused by the dielectric layer itself, and improve the transmission speed of the radio frequency signal.

[0046] In some embodiments, the electronic component packaging structure described above further includes a plastic encapsulation layer. The plastic encapsulation layer is arranged in close contact with the at least one redistribution layer. The plastic encapsulation layer, also referred to as Molding Compound (abbreviated as “Molding CPD”), mainly functions to encapsulate and protect the chip, such as the electronic component in the embodiment, from the influence of the processing process and the use environment. These responses include, for example, the performance degradation or failure of the chip caused by factors such as heat, radiation, humidity, mechanical stress, and the like.

[0047] The plastic encapsulation layer can be arranged in close contact with the outermost redistribution layer (such as the trace layer M1) of the at least one redistribution layer, or can be located between two adjacent redistribution layers (such as the feed line layer M2 and the active antenna layer M3) and arranged in close contact with the two redistribution layers. The plastic encapsulation layer is an insulating material, and can be plastic or glass. When the plastic encapsulation layer is located between two adjacent redistribution layers, the plastic encapsulation layer can also act as an insulating layer for isolating the two redistribution layers.

[0048] In some embodiments, the electronic component can be located inside the plastic encapsulation layer, such as Figure 3 In the example shown in FIG. 13, the plastic encapsulation layer 13 is arranged in close contact with the redistribution layer farthest from the dielectric layer 11, the electronic component 14 is located inside the plastic encapsulation layer 13, and the electronic component 14 is connected to the redistribution layer through at least one bump B.

[0049] Wherein, the bumping is formed on the wafer die surface, in some embodiments, the bumping can be formed as a solder ball or other solder bumping, the bumping can also be gold, copper, tin lead, or lead-free metal. The bumping is mostly used in flip chip packaging process. By growing the bumping on the front side of the chip provided with metal traces, and connecting the bumping with the chip to be inverted and buckled on the substrate, the electrical signal is conducted through the bumping, the chip is directly connected with the substrate, and the path between the chip and the substrate is very short, and the signal transmission time delay can be significantly reduced. In the present embodiment, the electronic component is connected to the redistribution layer by the bumping, and is connected to the redistribution layer (such as the trace layer M1) farthest from the dielectric layer 11 by, for example, soldering.

[0050] The plastic sealing layer 13 is also provided outside the redistribution layer farthest from the dielectric layer 11, and is provided in close contact with the redistribution layer (such as the trace layer M1). At this time, the electronic component 14 is located inside the plastic sealing layer 13, and the electronic component 14 is connected with the redistribution layer (such as the trace layer M1) through at least one bumping B. In actual process processing, the electronic component 14 can be first connected to the outermost redistribution layer (such as the trace layer M1) by the bumping B, and then the plastic sealing layer 13 is formed by the molding compound underfill between the electronic component 14 and the redistribution layer and around the electronic component 14, and the plastic sealing layer 13 wraps the electronic component 14 to protect it.

[0051] In some embodiments, as shown in Figure 3 The electronic component packaging structure further includes a plurality of solder balls 15 and a plurality of metal columns 16 penetrating the plastic sealing layer 13, the plurality of solder balls 15 are located on the side of the plastic sealing layer 13 away from the dielectric layer 11, and at least one redistribution layer is connected with the solder balls 15 through the metal columns 16.

[0052] Wherein, the solder balls 15 are used to solder the electronic component packaging structure to the externally connected PCB board, and the internal traces of the electronic component packaging structure are interconnected with the traces on the externally connected PCB board through the solder balls 15, thereby realizing the electrical connection between the electronic component 14 and the PCB board. The metal columns 16 are used to connect the redistribution layer (such as the trace layer M1) inside the electronic component packaging structure with the solder balls 15 to realize electrical signal communication. In some embodiments, the metal columns 16 can be formed by the process of plastic sealing through hole (Through Molding Via, TMV) or glass through hole (Through Glass Via, TGV), and then the metal is electroplated in the formed through hole.

[0053] In the embodiment, the medium layer and the plastic sealing layer can effectively replace the traditional substrate, which can support the overall packaging structure, and the electronic components are arranged in the plastic sealing layer to realize the packaging protection of the electronic components by the plastic sealing layer to avoid the influence of the processing process and the use environment. In the embodiment, the electronic components are connected with the redistribution layers through the bumps to realize the flip chip connection of the electronic components to the packaging structure. In the embodiment, the metal pillars are arranged in the plastic sealing layer to realize the connection between the redistribution layers on both sides of the plastic sealing layer and the solder balls, so that the redistribution layers are interconnected.

[0054] In some embodiments, the electronic components can be located outside the plastic sealing layer, for example, Figure 4 As exemplarily shown in the above embodiment, the electronic component packaging structure further includes a solder resist layer 17, which is located on the surface of the redistribution layer farthest from the medium layer 11, and the electronic component 14 is connected with the redistribution layer through the solder resist layer 17.

[0055] In the embodiment, the solder resist layer 17 is used to isolate the redistribution layer and the electronic component 14, and the solder resist layer is removed at the position where the redistribution layer and the electronic component 14 need to be connected, and the solder pad is arranged at the position where the solder resist layer is removed to realize the electrical connection between the redistribution layer and the electronic component 14. Similarly, the electronic component 14 is connected with the solder pad through the bump B and adopts the flip chip packaging process.

[0056] In the embodiment, the at least one redistribution layer is connected with the solder ball 15 through the solder resist layer 17.

[0057] In the embodiment, the solder ball 15 is used to weld the electronic component packaging structure to the externally connected PCB board, and the internal wiring of the electronic component packaging structure and the wiring on the externally connected PCB board are interconnected through the solder ball 15, so as to realize the electrical connection between the electronic component 14 and the PCB board. The solder ball 15 is arranged on the surface of the solder resist layer 17, the solder resist layer is removed at the position where the solder ball 15 needs to be connected with the redistribution layer, and the solder pad is arranged at the position where the solder resist layer is removed to realize the electrical connection between the redistribution layer and the solder ball 15.

[0058] Since the electronic component 14 is connected with the redistribution layer through the solder resist layer 17, and the plastic sealing layer 13 needs to be attached to the at least one redistribution layer, the electronic component 14 is arranged in the plastic sealing layer 13.

[0059] In some embodiments, Figure 4 As exemplarily shown, the plastic sealing layer 13 can be located between two adjacent redistribution layers (such as the feeder layer M2 and the active antenna layer M3 shown in the figure), and the metal wiring S1 is arranged in the plastic sealing layer 13 to connect the redistribution layers on both sides of the plastic sealing layer 13.

[0060] The plastic sealing layer 13 is located between two adjacent redistribution layers, and can act as an insulating layer between the two redistribution layers.

[0061] In some embodiments, Figure 4 For example, the electronic component 14 is located outside the plastic sealing layer 13.

[0062] The electronic component packaging structure has at least the following advantages:

[0063] 1) The medium layer with low dielectric constant (D k / D f ) is used to replace the traditional substrate, and the metal trace between the substrate (core & Pre-Preg) materials is replaced by the redistribution layer RDL, so as to realize shorter interconnection, and the line width and line spacing in the redistribution layer can reach 5-10 um, so as to realize smaller trace spacing, improve trace redundancy, and further reduce the packaging size.

[0064] 2) The FO (Fan Out, fan-out type)-AiP packaging can be realized in a thinner and smaller packaging size, so as to reduce the cost.

[0065] 3) The wafer-level packaging is used to replace the traditional bump and substrate-single package process, so as to save the processing period.

[0066] 4) The glass is used as the plastic sealing layer to replace the substrate or the plastic sealing material, so as to reduce the influence of the warping problem caused by the mismatch of the thermal expansion coefficients.

[0067] Another embodiment of the present application further provides an electronic component packaging structure, which relates to a packaging structure of double electronic components, as shown in Figure 5 The packaging structure of the electronic component includes:

[0068] The first electronic device 18, the second electronic device 19, and the first insulating layer L1, the plastic sealing layer 13, the second insulating layer L2, the medium layer, and the parasitic antenna layer arranged in sequence. Figure 5 The medium layer and the parasitic antenna layer are not shown in the electronic component packaging structure, and the arrangement of the medium layer 11 and the parasitic antenna layer 12 in the electronic component packaging structure can be referred to. Figures 2 to 4

[0069] ​The first insulating layer L1 and the second insulating layer L2 can be respectively composed of multiple layers of insulating material, and the insulating material of each layer can be the same or different. The reason for such division is that at least one redistribution layer can be included in the first insulating layer L1 and the second insulating layer L2, and an insulating material layer needs to be arranged between adjacent redistribution layers. Since the plastic sealing layer 13 is located in the middle of the insulating material layer (the upper and lower surfaces of the plastic sealing layer 13 are both insulating material layers), the insulating material layers on both sides of the plastic sealing layer 13 are collectively referred to as the first insulating layer L1 and the second insulating layer L2 according to the side on which they are located. The dielectric layer and the parasitic antenna layer are arranged in sequence on the surface of the second insulating layer L2.

[0070] The first electronic device 18 and the second electronic device 19 are arranged in a stack inside the plastic sealing layer 13, and in the embodiment of the application, they are arranged in a back-to-back manner, for example, the front surface of the first electronic device 18 faces the first insulating layer L1, and the front surface of the second electronic device 19 faces the second insulating layer L2. In order to ensure that the devices do not interfere with each other, an insulating material layer can be arranged between the first electronic device 18 and the second electronic device 19. If the first electronic device 18 and the second electronic device 19 need to be interconnected, a via hole can be arranged on the insulating material layer between them, and the interconnection can be achieved by arranging metal traces in the via hole.

[0071] The first insulating layer L1, the second insulating layer L2, and the inside of the plastic sealing layer 13 are all provided with interconnected metal traces S2. These metal traces S2 can complete the specified signal connection relationship according to the preset trace path.

[0072] The first electronic device 18 is electrically connected to the metal traces S2 through the bump B1 and connected to the solder ball 15 on the surface of the first insulating layer L1 through the metal traces S2. The first electronic device 18 couples the radio frequency signal to the parasitic antenna layer through the metal traces S2.

[0073] The first electronic device 18 can also be interconnected with the adjacent metal traces S2 by other connection methods such as through the use of pads. When connected to the solder ball 15 on the surface of the first insulating layer L1, the first electronic device 18 can preferentially realize electrical signal interconnection with the solder ball 15 through the traces S2 between the first electronic device 18 and the solder ball 15 to shorten the trace distance. When performing radio frequency signal transmission with the parasitic antenna layer, it is necessary to transmit the radio frequency signal to the metal traces S2 located in the second insulating layer L2, and then couple the radio frequency signal to the parasitic antenna layer based on these metal traces S2. In this process, the first electronic device 18 can first transmit the radio frequency signal to the metal traces S2 located in the first insulating layer L1, and then bypass the first electronic device 18 and the second electronic device 19 until the radio frequency signal is transmitted to the metal traces S2 on the surface of the second insulating layer L2, and then the radio frequency signal is coupled to the parasitic antenna layer.

[0074] The second electronic device 19 is electrically connected with the metal trace S2 through the bump B2, and is connected with the solder ball 15 on the surface of the first insulating layer L1 through the metal trace S2. The second electronic device 19 couples the radio frequency signal to the parasitic antenna layer through the metal trace S2.

[0075] The second electronic device 19 can also be interconnected with the adjacent metal trace S2 through other connection modes such as a bonding pad. When connected with the solder ball 15 on the surface of the first insulating layer L1, the electrical signal needs to be transmitted to the metal trace S2 in the first insulating layer L1, and then transmitted to the solder ball 15 based on the metal trace S2. In this process, the second electronic device 19 can first transmit the electrical signal to the metal trace S2 in the second insulating layer L2, and then bypass the second electronic device 19 and the first electronic device 18 until the electrical signal is transmitted to the metal trace S2 on the surface of the first insulating layer L1, and then transmitted to the solder ball 15. When transmitting the radio frequency signal with the parasitic antenna layer, the second electronic device 19 can preferentially couple the radio frequency signal to the parasitic antenna layer through the trace S2 between the dielectric layer, so as to shorten the trace distance.

[0076] The dielectric constant of the dielectric layer is less than or equal to 0.02 F / m.

[0077] All the structural features contained in the above embodiments can be applied to the present embodiment without conflict with the structural features in the present embodiment, and will not be repeated here.

[0078] Compared with the related art, in the electronic component packaging structure of the present embodiment, the first insulating layer, the plastic sealing layer, the second insulating layer, the dielectric layer and the parasitic antenna layer are sequentially arranged; the first electronic device and the second electronic device are arranged in the plastic sealing layer in a stacked manner, so as to realize the sharing of the same packaging structure by multiple devices; the first insulating layer, the second insulating layer and the plastic sealing layer are all provided with interconnected metal traces, so as to realize the replacement of the traditional substrate with the dielectric layer, and the multi-layer interconnection through the metal traces passing through the dielectric layer and the insulating layer, thereby saving the processing cost and processing period of the substrate, greatly reducing the overall packaging cost, and shortening the processing period; the first electronic device and the second electronic device are electrically connected with the metal traces through the bumps, and are connected with the solder balls on the surface of the first insulating layer through the metal traces. The first electronic device and the second electronic device couple the radio frequency signal to the parasitic antenna layer through the metal traces, so as to realize the transmission of the radio frequency signal. Meanwhile, the dielectric constant of the dielectric layer is less than or equal to 0.02 F / m, which can effectively reduce the loss of the dielectric layer to the radio frequency signal during the transmission of the radio frequency signal through the dielectric layer, and improve the transmission speed of the signal.

[0079] Another embodiment of the present embodiment also provides a preparation method of an electronic component packaging structure, as shown in Figure 6 The method comprises the following steps.

[0080] S101: providing a carrier, a parasitic antenna layer, a dielectric layer and at least one redistribution layer are sequentially formed on a first surface of the carrier; wherein the dielectric layer has a dielectric constant less than or equal to 0.02 F / m.

[0081] Figure 7a The formation process of the parasitic antenna layer 12 and the dielectric layer 11 is described exemplarily. In this embodiment, the carrier is a glass carrier. First, a polyimide coating (PI coating) is formed on the provided glass carrier. After a window for copper plating is opened on the PI coating by using a photolithography process, a seed layer is formed on the surface thereof. The RDL is electroplated on the seed layer, and the parasitic patch is grown by wet etching to form the parasitic antenna layer. The dielectric layer 11 is formed on the parasitic antenna layer by using a low dielectric constant material. In this embodiment, the dielectric layer of the low dielectric constant material has a dielectric constant less than or equal to 0.02 F / m. The low dielectric constant material can be resin, epoxy resin, organic polymer, polymer with or without silicon-based or glass filler.

[0082] Figure 7b The formation process of the redistribution layer is described exemplarily. In this embodiment, the four PI layers and three redistribution layers are formed by the cyclic generation process of the multi-layer PI&RDL. The first redistribution layer M3 is used to set the active patch antenna, the second redistribution layer M2 is used to set the transmission path of the radio frequency signal, and the third redistribution layer M1 is used to flip-chip connect the electronic component (chip) and the via interconnection.

[0083] S102: electrically connecting the electronic component and the redistribution layer through the bump.

[0084] Figure 7c The flip-chip connection process of the electronic component is described exemplarily. First, the bump is set on the electronic component 14, and the electronic component 14 is bonded with the redistribution layer (such as the wiring layer M1) by means of the bump to complete the electrical signal interconnection.

[0085] S103: filling the electronic component with encapsulating material to form a plastic encapsulation layer.

[0086] Figure 7cThe forming process of the plastic encapsulation layer is described as an example. The gap between the electronic element 14 and the redistribution layer and the gap around the electronic element 14 are filled with a molding compound underfill. The molding compound is a fluid material that can flow around the electronic element 14 after the electronic element 14 is mounted. Then, grinding is performed to expose the back of the electronic element 14 and to thin the molding compound on the back of the electronic element 14 to the same level as the back of the electronic element 14. The larger the proportion of the plastic encapsulation layer 13 in the electronic element package, the more likely the package is to warp, which affects the connectivity of the electronic element 14. Therefore, the plastic encapsulation layer 13 needs to be thinned as much as possible through grinding to reduce the warping effect on the electronic element 14.

[0087] S104: Forming a plurality of metal pillars between the upper and lower surfaces of the plastic encapsulation layer, and connecting the redistribution layer to the solder balls on the surface of the plastic encapsulation layer through the metal pillars.

[0088] Figure 7c The forming of the metal pillars 16 is described as an example. The metal pillars 16 are formed by a TMV process. A plurality of openings are formed between the upper and lower surfaces of the plastic encapsulation layer 13 by laser irradiation. Then, metal plating is performed in the openings to form a plurality of metal pillars 16.

[0089] Figure 7d A PI layer and two RDL layers are formed on the back of the plastic encapsulation layer 13. The first RDL layer is used to connect the through holes (metal pillars 16), and the second RDL layer is used to connect the solder balls 15. Finally, the redistribution layer is connected to the solder balls 15 on the surface of the plastic encapsulation layer 13 through the metal pillars 16.

[0090] S105: Removing the carrier.

[0091] Finally, the glass carrier is removed by laser peeling, and the die is singulated by a singulation process to obtain a complete electronic element package structure. Figure 7d

[0092] Another embodiment of the present application also provides a chip packaged by the electronic element package structure described in any of the above embodiments. The die inside the chip can be a wafer-level die, which can be the electronic element described above.

[0093] Another embodiment of the present application also provides a radar sensor, which includes the chip described in the above embodiments.

[0094] ​The radar sensor is configured to transmit a frequency-modulated continuous wave signal based on a reference frequency via a transmitting antenna, receive a reflected echo wave formed by a target object via a receiving antenna, and generate and output an intermediate frequency signal based on the transmitted radio frequency signal.

[0095] Optionally, in some embodiments, the frequency-modulated continuous wave signal is a millimeter wave signal, so that the electronic device equipped with the radar sensor can be applied in the fields of autonomous driving, industrial automation, smart home appliances, security inspection, etc. The radar sensor can be an AiP millimeter wave radar sensor chip integrated with an antenna.

[0096] For example, the radar sensor generates a chirp signal in a preset continuous frequency modulation manner, obtains a radio frequency transmitting signal through frequency multiplication processing, and feeds the radio frequency transmitting signal to the transmitting antenna to transmit a corresponding probe signal wave. When the probe signal wave is reflected by an object, a reflected echo signal wave is formed. The receiving antenna converts the reflected echo signal wave into a radio frequency receiving signal. The radar sensor performs down-conversion, filtering, etc. on the radio frequency receiving signal using the radio frequency transmitting signal, and then performs analog-to-digital conversion processing to output a baseband digital signal representing the difference frequency between the probe signal wave and the reflected echo signal wave. Then, measurement information is extracted from the baseband digital signal through signal processing, and measurement data is output. The signal processing includes at least one of phase, frequency, time domain, etc. digital signal processing calculation based on at least one signal provided by at least one receiving antenna. The measurement data includes at least one of distance data representing the relative distance of at least one detected obstacle, speed data representing the relative speed of at least one detected obstacle, angle data representing the relative angle of at least one detected obstacle, etc.

[0097] In some embodiments, the present embodiment also provides an electronic device comprising the aforementioned chip or the aforementioned radar sensor.

[0098] In some embodiments, the electronic device comprises a device body and a radar sensor or the like electronic device as described in the above embodiments disposed on the device body. The device body is a structure for carrying and signal-connecting radio devices. The radio devices transmit and / or receive radio signals that have been phase-shifted by a phase shifter to achieve functions such as target detection and / or communication within a range of beam scanning, so as to provide the device body with detection target information and / or communication information, thereby assisting or even controlling the operation of the device body.

[0099] In some embodiments, the electronic device comprising the device body and the at least one wireless device described above can be components and products applied in fields such as smart home, transportation, smart home, consumer electronics, monitoring, industrial automation, cabin detection, and health care. For example, the device body can be a smart transportation device (such as a car, a bicycle, a motorcycle, a ship, a subway, a train, etc.), a security device (such as a camera), a liquid level / flow rate detection device, a smart wearable device (such as a bracelet, glasses, etc.), a smart home device (such as a sweeping robot, a door lock, a television, an air conditioner, a smart lamp, etc.), various communication devices (such as a mobile phone, a tablet computer, etc.), etc., and can also be various instruments for detecting vital sign parameters and various devices carrying the instruments, such as cabin detection of a car, indoor personnel monitoring, smart medical devices, consumer electronic devices, etc.

[0100] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure, as long as the combination does not result in contradictions.

[0101] Those skilled in the art can understand that the above-described embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. An electronic component packaging structure, characterized in that, Comprise: at least one rewiring layer, a dielectric layer and a parasitic antenna layer arranged in sequence; the electronic component couples radio frequency signals to the parasitic antenna layer through at least one of the rewiring layers; and / or, the parasitic antenna layer couples received spatial radiation signals to the electronic component after transmission through at least one of the rewiring layers; wherein the dielectric layer has a dielectric constant less than or equal to 0.02 F / m.

2. The electronic component package structure according to claim 1, wherein Further comprise: a plastic encapsulation layer, which is arranged in close contact with the at least one rewiring layer.

3. The electronic component package structure of claim 2, wherein The plastic encapsulation layer is arranged in close contact with the rewiring layer farthest from the dielectric layer, and the electronic component is located inside the plastic encapsulation layer, and the electronic component is connected to the rewiring layer through at least one bump.

4. The electronic component package structure according to claim 3, wherein Further comprise a plurality of solder balls and a plurality of metal pillars penetrating the plastic encapsulation layer, the plurality of solder balls being located on the side of the plastic encapsulation layer away from the dielectric layer, and the at least one rewiring layer being connected to the solder balls through the metal pillars.

5. The electronic component package structure of claim 2, wherein Further comprise: a solder resist layer, which is located on the surface of the rewiring layer farthest from the dielectric layer, and the electronic component is connected to the rewiring layer through the solder resist layer.

6. The electronic component package structure of claim 5, wherein The at least one rewiring layer is connected to the solder ball through the solder resist layer.

7. The electronic component package structure of claim 5, wherein The plastic encapsulation layer is located between two adjacent rewiring layers, and the plastic encapsulation layer has metal traces inside, which are used to connect the rewiring layers on both sides of the plastic encapsulation layer.

8. The electronic component package structure of claim 2, wherein The electronic component is located outside the plastic encapsulation layer.

9. The electronic component package structure of claim 2, wherein The material of the plastic encapsulation layer is plastic or glass.

10. The electronic component package structure according to any one of claims 1 to 9, wherein The material of the dielectric layer is silicon or glass.

11. An electronic component packaging structure, characterized in that, Comprise: a first electronic device, a second electronic device and a first insulating layer, a plastic encapsulation layer, a second insulating layer, a dielectric layer and a parasitic antenna layer arranged in sequence; the first electronic device and the second electronic device are arranged in a stack inside the plastic encapsulation layer, and the first insulating layer, the second insulating layer and the plastic encapsulation layer inside all have interconnected metal traces; The first electronic device is electrically connected to the metal traces through a bump, and is connected to a solder ball located on the surface of the first insulating layer through the metal traces, and the first electronic device couples radio frequency signals to the parasitic antenna layer through the metal traces; The second electronic device is electrically connected to the metal traces through a bump, and is connected to a solder ball located on the surface of the first insulating layer through the metal traces, and the second electronic device couples radio frequency signals to the parasitic antenna layer through the metal traces; wherein the dielectric layer has a dielectric constant less than or equal to 0.02 F / m.

12. A method of fabricating an electronic component package structure, characterized by: Comprise: providing a carrier plate, and sequentially forming a parasitic antenna layer, a dielectric layer and at least one rewiring layer on the first surface of the carrier plate; electrically connecting an electronic component to the rewiring layer through a bump; filling the electronic component with packaging material to form a plastic encapsulation layer; forming a plurality of metal pillars between the upper and lower surfaces of the plastic encapsulation layer, and connecting the rewiring layer to a solder ball located on the surface of the plastic encapsulation layer through the metal pillars; removing the carrier plate; wherein the dielectric layer has a dielectric constant less than or equal to 0.02 F / m.

13. A chip, characterized by The chip is packaged with the electronic component packaging structure according to any one of claims 1-11.

14. A radar sensor, characterized by Comprise the chip according to claim 13.

15. An electronic device, comprising: The chip according to claim 13, or the radar sensor according to claim 14.

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