Packaging structure and forming method thereof

Abstract

The invention provides a packaging structure and a forming method thereof, in the packaging structure, the back surface of a bridging chip is connected with the front surface of a bottom re-wiring layer through a first bonding structure, the first bonding structure is an organic and inorganic mixed bonding structure or an organic mixed bonding structure, and the first bonding structure is connected with the bottom re-wiring layer through a second bonding structure. And / or the front surface of the bridging chip is connected with the back surface of the top rewiring layer through a second bonding structure, the second bonding structure is an organic hybrid bonding structure, and the bridging chip does not need to be connected with the bottom rewiring layer or the top rewiring layer through soldering tin, so that defects such as cavities or cracks of welding points do not exist, and the reliability of the bridging chip is improved. Therefore, the reliability problem of the packaging structure is solved, and the packaging structure provided by the invention has good reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular to a packaging structure and a forming method thereof. BACKGROUND

[0002] Advanced packaging is a new type of electronic packaging technology, which aims to integrate multiple chips or other electronic components together with higher integration, smaller size, lower power consumption and higher reliability through innovative technical means.

[0003] Embedded Multi-die Interconnect Bridge (EMIB) is a form of advanced packaging, which realizes the interconnection of various functional chips by embedding a bridge chip (Si Bridge Die) in the packaging substrate. The bridge chip has a wiring layer, which can provide an electrical connection path between functional chips to realize high-bandwidth and low-latency chip communication.

[0004] Advanced packaging in the form of embedded silicon bridge can be divided into die last and die first according to the process. The die last process is to first form a wiring interposer containing a bridge chip, and then put the functional chip on it after testing. The die first process is to first put the functional chip, and then form a wiring interposer containing a bridge chip. In the die last process, the back of the bridge chip is connected to the wiring layer on the surface of the packaging substrate through micro-bumps and soldering, and in the die first process, the front of the bridge chip is connected to the wiring layer on the surface of the functional chip through micro-bumps and soldering. However, during the packaging process of the packaging structure, the soldering points of the bridge chip are prone to voids and cracks after multiple medium layer deposition and re-wiring layer formation, as well as various packaging processes of the packaging structure, which causes reliability problems of the packaging structure.

[0005] Therefore, how to improve the reliability of the advanced packaging structure of the embedded silicon bridge has become the focus of current research. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a packaging structure and a forming method thereof, which can improve the reliability of the packaging structure.

[0007] To solve the above problems, the application provides a packaging structure, comprising a wiring insertion layer, the wiring insertion layer comprising: a bottom redistribution layer; a top redistribution layer, oppositely arranged with the bottom redistribution layer; a buried layer arranged between the bottom redistribution layer and the top redistribution layer, the buried layer comprising a bridge chip, the back surface of the bridge chip being connected with the front surface of the bottom redistribution layer through a first bonding structure, the first bonding structure being an organic and inorganic mixed bonding structure or an organic mixed bonding structure, and / or the front surface of the bridge chip being connected with the back surface of the top redistribution layer through a second bonding structure, the second bonding structure being an organic mixed bonding structure.

[0008] In an embodiment, a first organic interconnection layer is arranged on the surface of the bottom redistribution layer, the first organic interconnection layer comprising a first organic medium layer and a first conductive circuit, the bridge chip comprising a substrate, a through-silicon via penetrating through the substrate, and a first inorganic medium layer arranged on the back surface of the substrate, the through-silicon via protruding from the back surface of the substrate and having an end portion flush with the surface of the first inorganic medium layer, the first organic medium layer being bonded and connected with the first inorganic medium layer, and the end portion of the through-silicon via being bonded and connected with the first conductive circuit, so as to serve as the first bonding structure.

[0009] In an embodiment, the first inorganic medium layer is composed of a single-layer inorganic medium layer or a multi-layer inorganic medium layer.

[0010] In an embodiment, a second organic interconnection layer is arranged on the front surface of the bottom redistribution layer, the second organic interconnection layer comprising a second organic medium layer and a second conductive circuit, and a third organic interconnection layer is arranged on the back surface of the bridge chip, the third organic interconnection layer comprising a third organic medium layer and a third conductive circuit layer, the second organic medium layer being bonded and connected with the third organic medium layer, and the second conductive circuit layer being bonded and connected with the third conductive circuit layer, so as to serve as the first bonding structure.

[0011] In an embodiment, the bridge chip comprises a substrate, a through-silicon via penetrating through the substrate, and a second inorganic medium layer arranged on the back surface of the substrate, the through-silicon via protruding from the back surface of the substrate and having an end portion flush with the surface of the second inorganic medium layer, the third organic interconnection layer being arranged on the second inorganic medium layer, and the third conductive circuit being connected with the end portion of the through-silicon via.

[0012] In an embodiment, when the back surface of the bridge chip is connected with the front surface of the bottom redistribution layer through the first bonding structure, the top redistribution layer is formed on the front surface of the bridge chip by a redistribution process, and the front surface of the bridge chip is electrically connected with the top redistribution layer.

[0013] In an embodiment, the bridge chip comprises a substrate, a through-silicon via penetrating through the substrate, and an internal redistribution layer disposed on the front surface of the substrate, the internal redistribution layer being electrically connected with the top redistribution layer.

[0014] In an embodiment, the internal redistribution layer is provided with a conductive column, one end of the conductive column being electrically connected with the internal redistribution layer, and the other end being electrically connected with the top redistribution layer.

[0015] In an embodiment, a fourth organic interconnection layer is disposed on the back surface of the top redistribution layer, the fourth organic interconnection layer comprising a fourth organic medium layer and a fourth conductive circuit layer, a fifth organic interconnection layer is disposed on the front surface of the bridge chip, the fifth organic interconnection layer comprising a fifth organic medium layer and a fifth conductive circuit layer, the fourth organic medium layer being bonded with the fifth organic medium layer, and the fourth conductive circuit layer being bonded with the fifth conductive circuit layer, so as to serve as the second bonding structure.

[0016] In an embodiment, the bridge chip comprises a substrate and a through-silicon via penetrating through the substrate, and the front surface of the substrate is provided with an internal redistribution layer, and the fifth organic interconnection layer is disposed on the internal redistribution layer.

[0017] In an embodiment, when the front surface of the bridge chip is connected with the back surface of the top redistribution layer through the second bonding structure, the back surface of the substrate is provided with a micro bump, one side of the micro bump being connected with the end surface of the through-silicon via, and the other side being connected with the bottom redistribution layer.

[0018] In an embodiment, the back surface of the substrate is provided with a third inorganic medium layer, the through-silicon via protrudes from the back surface of the substrate, and the end thereof is flush with the surface of the third inorganic medium layer.

[0019] In an embodiment, the buried layer further comprises a first plastic encapsulation layer, the first plastic encapsulation layer encapsulating the side surface of the bridge chip, the bottom redistribution layer is further disposed on the back surface of the first plastic encapsulation layer, and the top redistribution layer is further disposed on the front surface of the first plastic encapsulation layer.

[0020] In an embodiment, the buried layer further comprises a metal column, the metal column penetrating through the first plastic encapsulation layer, the back surface of the metal column being connected with the bottom redistribution layer, and the front surface of the metal column being connected with the top redistribution layer.

[0021] In an embodiment, the material of the first plastic encapsulation layer is silicon oxide or silicon nitride.

[0022] In an embodiment, the bridge chip comprises a substrate and a through-silicon via penetrating through the substrate, and the side surface of the through-silicon via is provided with a passivation layer.

[0023] In an embodiment, the bridge chip further comprises a deep trench capacitor, which is disposed in the base.

[0024] In an embodiment, the package structure further comprises a chip package assembly, which is disposed on the front surface of the top redistribution layer.

[0025] In an embodiment, the chip package assembly comprises: a top device, which is disposed on the front surface of the top redistribution layer and electrically connected with the top redistribution layer; and a second plastic encapsulation layer, which encapsulates the top device.

[0026] In an embodiment, the package structure further comprises a conductive connection structure, which is disposed on the back surface of the bottom redistribution layer and electrically connected with the bottom redistribution layer.

[0027] In an embodiment, when the front surface of the bridge chip is connected with the back surface of the top redistribution layer through a second bonding structure, the back surface of the bridge chip is connected with the front surface of the bottom redistribution layer through a first bonding structure.

[0028] The present application also provides a method for forming a package structure, comprising: forming one of a bottom redistribution layer or a top redistribution layer; forming a buried layer on the bottom redistribution layer or the top redistribution layer, the buried layer comprising a bridge chip, the back surface of the bridge chip being connected with the front surface of the bottom redistribution layer through a first bonding structure, the first bonding structure being an organic and inorganic hybrid bonding structure or an organic hybrid bonding structure, or the front surface of the bridge chip being connected with the back surface of the top redistribution layer through a second bonding structure, the second bonding structure being an organic hybrid bonding structure; and forming the other of the bottom redistribution layer or the top redistribution layer on the buried layer.

[0029] In one embodiment, in the step of forming one of the bottom redistribution layer or the top redistribution layer, forming the bottom redistribution layer, the step of forming the buried layer on the bottom redistribution layer comprises: forming a first organic interconnection layer on the bottom redistribution layer, the first organic interconnection layer comprising a first organic dielectric layer and a first conductive line; bonding the bridge chip with the first organic interconnection layer, the bridge chip comprising a substrate, a through-silicon via penetrating through the substrate, and a first inorganic dielectric layer disposed on the back surface of the substrate, the through-silicon via of the bridge chip protruding from the back surface of the substrate and having an end portion flush with the surface of the first inorganic dielectric layer, the first organic dielectric layer being bonded with the first inorganic dielectric layer, and the end portion of the through-silicon via being bonded with the first conductive line as the first bonding structure; in the step of forming the other one of the bottom redistribution layer or the top redistribution layer on the buried layer, forming the top redistribution layer on the buried layer.

[0030] In one embodiment, the step of forming the first organic interconnection layer on the bottom redistribution layer comprises: forming the first organic dielectric layer on the front surface of the bottom redistribution layer by using a spin coating process; exposing and developing the first organic dielectric layer by using a photolithographic mask to form the first via; forming a first barrier layer covering the inner wall of the first via on the first via; filling a conductive material to form a first initial structure, the first initial structure filling the first via and covering the surface of the first organic dielectric layer; and thinning the first initial structure to form the first conductive line.

[0031] In one embodiment, the step of forming the first organic interconnection layer on the bottom redistribution layer further comprises thinning the first organic dielectric layer so that the first conductive line protrudes from the first organic dielectric layer.

[0032] In one embodiment, in the step of forming one of the bottom redistribution layer or the top redistribution layer, forming the bottom redistribution layer, the step of forming the buried layer on the bottom redistribution layer comprises: forming a second organic interconnection layer on the bottom redistribution layer, the second organic interconnection layer comprising a second organic dielectric layer and a second conductive line; forming a third organic interconnection layer on the back surface of the bridge chip, the third organic interconnection layer comprising a third organic dielectric layer and a third conductive line layer; bonding the third organic interconnection layer with the second organic interconnection layer, the second organic dielectric layer being bonded with the third organic dielectric layer, and the second conductive line layer being bonded with the third conductive line layer as the first bonding structure; in the step of forming the other one of the bottom redistribution layer or the top redistribution layer on the buried layer, forming the top redistribution layer on the buried layer.

[0033] In an embodiment, the step of forming a second organic interconnection layer on the bottom redistribution layer includes: forming the second organic dielectric layer on the front surface of the bottom redistribution layer by using a spin coating process; forming the second via by exposing and developing the second organic dielectric layer using a photomask; forming a second barrier layer covering the inner wall of the second via; filling the second via with a conductive material to form a second initial structure, which fills the second via and covers the surface of the second organic dielectric layer; thinning the second initial structure to form the second conductive line; the step of forming a third organic interconnection layer on the back surface of the bridge chip includes: forming the third organic dielectric layer on the back surface of the bridge chip by using a spin coating process; forming the third via by exposing and developing the third organic dielectric layer using a photomask; forming a third barrier layer covering the inner wall of the third via; filling the third via with a conductive material to form a third initial structure, which fills the third via and covers the surface of the third organic dielectric layer; thinning the third initial structure to form the third conductive line.

[0034] In an embodiment, the step of forming a second organic interconnection layer on the bottom redistribution layer further includes thinning the second organic dielectric layer so that the second conductive line protrudes from the second organic dielectric layer; the step of forming a third organic interconnection layer on the back surface of the bridge chip further includes thinning the third organic dielectric layer so that the third conductive line protrudes from the third organic dielectric layer.

[0035] In an embodiment, the step of forming a buried layer on the bottom redistribution layer further includes: plastic packaging to form a first plastic packaging layer, which covers the side surface of the bridge chip; and forming the top redistribution layer on the first plastic packaging layer and the bridge chip.

[0036] In an embodiment, the step of plastic packaging is further preceded by: forming a metal pillar on the bottom redistribution layer; in the step of plastic packaging, the first plastic packaging layer also covers the metal pillar, and the front surface of the metal pillar is exposed on the front surface of the first plastic packaging layer; in the step of forming the top redistribution layer, the top redistribution layer is connected to the front surface of the metal pillar.

[0037] In an embodiment, the step of forming the top redistribution layer on the first plastic packaging layer includes: forming a dielectric layer and a conductive line in the dielectric layer on the first plastic packaging layer and the bridge chip.

[0038] In one embodiment, in the step of forming one of the bottom redistribution layer or the top redistribution layer, the step of forming the top redistribution layer, the step of forming the buried layer on the top redistribution layer comprises: forming a fourth organic interconnection layer on the top redistribution layer, the fourth organic interconnection layer comprising a fourth organic dielectric layer and a fourth conductive line layer; forming a fifth organic interconnection layer on the front surface of the bridge chip, the fifth organic interconnection layer comprising a fifth organic dielectric layer and a fifth conductive line layer; bonding the fourth organic interconnection layer and the fifth organic interconnection layer, the fourth organic dielectric layer and the fifth organic dielectric layer being bonded, the fourth conductive line layer and the fifth conductive line layer being bonded, to form the second bonding structure; in the step of forming the other one of the bottom redistribution layer or the top redistribution layer on the buried layer, the bottom redistribution layer is formed on the buried layer.

[0039] In one embodiment, the step of forming the fourth organic interconnection layer on the top redistribution layer comprises: forming the fourth organic dielectric layer on the back surface of the top redistribution layer by using a spin coating process; exposing and developing the fourth organic dielectric layer by using a photomask to form the fourth via hole; forming a fourth barrier layer covering the inner wall of the fourth via hole on the fourth via hole; filling the fourth via hole with a conductive material to form a fourth initial structure, the fourth initial structure filling the fourth via hole and covering the surface of the fourth organic dielectric layer; thinning the fourth initial structure to form the fourth conductive line; the step of forming the fifth organic interconnection layer on the front surface of the bridge chip comprises: forming the fifth organic dielectric layer on the front surface of the bridge chip by using a spin coating process; exposing and developing the fifth organic dielectric layer by using a photomask to form the fifth via hole; forming a fifth barrier layer covering the inner wall of the fifth via hole on the fifth via hole; filling the fifth via hole with a conductive material to form a fifth initial structure, the fifth initial structure filling the fifth via hole and covering the surface of the fifth organic dielectric layer; thinning the fifth initial structure to form the fifth conductive line.

[0040] In one embodiment, the step of forming the fourth organic interconnection layer on the top redistribution layer further comprises: thinning the fourth organic dielectric layer so that the fourth conductive line protrudes from the fourth organic dielectric layer; the step of forming the fifth organic interconnection layer on the front surface of the bridge chip further comprises: thinning the fifth organic dielectric layer so that the fifth conductive line protrudes from the fifth organic dielectric layer.

[0041] In one embodiment, the bridge chip comprises a substrate and a through silicon via penetrating through the substrate, and an internal redistribution layer is arranged on the front surface of the substrate, and the step of forming the fifth organic interconnection layer on the front surface of the bridge chip comprises: forming the fifth organic interconnection layer on the internal redistribution layer.

[0042] In one embodiment, the back surface of the substrate is provided with micro-bumps, and the micro-bumps are connected with the end surface of the through silicon via. In the step of forming the bottom redistribution layer on the buried layer, the bottom redistribution layer is connected with the micro-bumps.

[0043] In one embodiment, the step of forming the buried layer on the top redistribution layer further comprises: plastic packaging to form a first plastic packaging layer, the first plastic packaging layer covering the bridge chip side surface; and forming the bottom redistribution layer on the first plastic packaging layer and the bridge chip.

[0044] In one embodiment, the step of plastic packaging is further preceded by: forming a metal column on the top redistribution layer; in the step of plastic packaging, the first plastic packaging layer also covers the metal column, and the end surface of the metal column is exposed on the back surface of the first plastic packaging layer; and in the step of forming the bottom redistribution layer, the bottom redistribution layer is connected with the end surface of the metal column.

[0045] In one embodiment, the step of forming the bottom redistribution layer on the first plastic packaging layer and the bridge chip comprises: forming a dielectric layer and a conductive circuit in the dielectric layer on the first plastic packaging layer and the bridge chip.

[0046] In one embodiment, the bonding process for forming the first bonding structure or the second bonding structure comprises: ion beam or plasma treatment on the bonding surface to activate the bonding surface.

[0047] In one embodiment, the packaging structure further comprises a chip packaging assembly, the chip packaging assembly comprising: a top device arranged on the front surface of the top redistribution layer, and the top device being electrically connected with the top redistribution layer; and a second plastic packaging layer covering the top device. The step of forming one of the bottom redistribution layer or the top redistribution layer further comprises: forming the top redistribution layer on the chip packaging assembly; or the step of forming the other of the bottom redistribution layer or the top redistribution layer on the buried layer further comprises: forming the bottom redistribution layer or the top redistribution layer on the buried layer, and the chip packaging assembly being arranged on the top redistribution layer.

[0048] In one embodiment, the forming method further comprises: forming a conductive connection structure on the bottom redistribution layer, the conductive connection structure being arranged on the back surface of the bottom redistribution layer and being electrically connected with the bottom redistribution layer.

[0049] In the packaging structure and its forming method provided in the specific embodiments of the present invention, the back side of the bridging chip is connected to the front side of the bottom redistribution layer through a first bonding structure, which is an organic-inorganic hybrid bonding structure or an organic hybrid bonding structure; or the front side of the bridging chip is connected to the back side of the top redistribution layer through a second bonding structure, which is an organic hybrid bonding structure. The bridging chip does not need to be connected to the bottom redistribution layer or the top redistribution layer by solder, so there is no reliability problem of the packaging structure caused by defects (voids or cracks) at the solder joints. The packaging structure provided in the specific embodiments of the present invention has good reliability.

[0050] If the bridging chip is connected to the bottom or top redistribution layer via solder, microbumps need to be formed on the top or bottom surface of the bridging chip. The microbumps are then soldered to the bottom or top redistribution layer. The critical dimensions of the microbumps, the spacing between two adjacent microbumps, and the distance between the bridging chip and the bottom or top redistribution layer cannot be too small, otherwise the connection requirements of the microbumps cannot be met.

[0051] In the packaging structure provided by the specific embodiments of the present invention, the bridging chip does not need to be soldered to the bottom redistribution layer or the top redistribution layer through microbumps. Instead, it is bonded to the bottom redistribution layer or the top redistribution layer through an organic-inorganic hybrid bonding structure or an organic hybrid bonding structure. The key dimensions and spacing of the conductive structures in the organic-inorganic hybrid bonding structure or the organic hybrid bonding structure are smaller, which can increase the number and density of I / O, thus enabling denser I / O interconnection.

[0052] Organic-inorganic hybrid bonding structures or organic-inorganic hybrid bonding structures can effectively reduce the distance between the bridging chip and the bottom or top redistribution layer, which is beneficial to further reduce the thickness of the wiring insertion layer, reduce the warpage of the wiring insertion layer, and avoid the warpage of the wiring insertion layer affecting the manufacturing process.

[0053] Furthermore, the use of a hybrid organic and inorganic bonding structure eliminates the need for molding compound between the bridging chip and the bottom or top redistribution layer. Heat conduction between the bridging chip and the bottom or top redistribution layer occurs through the conductive lines in the hybrid organic and inorganic bonding structure, further improving the heat dissipation performance of the packaging structure.

[0054] Compared with the inorganic hybrid bonding structure between the bridge chip and the bottom redistribution layer or the top redistribution layer, the packaging structure provided by the embodiment of the application has a simple manufacturing process flow, low manufacturing cost, relatively low bonding surface cleanliness requirement, no need for high-temperature annealing after bonding, no influence on the device of the packaging structure, and high reliability of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0056] Figure 1 is a schematic diagram of the packaging structure provided by the first embodiment of the application;

[0057] Figure 2 is a schematic diagram of the packaging structure provided by the second embodiment of the application;

[0058] Figure 3 is a schematic diagram of the packaging structure provided by the third embodiment of the application;

[0059] Figure 4 is a schematic diagram of the forming method of the packaging structure provided by some embodiments of the application;

[0060] Figure 5 is a schematic diagram of the forming of the bottom redistribution layer in the forming method of the packaging structure provided by the fourth embodiment of the application;

[0061] Figure 6 is a schematic diagram of the forming of the first organic medium layer on the bottom redistribution layer in the forming method of the packaging structure provided by the fourth embodiment of the application;

[0062] Figure 7 is a schematic diagram of the forming of the first via hole in the first organic medium layer in the forming method of the packaging structure provided by the fourth embodiment of the application;

[0063] Figure 8 is a schematic diagram of the forming of the first barrier layer in the first via hole in the forming method of the packaging structure provided by the fourth embodiment of the application;

[0064] Figure 9 is a schematic diagram of the forming of the first initial structure in the first via hole in the forming method of the packaging structure provided by the fourth embodiment of the application;

[0065] Figure 10is a schematic view of forming a first organic interconnection layer on the front surface of the bottom redistribution layer in the method for forming the packaging structure provided in the fourth specific embodiment of the present application;

[0066] Figure 11 is a schematic view of bonding the bridge chip with the first organic interconnection layer in the method for forming the packaging structure provided in the fourth specific embodiment of the present application;

[0067] Figure 12 is a schematic view of forming a first plastic encapsulation layer in the method for forming the packaging structure provided in the fourth specific embodiment of the present application;

[0068] Figure 13 is a schematic view of forming a top redistribution layer in the method for forming the packaging structure provided in the fourth specific embodiment of the present application;

[0069] Figure 14 is a schematic view of forming a chip packaging assembly in the method for forming the packaging structure provided in the fourth specific embodiment of the present application;

[0070] Figure 15 is a schematic view of forming a bottom redistribution layer and bonding the bridge chip with the bottom redistribution layer in the method for forming the packaging structure provided in the fifth specific embodiment of the present application;

[0071] Figure 16 is a schematic view of forming a first plastic encapsulation layer in the method for forming the packaging structure provided in the fifth specific embodiment of the present application;

[0072] Figure 17 is a schematic view of forming a top redistribution layer in the method for forming the packaging structure provided in the sixth specific embodiment of the present application;

[0073] Figure 18 is a schematic view of forming a fourth organic interconnection layer on the back surface of the top redistribution layer in the method for forming the packaging structure provided in the sixth specific embodiment of the present application;

[0074] Figure 19 is a schematic view of forming a fifth organic interconnection layer on the back surface of the bridge chip in the method for forming the packaging structure provided in the sixth specific embodiment of the present application;

[0075] Figure 20 is a schematic view of bonding the bridge chip with the top redistribution layer in the method for forming the packaging structure provided in the sixth specific embodiment of the present application;

[0076] Figure 21 is a schematic view of forming a first plastic encapsulation layer in the method for forming the packaging structure provided in the sixth specific embodiment of the present application;

[0077] Figure 22is a schematic view of forming the bottom redistribution layer in the forming method of the package structure provided in the sixth embodiment of the present application. DETAILED DESCRIPTION

[0078] The package structure and the forming method thereof provided in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0079] Figure 1 is a schematic view of the package structure provided in the first embodiment of the present application, please refer to Figure 1 , the package structure includes a wiring insertion layer 1, the wiring insertion layer 1 includes a bottom redistribution layer 10, a top redistribution layer 20 and a buried layer 30. The top redistribution layer 20 is arranged opposite to the bottom redistribution layer 10; the buried layer 30 is arranged between the bottom redistribution layer 10 and the top redistribution layer 20, the buried layer 30 includes a bridge chip 300, the back surface of the bridge chip 300 is connected with the front surface of the bottom redistribution layer 10 through a first bonding structure 40, the first bonding structure 40 is an organic and inorganic hybrid bonding structure or an organic hybrid bonding structure, the front surface of the bridge chip 300 is electrically connected with the back surface of the top redistribution layer 20.

[0080] The bottom redistribution layer 10 includes a dielectric layer 100 and a conductive circuit 110 in the dielectric layer 100, the conductive circuit 110 can be a plating circuit formed by sputtering and / or plating, the material of the dielectric layer 100 can be a high polymer material such as polystyrene butyl (PBO) and polyimide (PI) to further relieve stress. The plating circuit refers to a bump formed by a plating process. The bottom redistribution layer 10 includes a front surface and a back surface arranged opposite to each other, the back surface of the bridge chip 300 is connected with the front surface of the bottom redistribution layer 10.

[0081] Further, in the first embodiment, the package structure further includes a conductive connection structure 2, the conductive connection structure 2 is arranged on the back surface of the bottom redistribution layer 10 and is electrically connected with the bottom redistribution layer 10, the bottom redistribution layer 10 is electrically connected with a package substrate and other structures through the conductive connection structure 2. In some embodiments, the conductive connection structure 2 includes but is not limited to a controllable collapse chip connection bump (C4).

[0082] The top redistribution layer 20 is arranged opposite to the bottom redistribution layer 10. Further, the top redistribution layer 20 comprises a dielectric layer 200 and a conductive circuit 210 in the dielectric layer 200. The conductive circuit 210 can be a sputtered circuit and / or an electroplated circuit. The material of the dielectric layer 200 can be a high polymer material such as PBO, PI, etc. to further relieve stress. The electroplated circuit refers to a metal circuit and a connecting bump formed by an electroplating process. The top redistribution layer 20 comprises a front surface and a back surface arranged opposite to each other. The bridge chip 300 is connected to the back surface of the top redistribution layer 20.

[0083] Further, in the first specific embodiment, the packaging structure further comprises a chip packaging assembly 3 arranged on the front surface of the top redistribution layer 20. The chip packaging assembly 3 comprises a top device 31 and a second encapsulation layer 32. The top device 31 is arranged on the front surface of the top redistribution layer 20 and electrically connected to the top redistribution layer 20. The second encapsulation layer 32 encapsulates the top device 31. The top device 31 can be flip-chip arranged on the top redistribution layer 20. The top device 31 can be a SOC device, etc. Further, in the first specific embodiment, the chip packaging assembly 3 further comprises a top solder pad 33 arranged on the front surface of the top redistribution layer 20 and connected to the top redistribution layer 20. The top device 31 is connected to the top solder pad 33. Further, in the first specific embodiment, the packaging structure further comprises a filling layer 34 filled between the bottom of the top device 31 and the top redistribution layer 20. The filling layer 34 is used to protect the conductive structure of the top device 31 and the top solder pad 33. The second encapsulation layer 32 covers the top device 31, the surface of the top redistribution layer 20 and the surface of the filling layer 34.

[0084] The buried layer 30 is arranged between the bottom redistribution layer 10 and the top redistribution layer 20 and used as a connecting layer between the top redistribution layer 20 and the bottom redistribution layer 10. The buried layer 30 comprises the bridge chip 300. The back surface of the bridge chip 300 is connected to the front surface of the bottom redistribution layer 10 through a first bonding structure 40. The first bonding structure 40 is an organic and inorganic hybrid bonding structure or an organic hybrid bonding structure. The front surface of the bridge chip 300 is electrically connected to the back surface of the top redistribution layer 20.

[0085] Further, in the first embodiment, the buried layer 30 further comprises a first encapsulation layer 310, the first encapsulation layer 310 encapsulates the side of the bridge chip 300, the bottom redistribution layer 10 is further disposed on the back of the first encapsulation layer 310, and the top redistribution layer 20 is further disposed on the front of the first encapsulation layer 310. The first encapsulation layer 310 protects the bridge chip 300 and supports the bottom redistribution layer 10 and the top redistribution layer 20.

[0086] Further, in the first embodiment, the material of the first encapsulation layer 310 is silicon oxide or silicon nitride, or a resin system encapsulation material such as polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. Silicon oxide or silicon nitride has better wettability with the dielectric layer 100 (e.g., polyimide) of the bottom redistribution layer 10 and the dielectric layer 200 (e.g., polyimide) of the top redistribution layer 20, which can improve the adhesion between the first encapsulation layer 310 and the dielectric layer 100 of the bottom redistribution layer 10 and the dielectric layer 200 of the top redistribution layer 20, and improve the reliability of the packaging structure. Moreover, using silicon oxide or silicon nitride as the material of the first encapsulation layer 310, when the metal structure (e.g., the metal pillar 320 or the conductive pillar 306) encapsulated by the first encapsulation layer 310 is exposed, a chemical mechanical polishing process can be used to make the surface of the metal structure and the surface of the first encapsulation layer 310 more flat, which is beneficial to improving the yield of the bottom redistribution layer 10 or the top redistribution layer 20 formed on the surface of the first encapsulation layer 310.

[0087] Further, in the first embodiment, the buried layer 30 further comprises a metal pillar 320, the metal pillar 320 penetrates the first encapsulation layer 310, the back of the metal pillar 320 is flush with the back of the first encapsulation layer 310, the front of the metal pillar 320 is flush with the front of the first encapsulation layer 310, the back of the metal pillar 320 is connected to the bottom redistribution layer 10, and the front of the metal pillar 320 is connected to the top redistribution layer 20. The packaging structure can comprise a plurality of bridge chips 300 and a plurality of metal pillars 320, the metal pillars 320 are distributed around the bridge chips 300 and between two adjacent bridge chips 300.

[0088] Further, the bridge chip 300 comprises a substrate 301 and a through-silicon via 302 penetrating the substrate 301. In some embodiments, the substrate 301 is a silicon substrate 301, and the through-silicon via 302 is a copper pillar. Further, in the first embodiment, the through-silicon via 302 is provided with a passivation layer 303 on the side surface thereof, the passivation layer 303 being used to isolate the through-silicon via 302 from the substrate 301 to avoid diffusion of metal ions in the through-silicon via 302 into the substrate 301, the passivation layer 303 comprising but not limited to silicon oxide, silicon nitride, and combinations thereof. In the first embodiment, the bridge chip 300 further comprises a deep trench capacitor (DTC) 304, which is arranged in the substrate 301. In the first embodiment, the deep trench capacitor 304 extends from the front surface of the substrate 301 into the substrate 301.

[0089] Further, in the first embodiment, the bridge chip 300 further comprises an internal redistribution layer 305 arranged on the front surface of the substrate 301, the internal redistribution layer 305 being electrically connected to the top redistribution layer 20, and the first encapsulation layer 310 further encapsulating the side surface of the internal redistribution layer 305. The internal redistribution layer 305 comprises a dielectric layer and a conductive circuit in the dielectric layer, one side of the conductive circuit being electrically connected to the front surface of the through-silicon via 302, and the other side being electrically connected to the back surface of the top redistribution layer 20.

[0090] Further, in the first embodiment, the internal redistribution layer is provided with a conductive pillar 306 on the surface thereof. One end of the conductive pillar 306 is electrically connected to the internal redistribution layer 305, specifically, the one end of the conductive pillar 306 is connected to the conductive circuit of the internal redistribution layer 305. The other end of the conductive pillar 306 is electrically connected to the top redistribution layer 20. The first encapsulation layer 310 encapsulates the side surface of the conductive pillar 306, and the surface of the conductive pillar 306 away from the substrate 301 is flush with the front surface of the first encapsulation layer 310. The conductive pillar 306 comprises but not limited to a copper pillar. A plurality of the conductive pillars 306 are arranged in an array on the surface of the internal redistribution layer 305.

[0091] In the first embodiment, the back surface of the bridge chip 300 is connected with the front surface of the bottom redistribution layer 10 through the first bonding structure 40, which is an organic and inorganic hybrid bonding structure. The back surface of the bridge chip 300 does not need to be connected with the bottom redistribution layer 10 through soldering, so there is no problem of reliability of the packaging structure caused by defects (holes or cracks) of the soldering points. The packaging structure provided in the embodiment has good reliability. Moreover, the organic and inorganic hybrid bonding structure can effectively reduce the distance between the bridge chip 300 and the bottom redistribution layer 10 or the top redistribution layer 20, which is conducive to further reducing the thickness of the wiring insertion layer 1 and reducing the warping of the wiring insertion layer 1, thereby avoiding the influence of the warping of the wiring insertion layer 1 on the process operation. The key size and pitch of the conductive structure in the organic and inorganic hybrid bonding structure are relatively small, which can improve the number and density of I / O, so that more intensive I / O interconnection can be achieved.

[0092] Further, in the first embodiment, the first plastic sealing layer 310 covers the side surface of the first bonding structure 40 and does not fill between the back surface of the bridge chip 300 and the bottom redistribution layer 10. The bridge chip 300 and the bottom redistribution layer 10 are in thermal conduction through the conductive lines in the organic and inorganic hybrid bonding structure, which further improves the heat dissipation performance of the packaging structure. Moreover, since there is no first plastic sealing layer 310 between the bridge chip 300 and the bottom redistribution layer 10, the risk of incomplete filling of the back surface of the bridge chip 300 can be avoided, and the embedding design of thinner bridge chips 300 of different sizes can be met.

[0093] Further, in the first embodiment, a first organic interconnection layer 400 is arranged on the surface of the bottom redistribution layer 10, and the first organic interconnection layer 400 includes a first organic medium layer 401 and a first conductive line 402. In some embodiments, the first organic interconnection layer 400 is an organic Damascene structure formed by a Damascene process. In some embodiments, the first organic medium layer 401 can be a polyimide (PI) layer or other organic material layer, such as Benzo Cyclo Butene (BCB) or Poly Benz Oxazole (PBO), etc. The first conductive line 402 is arranged in the first organic medium layer 401, and the first conductive line 402 is respectively electrically connected with the end of the bottom redistribution layer 10 and the through silicon via 302 of the bridge chip 300.

[0094] Further, in the first embodiment, the bridge chip 300 comprises a substrate 301, a through silicon via 302 penetrating the substrate 301, and a first inorganic dielectric layer 3071 disposed on the back surface of the substrate 301. The through silicon via 302 protrudes from the back surface of the substrate 301, and the end thereof is flush with the surface of the first inorganic dielectric layer 3071. The first inorganic dielectric layer 3071 covers the surface of the substrate 301. In the process of thinning the through silicon via 302 on the back surface of the bridge chip 300, the first inorganic dielectric layer 3071 can protect the substrate 301, and the migration and diffusion of metal ions generated in the process of thinning the through silicon via 302 into the substrate 301 can be avoided. In some embodiments, the first inorganic dielectric layer 3071 is composed of a single inorganic dielectric layer or multiple inorganic dielectric layers.

[0095] Further, in the first embodiment, the first organic dielectric layer 401 is bonded to the first inorganic dielectric layer 3071, and the end of the through silicon via 302 is bonded to the first conductive circuit 402, forming an organic and inorganic hybrid bonding structure as the first bonding structure 40. The first inorganic dielectric layer 3071 is an inorganic dielectric layer used to protect the substrate 301 when the bridge chip 300 is formed. Therefore, the packaging structure provided by the embodiments of the present application does not need to separately form an inorganic bonding layer on the back surface of the bridge chip 300 for bonding with the first organic interconnection layer 400, avoiding the multiple etching processes and the process of removing photoresist when forming the inorganic bonding layer, and greatly simplifying the manufacturing process.

[0096] Further, in the first embodiment, when the first bonding structure 40 is an organic and inorganic hybrid bonding structure, the top redistribution layer 20 is formed on the front surface of the bridge chip 300 by a redistribution process, and the front surface of the bridge chip 300 is electrically connected to the top redistribution layer 20. Specifically, in an embodiment, the conductive pillar 306 on the front surface of the bridge chip 300 is electrically connected to the top redistribution layer 20. The front surface of the bridge chip 300 does not need to be connected to the top redistribution layer 20 by soldering, and therefore there is no problem of reliability of the packaging structure caused by defects (holes or cracks) of the soldering points. The packaging structure provided by the embodiments of the present application has good reliability.

[0097] Figure 2 is a schematic diagram of the packaging structure provided by the second embodiment of the present application. Please refer to Figure 2The second embodiment differs from the first embodiment in that the first bonding structure 40 is different. Specifically, in the second embodiment, the back surface of the bridge chip 300 is connected to the front surface of the bottom redistribution layer 10 through the first bonding structure 40, which is an organic hybrid bonding structure. The back surface of the bridge chip 300 does not need to be connected to the bottom redistribution layer 10 through soldering, so there is no problem of reliability of the packaging structure caused by defects (holes or cracks) of the soldering points. The packaging structure provided in the embodiment has good reliability. At the same time, the organic hybrid bonding structure can effectively reduce the distance between the bridge chip 300 and the bottom redistribution layer 10 or the top redistribution layer 20, which is conducive to further reducing the thickness of the wiring insertion layer 1, reducing the warping of the wiring insertion layer 1, and avoiding the influence of the warping of the wiring insertion layer 1 on the process operation. The critical dimensions and pitches of the conductive structures in the organic hybrid bonding structure are relatively small, which can improve the number and density of I / O, so more intensive I / O interconnection can be achieved. The first encapsulation layer 310 is not filled between the back surface of the bridge chip 300 and the bottom redistribution layer 10, and the bridge chip 300 and the bottom redistribution layer 10 are connected through the conductive lines in the organic hybrid bonding structure for heat conduction, which further improves the heat dissipation performance of the packaging structure, and can avoid the risk of filling the back surface of the bridge chip 300, and meet the design of embedding different sizes of thinner bridge chips 300.

[0098] Further, in the second embodiment, a second organic interconnection layer 410 is arranged on the front surface of the bottom redistribution layer 10, and the second organic interconnection layer 410 includes a second organic medium layer 411 and a second conductive line 412. In some embodiments, the second organic interconnection layer 410 is an organic Damascene structure formed by a Damascene process. In some embodiments, the second organic medium layer 411 can be a polyimide (PI) layer, or other organic material layers, such as Benzo Cyclo Butene (BCB) or Poly Benz Oxazole (PBO), etc. The second conductive line 412 is arranged in the second organic medium layer 411 and is electrically connected to the bottom redistribution layer 10.

[0099] Further, in the second embodiment, a third organic interconnection layer 420 is disposed on the back surface of the bridge chip 300, and the third organic interconnection layer 420 comprises a third organic medium layer 421 and a third conductive circuit layer 422. In some embodiments, the third organic interconnection layer 420 is an organic Damascene structure formed by a Damascene process. In some embodiments, the third organic medium layer 421 can be a polyimide (PI) layer, or other organic material layer, such as Benzo Cyclo Butene (BCB) or Poly Benz Oxazole (PBO), etc. The third conductive circuit is disposed in the third organic medium layer 421 and is electrically connected with the end of the through silicon via 302.

[0100] Further, in the second embodiment, the second organic medium layer 411 is bonded with the third organic medium layer 421, and the second conductive circuit layer 412 is bonded with the third conductive circuit layer 422, forming an organic hybrid bonding structure as the first bonding structure 40. Compared with the bonding between the bottom redistribution layer 10 and the bridge chip 300 by an inorganic bonding structure, the packaging structure provided by the embodiments of the present application does not need to separately form an inorganic bonding layer for bonding on the back surface of the bottom redistribution layer 10 and the bridge chip 300, avoiding the multiple etching processes and the process of removing photoresist when forming the inorganic bonding layer, greatly simplifying the manufacturing process. Moreover, the organic hybrid bonding structure of the packaging structure provided by the embodiments of the present application has relatively low requirements for the cleanliness of the bonding surface, and does not need high-temperature annealing, which will not affect the functional components.

[0101] Further, in the second embodiment, the bridge chip 300 comprises a substrate 301, a through silicon via 302 penetrating through the substrate 301, and a second inorganic medium layer 3072 disposed on the back surface of the substrate 301, the through silicon via 302 protruding from the back surface of the substrate 301, and the end of the through silicon via 302 being flush with the surface of the second inorganic medium layer 3072, the third organic interconnection layer 420 being disposed on the second inorganic medium layer 3072, and the third conductive circuit being connected with the end of the through silicon via 302. The second inorganic medium layer 3072 covers the surface of the substrate 301, and in the process of thinning the through silicon via 302 on the back surface of the bridge chip 300, the second inorganic medium layer 3072 can protect the substrate 301, avoiding the migration and diffusion of metal ions generated by the thinning of the through silicon via 302 into the substrate 301. In some embodiments, the second inorganic medium layer 3072 is composed of a single inorganic medium layer or multiple inorganic medium layers.

[0102] Further, in the second embodiment, when the first bonding structure 40 is an organic hybrid bonding structure, the top redistribution layer 20 is formed on the front surface of the bridge chip 300 by a redistribution process, and the front surface of the bridge chip 300 is electrically connected to the top redistribution layer 20. In particular, the conductive pillars 306 on the front surface of the bridge chip 300 are electrically connected to the top redistribution layer 20. The front surface of the bridge chip 300 does not need to be connected to the top redistribution layer 20 by soldering, and thus there is no problem of reliability of the packaging structure caused by defects (holes or cracks) of the soldering points. The packaging structure provided in the embodiment has good reliability.

[0103] Figure 3 is a schematic view of the packaging structure provided in the third embodiment of the present application. Please refer to Figure 3 The third embodiment is different from the first embodiment and the second embodiment in that the front surface of the bridge chip 300 is connected to the back surface of the top redistribution layer 20 by a second bonding structure 50, and the second bonding structure 50 is an organic hybrid bonding structure. Since the bridge chip 300 is connected to the top redistribution layer 20 by the organic hybrid bonding structure, the bridge chip 300 does not need to be soldered to the top redistribution layer 20 by forming micro-bumps on the top surface of the bridge chip 300, and thus there is no problem of reliability of the packaging structure caused by defects (holes or cracks) of the soldering points. The packaging structure provided in the embodiment has good reliability. Moreover, the organic hybrid bonding structure does not need to be limited by the critical dimension of the micro-bumps and the distance between two adjacent micro-bumps. The critical dimension and the distance between the conductive structures in the organic hybrid bonding structure are relatively small, which can increase the number and density of I / Os, and thus can achieve more intensive I / O interconnection. For example, the packaging structure provided in the present application can meet the requirement of I / O distance of less than 30 μm, while the I / O distance of a conventional packaging structure is usually greater than or equal to 40 μm. At the same time, the organic hybrid bonding structure can effectively reduce the distance between the bridge chip 300 and the top redistribution layer 20, which is beneficial to further reduce the thickness of the wiring interposition layer 1, reduce the warping of the wiring interposition layer 1, and avoid the warping of the wiring interposition layer 1 from affecting the process operation.

[0104] Further, in the third embodiment, the first plastic sealing layer 310 covers the side surface of the second bonding structure 50, and does not fill the space between the front surface of the bridge chip 300 and the top redistribution layer 20. The bridge chip 300 and the top redistribution layer 20 are thermally connected by the conductive lines in the organic hybrid bonding structure, which further improves the heat dissipation performance of the packaging structure.

[0105] Further, in the third embodiment, a fourth organic interconnection layer 500 is disposed on the back side of the top redistribution layer 20, and the fourth organic interconnection layer 500 includes a fourth organic dielectric layer 501 and a fourth conductive circuit 502. In some embodiments, the fourth organic interconnection layer 500 is an organic Damascene structure formed by a Damascene process. In some embodiments, the fourth organic dielectric layer 501 can be a polyimide (PI) layer, or other organic material layer, such as Benzo Cyclo Butene (BCB) or Poly Benz Oxazole (PBO), etc. The fourth conductive circuit 502 is disposed in the fourth organic dielectric layer 501 and is electrically connected to the top redistribution layer 20.

[0106] Further, in the third embodiment, a fifth organic interconnection layer 510 is disposed on the front side of the bridge chip 300, and the fifth organic interconnection layer 510 includes a fifth organic dielectric layer 511 and a fifth conductive circuit layer 512. In some embodiments, the fifth organic interconnection layer 510 is an organic Damascene structure formed by a Damascene process. In some embodiments, the fifth organic dielectric layer 511 can be a polyimide (PI) layer, or other organic material layer, such as Benzo Cyclo Butene (BCB) or Poly Benz Oxazole (PBO), etc. The fifth conductive circuit is disposed in the fifth organic dielectric layer 511 and is electrically connected to the front side of the bridge chip 300, such as the internal redistribution layer 305 on the front side of the bridge chip 300.

[0107] Further, in the third embodiment, the fourth organic dielectric layer 501 is bonded to the fifth organic dielectric layer 511, and the fourth conductive circuit layer 502 is bonded to the fifth conductive circuit layer 512, to serve as the second bonding structure 50. Compared to the inorganic bonding structure for bonding between the top redistribution layer 20 and the bridge chip 300, the packaging structure provided by the embodiments of the present application does not need to separately form an inorganic bonding layer for bonding on the front side of the top redistribution layer 20 and the bridge chip 300, avoiding the multiple etching processes and the process of removing photoresist when forming the inorganic bonding layer, greatly simplifying the manufacturing process. Moreover, the organic hybrid bonding structure of the packaging structure provided by the embodiments of the present application has relatively low requirements for the cleanliness of the bonding surface, and does not need high-temperature annealing, and will not affect the functional components.

[0108] Further, in the third specific embodiment, the bridge chip 300 comprises a substrate 301 and a through-silicon via 302 penetrating the substrate 301, the substrate 301 is provided with an internal redistribution layer 305 on the front surface, the fifth organic interconnection layer 510 is arranged on the internal redistribution layer 305, and the internal redistribution layer 305 is electrically connected to the top redistribution layer 20 through the second bonding structure 50. The through-silicon via 302 and other structures of the bridge chip 300 are fanned out through the internal redistribution layer 305. The I / O quantity and density can be further improved through the internal redistribution layer 305 and the second bonding structure 50, so that more intensive I / O interconnection can be achieved.

[0109] Further, in the third specific embodiment, when the second bonding structure 50 is an organic hybrid bonding structure, the substrate 301 is provided with a micro-bump 309 on the back surface, one side of the micro-bump 309 is connected to the end surface of the through-silicon via 302, and the other side is connected to the bottom redistribution layer 10.

[0110] Further, in the third specific embodiment, the substrate 301 is provided with a third inorganic medium layer 3073 on the back surface, the through-silicon via 302 protrudes from the back surface of the substrate 301, the end portion is flush with the surface of the third inorganic medium layer 3073, and the micro-bump 309 is located on the surface of the third inorganic medium layer 3073. The third inorganic medium layer 3073 covers the surface of the substrate 301, and in the process of thinning the through-silicon via 302 on the back surface of the bridge chip 300, the third inorganic medium layer 3073 can protect the substrate 301, so that the migration and diffusion of metal ions generated by thinning the through-silicon via 302 into the substrate 301 can be avoided. In some specific embodiments, the third inorganic medium layer 3073 is composed of a single inorganic medium layer or multiple inorganic medium layers.

[0111] The packaging structure provided by the specific embodiments of the present application avoids welding the bridge chip 300 and the bottom redistribution layer 10 or the top redistribution layer 20 by using the organic and inorganic hybrid bonding structure or the organic hybrid bonding structure, so that the reliability problem of the packaging structure caused by the defects (holes or cracks) of the welding points does not exist, and the packaging structure provided by the specific embodiments of the present application has good reliability.

[0112] The packaging structure provided by the fourth specific embodiment of the present application is different in that the front surface of the bridge chip 300 is connected to the back surface of the top redistribution layer 20 through the second bonding structure 50, the second bonding structure 50 is an organic hybrid bonding structure, the back surface of the bridge chip 300 is connected to the front surface of the bottom redistribution layer 10 through the first bonding structure 40, and the first bonding structure 40 is an organic and inorganic hybrid bonding structure or an organic hybrid bonding structure.

[0113] Based on the same inventive concept, the embodiments of the present application further provide a forming method of the packaging structure.

[0114] Figure 4 is a schematic diagram of steps of a forming method of the packaging structure provided by some embodiments of the present application, please refer to Figure 4 , the forming method comprises: step S40, forming one of the bottom redistribution layer 10 or the top redistribution layer 20; step S41, forming the embedded layer 30 on the bottom redistribution layer 10 or the top redistribution layer 20, the embedded layer 30 comprises the bridge chip 300, the back surface of the bridge chip 300 is connected with the front surface of the bottom redistribution layer 10 through the first bonding structure 40, or the front surface of the bridge chip 300 is connected with the back surface of the top redistribution layer 20 through the second bonding structure 50; step S42, forming the other of the bottom redistribution layer 10 or the top redistribution layer 20 on the embedded layer 30.

[0115] Figures 5-14 is a process flow chart of a forming method of the packaging structure provided by the fourth embodiment of the present application, and the forming method will be described in detail below in combination with Figure 1 , Figures 4-14 .

[0116] Please refer to Figure 5 and step S40, forming the bottom redistribution layer 10. In an embodiment, the dielectric layer 100 and the conductive circuit 110 located in the dielectric layer 100 are formed on the first bottom support plate 900, and the dielectric layer 100 and the conductive circuit 110 constitute the bottom redistribution layer 10. Specifically, the bottom redistribution layer 10 is formed on the first bottom support plate 900 by a photoetching process and an electroplating process, for example, the bottom redistribution layer 10 is formed by the processes of glue coating, exposure, development, electroplating, and glue removal.

[0117] Please refer to Figures 6-12 and step S41, forming the embedded layer 30 on the bottom redistribution layer 10, the embedded layer 30 comprises the bridge chip 300, the back surface of the bridge chip 300 is connected with the front surface of the bottom redistribution layer 10 through the first bonding structure 40, and the first bonding structure 40 is an organic and inorganic hybrid bonding structure.

[0118] Further, in the fourth embodiment, the step of forming the embedded layer 30 on the bottom redistribution layer 10 comprises:

[0119] Please refer to Figure 10A first organic interconnection layer 400 is formed on the bottom redistribution layer 10, and the first organic interconnection layer 400 includes a first organic dielectric layer 401 and a first conductive circuit 402. The first organic dielectric layer 401 is disposed on the front surface of the bottom redistribution layer 10, and the first conductive circuit 402 is disposed in the first organic dielectric layer 401 and electrically connected to the bottom redistribution layer 10.

[0120] Referring to Figure 11 The bridge chip 300 is bonded to the first organic interconnection layer 400, and the bridge chip 300 includes a substrate 301, a through-silicon via 302 penetrating the substrate 301, and a first inorganic dielectric layer 3071 disposed on the back surface of the substrate 301. The through-silicon via 302 of the bridge chip 300 protrudes from the back surface of the substrate 301 and has an end flush with the surface of the first inorganic dielectric layer 3071. The first organic dielectric layer 401 is bonded to the first inorganic dielectric layer 3071, and the end of the through-silicon via 302 is bonded to the first conductive circuit 402 to form the first bonding structure 40. The bonding can be performed at room temperature in an ultra-high vacuum environment.

[0121] The first inorganic dielectric layer 3071 covers the surface of the substrate 301. In the process of forming the bridge chip 300, when the through-silicon via 302 on the back surface of the bridge chip 300 is thinned, the first inorganic dielectric layer 3071 can protect the substrate 301, and metal ion migration and diffusion into the substrate 301 caused by thinning the through-silicon via 302 can be avoided. In some embodiments, the first inorganic dielectric layer 3071 is composed of a single-layer inorganic dielectric layer or a multi-layer inorganic dielectric layer.

[0122] The bonding process for forming the first bonding structure 40 further includes ion beam or plasma treatment of the bonding surface before the bonding operation is performed to activate the bonding surface. Specifically, the surfaces of the first organic dielectric layer 401 and the first conductive circuit 402 of the first organic interconnection layer 400, the first inorganic dielectric layer 3071, and the through-silicon via 302 are subjected to ion beam or plasma treatment to make the surface valence bonds active, thereby enhancing the bonding strength and reliability. In some embodiments, the back surface of the first organic interconnection layer 400 and the bridge chip 300 can be treated with an ion beam or plasma of oxygen, nitrogen, argon, or a mixture of two of oxygen, nitrogen, and argon. In some embodiments, the activation effect can be improved by controlling the flow rate, radio frequency power, treatment time, and gas pressure of the plasma.

[0123] The step of performing the bonding process further includes low-temperature annealing. Specifically, the bonding is heated to 150-300°C to promote the formation of covalent bonds between the bonding interface groups, thereby achieving high-strength bonding.

[0124] As an example, Figures 6-10 is a schematic diagram of forming the first organic interconnection layer 400 on the bottom redistribution layer 10 in the forming method of the packaging structure provided in the fourth specific embodiment of the present application, please refer to Figures 6-10 The first organic interconnection layer 400 is formed by using Damascene process, and the forming method comprises:

[0125] Please refer to Figure 6 The first organic dielectric layer 401 is formed on the front surface of the bottom redistribution layer 10 by using spin coating process. The first organic dielectric layer 401 can be a polyimide (PI) layer, or other organic material layer, for example, Benzo Cyclo Butene (BCB) or Poly Benz Oxazole (PBO) and the like.

[0126] Please refer to Figure 7 The first through hole 700 is formed by using photoetching mask to expose and develop the first organic dielectric layer 401. Since the first organic dielectric layer 401 is an organic material, the photoetching mask can be directly used as a shield to expose and develop the first organic dielectric layer 401, without the need of forming a patterned photoresist protective layer on the surface of the first organic dielectric layer 401, and then using the photoresist protective layer as a mask to etch the first organic dielectric layer 401 to form the first through hole 700. Moreover, after forming the first through hole 700, the first organic dielectric layer 401 does not need to be removed, while if the photoresist protective layer is used to form the first through hole 700, the photoresist protective layer needs to be removed. The forming method of the present application greatly saves the process flow and reduces the manufacturing cost.

[0127] Please refer to Figure 8 The first barrier layer 710 covering the inner wall of the first through hole 700 is formed. The first barrier layer 710 is used to block the diffusion of the conductive material formed subsequently into the first organic dielectric layer 401, so as to avoid electromigration and short circuit. In some specific embodiments, the first barrier layer 710 can be a Ta / TaN composite layer. In this step, the first barrier layer 710 also covers the surface of the first organic dielectric layer 401.

[0128] Please refer to Figure 9filling conductive material to form a first initial structure 720, which fills the first via hole 700 and covers the surface of the first organic dielectric layer 401. In this step, the first initial structure 720 covers the surface of the first barrier layer 710. In some embodiments, the conductive material can be filled by electroplating or sputtering.

[0129] Referring to Figure 10 thinning the first initial structure 720 to form the first conductive line 402. The first initial structure 720 on the surface of the first organic dielectric layer 401 and the first barrier layer 710 are removed by chemical mechanical polishing or other processes until the surface of the first initial structure 720 is flush with the surface of the first organic dielectric layer 401, leaving only the first barrier layer 710 and the first initial structure 720 in the first via hole 700, and the remaining first initial structure 720 as the first conductive line 402.

[0130] Further, referring to Figure 10 The step of forming the first organic interconnection layer 400 on the bottom redistribution layer 10 further includes thinning the first organic dielectric layer 401 so that the first conductive line 402 protrudes from the first organic dielectric layer 401 to prepare for subsequent bonding. In an embodiment, the first organic dielectric layer 401 can be thinned by etching, and the amount of thinning can be controlled by adjusting the etching parameters.

[0131] Further, referring to Figure 11 forming a metal pillar 320 on the bottom redistribution layer 10. In some embodiments, the metal pillar 320 can be formed on the first organic interconnection layer 400 before bonding the back surface of the bridge chip 300 to the first organic interconnection layer 400. The back surface of the metal pillar 320 is electrically connected to the first conductive line 402.

[0132] Referring to Figure 12The step of forming the embedded layer 30 on the bottom redistribution layer 10 further comprises: plastic packaging, forming a first plastic packaging layer 310, the first plastic packaging layer 310 covering the side of the bridge chip 300 and the side of the metal column 320, the front of the conductive column 306 of the bridge chip 300 and the front of the metal column 320 being exposed to the front of the first plastic packaging layer 310. The material of the first plastic packaging layer 310 can be silicon oxide or silicon nitride, which has better wettability with the medium layer (such as polyimide) of the bottom redistribution layer and the medium layer (such as polyimide) of the top redistribution layer 20, can improve the adhesion between the first plastic packaging layer 310 and the medium layer 100 of the bottom redistribution layer 10 and the medium layer 200 of the top redistribution layer 20, and improve the reliability of the packaging structure.

[0133] Referring to Figure 13 and step S42, the top redistribution layer 20 is formed on the embedded layer 30. Specifically, in this specific embodiment, the top redistribution layer 20 is formed on the first plastic packaging layer 310 and the bridge chip 300, and the top redistribution layer 20 is electrically connected to the front of the metal column 320 and the conductive column 306 on the front of the bridge chip 300.

[0134] In the fourth specific embodiment, the step of forming the top redistribution layer 20 on the first plastic packaging layer 310 and the bridge chip 300 comprises: forming a medium layer 200 and a conductive circuit 210 in the medium layer 200 on the first plastic packaging layer 310 and the bridge chip 300, the medium layer 200 and the conductive circuit 210 constituting the top redistribution layer 20. Specifically, the top redistribution layer 20 is formed on the first plastic packaging layer 310 and the bridge chip 300 by a photoetching process and an electroplating process, for example, the top redistribution layer 20 is formed by processes such as glue coating, exposure, development, electroplating, and glue removal.

[0135] Referring to Figure 14 After the top redistribution layer 20 is formed on the embedded layer 30, the forming method further comprises: forming the chip packaging assembly 3 on the top redistribution layer 20.

[0136] As an example, the step of forming the chip package assembly 3 on the top redistribution layer 20 includes forming top pads 33 on the front side of the top redistribution layer 20, the top pads 33 being electrically connected to the top redistribution layer 20. Top devices 31 are disposed on the front side of the top redistribution layer 20, the top devices 31 being soldered to the top pads 33. In some embodiments, the top devices 31 are flip-chip mounted on the front side of the top redistribution layer 20. The top devices 31 are soldered to the top pads 33 by conductive bumps. The top devices 31 are encapsulated to form a second encapsulation layer 32, the second encapsulation layer 32 encapsulating the top devices 31. In some embodiments, the step of encapsulating the top devices 31 further includes filling a filler layer 34 between the bottom of the top devices 31 and the front side of the top redistribution layer 20 before encapsulating the top devices 31, the second encapsulation layer 32 also covering the filler layer 34.

[0137] After the chip package assembly 3 is formed, the first bottom support plate 900 is removed, and a conductive connection structure 2 is formed. As shown in Figure 1 The forming method further includes forming a conductive connection structure 2 on the bottom redistribution layer 10, the conductive connection structure 2 being disposed on the back side of the bottom redistribution layer 10 and being electrically connected to the bottom redistribution layer 10. The conductive connection structure 2 includes, but is not limited to, a controllable collapse chip connection bump (C4).

[0138] In a fourth specific embodiment, the back side of the bridge chip 300 is connected to the front side of the bottom redistribution layer 10 by a first bonding structure 40, the first bonding structure 40 being an organic and inorganic hybrid bonding structure. A fifth specific embodiment is also provided, in which the back side of the bridge chip 300 is connected to the front side of the bottom redistribution layer 10 by a first bonding structure 40, the first bonding structure 40 being an organic hybrid bonding structure.

[0139] Figures 15-16 is a process flow diagram of the forming method of the package structure provided in the fifth specific embodiment of the present application, which will be described in detail below. Figure 2 , Figures 15-16 The forming method will be described in detail.

[0140] In the fifth specific embodiment, the forming method includes the following steps:

[0141] Please refer to Figure 15forming a bottom redistribution layer 10 on the first bottom support plate 900; forming a second organic interconnection layer 410 on the bottom redistribution layer 10, the second organic interconnection layer 410 comprising a second organic dielectric layer 411 and a second conductive circuit 412; forming a third organic interconnection layer 420 on the back surface of the bridge chip 300, the third organic interconnection layer 420 comprising a third organic dielectric layer 421 and a third conductive circuit layer 422; and bonding the third organic interconnection layer 420 and the second organic interconnection layer 410, the second organic dielectric layer 411 and the third organic dielectric layer 421 being bonded, and the second conductive circuit 412 and the third conductive circuit layer 422 being bonded, to form the first bonding structure 40.

[0142] In one embodiment, a dielectric layer 100 and a conductive circuit 110 in the dielectric layer 100 are formed on the first bottom support plate 900, and the dielectric layer 100 and the conductive circuit 110 constitute the bottom redistribution layer 10. Specifically, the bottom redistribution layer 10 is formed on the first bottom support plate 900 by a photolithography process and an electroplating process, for example, by coating, exposure, development, electroplating, and stripping to form the bottom redistribution layer 10 by layer-by-layer addition.

[0143] As an example, in some embodiments, the Damascene process is used to form the second organic interconnection layer 410 on the bottom redistribution layer 10, and the method of forming the second organic interconnection layer 410 is the same as that of forming the first organic interconnection layer 400, and specifically includes the following steps: forming the second organic dielectric layer 411 on the front surface of the bottom redistribution layer 10 by a spin coating process; exposing and developing the second organic dielectric layer 411 using a photomask to form the second via (not shown in the figure); forming a second barrier layer 711 covering the inner wall of the second via; filling the conductive material to form a second initial structure (not shown in the figure), which fills the second via and covers the surface of the second organic dielectric layer 411; and thinning the second initial structure to form the second conductive circuit 412. The specific formation process can be referred to in Figures 6-10 .

[0144] Further, in the fifth embodiment, the step of forming the second organic interconnection layer 410 on the bottom redistribution layer 10 further includes thinning the second organic dielectric layer 411 so that the second conductive circuit 412 protrudes from the second organic dielectric layer 411 to prepare for subsequent bonding. In one embodiment, the second organic dielectric layer 411 can be thinned by an etching process, and adjusting the etching parameters can control the amount of thinning of the second organic dielectric layer 411.

[0145] As an example, in some embodiments, the step of forming the third organic interconnection layer 420 on the back side of the bridge chip 300 comprises: forming the third organic dielectric layer 421 on the back side of the bridge chip 300 by using a spin coating process; exposing and developing the third organic dielectric layer 421 by using a photomask to form the third via (not shown in the figure); forming the third barrier layer 712 on the inner wall of the third via; filling the third via with a conductive material to form a third initial structure (not shown in the figure), which fills the third via and covers the surface of the third organic dielectric layer 421; and thinning the third initial structure to form the third conductive line. The detailed forming process can refer to Figures 6-10 .

[0146] Further, in the fifth embodiment, the step of forming the third organic interconnection layer 420 on the back side of the bridge chip 300 further comprises thinning the third organic dielectric layer 421 so that the third conductive line protrudes from the third organic dielectric layer 421 to prepare for the subsequent bonding. In an embodiment, the third organic dielectric layer 421 can be thinned by an etching process, and the etching parameters can be adjusted to control the thinning amount of the third organic dielectric layer 421.

[0147] Further, in the fifth embodiment, the metal pillar 320 is formed on the bottom redistribution layer 10. In some embodiments, the metal pillar 320 can be formed on the second organic interconnection layer 410 first, and then the third organic interconnection layer 420 on the back side of the bridge chip 300 is bonded to the second organic interconnection layer 410. The back side of the metal pillar 320 is electrically connected to the second conductive line 412.

[0148] Further, in the fifth embodiment, before the bonding operation is performed, the bonding surface is treated by ion beam or plasma to activate the bonding surface. Specifically, the surface of the second organic dielectric layer 411 and the second conductive line 412 of the second organic interconnection layer 410, and the surface of the third organic dielectric layer 421 and the third conductive line of the third organic interconnection layer 420 are treated by ion beam or plasma to make the surface valence bond active and enhance the bonding strength and reliability. In some embodiments, the second organic interconnection layer 410 and the third organic interconnection layer 420 that need to perform the bonding process can be treated by using oxygen, nitrogen, argon, or a mixture of two of oxygen, nitrogen, and argon. In some embodiments, the activation effect can be improved by controlling the parameters such as the flow rate of the plasma, the radio frequency power, the treatment time, and the gas pressure. After the bonding, low-temperature annealing can be performed.

[0149] Please refer to Figure 16The step of forming the buried layer 30 on the bottom redistribution layer 10 further comprises: plastic packaging, forming a first plastic packaging layer 310, the first plastic packaging layer 310 covering the side of the bridge chip 300 and the side of the metal column 320, the front surface of the conductive column 306 of the bridge chip 300 and the front surface of the metal column 320 being exposed to the front surface of the first plastic packaging layer 310.

[0150] Please refer to Figure 2 The chip packaging assembly 3 is formed on the top redistribution layer 20 formed on the buried layer 30. In this specific embodiment, the top redistribution layer 20 is formed on the first plastic packaging layer 310 and the bridge chip 300 by a photoetching process and an electroplating process, for example, by the processes of glue coating, exposure, development, electroplating, and glue removal to form the top redistribution layer 20 by layer-by-layer stacking.

[0151] The chip packaging assembly 3 includes a top device 31 and a second plastic packaging layer 32, the top device 31 being arranged on the front surface of the top redistribution layer 20, and the top device 31 being electrically connected to the top redistribution layer 20; the second plastic packaging layer 32 covering the top device 31. The specific process of forming the chip packaging assembly 3 on the top redistribution layer 20 can be referred to the related description of the fourth specific embodiment.

[0152] After the chip packaging assembly 3 is formed, the first bottom support plate 900 is removed, and a conductive connection structure 2 is formed, the conductive connection structure 2 being arranged on the back surface of the bottom redistribution layer 10 and being electrically connected to the bottom redistribution layer 10. The conductive connection structure 2 includes but is not limited to a controllable chip connection bump (C4).

[0153] In the fourth specific embodiment and the fifth specific embodiment, the back surface of the bridge chip 300 is connected to the front surface of the bottom redistribution layer 10 through a first bonding structure 40, the first bonding structure 40 being an organic and inorganic hybrid bonding structure or an organic hybrid bonding structure. The present application further provides a sixth specific embodiment, in which the front surface of the bridge chip 300 is connected to the back surface of the top redistribution layer 20 through a second bonding structure 50, the second bonding structure 50 being an organic hybrid bonding structure.

[0154] Figures 17-22 is a process flow chart of the forming method of the packaging structure provided by the sixth specific embodiment of the present application, which will be described in detail below Figure 3 、 Figures 17-22 The forming method is described in detail.

[0155] Please refer to Figure 17 and step S40, forming a top redistribution layer 20.

[0156] In one specific embodiment, the chip packaging assembly 3 is first formed, and then the top redistribution layer 20 is formed on the chip packaging assembly 3. The chip packaging assembly 3 includes a top device 31 and a second molding compound 32. The top device 31 is disposed on the front side of the top redistribution layer 20 and is electrically connected to the top redistribution layer 20; the second molding compound 32 covers the top device 31.

[0157] Specifically, a top device 31 is mounted on a second bottom support plate (not shown in the figures); a second molding layer 32 is formed, which covers the top device 31; the second bottom support plate is removed, exposing the pads of the top device 31 to the second molding layer 32; and the top redistribution layer 20 is formed on the second molding layer 32.

[0158] In one specific embodiment, the method for forming the top redistribution layer 20 includes: forming a dielectric layer 200 and conductive lines 210 located in the dielectric layer 200 on the chip packaging assembly 3, wherein the dielectric layer 200 and the conductive lines 210 constitute the top redistribution layer 20. Specifically, the top redistribution layer 20 is formed on the chip packaging assembly 3 by photolithography and electroplating processes. For example, the top redistribution layer 20 is formed by layer stacking through processes such as resist coating, exposure, development, electroplating, and resist removal.

[0159] Please see Figures 18-20 In step S41, a buried layer 30 is formed on the top redistribution layer 20. The buried layer 30 includes a bridging chip 300. The front side of the bridging chip 300 is connected to the back side of the top redistribution layer 20 through a second bonding structure 50, which is an organic hybrid bonding structure.

[0160] Furthermore, in the sixth embodiment, the step of forming an embedded layer 30 on the top redistribution layer 20 includes:

[0161] Please see Figure 18 A fourth organic interconnect layer 500 is formed on the top redistribution layer 20. The fourth organic interconnect layer 500 includes a fourth organic dielectric layer 501 and a fourth conductive line 502. The fourth organic dielectric layer 501 is disposed on the back side of the top redistribution layer 20, and the fourth conductive line 502 is disposed within the fourth organic dielectric layer 501 and is electrically connected to the top redistribution layer 20.

[0162] As an example, the fourth organic interconnection layer 500 is formed on the back surface of the top redistribution layer 20 by a Damascene process, and the method for forming the fourth organic interconnection layer 500 is the same as that for forming the first organic interconnection layer 400, specifically including the following steps: forming the fourth organic dielectric layer 501 on the back surface of the top redistribution layer 20 by a spin coating process; exposing and developing the fourth organic dielectric layer 501 by a photolithographic mask to form the fourth via (not shown in the figure); forming the fourth barrier layer 713 covering the inner wall of the fourth via on the fourth via; filling the fourth initial structure (not shown in the figure) with a conductive material, which fills the fourth via and covers the surface of the fourth organic dielectric layer 501; and thinning the fourth initial structure to form the fourth conductive circuit 502. The specific forming process can be referred to Figures 6-10 .

[0163] Further, in the sixth specific embodiment, the step of forming the fourth organic interconnection layer 500 on the top redistribution layer 20 further includes thinning the fourth organic dielectric layer 501 so that the fourth conductive circuit 502 protrudes from the fourth organic dielectric layer 501 to prepare for subsequent bonding. In a specific embodiment, the fourth organic dielectric layer 501 can be thinned by an etching process, and the amount of thinning of the fourth organic dielectric layer 501 can be controlled by adjusting the etching parameters.

[0164] Please refer to Figure 19 The fifth organic interconnection layer 510 is formed on the front surface of the bridge chip 300, and the fifth organic interconnection layer 510 includes a fifth organic dielectric layer 511 and a fifth conductive circuit layer 512. The fifth organic dielectric layer 511 is formed on the front surface of the internal redistribution layer 305, and the fifth conductive circuit layer 512 is located in the fifth organic dielectric layer 511 and connected to the internal redistribution layer 305.

[0165] As an example, the fifth organic interconnection layer 510 is formed on the front surface of the bridge chip 300 by a Damascene process, and the method for forming the fifth organic interconnection layer 510 is the same as that for forming the first organic interconnection layer 400, specifically including the following steps: forming the fifth organic dielectric layer 511 on the front surface of the bridge chip 300 by a spin coating process; exposing and developing the fifth organic dielectric layer 511 by a photolithographic mask to form the fifth via (not shown in the figure); forming the fifth barrier layer 714 covering the inner wall of the fifth via on the fifth via; filling the fifth initial structure (not shown in the figure) with a conductive material, which fills the fifth via and covers the surface of the fifth organic dielectric layer 511; and thinning the fifth initial structure to form the fifth conductive circuit. The specific forming process can be referred toFigures 6-10 .

[0166] Further, in the sixth embodiment, the step of forming the fifth organic interconnection layer 510 on the front side of the bridge chip 300 further comprises: thinning the fifth organic dielectric layer 511 so that the fifth conductive lines protrude from the fifth organic dielectric layer 511 to prepare for the subsequent bonding. In an embodiment, the fifth organic dielectric layer 511 can be thinned by an etching process, and the etching parameters can be adjusted to control the thinning amount of the fifth organic dielectric layer 511.

[0167] Referring to Figure 20 The fourth organic interconnection layer 500 and the fifth organic interconnection layer 510 are bonded, the fourth organic dielectric layer 501 and the fifth organic dielectric layer 511 are bonded, and the fourth conductive line layer 502 and the fifth conductive line layer 512 are bonded to form the second bonding structure 50.

[0168] Further, in the sixth embodiment, before the bonding operation is performed, the bonding surface is subjected to ion beam or plasma treatment to activate the bonding surface. Specifically, the surfaces of the fourth organic dielectric layer 501 and the fourth conductive line 502 of the fourth organic interconnection layer 500, and the surfaces of the fifth organic dielectric layer 511 and the fifth conductive line of the fifth organic interconnection layer 510 are subjected to ion beam or plasma treatment to make the surfaces of the fourth organic dielectric layer 501 and the fourth conductive line 502 of the fourth organic interconnection layer 500, and the surfaces of the fifth organic dielectric layer 511 and the fifth conductive line of the fifth organic interconnection layer 510 active in valence bond, thereby enhancing the bonding strength and reliability. In some embodiments, oxygen, nitrogen, argon, or a mixture of two of oxygen, nitrogen, and argon can be used for the ion beam or plasma treatment. In some embodiments, the activation effect can be improved by controlling the flow rate, radio frequency power, treatment time, gas pressure, and other parameters of the plasma. Low-temperature annealing can be performed after the bonding.

[0169] Further, in the sixth embodiment, a metal pillar 320 is formed on the top redistribution layer 20. In some embodiments, the metal pillar 320 can be formed on the fourth organic interconnection layer 500 first, and then the fifth organic interconnection layer 510 on the back side of the bridge chip 300 is bonded to the fourth organic interconnection layer 500. The back side of the metal pillar 320 is electrically connected to the fourth conductive line 502.

[0170] Further, in the sixth embodiment, the back side of the substrate 301 of the bridge chip 300 is provided with a micro bump 309 connected to the end surface of the through silicon via 302.

[0171] Referring to Figure 21A first molding compound 310 is formed by molding the bridging chip 300. The first molding compound 310 covers the sides of the bridging chip 300. In this specific embodiment, the molding compound also covers the sides of the metal pillars 320 and the microbumps 309, with the back sides of the metal pillars 320 and the microbumps 309 exposed to the first molding compound 310. The material of the first molding compound 310 can be silicon oxide or silicon nitride. Silicon oxide or silicon nitride has better wettability with the dielectric layer 100 (e.g., polyimide) of the bottom redistribution layer 10 and the dielectric layer 200 (e.g., polyimide) of the top redistribution layer 20, which can improve the adhesion between the first molding compound 310 and the dielectric layers 100 and 200 of the bottom redistribution layer 10 and the top redistribution layer 20, thereby improving the reliability of the packaging structure.

[0172] Please see Figure 22 The bottom redistribution layer 10 is formed on the buried layer 30. Specifically, the bottom redistribution layer 10 is formed on the first molding layer 310 and the bridging chip 300, and the bottom redistribution layer 10 is connected to the microbumps 309 and the metal pillars 320. As an example, the method of forming the bottom redistribution layer 10 on the buried layer 30 includes forming a dielectric layer 100 and conductive lines 110 located in the dielectric layer 100 on the first molding layer 310 and the bridging chip 300, and the dielectric layer 100 and the conductive lines 110 constitute the bottom redistribution layer 10. Specifically, the bottom redistribution layer 10 is formed on the buried layer 30 by photolithography and electroplating processes, for example, by layer stacking through processes such as resist coating, exposure, development, electroplating, and resist removal to form the bottom redistribution layer 10.

[0173] Please see Figure 3 A conductive connection structure 2 is formed on the bottom redistribution layer 10. The conductive connection structure 2 is disposed on the back side of the bottom redistribution layer 10 and is electrically connected to the bottom redistribution layer 10.

[0174] In the forming method of the packaging structure provided by the embodiment, the back surface of the bridge chip 300 is connected with the front surface of the bottom redistribution layer 10 through the first bonding structure 40, the first bonding structure 40 is an organic and inorganic mixed bonding structure or an organic mixed bonding structure, or the front surface of the bridge chip 300 is connected with the back surface of the top redistribution layer 20 through the second bonding structure 50, the second bonding structure 50 is an organic mixed bonding structure, the bridge chip 300 does not need to be connected with the bottom redistribution layer 10 or the top redistribution layer 20 through soldering, and therefore there is no reliability problem of the packaging structure caused by defects (holes or cracks) of the soldering points. Moreover, the distance between the bridge chip 300 and the bottom redistribution layer 10 or the top redistribution layer 20 can be effectively reduced, which is beneficial to further reducing the thickness of the wiring insertion layer 1, reducing the warping of the wiring insertion layer 1, and avoiding the influence of the warping of the wiring insertion layer 1 on the process operation. Compared with the inorganic mixed bonding structure between the bridge chip 300 and the bottom redistribution layer 10 or the top redistribution layer 20, the forming method of the packaging structure provided by the embodiment has a simple process flow, low manufacturing cost, and relatively low bonding surface cleanliness requirement, does not need to be annealed at high temperature after bonding, does not affect the devices of the packaging structure, and has high reliability.

[0175] It should be noted that the terms "comprising" and "having" and their conjugates, involved in the file of the present application, are intended to cover the non-exclusive inclusion. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise, and it should be understood that the data thus used can be interchanged under appropriate circumstances. The term "one or more" can be used to describe a feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense, depending at least in part on the context. The term "based on" can be understood as not necessarily expressing a set of exclusive factors, but can instead, depending at least in part on the context, allow the presence of other factors not necessarily explicitly described. In addition, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Furthermore, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present application. In each of the above embodiments, each embodiment focuses on the difference from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0176] The above is only the preferred embodiment of the present application, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the present application, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A package structure, characterized by, The wiring insertion layer comprises: a bottom redistribution layer; a top redistribution layer disposed opposite to the bottom redistribution layer; a buried layer disposed between the bottom redistribution layer and the top redistribution layer, the buried layer comprising a bridge chip, a back surface of the bridge chip being connected to a front surface of the bottom redistribution layer through a first bonding structure, the first bonding structure being an organic and inorganic hybrid bonding structure or an organic hybrid bonding structure, and / or a front surface of the bridge chip being connected to a back surface of the top redistribution layer through a second bonding structure, the second bonding structure being an organic hybrid bonding structure.

2. The package structure of claim 1, wherein, A first organic interconnection layer is disposed on a surface of the bottom redistribution layer, the first organic interconnection layer comprising a first organic medium layer and a first conductive circuit, the bridge chip comprising a substrate, a through-silicon via penetrating through the substrate, and a first inorganic medium layer disposed on a back surface of the substrate, the through-silicon via protruding from the back surface of the substrate and having an end portion flush with a surface of the first inorganic medium layer, the first organic medium layer being bonded to the first inorganic medium layer, and the end portion of the through-silicon via being bonded to the first conductive circuit to serve as the first bonding structure.

3. The package structure of claim 2, wherein, The first inorganic medium layer is composed of a single-layer inorganic medium layer or a multi-layer inorganic medium layer.

4. The package structure of claim 1, wherein, A second organic interconnection layer is disposed on a front surface of the bottom redistribution layer, the second organic interconnection layer comprising a second organic medium layer and a second conductive circuit, and a third organic interconnection layer is disposed on a back surface of the bridge chip, the third organic interconnection layer comprising a third organic medium layer and a third conductive circuit layer, the second organic medium layer being bonded to the third organic medium layer, and the second conductive circuit layer being bonded to the third conductive circuit layer to serve as the first bonding structure.

5. The package structure of claim 4, wherein, The bridge chip comprises a substrate, a through-silicon via penetrating through the substrate, and a second inorganic medium layer disposed on a front surface of the substrate, the through-silicon via protruding from the front surface of the substrate and having an end portion flush with a surface of the second inorganic medium layer, the third organic interconnection layer being disposed on the second inorganic medium layer, and the third conductive circuit being connected to the end portion of the through-silicon via.

6. The package structure of claim 1, wherein, When the back surface of the bridge chip is connected to the front surface of the bottom redistribution layer through the first bonding structure, the top redistribution layer is disposed on a front surface of the bridge chip and the front surface of the bridge chip is electrically connected to the top redistribution layer.

7. The package structure of claim 6, wherein, The bridge chip comprises a substrate, a through-silicon via penetrating through the substrate, and an internal redistribution layer disposed on a front surface of the substrate, the internal redistribution layer being electrically connected to the top redistribution layer.

8. The package structure of claim 7, wherein, A conductive column is disposed on a surface of the internal redistribution layer, one end of the conductive column being electrically connected to the internal redistribution layer and the other end being electrically connected to the top redistribution layer.

9. The package structure of claim 1, wherein, A fourth organic interconnection layer is arranged on the back surface of the top redistribution layer, and the fourth organic interconnection layer comprises a fourth organic medium layer and a fourth conductive circuit.

10. The package structure of claim 9, wherein, The bridge chip comprises a substrate and a through silicon via penetrating through the substrate, and an inner redistribution layer is arranged on the front surface of the substrate, and the fifth organic interconnection layer is arranged on the inner redistribution layer.

11. The package structure of claim 10, wherein, When the front surface of the bridge chip is connected to the back surface of the top redistribution layer through the second bonding structure, a micro bump is arranged on the back surface of the substrate, one side of the micro bump is connected to the through silicon via, and the other side of the micro bump is connected to the bottom redistribution layer.

12. The package structure of claim 10, wherein, The back surface of the substrate is provided with a third inorganic medium layer, the through silicon via protrudes from the back surface of the substrate, and the back surface of the through silicon via is flush with the surface of the third inorganic medium layer.

13. The package structure of claim 1, wherein, When the front surface of the bridge chip is connected to the back surface of the top redistribution layer through the second bonding structure, the back surface of the bridge chip is connected to the front surface of the bottom redistribution layer through the first bonding structure.

14. The package structure of claim 1, wherein, The embedded layer further comprises a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip, the bottom redistribution layer is further arranged on the back surface of the first plastic sealing layer, and the top redistribution layer is further arranged on the front surface of the first plastic sealing layer.

15. The package structure of claim 14, wherein, The embedded layer further comprises a metal column, the metal column penetrates through the first plastic sealing layer, the back surface of the metal column is connected to the bottom redistribution layer, and the front surface of the metal column is connected to the top redistribution layer.

16. The package structure of claim 1, wherein, The bridge chip comprises a substrate and a through silicon via penetrating through the substrate, and a passivation layer is arranged on the side surface of the through silicon via.

17. The package structure of claim 16, wherein, The bridge chip further comprises a deep trench capacitor, and the deep trench capacitor is arranged in the substrate.

18. The package structure of claim 1, wherein, The packaging structure further comprises a chip packaging assembly, and the chip packaging assembly is arranged on the front surface of the top redistribution layer.

19. The package structure of claim 18, wherein, The chip packaging assembly comprises: a top device, arranged on the front surface of the top redistribution layer and electrically connected to the top redistribution layer; and a second plastic sealing layer, covering the top device. The packaging structure further comprises a conductive connection structure, and the conductive connection structure is arranged on the back surface of the bottom redistribution layer and electrically connected to the bottom redistribution layer.

20. The package structure of claim 1, wherein, The method comprises:

21. A method of forming a package structure, comprising: forming one of the bottom redistribution layer or the top redistribution layer; forming an embedded layer on the bottom redistribution layer or the top redistribution layer, the embedded layer comprising a bridge chip, the back surface of the bridge chip being connected to the front surface of the bottom redistribution layer through a first bonding structure, or the front surface of the bridge chip being connected to the back surface of the top redistribution layer through a second bonding structure; and forming the other of the bottom redistribution layer or the top redistribution layer on the embedded layer. In the step of forming one of the bottom redistribution layer or the top redistribution layer, the bottom redistribution layer is formed, and the step of forming the embedded layer on the bottom redistribution layer comprises:

22. The method of claim 21, wherein ​ forming a first organic interconnection layer on the bottom redistribution layer, the first organic interconnection layer comprising a first organic dielectric layer and a first conductive circuit; bonding the bridge chip with the first organic interconnection layer, the bridge chip comprising a substrate, a through-silicon via penetrating the substrate, and a first inorganic dielectric layer disposed on a back surface of the substrate, the through-silicon via of the bridge chip protruding from the back surface of the substrate and having an end portion flush with a surface of the first inorganic dielectric layer, the first organic dielectric layer being bonded with the first inorganic dielectric layer, and the end portion of the through-silicon via being bonded with the first conductive circuit to serve as the first bonding structure; in the step of forming the other one of the bottom redistribution layer or the top redistribution layer on the buried layer, the top redistribution layer is formed on the buried layer.

23. The method of claim 22, wherein The step of forming the first organic interconnection layer on the bottom redistribution layer comprises: forming the first organic dielectric layer on a front surface of the bottom redistribution layer by a spin coating process; exposing and developing the first organic dielectric layer by a photolithographic mask to form the first via; forming a first barrier layer covering an inner wall of the first via on the first via; filling a conductive material to form a first initial structure, the first initial structure filling the first via and covering a surface of the first organic dielectric layer; thinning the first initial structure to form the first conductive circuit.

24. The method of claim 22, wherein The step of forming the first organic interconnection layer on the bottom redistribution layer further comprises thinning the first organic dielectric layer so that the first conductive circuit protrudes from the first organic dielectric layer.

25. The method of claim 21, wherein In the step of forming one of the bottom redistribution layer or the top redistribution layer, the bottom redistribution layer is formed, and the step of forming a buried layer on the bottom redistribution layer comprises: forming a second organic interconnection layer on the bottom redistribution layer, the second organic interconnection layer comprising a second organic dielectric layer and a second conductive circuit; forming a third organic interconnection layer on a back surface of the bridge chip, the third organic interconnection layer comprising a third organic dielectric layer and a third conductive circuit layer; bonding the third organic interconnection layer with the second organic interconnection layer, the second organic dielectric layer being bonded with the third organic dielectric layer, and the second conductive circuit layer being bonded with the third conductive circuit layer to serve as the first bonding structure; in the step of forming the other one of the bottom redistribution layer or the top redistribution layer on the buried layer, the top redistribution layer is formed on the buried layer.

26. The method of claim 25, wherein The step of forming the second organic interconnection layer on the bottom redistribution layer comprises: forming the second organic dielectric layer on a front surface of the bottom redistribution layer by a spin coating process; exposing and developing the second organic dielectric layer by a photolithographic mask to form the second via; forming a second barrier layer covering an inner wall of the second via on the second via; filling a conductive material to form a second initial structure, the second initial structure filling the second via and covering a surface of the second organic dielectric layer; thinning the second initial structure to form the second conductive circuit. The step of forming a third organic interconnection layer on the back of the bridge chip comprises: forming the third organic dielectric layer on the back of the bridge chip by using a spin coating process; exposing and developing the third organic dielectric layer by using a photolithography mask to form the third via hole; forming a third barrier layer covering the inner wall of the third via hole on the third via hole; filling a conductive material to form a third initial structure, which fills the third via hole and covers the surface of the third organic dielectric layer; thinning the third initial structure to form the third conductive circuit.

27. The method of claim 25, wherein The step of forming a second organic interconnection layer on the bottom redistribution layer further comprises thinning the second organic dielectric layer so that the second conductive circuit protrudes from the second organic dielectric layer. The step of forming a third organic interconnection layer on the back of the bridge chip further comprises thinning the third organic dielectric layer so that the third conductive circuit protrudes from the third organic dielectric layer.

28. The method of claim 22 or 25, wherein The step of forming a buried layer on the bottom redistribution layer further comprises: plastic packaging to form a first plastic packaging layer, which covers the side of the bridge chip; forming the top redistribution layer on the first plastic packaging layer and the bridge chip.

29. The method of claim 28, wherein Before the step of plastic packaging, a metal column is formed on the bottom redistribution layer; in the step of plastic packaging, the first plastic packaging layer also covers the metal column, and the front surface of the metal column is exposed to the front surface of the first plastic packaging layer; in the step of forming the top redistribution layer, the top redistribution layer is connected with the front surface of the metal column.

30. The method of claim 28, wherein The step of forming the top redistribution layer on the first plastic packaging layer comprises forming a dielectric layer and a conductive circuit in the dielectric layer on the first plastic packaging layer and the bridge chip.

31. The method of claim 21, wherein In the step of forming one of the bottom redistribution layer or the top redistribution layer, the top redistribution layer is formed, and the step of forming a buried layer on the top redistribution layer comprises: forming a fourth organic interconnection layer on the top redistribution layer, which comprises a fourth organic dielectric layer and a fourth conductive circuit layer; forming a fifth organic interconnection layer on the front surface of the bridge chip, which comprises a fifth organic dielectric layer and a fifth conductive circuit layer; bonding the fourth organic interconnection layer and the fifth organic interconnection layer, bonding the fourth organic dielectric layer and the fifth organic dielectric layer, and bonding the fourth conductive circuit layer and the fifth conductive circuit layer to serve as the second bonding structure; In the step of forming the other of the bottom redistribution layer or the top redistribution layer on the buried layer, the bottom redistribution layer is formed on the buried layer.

32. The method of claim 31, wherein The step of forming a fourth organic interconnection layer on the top redistribution layer comprises: forming the fourth organic dielectric layer on the back of the top redistribution layer by using a spin coating process; exposing and developing the fourth organic dielectric layer by using a photolithography mask to form the fourth via hole; forming a fourth barrier layer covering the inner wall of the fourth via hole on the fourth via hole; filling conductive material to form a fourth initial structure, the fourth initial structure filling the fourth via and covering the surface of the fourth organic dielectric layer; thinning the fourth initial structure to form the fourth conductive line; the step of forming a fifth organic interconnection layer on the front surface of the bridge chip further comprises: forming the fifth organic dielectric layer on the front surface of the bridge chip by spin coating process; exposing and developing the fifth organic dielectric layer by photolithography mask to form the fifth via; forming a fifth barrier layer covering the inner wall of the fifth via in the fifth via; filling conductive material to form a fifth initial structure, the fifth initial structure filling the fifth via and covering the surface of the fifth organic dielectric layer; thinning the fifth initial structure to form the fifth conductive line.

33. The method of claim 31, wherein the step of forming a fourth organic interconnection layer on the top redistribution layer further comprises thinning the fourth organic dielectric layer so that the fourth conductive line protrudes from the fourth organic dielectric layer; the step of forming a fifth organic interconnection layer on the front surface of the bridge chip further comprises thinning the fifth organic dielectric layer so that the fifth conductive line protrudes from the fifth organic dielectric layer.

34. The method of forming a package structure of claim 31, wherein the bridge chip comprises a substrate and a through-silicon via penetrating the substrate, the substrate front surface is provided with an internal redistribution layer, and the fifth organic interconnection layer is formed on the internal redistribution layer in the step of forming a fifth organic interconnection layer on the front surface of the bridge chip.

35. The method of claim 34, wherein the substrate back surface is provided with a micro bump connected with the end surface of the through-silicon via, and the bottom redistribution layer is connected with the micro bump in the step of forming the bottom redistribution layer on the buried layer.

36. The method of forming a package structure of claim 31, wherein the step of forming a buried layer on the top redistribution layer further comprises: plastic packaging to form a first plastic packaging layer, the first plastic packaging layer covering the side surface of the bridge chip; forming the bottom redistribution layer on the first plastic packaging layer and the bridge chip.

37. The method of claim 36, wherein the step of plastic packaging further comprises forming a metal column on the top redistribution layer before the step of plastic packaging, the first plastic packaging layer also covers the metal column in the step of plastic packaging, the end surface of the metal column is exposed to the back surface of the first plastic packaging layer, and the bottom redistribution layer is connected with the end surface of the metal column in the step of forming the bottom redistribution layer.

38. The method of forming a package structure of claim 36, wherein the step of forming the bottom redistribution layer on the first plastic packaging layer and the bridge chip comprises forming a dielectric layer and a conductive line in the dielectric layer on the first plastic packaging layer and the bridge chip.

39. The method of claim 21, wherein the bonding process of forming the first bonding structure or the second bonding structure comprises ion beam or plasma treatment on the bonding surface to activate the bonding surface.

40. The method of claim 21, wherein The packaging structure further comprises a chip packaging component, the chip packaging component comprising: a top device arranged on the front surface of the top redistribution layer and electrically connected with the top redistribution layer; and a second plastic packaging layer covering the top device.

41. The method of forming a package structure of claim 21, wherein, The forming method further comprises: forming a conductive connection structure on the bottom redistribution layer, the conductive connection structure being arranged on the back surface of the bottom redistribution layer and electrically connected with the bottom redistribution layer. The forming method further comprises: forming a conductive connection structure on the bottom redistribution layer, the conductive connection structure being arranged on the back surface of the bottom redistribution layer and electrically connected with the bottom redistribution layer.

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