Packaging structure and manufacturing method thereof
By designing embedded component circuit structure layers, signal interconnect structure layers, and power supply structure layers, and controlling the differences in thermal expansion coefficients, the problems of high cost and insufficient reliability in heterogeneous chip integration are solved, achieving low-cost, high-density interconnection and structural stability.
Patent Information
- Application Number
- CN202410967491.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-18
- Publication Date
- 2026-01-23
AI Technical Summary
In existing technologies, the electrical connection methods for integrating heterogeneous chips have high costs, and the flatness and structural reliability of organic core interconnect substrates are insufficient.
By adopting an embedded component circuit structure layer, signal interconnection structure layer, and power supply structure layer design, and controlling the difference in thermal expansion coefficients of each layer, a stable packaging structure is formed, which reduces production costs and improves structural reliability.
It achieves low-cost, high-density interconnection, reduces board warpage in the packaging structure, and improves the reliability and stability of the structure.
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Figure CN121398657A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor structure and a method of fabricating the same, and more particularly to a packaging structure and a method of fabricating the same. BACKGROUND
[0002] The key of heterogeneous chiplet integration is the electrical connection between two chips. Currently, Intel’s is connecting two chips by the way of Embedded Multi-Die Interconnect Bridge (EMIB) to achieve partial or local high-density interconnection. However, the problem encountered by the above-mentioned technology is that the bridge must be embedded in the organic core interconnect substrate by lamination technology, so in addition to whether the surface is flat enough for subsequent flip-chip packaging operations, the high cost of the organic core interconnect substrate must also be faced. SUMMARY
[0003] The present application is directed to a packaging structure and a method of fabricating the same, which can solve the problems of the prior art, and can have lower cost and better structural reliability.
[0004] According to an embodiment of the present application, a packaging structure includes a buried component line structure layer, a signal interconnection structure layer, a power supply structure layer, and an electronic component layer. The buried component line structure layer includes at least one buried component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface of the buried component line structure layer and is electrically connected to the buried component line structure layer. The power supply structure layer is disposed on the signal interconnection structure layer and is electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface of the buried component line structure layer, and is electrically connected to the buried component line structure layer. The signal interconnection structure layer has a higher coefficient of thermal expansion than the electronic component layer and the power supply structure layer, and the coefficients of thermal expansion of the latter two are similar.
[0005] In the packaging structure according to an embodiment of the present application, the buried component line structure layer further includes a plurality of metal pillars, a dielectric layer, a plurality of conductive vias, and a patterned line layer. The dielectric layer has a first surface and a second surface. The dielectric layer covers the metal pillars and the buried components, wherein the second surface of the dielectric layer is flush with at least one active surface of the at least one buried component and a top surface of each metal pillar. The conductive vias respectively extend from the first surface of the dielectric layer and connect the metal pillars. The patterned line layer is disposed on the first surface of the dielectric layer and is electrically connected to the conductive vias.
[0006] In the package structure according to embodiments of the present application, the dielectric layer has a thickness of 75-300 micrometers. The dielectric layer is made of epoxy molding compound or Ajinomoto build-up film (ABF).
[0007] In the package structure according to embodiments of the present application, the signal interconnect structure layer includes multiple dielectric layers, multiple patterned circuit layers, and multiple conductive blind vias. The dielectric layers and the patterned circuit layers are arranged alternately, and the conductive blind vias electrically connect two adjacent patterned circuit layers.
[0008] In the package structure according to embodiments of the present application, the power supply structure layer is a wiring-free substrate but contains one or multiple different power supplies sharing a same plane and has multiple copper layers, multiple dielectric layers, multiple through vias, and a solder mask. The through vias penetrate the dielectric layers and are electrically connected to the signal interconnect structure layer.
[0009] In the package structure according to embodiments of the present application, the power supply structure layer further includes a deep trench capacitor (DTC) and an integrated voltage regulator (IVR), and the two types of chips are arranged in at least one of the dielectric layers.
[0010] In the package structure according to embodiments of the present application, the electronic assembly includes co-packaged optics (CPO), at least one artificial intelligence super chip, at least one passive component, or a combination thereof.
[0011] In the package structure according to embodiments of the present application, the embedded assembly includes an embedded multi-die interconnect bridge (EMIB) chip.
[0012] In the package structure according to embodiments of the present application, the package structure further includes a stabilizing ring arranged on the second surface of the embedded assembly circuit structure layer and surrounding the electronic assembly.
[0013] According to an embodiment of the present application, a method for fabricating a package structure includes the following steps. A carrier plate is provided. The carrier plate includes a substrate, a stainless steel layer, and a metal layer. The stainless steel layer is formed on the substrate and conformally covers the substrate, and the metal layer is formed on the stainless steel layer and conformally covers the stainless steel layer. An embedded component circuit structure layer is formed on the carrier plate. The embedded component circuit structure layer includes at least one embedded component. An active surface of the at least one embedded component contacts the carrier plate and an insulating layer. A signal interconnect structure layer is formed on a first surface of the embedded component circuit structure layer. The signal interconnect structure layer is electrically connected to the embedded component circuit structure layer. A power supply structure layer is formed on the signal interconnect structure layer. The power supply structure layer is electrically connected to the signal interconnect structure layer. The carrier plate is removed to expose the active surface of the at least one embedded component and a second surface of the embedded component circuit structure layer. An electronic component layer is disposed on the second surface of the embedded component circuit structure layer, wherein the electronic component layer includes a plurality of electronic components. The electronic components are electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnect structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power supply structure layer.
[0014] Based on the above, in the package structure of the present application, the coefficient of thermal expansion of the signal interconnect structure layer between the embedded component circuit structure layer and the power supply structure layer is higher than the coefficient of thermal expansion of the electronic component layer and the coefficient of thermal expansion of the power supply structure layer, and the latter two coefficients of thermal expansion are similar, so that a stable balance effect can be maintained during temperature difference changes, and board warping can be effectively reduced, and the structural reliability of the package structure of the present application can be increased. In addition, compared with the prior art organic core interconnect substrate with embedded multi-chip interconnect bridge chips, the fabrication of the embedded component circuit structure layer, the signal interconnect structure layer, and the power supply structure layer of the present application can effectively reduce production costs. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figures 1A-1H is a cross-sectional schematic view of a method for fabricating a package structure according to an embodiment of the present application.
[0016] REFERENCE NUMERALS
[0017] 10: carrier plate;
[0018] 12: substrate;
[0019] 14: stainless steel layer;
[0020] 16: metal layer;
[0021] 100: package structure
[0022] 110: embedded component circuit structure layer;
[0023] 111: first surface;
[0024] 112: metal pillar;
[0025] 113: second surface;
[0026] 114: dielectric layer;
[0027] 115: embedded component;
[0028] 116: conductive via;
[0029] 118: patterned line layer;
[0030] 120: signal interconnect structure layer;
[0031] 122: patterned line layer;
[0032] 124: dielectric layer;
[0033] 126: conductive blind via;
[0034] 130: power supply structure layer;
[0035] 131: deep trench capacitor;
[0036] 132: copper layer;
[0037] 133: integrated voltage regulator;
[0038] 134: dielectric layer;
[0039] 136: via;
[0040] 138: anti-etch layer;
[0041] 140: electronic component layer;
[0042] 142, 144, 146, 148: electronic component;
[0043] 150: stabilization ring;
[0044] 160: build-up structure layer;
[0045] 162: conductive structure;
[0046] 164: dielectric layer;
[0047] A: active surface;
[0048] B: blind via;
[0049] D: thickness;
[0050] T: top surface. DETAILED DESCRIPTION
[0051] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
[0052] Embodiments of the application can be understood more readily by reference to the following detailed description of the embodiments and the examples and claims appended hereto. The application will be described with reference to the attached drawings, which are meant to be non-limiting illustrative and are included solely for explaining features that are otherwise described in the detailed description. It should be appreciated that the drawings depicted are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to depict the general structure of the application.
[0053] Figures 1A-1H is a cross-sectional view of a method of fabricating a package structure according to an embodiment of the application. It is noted that the following is exemplified by a double-sided process to increase throughput and structural strength. However, in other embodiments, a single-sided process can be used as desired, which is still within the scope of the application.
[0054] With regard to the method of fabricating a package structure according to the present embodiment, first, please refer to Figure 1A , a carrier 10 is provided. The carrier 10 includes a substrate 12, a stainless steel layer 14, and a metal layer 16. The stainless steel layer 14 is formed on the substrate 12 and conformally covers the substrate 12. The metal layer 16 is formed on the stainless steel layer 14 and conformally covers the stainless steel layer 14. Here, the substrate 12 can be, for example, a core substrate composed of a sheet-shaped glass resin base and copper foils disposed on opposite sides of the sheet-shaped glass resin base, which can be considered as a kind of hard board, but is not limited thereto.
[0055] Next, please refer to Figure 1B , the metal layer 16 is used as a seed layer to electroplate a metal material layer to form a plurality of metal pillars 112 separated from each other. In an embodiment, each metal pillar 112 has a height of, for example, 70 microns, a diameter of, for example, 70 microns, and a pitch of, for example, 90 microns, but is not limited thereto.
[0056] Next, please refer to Figure 1C , at least one embedded component (two embedded components 115 are shown schematically) is attached to the metal layer 16, where an active surface A of the embedded component 115 contacts the metal layer 16 of the carrier 10, and the metal pillars 112 surround the embedded component 115. In an embodiment, the embedded component 115 is, for example, an Embedded Multi-die Interconnect Bridge (EMIB) chip, but is not limited thereto.
[0057] Next, please refer to Figure 1DThe dielectric layer 114 is formed to cover the metal pillars 112 and the embedded component 115, wherein the dielectric layer 114 has a first surface 111 and a second surface 113, and the second surface 113 of the dielectric layer 114 is flush with the active surface A of the embedded component 115 and the top surface T of each metal pillar 112. In an embodiment, the thickness D of the dielectric layer 114 is between 75 microns and 300 microns, which can be considered as a planar layer. In an embodiment, the material of the dielectric layer 114 is, for example, an epoxy molding compound or an Ajinomoto build-up film (ABF), but is not limited thereto.
[0058] Next, referring to Figure 1E The dielectric layer 114 is subjected to a laser process, for example, laser drilling, to form a plurality of blind vias B on the first surface 111 of the dielectric layer 114, wherein the blind vias B extend from the first surface 111 to the metal pillars 112. Subsequently, a metal material layer is electroplated in the blind vias B and on the first surface 111 of the dielectric layer 114, thereby forming conductive vias 116 structurally and electrically connected to the metal pillars 112 and a patterned circuit layer 118 on the first surface 111 of the dielectric layer 114 and electrically connected to the conductive vias 116. At this point, the embedded component circuit structure layer 110 has been formed on the carrier board 10, wherein the embedded component circuit structure layer 110 includes the embedded component 115, and the active surface A of the embedded component 115 contacts the carrier board 10.
[0059] Next, referring to Figure 1F The signal interconnection structure layer 120 is formed on the first surface 111 of the embedded component circuit structure layer 110, wherein the signal interconnection structure layer 120 is electrically connected to the embedded component circuit structure layer 110. In an embodiment, the signal interconnection structure layer 120 includes a plurality of patterned circuit layers 122, a plurality of dielectric layers 124, and a plurality of conductive blind vias 126. The dielectric layers 124 and the patterned circuit layers 122 are arranged alternately Figure 1FThe middle multi-layers of the signal interconnection structure layer 120 are shown in an omitted manner with conductive blind vias 126 connecting between the layers, and a dielectric layer 124 covering the first surface 111 of the embedded component circuit structure layer 110 and the patterned circuit layer 118, and the conductive blind vias 126 electrically connecting two adjacent patterned circuit layers 122. In an embodiment, the material of the dielectric layer 124 is, for example, polyimide (PI), Ajinomoto build-up film (ABF), or benzocyclobutene (BCB), but is not limited thereto. The material of the patterned circuit layer 122 and the conductive blind via 126 can be, for example, copper, but is not limited thereto. In an embodiment, the signal interconnection structure layer 120 can have nine patterned circuit layers 122, wherein the line width / space of each patterned circuit layer 122 is, for example, 8 microns, and the thickness of the patterned circuit layer 122 is, for example, 12 microns, but is not limited thereto.
[0060] Next, referring to Figure 1G A power supply structure layer 130 is formed on the signal interconnection structure layer 120, wherein the power supply structure layer 130 is electrically connected to the signal interconnection structure layer 120. In an embodiment, the power supply structure layer 130 is a wireless circuit substrate, but contains one or several different power supplies sharing a plane, and has multi-layer copper layers 132, multi-layer dielectric layers 134, a plurality of through holes 136, and a solder mask layer 138. The through holes 136 penetrate through the dielectric layers 134 and are electrically connected to the signal interconnection structure layer 120 to achieve power supply transmission. That is, the power supply structure layer 130 of the present embodiment does not have a circuit structure, but only has the through holes 136 for transmitting power and signals. In an embodiment, the power supply structure layer 130 can be attached to the corresponding patterned circuit layer 118 on the signal interconnection structure layer 120 by hot pressing after filling conductive paste into the through hole part of the power supply structure layer 130 after laser perforation, for example, by using a bonding film.
[0061] In one embodiment, the dielectric layer 134 is made of, for example, a pre-preg (PP) or other low coefficient of thermal expansion (CTE) material. In this regard, the low coefficient of thermal expansion is, for example, between 1 ppm / K and 3 ppm / K, but is not limited thereto. The via 136 is made of, for example, copper, but is not limited thereto. Preferably, the peripheral surface of the signal interconnect structure layer 120 can be trimmed to the peripheral surface of the power structure layer 130. That is, the size of the power structure layer 130 in the present embodiment is the same as the size of the signal interconnect structure layer 120. In this regard, the size can include length, width, and / or area. In one embodiment, the signal interconnect structure layer 120 and the power structure layer 130 can be considered as a coreless substrate.
[0062] Further, please refer to Figure 1G In the present embodiment, the power structure layer 130 further includes a deep trench capacitor (DTC) 131 and an integrated voltage regulator (IVR) 133, which are disposed in the same dielectric layer 134. In one embodiment, the deep trench capacitor 131 and the integrated voltage regulator 133 are directly electrically connected to the patterned line layer 122 of the signal interconnect structure layer 120, but are not limited thereto.
[0063] Next, please refer to Figure 1G and Figure 1H The carrier substrate 10 is removed, thereby exposing the active surface A of the embedded component 150 110 and the second surface 113 of the embedded component line structure layer 110.
[0064] Finally, please refer to Figure 1H The electronic component layer 140 is disposed on the second surface 113 of the embedded component line structure layer 110, wherein the electronic component layer 140 includes a plurality of electronic components 142, 144, 146, 148, which are electrically connected to the embedded component 115 and the metal pillar 112 of the embedded component line structure layer 110 through the build-up structure layer 160. The build-up structure layer 160 includes a conductive structure 162 and a dielectric layer 164, wherein the conductive structure 162 penetrates through the dielectric layer 164 and electrically connects the electronic components 142, 144, 146, 148 and the embedded component 115 and the metal pillar 112 of the embedded component line structure layer 110, thereby achieving high-density interconnection. In particular, in the present embodiment, the coefficient of thermal expansion of the signal interconnect structure layer 120 is higher than the coefficients of thermal expansion of the electronic component layer 140 and the power structure layer 130, and the coefficients of thermal expansion of the latter two are similar, so that stable balance can be maintained during temperature change, thereby effectively reducing board warping.
[0065] Furthermore, refer to Figure 1H A stabilization ring 150 is formed on the second surface 113 of the embedded component circuitry structure layer 110, wherein the stabilization ring 150 surrounds the electronic components 142, 144, 146, 148. In an embodiment, the stabilization ring 150 can be made of, for example, stainless steel, but is not limited thereto. In an embodiment, solder balls electrically connected to the outside can also be formed at the solder mask 138 of the power supply structure layer 130, but are not limited thereto. In this way, the fabrication of the package structure 100 is completed.
[0066] Furthermore, refer to Figure 1H In terms of structure, the package structure 100 includes an embedded component circuitry structure layer 110, a signal interconnection structure layer 120, a power supply structure layer 130, and an electronic component layer 140. The embedded component circuitry structure layer 110 includes an embedded component 115 and has a first surface 111 and a second surface 113 opposite to each other. The signal interconnection structure layer 120 is disposed on the first surface 111 of the embedded component circuitry structure layer 110 and is electrically connected to the embedded component circuitry structure layer 110. The power supply structure layer 130 is disposed on the signal interconnection structure layer 120 and is electrically connected to the signal interconnection structure layer 120. The electronic component layer 140 includes a plurality of electronic components 142, 144, 146, 148, is disposed on the second surface 113 of the embedded component circuitry structure layer 110, and is electrically connected to the embedded component circuitry structure layer 110. The signal interconnection structure layer 120 has a higher coefficient of thermal expansion than the electronic component layer 140 and the power supply structure layer 130.
[0067] In an embodiment, the embedded component 115 is, for example, an Embedded Multi-die Interconnect Bridge (EMIB) chip, which can be electrically connected to the electronic components 142, 144, 146, 148 through the conductive structures 162 of the build-up structure layer 160 to achieve high-density interconnection. In an embodiment, the electronic components 142, 144 can be, for example, artificial intelligence super chips, and the electronic component 146 can be, for example, a passive component, and the electronic component 146 can be, for example, an optical co-package, but are not limited thereto. Furthermore, in the present embodiment, the power supply structure layer 130 further includes a deep trench capacitor 131 and an integrated voltage regulator 133 embedded therein. In addition, the package structure 100 further includes a stabilization ring 150 disposed on the second surface 113 of the embedded component circuitry structure layer 110 and surrounding the electronic components 142, 144, 146, 148.
[0068] In summary, in the packaging structure of the present application, the thermal expansion coefficient of the signal interconnection structure layer between the embedded component circuit structure layer and the power supply structure layer is higher than the thermal expansion coefficients of the electronic component layer and the power supply structure layer, and the thermal expansion coefficients of the latter two are similar, so that the stable balance effect can be maintained in the temperature difference change, the board warping can be effectively slowed down, and the structural reliability of the packaging structure of the present application can be increased. In addition, compared with the prior art of using the core interconnection substrate embedded with the embedded multi-chip interconnection bridge chip, the production of the embedded component circuit structure layer, the signal interconnection structure layer and the power supply structure layer of the present application can effectively reduce the production cost.
[0069] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A packaging structure, characterized in that, include: An embedded component wiring structure layer includes at least one embedded component and has a first surface and a second surface that are opposite to each other. A signal interconnect structure layer is disposed on the first surface of the embedded component circuit structure layer and is electrically connected to the embedded component circuit structure layer. A power structure layer is disposed on the signal interconnect structure layer and electrically connected to the signal interconnect structure layer; as well as An electronic component layer, comprising a plurality of electronic components, is disposed on the second surface of the embedded component circuit structure layer and electrically connected to the embedded component circuit structure layer, wherein the coefficient of thermal expansion of the signal interconnect structure layer is higher than that of the electronic component layer and the power supply structure layer, and the latter two have similar coefficients of thermal expansion.
2. The packaging structure according to claim 1, characterized in that, The embedded component circuit structure layer also includes: Multiple metal pillars; A dielectric layer having a first surface and a second surface, the dielectric layer covering the plurality of metal pillars and the embedded component, wherein the second surface of the dielectric layer is flush with at least one active surface of the at least one embedded component and the top surface of each of the plurality of metal pillars; Multiple conductive vias extend from the first surface of the dielectric layer and connect to the multiple metal pillars; and A patterned circuit layer is disposed on the first surface of the dielectric layer and electrically connected to the plurality of conductive vias.
3. The packaging structure according to claim 2, characterized in that, The thickness of the dielectric layer is between 75 micrometers and 300 micrometers, and the material of the dielectric layer includes epoxy molding resin or Ajinomoto stacked film.
4. The packaging structure according to claim 1, characterized in that, The signal interconnect structure layer includes multiple dielectric layers, multiple patterned circuit layers, and multiple conductive blind vias. The multiple dielectric layers and the multiple patterned circuit layers are arranged alternately, and the multiple conductive blind vias are electrically connected to two adjacent patterned circuit layers.
5. The packaging structure according to claim 1, characterized in that, The power structure layer is a circuitless substrate but contains one or more different power supplies in a common plane and has multiple copper layers, multiple dielectric layers, multiple vias and a solder mask layer. The multiple vias penetrate the multiple dielectric layers and are electrically connected to the signal interconnect structure layer.
6. The packaging structure according to claim 5, characterized in that, The power supply structure layer also includes: Deep trench capacitors and integrated voltage regulators are disposed within at least one of the plurality of dielectric layers.
7. The packaging structure according to claim 1, characterized in that, The plurality of electronic components include optical co-packaging, at least one artificial intelligence super chip, at least one passive component, or a combination thereof.
8. The packaging structure according to claim 1, characterized in that, The embedded component includes an embedded multi-chip interconnect bridge chip.
9. The packaging structure according to claim 1, characterized in that, Also includes: A stabilizing ring is disposed on the second surface of the embedded component circuit structure layer and surrounds the plurality of electronic components.
10. A method for manufacturing an encapsulation structure, characterized in that, include: A carrier plate is provided, the carrier plate including a substrate, a stainless steel layer and a metal layer, the stainless steel layer being formed on the substrate and conformally covering the substrate, and the metal layer being formed on the stainless steel layer and conformally covering the stainless steel layer; An embedded component circuit structure layer is formed on the carrier plate, the embedded component circuit structure layer includes at least one embedded component, and at least one active surface of the at least one embedded component contacts the carrier plate; A signal interconnect structure layer is formed on the first surface of the embedded component circuit structure layer, and the signal interconnect structure layer is electrically connected to the embedded component circuit structure layer. A power structure layer is formed on the signal interconnect structure layer, and the power structure layer is electrically connected to the signal interconnect structure layer; Remove the carrier board to expose the active surface of the at least one embedded component and the second surface of the embedded component circuit structure layer; as well as An electronic component layer is configured on the second surface of the embedded component circuit structure layer. The electronic component layer includes a plurality of electronic components, wherein the plurality of electronic components are electrically connected to the embedded component circuit structure layer, and the coefficient of thermal expansion of the signal interconnect structure layer is higher than the coefficient of thermal expansion of the electronic component layer and the coefficient of thermal expansion of the power supply structure layer.