Circuit transient interference verification method and device and electronic equipment
By calculating the flip-off time difference of integrated circuit signal paths using different simulation models, the problem of low efficiency in transient interference verification in existing technologies is solved, and more efficient transient interference identification and localization are achieved.
Patent Information
- Application Number
- CN202511351469.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-22
- Publication Date
- 2026-01-27
AI Technical Summary
In existing technologies, transient interference verification is inefficient, especially in integrated circuits where it is difficult to efficiently identify transient invalid flips caused by differences in signal path delays and coupling noise, leading to a surge in dynamic power consumption and timing violations.
By acquiring the first and second simulation data of the target circuit, the difference in the switching time of the signal path is calculated using different simulation models (such as the nonlinear delay model and the composite current source model), the existence of transient interference in the circuit is verified, and the verification process is optimized through scenario expansion and interpolation.
It improves the efficiency of transient interference verification in circuits, reduces the need for specific waveform analysis for each circuit, and enables faster identification and location of transient interference.
Smart Images
Figure CN121413530A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a circuit glitch verification method and device, an electronic device, and a storage medium. BACKGROUND
[0002] Glitch is a short-term invalid flip phenomenon caused by signal path delay difference or coupling noise in an integrated circuit, which has a serious impact on circuit power consumption, timing and reliability. The specific impacts include:
[0003] 1. Dynamic power surge
[0004] Glitch can cause multiple invalid flips at the output end of the combinational logic, resulting in additional charge and discharge operations. In advanced processes (such as below 16nm), Glitch power consumption can account for more than 20% of the total dynamic power consumption, which is particularly significant for high-performance chips such as AI accelerators. For example, the multiply-accumulate unit in a neural network processor frequently produces Glitch due to deep-level combinational logic and signal delay differences, resulting in energy waste.
[0005] 2. Timing violations and signal integrity
[0006] Glitch can change the delay (Delta Delay) of adjacent signals through crosstalk. For example, when the aggressor and victim signal flip directions are opposite, the propagation delay of the victim line increases, causing critical path timing violations. In high-sensitive areas such as clock networks, such interference can cause metastability or functional errors.
[0007] Therefore, effective glitch verification is extremely important. In the prior art, tools such as HSPICE and Cadence Spectre can simulate Glitch caused by switching transients, such as MOS tube charging and discharging, Miller capacitance effect, which are mainly used in transistor-level simulation. In gate-level timing simulation, Glitch in the signal path can be verified by combinational logic competition and hazards in the logic design stage combined with process library models. However, these glitch verification methods mostly need to be analyzed specifically for different circuits, such as detailed viewing of simulation signal waveform graphs of each circuit, and therefore the verification efficiency is low. SUMMARY
[0008] Therefore, the embodiments of the present application provide a glitch verification method and device, an electronic device, and a storage medium, which can effectively improve the verification efficiency of circuit glitch.
[0009] In a first aspect, embodiments of the present invention provide a method for verifying transient interference in a circuit, comprising: acquiring first simulation data and second simulation data of a target circuit, wherein the first simulation data and the second simulation data are obtained based on different simulation models; the simulation models are used to determine the flip-off time of the output signal of each signal path in the target circuit; the flip-off time includes the first flip-off time in the first simulation data and the second flip-off time in the second simulation data; and verifying whether transient interference exists in each signal path of the target circuit based on the difference between the first flip-off time and the second flip-off time.
[0010] In one embodiment, obtaining the first simulation data and the second simulation data of the target circuit includes: obtaining the netlist file of the target circuit; determining the first simulation data of the target circuit based on the netlist file and the first simulation model; and determining the second simulation data of the target circuit based on the netlist file and the second simulation model, wherein the first simulation model and the second simulation model are different.
[0011] In one implementation, the first simulation model includes a nonlinear delay model, and the second simulation model includes a composite current source model.
[0012] In one embodiment, verifying whether transient interference exists in each signal path of the target circuit based on the difference between the first flip time and the second flip time includes: for each signal path in the target circuit, verifying whether the absolute value of the difference between the first flip time and the second flip time is greater than a preset duration threshold; if the absolute value of the difference between the first flip time and the second flip time is greater than the preset duration threshold, determining that transient interference exists in the signal path; or, if the absolute value of the difference between the first flip time and the second flip time is less than or equal to the preset duration threshold, determining that transient interference does not exist in the signal path.
[0013] In one embodiment, after determining that transient interference exists in the signal path, the method further includes: determining the circuit operating scenario in which the transient interference occurs in the signal path, wherein the circuit operating scenario is determined by the temperature, voltage, process angle, input signal flip time, and output load capacitance of the target circuit.
[0014] In one implementation, the circuit operation scenario includes multiple original operation scenarios, which form an original operation scenario set; the first simulation data and the second simulation data are obtained based on simulations of each of the original operation scenarios; determining the circuit operation scenario in which the transient interference is located in the signal path includes: determining the scenario set in which the transient interference is located in the original operation scenario set to obtain a first target scenario set, and determining the scenario set in the original operation scenario set where the transient interference does not exist to obtain a non-target scenario set; expanding the scenario based on the first target scenario set to obtain a second target scenario set, wherein the second target scenario set includes the first target scenario set and part of the non-target scenario set; performing scenario interpolation on the second target scenario set to obtain a third target scenario set, wherein the third target scenario set includes The number of scenarios included in the third target scenario set is greater than the number of scenarios included in the second target scenario set; the difference between the third target scenario set and the first target scenario set is determined to obtain a supplementary set; based on the first simulation model, the first supplementary data for the signal path under each operating scenario in the supplementary set is determined, and the second supplementary data for the signal path under each operating scenario in the supplementary set is determined based on the second simulation model; the first supplementary data is used as the new first simulation data, and the second supplementary data is used as the new second simulation data, and the process jumps to the step of obtaining the first simulation data and the second simulation data of the target circuit to continue execution, iterating N times, and obtaining the corresponding first target scenario set in each iteration, where N is a positive integer; the scenarios in the first target scenario set corresponding to each iteration are taken as the circuit operating scenario where the transient interference is located in the signal path.
[0015] In one embodiment, after determining that transient interference exists in the signal path, the method further includes: determining the location of the transient interference in the signal path.
[0016] In one implementation, determining the location of the transient interference in the signal path includes: dividing the target circuit into multiple channel connection blocks according to the netlist file of the target circuit, so that the signal path is distributed in at least two channel connection blocks, forming at least two corresponding signal segments; taking each channel connection block as a new target circuit and the signal segment in the channel connection block as a new signal path, jumping to the step of obtaining the first simulation data and the second simulation data of the target circuit to continue execution, to determine whether transient interference exists in the signal segment in each channel connection block; and determining the location of the transient interference in the signal path based on whether transient interference exists in the signal segment in each channel connection block.
[0017] Secondly, embodiments of the present invention also provide a circuit transient interference verification device, comprising: an acquisition unit, configured to acquire first simulation data and second simulation data of a target circuit, wherein the first simulation data and the second simulation data are obtained based on different simulation models; the simulation models are used to determine the flip time of the output signal of each signal path in the target circuit; the flip time includes the first flip time in the first simulation data and the second flip time in the second simulation data; and a verification unit, configured to verify whether transient interference exists in each signal path of the target circuit based on the difference between the first flip time and the second flip time.
[0018] In one embodiment, the acquisition unit is specifically used to: acquire the netlist file of the target circuit; determine the first simulation data of the target circuit based on the netlist file and the first simulation model; and determine the second simulation data of the target circuit based on the netlist file and the second simulation model, wherein the first simulation model and the second simulation model are different.
[0019] In one implementation, the first simulation model includes a nonlinear delay model, and the second simulation model includes a composite current source model.
[0020] In one embodiment, the verification unit is specifically configured to: for each signal path in the target circuit, verify whether the absolute value of the difference between the first flip time and the second flip time is greater than a preset duration threshold; if the absolute value of the difference between the first flip time and the second flip time is greater than the preset duration threshold, determine that the signal path has transient interference; or, if the absolute value of the difference between the first flip time and the second flip time is less than or equal to the preset duration threshold, determine that the signal path does not have transient interference.
[0021] In one embodiment, the device further includes a scenario determination unit, configured to determine, after determining that transient interference exists in the signal path, the circuit operation scenario in which the transient interference is located, wherein the circuit operation scenario is determined by the temperature, voltage, process angle, input signal flip time, and output load capacitance of the target circuit.
[0022] In one embodiment, the circuit operation scenario includes multiple original operation scenarios, which form an original operation scenario set; the first simulation data and the second simulation data are obtained based on simulations of each of the original operation scenarios; the scenario determination unit is specifically used to: determine the scenario set where the transient interference is located in the original operation scenario set to obtain a first target scenario set, and determine the scenario set where the transient interference does not exist in the original operation scenario set to obtain a non-target scenario set; expand the scenarios based on the first target scenario set to obtain a second target scenario set, wherein the second target scenario set includes the first target scenario set and part of the non-target scenario set; perform scenario interpolation on the second target scenario set to obtain a third target scenario set, wherein the third target scenario set... The number of scenarios included in the third target scenario set is greater than the number of scenarios included in the second target scenario set; the difference between the third target scenario set and the first target scenario set is determined to obtain a supplementary set; based on the first simulation model, the first supplementary data for the signal path under each operating scenario in the supplementary set is determined, and the second supplementary data for the signal path under each operating scenario in the supplementary set is determined based on the second simulation model; the first supplementary data is used as the new first simulation data, and the second supplementary data is used as the new second simulation data, triggering the acquisition unit to continue execution, iterating N times, and obtaining the corresponding first target scenario set in each iteration, where N is a positive integer; the scenarios in the first target scenario set corresponding to each iteration are taken as the circuit operating scenario where the transient interference is located in the signal path.
[0023] In one embodiment, the device further includes a position determination unit, configured to determine the position of the transient interference in the signal path after determining that transient interference exists in the signal path.
[0024] In one implementation, the location determination unit is specifically used to: divide the target circuit into multiple channel connection blocks according to the netlist file of the target circuit, so that the signal path is distributed in at least two channel connection blocks, forming at least two corresponding signal segments; take each channel connection block as the new target circuit, and take the signal segment in the channel connection block as the new signal path, trigger the acquisition unit to continue execution, so as to determine whether there is transient interference in the signal segment in each channel connection block; and determine the location of the transient interference in the signal path according to whether there is transient interference in the signal segment in each channel connection block.
[0025] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a processor and a memory, the processor being electrically connected to the memory; the memory being used to store executable program code; the processor running a program corresponding to the executable program code by reading the executable program code stored in the memory, thereby implementing the circuit transient interference method provided by any one of the embodiments of the present invention.
[0026] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the circuit transient interference methods provided in the embodiments of the present invention.
[0027] The circuit transient interference verification method, apparatus, electronic device, and storage medium provided by embodiments of the present invention can acquire first and second simulation data of a target circuit, and verify whether transient interference exists in each signal path of the target circuit based on the difference between the first and second flip times. Thus, for various circuits, the first and second flip times can be obtained through co-simulation of different models, and the difference between the first and second flip times can be used to verify whether transient interference exists in each signal path of the target circuit, without requiring specific waveform analysis for each circuit. Therefore, it can effectively improve the verification efficiency of circuit transient interference. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 A flowchart of a method for verifying transient interference in a circuit, provided as an embodiment of the present invention;
[0030] Figure 2 The NLDM model and CCSM model, and the schematic diagram of flip-over time calculation provided for embodiments of the present invention;
[0031] Figure 3 A schematic diagram of the scenario distribution of transient interference in a circuit provided for an embodiment of the present invention;
[0032] Figure 4 A schematic diagram of the scene interpolation process provided for an embodiment of the present invention;
[0033] Figure 5A schematic diagram of scene interpolation results provided for an embodiment of the present invention;
[0034] Figure 6 A schematic diagram illustrating the disassembly and determination of transient interference locations using a channel connecting block, provided as an embodiment of the present invention;
[0035] Figure 7 A detailed flowchart of a method for verifying transient interference in circuits provided in an embodiment of the present invention;
[0036] Figure 8 A schematic diagram of a circuit transient interference verification device provided for an embodiment of the present invention;
[0037] Figure 9 A schematic diagram of an electronic device provided as an embodiment of the present invention. Detailed Implementation
[0038] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0039] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0040] In a first aspect, embodiments of the present invention provide a method for verifying transient interference in circuits, which can effectively improve the verification efficiency of transient interference in circuits.
[0041] like Figure 1 As shown, an embodiment of the present invention provides a method for verifying transient interference in a circuit, which may include:
[0042] S11, acquire first simulation data and second simulation data of the target circuit, wherein the first simulation data and the second simulation data are obtained based on different simulation models; the simulation models are used to determine the flip time of the output signal of each signal path in the target circuit; the flip time includes the first flip time in the first simulation data and the second flip time in the second simulation data;
[0043] In this step, the first flip time in the first simulation data and the second flip time in the second simulation data of the target circuit can be obtained.
[0044] A simulation model can be a computer program or algorithm that mathematically abstracts and describes a target circuit, defining the behavior, interconnections, and response characteristics of circuit elements (such as transistors, resistors, and capacitors) under the influence of input signals. Different simulation models imply the use of different modeling assumptions or parameter settings. For example, one model may use ideal device parameters and wiring (fast model), while another model may include more accurate process variations, parasitic resistance / capacitance effects, or temperature and voltage fluctuations (slow model or corner model).
[0045] The specific results generated by running these models are the simulation data. Simulation data contains precise waveform information showing the voltage changes over time at key nodes in the circuit. A signal path can refer to the complete link of logic gates and interconnects that a signal passes through from its starting point to its ending point in the circuit. From the waveforms of the simulation data, the specific time at which the logic state of the output signal at the end of each signal path changes (e.g., from 0 to 1 or vice versa) can be extracted; this is the toggle time. The toggle time extracted from the simulation data obtained based on the first simulation model is the first toggle time, while the toggle time extracted from the simulation data obtained based on a second, different model is the second toggle time.
[0046] S12, based on the difference between the first flip time and the second flip time, verify whether there is transient interference in each signal path of the target circuit.
[0047] In this step, it can be verified whether there is transient interference in each signal path of the target circuit.
[0048] For each signal path in the target circuit, the first and second flip times of two different simulation models are compared, and the time difference between them is calculated to realize the transient interference verification of the target circuit.
[0049] The circuit transient interference verification method provided by the embodiments of the present invention can acquire first simulation data and second simulation data of the target circuit, and verify whether transient interference exists in each signal path of the target circuit based on the difference between the first flip time and the second flip time. In this way, the first flip time and the second flip time can be obtained through co-simulation of different models for various circuits, and the difference between the first flip time and the second flip time can be used to verify whether transient interference exists in each signal path of the target circuit, without the need for specific waveform analysis for each circuit. Therefore, it can effectively improve the verification efficiency of circuit transient interference.
[0050] Specifically, in step S11, the first simulation data and the second simulation data of the target circuit can be obtained by acquiring the netlist file of the target circuit. For example, in one embodiment, acquiring the first simulation data and the second simulation data of the target circuit may include: acquiring the netlist file of the target circuit; determining the first simulation data of the target circuit based on the netlist file and the first simulation model; and determining the second simulation data of the target circuit based on the netlist file and the second simulation model. Here, the first simulation model and the second simulation model use different simulation models.
[0051] For example, in a specific implementation, the netlist file of the target circuit can be obtained. The netlist file of the target circuit can be a Circuit Description Language (CDL) or a Detailed Standard Parasitic Format (DSPF), and this invention does not limit it. For example, in one embodiment, the netlist file of the target circuit can be feature data generated by the integrated circuit based on the Composite Current Source Model (CCSM) and the Non-linear Delay Model (NLDM).
[0052] Accordingly, the simulation model can include a nonlinear delay model or a composite current source model. For example, in one implementation, the first simulation model includes a nonlinear delay model, and the second simulation model includes a composite current source model.
[0053] Specifically, the NLDM model and the CCSM model calculate the flip-off time, such as... Figure 2 As shown. For the NLDM model, threshold 1 and threshold 2 can be defined as the voltage start and end values for calculating the switching time of the output signal in the NLDM model. For threshold 1, the minimum voltage threshold (or maximum voltage threshold) for calculating the switching time of the signal in the NLDM model is typically slightly less than the absolute value of the voltage change value represented by the transient interference. For threshold 2, the maximum voltage threshold (or minimum voltage threshold) for calculating the switching time of the signal in the NLDM model is typically slightly higher than 0.5 times (slightly lower than 0.5 times VDD). Therefore, the switching time of the NLDM model can be defined as:
[0054] = T 阈值2 -T 阈值1
[0055] NLDM directly uses the change in the output voltage value to calculate the switching time, which can be expressed as the time difference between the output voltage reaching threshold 2 and the time it reaches threshold 1.
[0056] The CCSM model abstracts the output behavior of driver units (such as logic gates) as a time- and voltage-dependent current source. Through pre-characterized current waveforms, dynamic capacitance modeling, and waveform integration, this model can accurately calculate the circuit's toggle time, making it particularly suitable for timing analysis at advanced process nodes. The toggle time of the CCSM model can be defined as:
[0057] =
[0058] That is, the time difference between the current integral causing the output voltage to reach threshold 2 and threshold 1.
[0059] Threshold 3 can be defined as the maximum value of the time difference between the output signal flipping time calculated by NLDM and CCSM.
[0060] After obtaining the first and second simulation data of the target circuit through the netlist file of the target circuit, step S12 can be used to verify whether transient interference exists in each signal path of the target circuit. For example, in one embodiment, verifying whether transient interference exists in each signal path of the target circuit based on the difference between the first and second flip times can include: for each signal path in the target circuit, verifying whether the absolute value of the difference between the first and second flip times is greater than a preset duration threshold; if the absolute value of the difference between the first and second flip times is greater than the preset duration threshold, determining that transient interference exists in that signal path; or, if the absolute value of the difference between the first and second flip times is less than or equal to the preset duration threshold, determining that transient interference does not exist in that signal path.
[0061] Specifically, in this embodiment, it is verified whether the absolute value of the difference between the first flip time and the second flip time is greater than a preset duration threshold. If the absolute value of the difference between the first flip time and the second flip time is greater than the preset duration threshold, it can be determined that transient interference exists in the signal path; if the absolute value of the difference between the first flip time and the second flip time is less than or equal to the preset duration threshold, it can be determined that there is no transient interference in the signal path. For example, if the preset duration threshold for the signal path is 0.015, and a signal path is verified to have an absolute value of 0.045 for the difference between the first flip time and the second flip time, it can be determined that the signal path has transient interference. Similarly, if a signal path is verified to have an absolute value of 0.005 for the difference between the first flip time and the second flip time, it can be determined that the signal path does not have transient interference.
[0062] The above embodiments detail how to determine the presence of transient interference in a signal path, but the embodiments of the present invention are not limited thereto. For example, in one embodiment of the present invention, after determining that transient interference exists in a signal path, the method may further include: determining the circuit operating scenario in which the transient interference occurs in the signal path, wherein the circuit operating scenario is determined by the temperature, voltage, process angle, input signal switching time, and output load capacitance of the target circuit.
[0063] Specifically, the circuit operation scenario in this embodiment is determined by the target circuit's temperature, voltage, process angle, input signal transition time, and output load capacitance. For example, it may include the input signal transition time range and the output load capacitance value range. In a specific implementation, the circuit operation scenario may include multiple original operation scenarios, and the first simulation data and second simulation data are obtained based on simulations of each original operation scenario.
[0064] For example, a circuit operating scenario includes multiple original operating scenarios, which together form a set of original operating scenarios; the first simulation data and the second simulation data are obtained based on simulations of each original operating scenario. In one implementation, determining the circuit operating scenario in which the transient interference in the signal path is located may include:
[0065] S21, determine the set of scenarios where transient interference is located in the original set of operating scenarios to obtain the first target scenario set, and determine the set of scenarios where there is no transient interference in the original set of operating scenarios to obtain the non-target scenario set;
[0066] S22, expand the first target scene set to obtain a second target scene set, wherein the second target scene set includes the first target scene set and a part of the non-target scene set;
[0067] S23, perform scene interpolation on the second target scene set to obtain the third target scene set, wherein the number of scenes contained in the third target scene set is greater than the number of scenes contained in the second target scene set;
[0068] S24, determine the difference between the third target scene set and the first target scene set to obtain the supplementary set;
[0069] S25, based on the first simulation model, determine the first supplementary data of the signal path under each operating scenario in the supplementary set, and based on the second simulation model, determine the second supplementary data of the signal path under each operating scenario in the supplementary set; use the first supplementary data as the new first simulation data, use the second supplementary data as the new second simulation data, jump to the step of obtaining the first simulation data and the second simulation data of the target circuit and continue execution, iterate N times, and each iteration obtains the corresponding first target scenario set, where N is a positive integer;
[0070] S26, take the scene in the first target scene set corresponding to each loop iteration as the circuit operation scene where the transient interference is located in the signal path.
[0071] Specifically, and exemplaryly, in this embodiment, the application scenario uses NLDM and CCSM to perform output signal flip-time feature calculations on the netlist file, generating a feature data matrix. The discrete points of the two indicator axes in the scenario (such as input signal flip-time and output load capacitance) adopt a linear distribution or an exponential distribution (covering the range from minimum to maximum value).
[0072] In practical implementation, the horizontal and vertical coordinates of the region can be refined to meet the characteristic rules. The refinement rules can be, but are not limited to: defining the values of the two indices (input signal flip time threshold and output load capacitance) of the located matrix region as the new maximum values of the indices in the new feature data matrix; defining a scenario for calculating the feature data in the new matrix; and defining the discrete points of the new scenario as either a linear or exponential distribution from the minimum to the maximum value of each indice axis. In the refined scenario, the output signal flip time characteristic calculation is performed, and the characteristic data matrix is generated again.
[0073] like Figure 3 As shown, it can record the regions within the feature data matrix that are greater than the threshold 3 for all process angles, voltages, and temperatures. Figure 3 The shaded area represents the region where the co-simulation results do not match. In other words, the shaded region represents the set of scenarios in the original set of running scenarios where transient interference is identified, i.e., the first target scenario set. Correspondingly, the set of scenarios in the original set of running scenarios where no transient interference is identified yields the non-target scenario set, i.e., the region outside the shaded area.
[0074] In this embodiment, after determining the first target scene set, the first target scene set can be used as a basis to expand the scene set, thereby obtaining a second target scene set. For example... Figure 4 As shown, the circular area on the left represents the second set of target scenes. It can be understood that the second set of target scenes includes the first set of target scenes and a portion of the non-target scene set. Figure 4The second target scene set shown is in Figure 3 The first target scene set shown is expanded by one unit to the right and downward respectively.
[0075] After obtaining the second target scene set, scene interpolation can be performed on the second target scene set to obtain the third target scene set. Figure 4 This is a scene interpolation diagram, where the shaded area on the right represents the newly added scene area. In this scene interpolation, the original scene 4... The area of 4 is expanded to 8. The region is 8. It is understandable that the third target scene set, obtained after scene interpolation of the second target scene set, contains more scenes than the second target scene set.
[0076] It should be noted that in this embodiment, the original scenario 4 4 areas expanded to 8 The region is 8, but this invention does not limit the specific extended region. That is, the interpolation scenario can be extended to a specific region as needed, such as 4, depending on the application requirements of the specific implementation. 8, 6 6, 6 8, etc. Furthermore, the method used for scene interpolation is not limited; mean interpolation or polynomial interpolation can be used, etc.
[0077] In specific implementation, after scene interpolation, the difference between the third target scene set and the first target scene set can be determined to obtain a supplementary set. Based on the first simulation model, the first supplementary data for each operating scenario in the supplementary set is determined, and the second supplementary data for each operating scenario in the supplementary set is determined based on the second simulation model. Based on this, the first supplementary data is used as the new first simulation data, and the second supplementary data is used as the new second simulation data. The process then jumps to the step of obtaining the first and second simulation data of the target circuit and continues execution, iterating N times. Each iteration yields the corresponding first target scene set, where N is a positive integer. This results in a complete and supplementary scene set.
[0078] After the complete set of scenarios is completed, for example, such as Figure 5 As shown, it can be determined that there is a matrix region where the time difference between the output signal flips exceeding a threshold of 3, calculated by NLDM and CCSM: that is, the corresponding input signal flip time threshold and output load capacitance threshold are determined. After this step, the application scenario range for the confirmed integrated circuit to generate transient interference can be obtained.
[0079] It should be noted that, in this embodiment, through the above process, after determining the set of scenes where transient interference is located in the original set of operating scenes and obtaining the first target scene set, the scene is expanded based on the first target scene set to obtain the second target scene set; and scene interpolation is performed on the second target scene set to obtain the third target scene set and supplementary data; thus, it is possible to more accurately locate the scene where transient interference exists.
[0080] Furthermore, in the embodiments provided by the present invention, after determining that transient interference exists in the signal path, the location of the transient interference within the signal path can also be determined. For example, in one embodiment, after determining that transient interference exists in the signal path, the method further includes: determining the location of the transient interference within the signal path. That is, based on the determination that transient interference exists in the signal path, the specific location of the transient interference within the signal path can be determined.
[0081] In this embodiment of the invention, the location of transient interference in a signal path can be determined. In specific examples, different methods may be used to determine the location, and this invention is not limited to these. For example, in one implementation, determining the location of transient interference in a signal path may include: dividing the target circuit into multiple channel connection blocks according to the netlist file of the target circuit, so that the signal path is distributed in at least two channel connection blocks, forming at least two corresponding signal segments; taking each channel connection block as a new target circuit and the signal segment in the channel connection block as a new signal path, jumping to the step of obtaining the first simulation data and the second simulation data of the target circuit to continue execution, to determine whether transient interference exists in the signal segment of each channel connection block; and determining the location of transient interference in the signal path based on whether transient interference exists in the signal segment of each channel connection block. Further, the source of transient interference can also be determined based on the signal flow direction, identifying the first signal segment in a signal path where transient interference occurs.
[0082] It's important to note that a Channel Connected Block (CCB) is a basic functional unit or logical region that a netlist is topologically divided into. A CCB typically contains a group of circuit elements (such as transistors, gates, and standard cells) directly and tightly connected via channels (e.g., metal interconnects, transistor channels), excluding the gate levels of transistors within the same CCB. By partitioning the target circuit based on the connections of signals through "channels," a long signal path spanning an entire complex circuit can be physically / logically divided into multiple shorter signal segments. Each segment is entirely within a single CCB.
[0083] Specifically, the unit is divided into channel connection modules (CCBs) according to the circuit structure. For the process angle, voltage, and temperature determined in the above steps, the input-to-output path and the scenario with transient interference are used. Output signal flip-time characterization calculations are performed separately using NLDM and CCSM in each channel connection module, or in a combination of channel connection modules. Based on the determined process angle, voltage, and temperature, the extreme values of the input-to-output path and the scenario with transient interference are characteristically calculated. The process of CCB splitting and transient interference localization based on CCBs can be described as follows: Figure 6 As shown. First, we can determine the signal path where the input signal InputA is located (e.g., ...). Figure 6 Transient interference exists in the area shown by the dashed line (e.g.) Figure 6 (As indicated by the "mismatch" arrow in the middle), after CCB splitting, multiple channel interconnect blocks can be formed (such as...) Figure 6 In blocks 1, 2, etc., the difference distribution between NLDM and CCSM calculation results is statistically analyzed in each channel connection module (CCB) to pinpoint the specific source of transient interference at the circuit level (e.g., ...). Figure 6 (As indicated by the glitch arrow).
[0084] The following detailed description of the circuit transient interference verification method provided by the embodiments of the present invention is based on a specific example.
[0085] like Figure 7 As shown, the circuit transient interference verification method provided by the embodiments of the present invention may include:
[0086] S301. Obtain the netlist file of the target circuit;
[0087] S302. Determine the first simulation data of the target circuit based on the netlist file and the first simulation model, and determine the second simulation data of the target circuit based on the netlist file and the second simulation model; wherein the first simulation data and the second simulation data are obtained based on different simulation models; the simulation model is used to determine the flip time of the output signal of each signal path in the target circuit; the flip time includes the first flip time in the first simulation data and the second flip time in the second simulation data;
[0088] Optionally, the first simulation model includes a nonlinear delay model, and the second simulation model includes a composite current source model;
[0089] S303. For each signal path in the target circuit, verify whether the absolute value of the difference between the first flip time and the second flip time is greater than a preset duration threshold.
[0090] S304. If the absolute value of the difference between the first flip time and the second flip time is greater than the preset duration threshold, it is determined that there is transient interference in the signal path.
[0091] S305. Determine the circuit operating scenario in which the transient interference occurs in the signal path, wherein the circuit operating scenario is determined by the temperature, voltage, process angle, input signal flip time, and output load capacitance of the target circuit.
[0092] S306. Based on the netlist file of the target circuit, the target circuit is divided into multiple channel connection blocks so that the signal path is distributed in at least two channel connection blocks, forming at least two corresponding signal segments;
[0093] S307. Taking each of the channel connection blocks as the new target circuit and the signal segment in the channel connection block as the new signal path, jump to step S302 to continue execution, in order to determine whether there is transient interference in the signal segment in each of the channel connection blocks;
[0094] S308. Determine the location of the transient interference in the signal path based on whether there is transient interference in the signal segment of each of the channel connecting blocks.
[0095] Secondly, embodiments of the present invention provide a circuit transient interference verification device, which can effectively improve the verification efficiency of circuit transient interference.
[0096] like Figure 8 As shown, the circuit transient interference verification device provided in the embodiments of the present invention may include:
[0097] The acquisition unit 41 is used to acquire first simulation data and second simulation data of the target circuit, wherein the first simulation data and the second simulation data are obtained based on different simulation models; the simulation models are used to determine the flip time of the output signal of each signal path in the target circuit; the flip time includes the first flip time in the first simulation data and the second flip time in the second simulation data.
[0098] The verification unit 42 is used to verify whether there is transient interference in each signal path of the target circuit based on the difference between the first flip time and the second flip time.
[0099] The circuit transient interference verification device provided in the embodiments of the present invention can acquire first simulation data and second simulation data of a target circuit, and verify whether transient interference exists in each signal path of the target circuit based on the difference between the first and second flip times. In this way, the first and second flip times can be obtained through co-simulation of different models for various circuits, and the difference between the first and second flip times can be used to verify whether transient interference exists in each signal path of the target circuit, without the need for specific waveform analysis for each circuit. Therefore, it can effectively improve the verification efficiency of circuit transient interference.
[0100] In one embodiment, the acquisition unit 41 is specifically used to: acquire the netlist file of the target circuit; determine the first simulation data of the target circuit based on the netlist file and the first simulation model; and determine the second simulation data of the target circuit based on the netlist file and the second simulation model, wherein the first simulation model and the second simulation model are different.
[0101] In one implementation, the first simulation model includes a nonlinear delay model, and the second simulation model includes a composite current source model.
[0102] In one embodiment, the verification unit 42 is specifically configured to: for each signal path in the target circuit, verify whether the absolute value of the difference between the first flip time and the second flip time is greater than a preset duration threshold; if the absolute value of the difference between the first flip time and the second flip time is greater than the preset duration threshold, determine that the signal path has transient interference; or, if the absolute value of the difference between the first flip time and the second flip time is less than or equal to the preset duration threshold, determine that the signal path does not have transient interference.
[0103] In one embodiment, the device further includes a scenario determination unit, configured to determine, after determining that transient interference exists in the signal path, the circuit operation scenario in which the transient interference is located, wherein the circuit operation scenario is determined by the temperature, voltage, process angle, input signal flip time, and output load capacitance of the target circuit.
[0104] In one embodiment, the circuit operation scenario includes multiple original operation scenarios, which form an original operation scenario set; the first simulation data and the second simulation data are obtained based on simulations of each of the original operation scenarios; the scenario determination unit is specifically used to: determine the scenario set where the transient interference is located in the original operation scenario set to obtain a first target scenario set, and determine the scenario set where the transient interference does not exist in the original operation scenario set to obtain a non-target scenario set; expand the scenarios based on the first target scenario set to obtain a second target scenario set, wherein the second target scenario set includes the first target scenario set and part of the non-target scenario set; perform scenario interpolation on the second target scenario set to obtain a third target scenario set, wherein the third target scenario set... The number of scenarios included in the third target scenario set is greater than the number of scenarios included in the second target scenario set; the difference between the third target scenario set and the first target scenario set is determined to obtain a supplementary set; based on the first simulation model, the first supplementary data of the signal path under each operating scenario in the supplementary set is determined, and the second supplementary data of the signal path under each operating scenario in the supplementary set is determined based on the second simulation model; the first supplementary data is used as the new first simulation data, and the second supplementary data is used as the new second simulation data, triggering the acquisition unit 41 to continue execution, iterating N times, and obtaining the corresponding first target scenario set in each iteration, where N is a positive integer; the scenarios in the first target scenario set corresponding to each iteration are taken as the circuit operating scenario where the transient interference is located in the signal path.
[0105] In one embodiment, the device further includes a position determination unit, configured to determine the position of the transient interference in the signal path after determining that transient interference exists in the signal path.
[0106] In one embodiment, the location determination unit is specifically used to: divide the target circuit into multiple channel connection blocks according to the netlist file of the target circuit, so that the signal path is distributed in at least two channel connection blocks, forming at least two corresponding signal segments; take each channel connection block as the new target circuit, and take the signal segment in the channel connection block as the new signal path, trigger the acquisition unit 41 to continue execution, so as to determine whether there is transient interference in the signal segment in each channel connection block; and determine the location of the transient interference in the signal path according to whether there is transient interference in the signal segment in each channel connection block.
[0107] Thirdly, embodiments of the present invention also provide an electronic device that can effectively improve the verification efficiency of transient interference in circuits.
[0108] like Figure 9 As shown, the electronic device provided in the embodiments of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 and the memory 72 are electrically connected; the memory 72 is used to store executable program code; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement any of the circuit transient interference verification methods provided in the foregoing embodiments.
[0109] The specific execution process of the above steps by the processor 71, as well as the steps further executed by the processor 71 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.
[0110] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the circuit transient interference verification methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.
[0111] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0112] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0113] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.
[0114] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.
[0115] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0116] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for verifying transient interference in a circuit, characterized in that, include: Acquire first and second simulation data of the target circuit, wherein the first and second simulation data are obtained based on different simulation models; The simulation model is used to determine the flip time of the output signal of each signal path in the target circuit; the flip time includes the first flip time in the first simulation data and the second flip time in the second simulation data; Based on the difference between the first flip time and the second flip time, verify whether there is transient interference in each signal path of the target circuit.
2. The method for verifying transient interference in a circuit according to claim 1, characterized in that, The acquisition of the first and second simulation data of the target circuit includes: Obtain the netlist file of the target circuit; The first simulation data of the target circuit is determined based on the netlist file and the first simulation model, and the second simulation data of the target circuit is determined based on the netlist file and the second simulation model, wherein the first simulation model and the second simulation model are different.
3. The method for verifying transient interference in a circuit according to claim 1, characterized in that, The first simulation model includes a nonlinear delay model, and the second simulation model includes a composite current source model.
4. The method for verifying transient interference in a circuit according to any one of claims 1 to 3, characterized in that, The step of verifying whether transient interference exists in each signal path of the target circuit based on the difference between the first flip time and the second flip time includes: For each signal path in the target circuit, verify whether the absolute value of the difference between the first flip time and the second flip time is greater than a preset duration threshold. If the absolute value of the difference between the first flip time and the second flip time is greater than the preset duration threshold, it is determined that there is transient interference in the signal path; or, If the absolute value of the difference between the first flip time and the second flip time is less than or equal to the preset duration threshold, it is determined that there is no transient interference in the signal path.
5. The method for verifying transient interference in a circuit according to claim 4, characterized in that, After determining that transient interference exists in the signal path, the method further includes: Determine the circuit operating scenario in which the transient interference occurs within the signal path, wherein the circuit operating scenario is determined by the temperature, voltage, process angle, input signal flip time, and output load capacitance of the target circuit.
6. The method for verifying transient interference in a circuit according to claim 5, characterized in that, The circuit operation scenario includes multiple original operation scenarios, and the multiple original operation scenarios form an original operation scenario set; The first simulation data and the second simulation data are obtained based on simulations of each of the original operating scenarios; The circuit operating scenario in which the transient interference occurs within the determined signal path includes: The set of scenarios in which the transient interference is located is determined from the original set of operating scenarios to obtain a first target set of scenarios; and the set of scenarios in which the transient interference does not exist is determined from the original set of operating scenarios to obtain a non-target set of scenarios. Based on the first target scene set, scene expansion is performed to obtain a second target scene set, wherein the second target scene set includes the first target scene set and a portion of the non-target scene set; The second target scene set is interpolated to obtain a third target scene set, wherein the third target scene set contains more scenes than the second target scene set. The difference between the third target scene set and the first target scene set is determined to obtain a supplementary set; Based on the first simulation model, the first supplementary data of the signal path in each operating scenario in the supplementary set is determined, and based on the second simulation model, the second supplementary data of the signal path in each operating scenario in the supplementary set is determined; The first supplementary data is used as the new first simulation data, and the second supplementary data is used as the new second simulation data. The process jumps to the step of obtaining the first simulation data and the second simulation data of the target circuit and continues to execute. The process is iterated N times, and each iteration obtains the corresponding first target scene set, where N is a positive integer. The scene in the first target scene set corresponding to each iteration is taken as the circuit operation scene where the transient interference is located in the signal path.
7. The method for verifying transient interference in a circuit according to claim 4, characterized in that, After determining that transient interference exists in the signal path, the method further includes: Determine the location of the transient interference in the signal path.
8. The method for verifying transient interference in a circuit according to claim 7, characterized in that, Determining the location of the transient interference in the signal path includes: Based on the netlist file of the target circuit, the target circuit is divided into multiple channel connection blocks, so that the signal path is distributed in at least two of the channel connection blocks, forming at least two corresponding signal segments; Taking each of the channel connection blocks as the new target circuit and the signal segment in the channel connection block as the new signal path, the process jumps to the step of obtaining the first simulation data and the second simulation data of the target circuit to continue execution, in order to determine whether there is transient interference in the signal segment in each of the channel connection blocks; The location of the transient interference in the signal path is determined based on whether transient interference exists in the signal segment of each of the aforementioned channel connection blocks.
9. A device for verifying transient interference in a circuit, characterized in that, include: An acquisition unit is configured to acquire first simulation data and second simulation data of a target circuit, wherein the first simulation data and the second simulation data are obtained based on different simulation models; the simulation models are used to determine the flip time of the output signal of each signal path in the target circuit; the flip time includes the first flip time in the first simulation data and the second flip time in the second simulation data. The verification unit is used to verify whether there is transient interference in each signal path of the target circuit based on the difference between the first flip time and the second flip time.
10. An electronic device, characterized in that, The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the circuit transient interference verification method according to any one of claims 1 to 8.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the method for verifying circuit transient interference as described in any one of claims 1 to 8.