Heterojunction voltage-stabilizing silicon carbide MOSFET and manufacturing method thereof

Abstract

The invention provides a heterojunction voltage-stabilizing silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices. An electrostatic protection unit is integrated between a grid electrode and a source electrode and comprises a heterojunction diode formed by an N-type polycrystalline silicon grid electrode and a specific heavily doped P + region in a direct contact mode and a homojunction diode formed by an N + source region and a P-type body region, and the heterojunction diode and the homojunction diode are connected in a reverse series connection mode. The specific heavily-doped P + region and the terminal region P + field limiting ring are formed through the same ion implantation process, and a thick medium buffer strip is optionally arranged on the heterojunction contact edge. The structure realizes compact integration, provides accurate bidirectional overvoltage clamping, and has the advantages of low leakage and high consistency.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a heterojunction voltage-regulated silicon carbide MOSFET and its fabrication method. Background Technology

[0002] Silicon carbide MOSFETs, as representatives of the new generation of power switching devices, have been widely used in electric vehicles, charging piles, industrial motor drives, and other applications. Their performance and reliability directly affect the efficiency of the entire system. To achieve low on-resistance and good gate control capability, SiC-MOSFETs typically employ an extremely thin gate oxide layer. However, this makes their gate-source ports highly susceptible to overvoltage damage caused by electrostatic discharge, drive oscillations, or electromagnetic interference. Once the gate oxide breaks down, it leads to permanent device failure.

[0003] Currently, a common protection strategy is to place TVS diodes near the device's gate-source pins on the application board. This external solution not only occupies additional board space and increases material costs, but its protection effectiveness is also greatly affected by the package lead inductance and PCB layout, and response delays may lead to inadequate protection. On the other hand, if simple ESD structures, such as silicide-based diodes or inherent body diodes, are integrated inside the chip, their trigger voltages are often fixed and high, which cannot meet the refined protection requirements of modern electronic control systems for asymmetric drive voltages. Complex integrated protection circuits may introduce significant parasitic capacitance, degrading high-frequency switching performance, or increasing chip area and on-resistance due to their placement encroaching on the active area. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, the technical problem to be solved by this invention is to propose a heterojunction voltage-stabilized silicon carbide MOSFET and its fabrication method, employing the following technical solution: The present invention provides a heterojunction voltage-regulated silicon carbide MOSFET, comprising: an N-type silicon carbide substrate and an N-type epitaxial layer thereon; a P-type body region disposed in the active region of the N-type epitaxial layer and a heavily doped N+ source region therein; a gate dielectric layer covering the P-type body region and an N-type polysilicon gate; a source metal electrode electrically connected to the N+ source region; and an electrostatic discharge protection unit integrated between the gate and the source. The aforementioned electrostatic discharge protection unit includes: a first Zener diode formed by direct contact between the aforementioned N-type polysilicon gate and a specific heavily doped P+ region to form a heterojunction, and a second Zener diode formed by the aforementioned N+ source region and the aforementioned P-type body region to form a homojunction. The two are connected in reverse series between the gate and the source, and the aforementioned heavily doped P+ region is electrically connected to the aforementioned source metal electrode.

[0005] As a further improvement, a gate contact window overlapping the aforementioned heavily doped P+ region is provided on the plane, so that the gate is in direct contact with the aforementioned heavily doped P+ region, and the boundary of the contact window is integrally formed with the gate body through conductive lines.

[0006] As a further improvement, the total ion implantation dose for the aforementioned heavily doped P+ region is 8 × 10⁻⁶. 14 cm -2 Up to 2×10 15 cm -2 Furthermore, its junction depth is greater than that of the aforementioned N+ source region.

[0007] As a further improvement, the aforementioned specific heavily doped P+ region is adjacent to the P+ field confinement ring of the terminal region on the layout, and is formed with the aforementioned P+ field confinement ring through the same heavily doped P+ ion implantation process.

[0008] As a further improvement, the reverse breakdown voltage of the first Zener diode is 18V to 22V, and the absolute value of the reverse breakdown voltage of the second Zener diode is 5V to 9V.

[0009] As a further improvement, a dielectric buffer band is provided around the direct contact edge between the gate and the specific heavily doped P+ region. The dielectric thickness of the dielectric buffer band is greater than the thickness of the channel gate dielectric layer, which is used to reduce the peak electric field at the contact edge and suppress static leakage and batch drift.

[0010] Another aspect of the present invention provides a method for fabricating a heterojunction-regulated silicon carbide MOSFET, for fabricating the aforementioned silicon carbide MOSFET, comprising the following steps: S1: Formation of the P-type body region; S2: Form gate sidewalls and implant to form heavily doped N+ source regions; S3: Photolithography and ion implantation form P+ regions for bulk contact and form the aforementioned specific heavily doped P+ regions; S4: High-temperature annealing activates impurities; S5: Form the gate dielectric layer and the N-type polysilicon gate, and etch a gate contact window that overlaps with the above-mentioned specific heavily doped P+ region to achieve direct contact; S6: Forms the interlayer dielectric, contact holes and front metal, and forms the drain metal on the back side of the substrate.

[0011] As a further improvement, in step S3, the specific heavily doped P+ region and the P+ field confinement ring mentioned above are implanted with the same ion implantation dose and energy and are completed under the same photolithography pattern.

[0012] As a further improvement, in step S5, the aforementioned medium buffer zone is simultaneously formed at the aforementioned direct contact edge, and the aforementioned medium buffer zone is formed by locally thickened medium layer or shallow groove filled with medium.

[0013] Compared with the prior art, the beneficial effects of the present invention are: Firstly, this invention utilizes an N-type polysilicon gate in direct contact with a heavily doped P+ region to form a heterojunction Zener diode, and connects it in reverse series with a source region PN junction diode, creating an extremely simple and efficient built-in protection unit. This achieves near-zero cost integration without introducing any new materials or additional photolithography steps. This back-to-back diode structure can clamp both forward and reverse overvoltages between the gate and source, exhibiting a fast response speed.

[0014] Secondly, this invention achieves a high degree of process integration between the protection unit and the termination structure by completing the P+ field confinement ring of the specific heavily doped P+ region and the termination region in the same photolithography and ion implantation steps. This design not only maximizes savings in process costs and subsequent chip area, but also ensures that the heterojunction diode has stable and repeatable breakdown characteristics by sharing high-dose implantation conditions. It also facilitates setting the protection threshold within a certain range by adjusting the implantation parameters, thus enhancing design flexibility.

[0015] Thirdly, this invention introduces a dielectric buffer strip at the direct contact edge between the gate and the P+ region. The dielectric thickness of this buffer strip is greater than the gate oxide thickness of the channel, effectively mitigating the electric field concentration effect at the heterojunction edge. This design significantly reduces the static leakage current of the protection unit during normal operation. Furthermore, its reduced sensitivity to process fluctuations such as lithography alignment deviations greatly improves batch-to-batch consistency and long-term stability of breakdown voltage parameters. This built-in protection solution ensures high performance while also possessing high reliability and high mass production capability, making it ideal for automotive applications with stringent cost and reliability requirements. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a silicon carbide IGBT application circuit according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the cross-sectional structure of the device after step S2 is performed according to the method of the present invention; Figure 3 This is a schematic diagram of the cross-sectional structure of the device after step S3 of the present invention is performed; Figure 4 This is a cross-sectional view of the silicon carbide IGBT structure of the present invention; Figure 5 This is a flowchart of the method of the present invention.

[0018] Figure label: 101 - N-type silicon carbide substrate; 102 - N-type epitaxial layer; 103 - P-type body region; 104 - heavily doped N+ source region; 105 - specific heavily doped P+ region; 106 - N-type polysilicon gate; 107 - gate dielectric layer; 108 - source metal electrode; 109 - drain metal electrode. Detailed Implementation

[0019] To facilitate understanding by those skilled in the art, the structure of the present invention will now be described in further detail with reference to the accompanying drawings: This invention provides a heterojunction Zener silicon carbide MOSFET and its fabrication method. Based on a back-to-back Zener diode structure with a heterojunction, it achieves high integration with the main device, thereby providing low-cost, high-reliability bidirectional overvoltage protection for the gate oxide without introducing additional photomasks and process complexity.

[0020] like Figures 2-4 As shown, the basic structure of this silicon carbide MOSFET includes an N-type silicon carbide substrate 101 and an N-type silicon carbide epitaxial layer formed thereon through epitaxial growth. An active region is defined in the N-type epitaxial layer 102, where a P-type body region 103 is formed by ion implantation, and an N+ source region is formed within the P-type body region 103 through selective heavy doping. Above the P-type body region 103, a dielectric material such as silicon dioxide or silicon oxynitride is grown as a gate dielectric layer 107, which is covered by an N-type polysilicon layer serving as the gate control electrode. A source metal electrode 108 is disposed on the front side of the silicon carbide MOSFET, which achieves ohmic contact with the N+ source region through a contact hole. An improvement of this invention is that a simple and efficient electrostatic discharge (ESD) protection unit is integrated between the gate and the source.

[0021] Specifically, the electrostatic discharge (ESD) protection unit consists of two Zener diodes connected in reverse series. The first Zener diode is a heterojunction diode, formed by the direct contact between an N-type polysilicon gate 106 and a heavily doped P+ region 105. The second Zener diode is a homojunction diode, formed by an N+ source region and the P-type body region 103 where they are located. This heavily doped P+ region 105 is electrically connected to the source metal electrode 108 on the front side of the silicon carbide MOSFET. This connection allows the two diodes to share a node at the source metal, thus forming a back-to-back bidirectional clamping circuit between the gate and source. When the gate-source voltage is too high in the forward direction, the heterojunction diode preferentially breaks down to discharge current; when the gate-source voltage is too low in the reverse direction, the homojunction diode preferentially breaks down to discharge current.

[0022] To achieve stable formation of the heterojunction diode, a gate contact window overlapping with a heavily doped P+ region 105 is incorporated into the planar layout of the silicon carbide MOSFET. This window means that in this region, the upper N-type polysilicon gate 106 directly contacts the lower heavily doped P+ region 105 through a deliberately created opening, rather than being separated by the gate dielectric layer 107 as in the active channel region. The boundary of this contact window is integrally formed with the main body of the gate via conductive polysilicon interconnects, ensuring that the gate potential can be effectively led to this heterojunction. This design makes the guard unit an integral part of the gate structure, rather than a separate additional device.

[0023] To ensure stable and repeatable breakdown characteristics of the heterojunction diode, the process parameters of the heavily doped P+ region 105 were precisely designed and controlled. In a preferred embodiment, the P+ region is formed by ion implantation, and the total implanted dose is controlled at 8 × 10⁻⁶. 14 cm -2 Up to 2×10 15 cm -2 Within a relatively high range. Simultaneously, the junction depth in this region is designed to be greater than that of the N+ source region. A higher doping dose helps to form a high concentration of charge carriers at the heterojunction interface, thereby achieving the desired avalanche breakdown voltage, typically around 20V; while a larger junction depth helps to improve the junction edge shape, disperse the electric field, and make the breakdown characteristics harder and more repeatable.

[0024] This invention offers significant advantages in terms of chip layout integration and process compatibility. The heavily doped P+ region 105 can be positioned adjacent to the P+ field-limiting ring of the termination region in the layout. Preferably, this heavily doped P+ region 105 and the P+ field-limiting ring of the termination region can be formed simultaneously through the same heavily doped P+ ion implantation process. This means that using the same photomask and the same ion implantation step, a portion of the termination protection structure and the core protection unit can be defined simultaneously. This design significantly reduces process costs, simplifies the process, and ensures consistency in doping characteristics between different functional regions.

[0025] Based on the above structural and process design, this invention can effectively control the breakdown voltage of two Zener diodes, adapting them to the needs of modern electronic control systems. In a typical application, the reverse breakdown voltage of the first Zener diode, i.e., the heterojunction diode, is set in the range of 18V to 22V, while the absolute value of the reverse breakdown voltage of the second Zener diode, i.e., the homojunction diode, is set in the range of 5V to 9V. For example, it can be specifically implemented as a forward breakdown of 20V and a reverse breakdown of -7V. This asymmetric breakdown characteristic perfectly matches the asymmetric drive voltage window such as +18V turn-on and -5V turn-off, providing reliable protection with a safety margin for the gate oxide in both positive and negative directions.

[0026] To further enhance the long-term reliability and stability of the protection unit, especially the heterojunction diode, this invention specifically incorporates a dielectric buffer strip at the direct contact edge between the gate and the heavily doped P+ region 105. In semiconductor devices, the contact edge between metal-semiconductor or different materials is often a region of concentrated electric field, which can easily lead to high static leakage current and may cause drift in electrical parameters between different manufacturing batches due to process variations. This dielectric buffer strip is composed of a dielectric material, and its key feature is that its dielectric thickness is significantly greater than the thickness of the gate dielectric layer 107 in the active channel region.

[0027] Specifically, this dielectric buffer can be implemented in two main ways. One way is to selectively grow a thicker oxide layer at the edge of the contact window through localized thermal oxidation or chemical vapor deposition. The other way is to etch a shallow trench at the edge of the contact window using shallow trench etching technology, and then fill and planarize it with a dielectric material. This thicker dielectric layer can effectively reduce the peak electric field at the contact edge, reducing leakage current caused by carrier tunneling. At the same time, because the thicker dielectric has a stronger modulating effect on the electric field of the underlying semiconductor surface, its sensitivity to process fluctuations such as photolithography alignment and etching deviation is significantly reduced. This effectively suppresses the drift of key parameters such as breakdown voltage between different production batches, greatly improving product consistency and yield.

[0028] The following will further elaborate on the above-mentioned device structure and its fabrication method using a specific example of the fabrication process of a 1200V N-type silicon carbide MOSFET. Figure 5 As shown: Step S1: Forming the P-type body region 103. Prepare an N-type 4H-SiC epitaxial wafer with a predetermined doping concentration and thickness. Prepare a layer of polysilicon as a hard mask using thermal oxidation and chemical vapor deposition. Open the implantation window using photolithography and dry etching with a Pwell photolithography plate. Next, deposit silicon dioxide within the window as a shielding layer for ion implantation using plasma-enhanced chemical vapor deposition. Aluminum is selected as the implantation element, and a four-stage implantation process is employed to form an approximately box-shaped doping distribution. The first implantation dose is 2 × 10⁻⁶. 13 cm -2 The initial energy was 610 keV; the dose and energy of the subsequent three injections were gradually reduced, with the total dose controlled at approximately 8 × 10⁻⁶ keV. 13 cm -2 After the injection is complete, remove the silica shielding layer.

[0029] Step S2: Forming the gate sidewall and implanting to form a heavily doped N+ source region 104. After removing the polysilicon hard mask, a 0.5 μm thick N-type polysilicon layer is directly deposited by low-pressure chemical vapor deposition. The gate pattern is formed by photolithography and dry etching. Subsequently, anisotropic etching is used to form a polysilicon sidewall approximately 0.5 μm wide on the gate sidewall. The thickness of this sidewall precisely controls the alignment of the subsequent N+ source region with the channel. Next, a silicon dioxide implantation mask layer is deposited again, using the polysilicon sidewall as a self-aligned mask, to perform nitrogen ion implantation to form the N+ source region. Four implantations are used, with the first implantation dose being 1.1 × 10⁻⁶. 14 cm -2 The energy was 175 keV, with subsequent injections decreasing in both dose and energy, for a total dose of approximately 3 × 10⁻⁶. 14 cm -2 Remove the silica shielding layer after injection.

[0030] Step S3 involves forming the P+ region for conventional bulk contacts and a specific heavily doped P+ region 105, a key component of the protective unit, through photolithography and ion implantation. A silicon dioxide implantation masking layer is deposited using PECVD. Using a single photolithography mask, the regions where the bulk contact P+ regions, the specific heavily doped P+ regions 105, and the P+ field confinement ring pattern of the termination region are simultaneously defined. High-dose aluminum ion implantation is performed using four implantations, with the first implantation dose being 8 × 10⁻⁶. 14 cm -2 The energy was 610 keV, with subsequent doses and energy decreasing, and the total dose was approximately 2 × 10⁻⁶. 15 cm -2 This step enables the one-time forming of the multifunctional P+ zone, which is the core of process simplification.

[0031] Step S4 involves high-temperature activation annealing. Using a standard carbon film protection process, annealing is performed at 1650°C for 30 minutes under an argon atmosphere to activate all injected aluminum and nitrogen impurities and repair lattice damage. After annealing, the carbon film on the surface is removed using oxygen plasma.

[0032] Step S5 involves forming a gate dielectric layer 107 and an N-type polysilicon gate 106, and etching to create a gate contact window overlapping with the heavily doped P+ region 105. First, a sacrificial oxidation process is performed to grow a sacrificial oxide layer approximately 20 nm thick via thermal oxidation, which is then completely removed using hydrofluoric acid. Next, a gate oxide layer approximately 40 nm thick is grown in a humid oxygen atmosphere at 1000°C to 1100°C. Subsequently, an N-type polysilicon layer approximately 0.5 μm thick is deposited via low-pressure chemical vapor deposition. The polysilicon layer is patterned using photolithography and dry etching processes. During this patterning process, the gate polysilicon is etched away above the heavily doped P+ region 105, forming a contact window and exposing the underlying dielectric layer. Then, a precisely controlled etching process removes the dielectric layer from the exposed area, allowing the N-type polysilicon gate 106 to directly contact the heavily doped P+ region 105 below, forming a heterojunction.

[0033] Meanwhile, in step S5, a dielectric buffer band is formed at the direct contact edge. For example, after growing the gate oxide layer and before depositing polysilicon, an additional photolithography step can be used to form a thickened oxide ring with a thickness between 80 nm and 150 nm at the planned contact window edge region through local thermal oxidation or deposition and etch-back. Alternatively, during the etching of the contact window dielectric layer, a shallow annular trench can be formed at the contact hole edge and filled with dielectric by adjusting the etching conditions or using an additional mask. This dielectric buffer band acts as a buffer pad, effectively alleviating the electric field concentration at the heterojunction edge.

[0034] Finally, step S6 is performed to form the interlayer dielectric, contact holes, and front-side metal, and to form the drain metal on the back side of the substrate. A low-temperature oxide and borosilicate glass layer are sequentially deposited using low-pressure chemical vapor deposition to form the interlayer dielectric layer, followed by planarization. Source contact holes are formed using ohmic contact photolithography and dry etching, exposing the N+ source region and a specific heavily doped P+ region 105. Simultaneously, the lead contact region of the gate polysilicon is etched. Subsequently, front-side metallization is performed, using a magnetron sputtering system to sequentially deposit a stack of titanium, nickel, and silver with a total thickness of approximately 4 μm. The source and gate electrodes are then formed using photolithography and etching to create the contact points and interconnects. The wafer is flipped, and the back side of the N+ substrate is thinned to the target thickness. Then, a stack of nickel / silver and other metals is formed on the back side by evaporation or sputtering to serve as the drain metal electrode 109.

[0035] In this fabrication method, the heavily doped P+ region 105 and the terminal field-limiting ring are implanted with the same ion implantation parameters and completed in the same photolithography step, ensuring process simplification and consistency. The introduction of the dielectric buffer band effectively improves the electrical stability of the heterojunction diode. By precisely controlling the parameters of each process step, an electrostatic discharge (ESD) protection unit with accurate breakdown characteristics, low leakage current, and good consistency can be obtained. This invention... Figure 1 Based on the principle of the basic structure, a Zener diode composed of a heterojunction diode consisting of an N-type polysilicon gate 106 and a heavily doped P+ region 105 breaks down prematurely when overvoltage occurs at the gate. The current flows to the source through the heavily doped P+ region 105, the P-type body region 103, and the heavily doped N+ source region 104, forming a discharge channel. This structure does not require an additional photomask.

[0036] The silicon carbide MOSFET fabricated through the above embodiments features a built-in electrostatic discharge (ESD) protection unit with precise breakdown voltage characteristics, low leakage current, and good parameter consistency, providing reliable overvoltage protection for the device. This protection structure is implemented entirely based on standard silicon carbide processes, without requiring additional photomasks, and offers excellent process compatibility and cost-effectiveness.

[0037] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A heterojunction voltage-regulated silicon carbide MOSFET, characterized in that, Includes: an N-type silicon carbide substrate and an N-type epitaxial layer thereon; a P-type body region disposed in the active region of the N-type epitaxial layer and a heavily doped N+ source region therein; A gate dielectric layer covering the P-type body region and an N-type polysilicon gate; The source metal electrode is electrically connected to the N+ source region; An electrostatic discharge protection unit integrated between the gate and the source; The electrostatic discharge protection unit includes: a first Zener diode in which the N-type polysilicon gate and a specific heavily doped P+ region are in direct contact to form a heterojunction, and a second Zener diode in which the N+ source region and the P-type body region form a homojunction. The two are connected in reverse series between the gate and the source. The specific heavily doped P+ region is electrically connected to the source metal electrode.

2. The heterojunction voltage-stabilized silicon carbide MOSFET according to claim 1, characterized in that: A gate contact window is provided on the plane that overlaps with the specific heavily doped P+ region, so that the gate is in direct contact with the specific heavily doped P+ region, and the boundary of the contact window is integrally formed with the gate body through conductive lines.

3. The heterojunction voltage-stabilized silicon carbide MOSFET according to claim 2, characterized in that: The total ion implantation dose for the specific heavily doped P+ region is 8 × 10⁻⁶. 14 cm -2 Up to 2×10 15 cm -2 Furthermore, its junction depth is greater than that of the N+ source region.

4. The heterojunction voltage-stabilized silicon carbide MOSFET according to claim 3, characterized in that: The specific heavily doped P+ region is adjacent to the P+ field confinement ring of the terminal region on the layout, and is formed with the P+ field confinement ring through the same heavily doped P+ ion implantation process.

5. The heterojunction voltage-stabilized silicon carbide MOSFET according to claim 4, characterized in that: The reverse breakdown voltage of the first Zener diode is 18V to 22V, and the absolute value of the reverse breakdown voltage of the second Zener diode is 5V to 9V.

6. The heterojunction voltage-stabilized silicon carbide MOSFET according to claim 5, characterized in that: A dielectric buffer band is provided around the direct contact edge between the gate and the specific heavily doped P+ region. The dielectric thickness of the dielectric buffer band is greater than the thickness of the channel gate dielectric layer. This is used to reduce the peak electric field at the contact edge and suppress static leakage and batch drift.

7. A method for fabricating a heterojunction voltage-regulated silicon carbide MOSFET, used to fabricate the silicon carbide MOSFET as described in any one of claims 1-6, characterized in that, Includes the following steps: S1: Formation of P-type body region; S2: Form gate sidewalls and implant to form heavily doped N+ source regions; S3: Photolithography and ion implantation form the P+ region for bulk contact and form the specific heavily doped P+ region; S4: High-temperature annealing activates impurities; S5: Form a gate dielectric layer and an N-type polysilicon gate, and etch a gate contact window that overlaps with the specific heavily doped P+ region to achieve direct contact; S6: Forms the interlayer dielectric, contact holes and front metal, and forms the drain metal on the back side of the substrate.

8. The method for fabricating a heterojunction voltage-regulated silicon carbide MOSFET according to claim 7, characterized in that: In step S3, the specific heavily doped P+ region and the P+ field confinement ring are implanted with the same ion implantation dose and energy and are completed under the same photolithography pattern.

9. The method for fabricating a heterojunction voltage-stabilized silicon carbide MOSFET according to claim 8, characterized in that: In step S5, the medium buffer strip is simultaneously formed at the direct contact edge. The medium buffer strip is formed by locally thickened medium layers or shallow grooves filled with medium.

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