Array substrate, manufacturing method thereof and display panel

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate and a first polycrystalline silicon thin film transistor. The first polycrystalline silicon thin film transistor is located on the substrate. A plurality of crystal grains are arranged in a channel of the first polycrystalline silicon thin film transistor. In a channel of the first polycrystalline silicon thin film transistor, the length of a crystal grain in the first direction is larger than that in the second direction. The first direction is the length direction of the channel region, and the second direction is the width direction of the channel region. Therefore, the resolution ratio and the refresh rate of the display panel are improved, the display effect is optimized, and the user experience is improved.

Description

Array substrate, manufacturing method thereof and display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a manufacturing method thereof and a display panel. BACKGROUND

[0002] Low Temperature Poly-Silicon (LTPS) material has high mobility, which is conducive to reducing the size of a Thin Film Transistor (TFT) element, and is conducive to improving the aperture ratio, refresh rate and definition when applied to a display panel. With the development of display technologies such as Virtual Reality (VR) and Augmented Reality (AR), users have further improved requirements for the resolution and refresh rate of display products, and the LTPS display panel manufactured by using the existing structure and process has been difficult to meet the user demand.

[0003] SUMMARY

[0004] The present disclosure provides an array substrate, a manufacturing method thereof and a display panel, to optimize the display effect.

[0005] In a first aspect, the present disclosure provides an array substrate, comprising:

[0006] a substrate;

[0007] a first polysilicon thin film transistor located on the substrate; the channel of the first polysilicon thin film transistor comprises a plurality of crystal grains; the length of the crystal grains along a first direction in the channel of the first polysilicon thin film transistor is greater than the length along a second direction; the first direction is the length direction of the channel region, and the second direction is the width direction of the channel region.

[0008] In the array substrate provided by the present disclosure, the ratio of the length of the crystal grains along the first direction to the length along the second direction in the channel of the first polysilicon thin film transistor is greater than or equal to 5:1.

[0009] In the array substrate provided by the present disclosure, the length of the crystal grains along the first direction in the channel of the first polysilicon thin film transistor is 1-10 μm, and the length of the crystal grains along the second direction is less than 1 μm.

[0010] In the array substrate provided by the present disclosure, in the channel of the first polysilicon thin film transistor, the same crystal grain penetrates through the channel region along the first direction.

[0011] In the channel of the first polysilicon thin film transistor, a plurality of crystal grains are arranged side by side along the second direction.

[0012] The array substrate provided by the present disclosure further comprises: a single-crystal silicon thin film transistor, which is located at the same layer as the first polycrystalline silicon thin film transistor; and the channel of the single-crystal silicon thin film transistor comprises only one crystal grain.

[0013] The array substrate provided by the present disclosure further comprises: a single-crystal silicon thin film transistor, which is located at the same layer as the first polycrystalline silicon thin film transistor; and the channel of the single-crystal silicon thin film transistor comprises only one crystal grain. 2 The mobility of the first polycrystalline silicon thin film transistor is greater than 200 cm

[0014] The array substrate provided by the present disclosure further comprises:

[0015] The oxide semiconductor thin film transistor or the amorphous silicon thin film transistor is used as a driving thin film transistor, and the oxide semiconductor thin film transistor or the amorphous silicon thin film transistor is used as a switching thin film transistor.

[0016] The array substrate provided by the present disclosure further comprises:

[0017] The buffer layer is located between the substrate and the first polycrystalline silicon thin film transistor, and the channel of the first polycrystalline silicon thin film transistor is formed on the buffer layer.

[0018] The buffer layer comprises:

[0019] The silicon nitride layer;

[0020] The silicon oxide layer is located on the side of the silicon nitride layer away from the substrate.

[0021] The second aspect of the present disclosure provides a display panel comprising the array substrate of any one of the above.

[0022] The third aspect of the present disclosure provides a manufacturing method of an array substrate, comprising:

[0023] forming a crystallization guide pattern on one side of the substrate; the crystallization guide pattern comprises a crystallization guide structure and a crystallization region defined by the crystallization guide structure;

[0024] forming an amorphous silicon layer on the side of the crystallization guide pattern away from the substrate;

[0025] performing a laser annealing process on the amorphous silicon layer to crystallize and grow the amorphous silicon layer into a polycrystalline silicon layer;

[0026] etching the polycrystalline silicon layer in the crystallization region to form a channel of the first polycrystalline silicon thin film transistor.

[0027] In the method provided by the present disclosure, the material of the crystallization guide structure is metal; and the crystallization guide structure has a temperature resistance greater than or equal to 450℃.

[0028] The present disclosure has the following beneficial effects:

[0029] The array substrate, the manufacturing method thereof and the display panel provided by the present disclosure are beneficial to improving the carrier mobility of the first polysilicon thin film transistor, reducing the size of the thin film transistor, improving the aperture ratio of the display panel, improving the resolution and refresh rate of the display panel, optimizing the display effect, and thus improving the user experience. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings introduced below are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0031] FIG. 1 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure;

[0032] FIG. 2 is a schematic diagram of a top view structure of a first polysilicon thin film transistor provided by an embodiment of the present disclosure;

[0033] FIG. 3 is a schematic diagram of an enlarged channel of a first polysilicon thin film transistor provided by an embodiment of the present disclosure;

[0034] FIG. 4 is a schematic diagram of a manufacturing process of an array substrate provided by an embodiment of the present disclosure;

[0035] FIG. 5 is a schematic diagram of a polysilicon growth process in the manufacturing process of an array substrate provided by an embodiment of the present disclosure;

[0036] FIG. 6 is a microscopic enlarged view of an actual polysilicon growth result in the manufacturing process of an array substrate provided by an embodiment of the present disclosure;

[0037] FIG. 7 is a schematic diagram of a top view structure of a crystallization guide pattern provided by an embodiment of the present disclosure;

[0038] FIG. 8 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure;

[0039] FIG. 9 is a schematic diagram of a pixel driving circuit structure of an array substrate provided by an embodiment of the present disclosure;

[0040] FIG. 10 is a flow chart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] The above and other objects, features and advantages of the present disclosure will be more apparent from the following embodiments taken in conjunction with the accompanying drawings, in which like reference characters refer to the like elements throughout the charts, and the explanatory words indicating the position and direction described in the present disclosure are described based on the charts, but can be changed according to necessity, and the changes are included in the scope of protection of the present disclosure. The charts of the present disclosure are only used to show the relative positional relationship and do not represent the real proportion.

[0042] Low Temperature Poly-Silicon (LTPS) material has high mobility, which is beneficial to reduce the size of Thin Film Transistor (TFT) element, and is applied to display panels to improve the aperture ratio, refresh rate, and definition, etc. With the development of Virtual Reality (VR) and Augmented Reality (AR) display technologies, users have further improved requirements on the resolution, refresh rate, and other performance of display products. The LTPS display panel manufactured by using the existing structure and process has been difficult to meet the user demand.

[0043] In a first aspect, an array substrate is provided to solve the above problems.

[0044] FIG. 1 is a schematic diagram of a cross-sectional structure of an array substrate according to an embodiment of the present disclosure; FIG. 2 is a schematic diagram of a top view of a first polysilicon thin film transistor according to an embodiment of the present disclosure; and FIG. 3 is a schematic diagram of a channel amplification of the first polysilicon thin film transistor according to an embodiment of the present disclosure.

[0045] In the embodiments of the present disclosure, as shown in FIG. 1, the array substrate includes a substrate 1 and a first polysilicon thin film transistor T1.

[0046] The substrate 1 is located at the bottom of the array substrate. The substrate 1 has the functions of supporting and carrying other film layers located thereon. The shape of the substrate 1 can be rectangular, square, etc., and can also be an irregular shape such as a circle according to the specific shape of the array substrate. The material of the substrate 1 can be made of different materials according to the type of display panel to be made. For example, when applied to a transparent display panel such as a liquid crystal display (LCD) panel, the substrate 1 can be made of a transparent material. When applied to a non-transparent display panel such as an organic light emitting diode (OLED) display panel or a micro light emitting diode (Micro LED) display panel, the substrate 1 can be made of a non-transparent material. When applied to a flexible display panel, the substrate 1 can be made of a flexible material. When applied to a non-flexible display panel, the substrate 1 can be made of a rigid material. In this embodiment, the material of the substrate 1 can be glass, resin, etc., which is not limited herein.

[0047] The first polysilicon thin film transistor T1 is located on the substrate 1. As shown in FIG. 1, the first polysilicon thin film transistor T1 includes an active layer A, a source S, a drain D, and a gate G. The active layer A includes oppositely arranged source and drain regions, and the source S and the drain D are located on the same side of the active layer A and are connected to the source and drain regions, respectively. The active layer A further includes a channel C. The channel C is located between the source and drain regions. Specifically, as shown in FIGS. 1 and 2, the channel region C can be arranged between the orthographic projection of the source S on the active layer A and the orthographic projection of the drain D on the active layer A. The gate G is located on one side of the active layer A. In specific embodiments, the gate G can be arranged on the same side of the active layer A as the source S and the drain D, or on the side of the active layer A away from the source S and the drain D, which is not limited herein. The orthographic projection of the gate G on the active layer A at least partially overlaps the channel C. Specifically, the orthographic projection of the gate G on the active layer A can be arranged to completely overlap the channel C, or the orthographic projection of the gate G on the active layer A can be arranged to be slightly smaller than the channel C, or the orthographic projection of the gate G on the active layer A can be arranged to be slightly larger than the channel C, which is not limited herein.

[0048] The array substrate provided by the embodiments of the present disclosure is shown in FIG. 2 and FIG. 3. The channel C of the first polysilicon thin film transistor T1 includes a plurality of crystal grains S. In the channel C of the first polysilicon thin film transistor T1, the length W of the crystal grains S along the first direction x is greater than the length L along the second direction y. The first direction x is the length direction of the channel region C, that is, the direction in which the source electrode S points to the drain electrode D. The second direction y is the width direction of the channel region C. In specific implementation, the first direction x can be perpendicular to the second direction y, which is not limited herein. In specific implementation, when the first polysilicon thin film transistor T1 is turned on, the carriers in the channel C mainly flow in the direction parallel to the first direction x. In the embodiments of the present disclosure, the crystal grains S in the channel C of the first polysilicon thin film transistor T1 have a larger size along the first direction x. Therefore, the number of crystal grains along the first direction x can be reduced, the number of grain boundaries of the channel C along the first direction x can be greatly reduced, the difficulty of carrier migration in the direction parallel to the first direction x can be reduced, the carrier mobility of the first polysilicon thin film transistor T1 can be improved, the size of the thin film transistor (such as the channel width) can be reduced, the aperture ratio of the display panel can be improved when the display panel is applied, the resolution and refresh rate of the display panel can be improved, and the user experience can be improved.

[0049] In specific implementation, a plurality of first polysilicon thin film transistors T1 can be arranged in the array substrate, which is not limited herein.

[0050] FIG. 4 is a schematic diagram of the manufacturing process of the array substrate provided by the embodiments of the present disclosure. FIG. 5 is a schematic diagram of the polysilicon growth process in the manufacturing process of the array substrate provided by the embodiments of the present disclosure. FIG. 6 is a micrograph of the actual polysilicon growth result in the manufacturing process of the array substrate provided by the embodiments of the present disclosure.

[0051] The manufacturing of the array substrate provided by the embodiments of the present disclosure can specifically include the following processes:

[0052] 1. Form a crystal guiding pattern F on one side of the substrate 1. The crystal guiding pattern F includes a crystal guiding structure and a crystal region defined by the crystal guiding structure. For example, as shown in FIG. 4 and FIG. 5, the crystal guiding structure can include a first guiding structure F1, a second guiding structure F2 and a third guiding structure F3 arranged parallel to each other and at a certain distance. The first guiding structure F1 and the second guiding structure F2 define a crystal region R located between the first guiding structure F1 and the second guiding structure F2. The second guiding structure F2 and the third guiding structure F3 define a crystal region R located between the second guiding structure F2 and the third guiding structure F3. The thickness of the crystal guiding structure F can be set according to actual conditions, and can be set to For example, it can be which is not limited herein.

[0053] In practice, the crystallization guiding structure can be made of a material with good heat conduction efficiency, such as metal, so that a supercooling region can be formed on the crystallization guiding structure during annealing, which is conducive to the nucleation and growth of the crystal grains. The crystallization guiding structure also needs to have good thermal stability to ensure that the crystallization guiding structure does not change significantly in physical and chemical properties under high temperature conditions. Specifically, the crystallization guiding structure needs to withstand a temperature greater than or equal to 450°C to ensure that the crystallization guiding structure does not change significantly in physical and chemical properties during subsequent processes. For example, the crystallization guiding structure can be made of a metal material such as molybdenum (Mu) or titanium (Ti), without limitation.

[0054] When the crystallization guiding structure is made of a metal material, a surface oxide layer can also be formed on the surface of the crystallization guiding structure by thermal oxidation technology, which is conducive to the uniform distribution of the electric field during the subsequent amorphous silicon layer deposition process. In some embodiments, an insulating film can also be plated on the surface of the crystallization guiding structure to achieve the same effect as the surface oxide layer. For example, a silicon oxide (SiO ) thin film can be made on the surface of the crystallization guiding structure by deposition process, without limitation. x In some embodiments, the surface of the crystallization guiding structure can also not be made of a surface oxide layer or an insulating film, but directly expose the metal material of the crystallization guiding structure, without limitation.

[0055] 2. Forming an amorphous silicon layer a on the side of the crystallization guiding pattern F away from the substrate 1. In practice, the amorphous silicon layer a can be made by conventional processes in semiconductor technology. For example, the specific manufacturing process of the amorphous silicon layer a can include: depositing an amorphous silicon thin film by thin film deposition process, which can have a thickness of 25 nm to 150 nm, such as 100 nm, without limitation; then performing dehydrogenation treatment on the amorphous silicon thin film at high temperature, which can be at a temperature of 400°C to 450°C, such as 420°C, and the dehydrogenation time can be 30 min to 100 min, such as 50 min, without limitation; finally, the surface of the amorphous silicon thin film is cleaned with hydrogen fluoride (HF) and treated with ozone (O3) to form the amorphous silicon layer a, without limitation. In practice, the amorphous silicon layer a can be formed only in the crystallization region R, or formed on one side of the substrate 1, without limitation.

[0056] 3. performing a laser annealing process on the amorphous silicon layer a to crystallize the amorphous silicon layer a into a polysilicon layer p; in a specific implementation, the amorphous silicon layer a can be heated by a quasi-molecular laser and then annealed to form the polysilicon grains; during the annealing process, the heat conduction rate of the crystallization guide structure is relatively fast, and a plurality of supercooling regions are formed on the crystallization guide structure; the contact part of the amorphous silicon layer a with the crystallization guide structure starts to nucleate at the position of the supercooling region of the crystallization guide structure, and grows rapidly in a direction perpendicular to the crystallization guide structure and slowly in a direction parallel to the crystallization guide structure due to the extrusion between the grains, thereby forming a grain structure with a relatively large length in the direction perpendicular to the crystallization guide structure and a relatively small length in the direction parallel to the crystallization guide structure; for example, as shown in FIG. 5, after the amorphous silicon layer a nucleates at the supercooling region in contact with the first guide structure F1, the grain S grows to a relatively long length in the direction D1 perpendicular to the first guide structure F1; after the amorphous silicon layer a nucleates at the supercooling region in contact with the second guide structure F2, the grain S grows to a relatively long length in the direction D2 perpendicular to the second guide structure F2; thus, the grain S has a length in the direction perpendicular to the crystallization guide structure greater than a length in the direction parallel to the crystallization guide structure in the finally formed polysilicon layer p; it should be noted that only part of the film structure of the polysilicon layer p is shown in FIG. 5 for ease of illustration;

[0057] 4. etching the polysilicon layer p in the crystallization region to form a channel C of the first polysilicon thin film transistor T; specifically, the polysilicon layer p in the crystallization region R is etched to form an active layer A of the first polysilicon thin film transistor T, and the channel C is located in the active layer A of the first polysilicon thin film transistor T; by adjusting the shape and position of the mask opening to match the growth direction of the grains in the polysilicon layer p, the grains in the channel C of the first polysilicon thin film transistor T have a length in the length direction of the channel region greater than a length in the width direction of the channel region; in a specific etching process, the distance between the edge of the channel C and the edge of the crystallization region R can be controlled to be greater than or equal to 0.5 μm during the etching process, which is not limited herein; in a specific etching process, one or more active layers A of the first polysilicon thin film transistor T can be etched in one crystallization region R, which is not limited herein;

[0058] In some embodiments, the crystallization guide structure and the amorphous silicon or polysilicon formed on the surface of the crystallization guide structure can be removed after etching the polysilicon layer p in the crystallization region and forming the active layer A of the first polysilicon thin film transistor T. In some embodiments, the crystallization guide structure and the amorphous silicon or polysilicon formed on the surface of the crystallization guide structure can also be removed before etching the polysilicon layer p in the crystallization region and forming the active layer A of the first polysilicon thin film transistor T, and then the polysilicon layer p in the crystallization region is etched to form the active layer A, which is not limited herein.

[0059] As shown in FIG. 6, in one specific embodiment, a microscope magnified schematic diagram of the microstructure of the actual growth result of the polysilicon is shown. As shown in FIG. 6, since the amorphous silicon is nucleated on the surface of the first guide structure F1 and the second guide structure F2, the growth speed of the crystal grains along the direction D1 perpendicular to the first guide structure F1 and the direction D2 perpendicular to the second guide structure F2 is greater than the growth speed of the crystal grains along the direction parallel to the first guide structure F1 and the direction parallel to the second guide structure F2, and in the final growth result, the polysilicon crystal grains have the characteristic that the length along the direction perpendicular to the crystallization guide structure is greater than the length along the direction parallel to the crystallization guide structure. Taking the crystal grain S selected by the white dashed line frame in FIG. 6 as an example, the length d1 of the crystal grain S along the direction perpendicular to the crystallization guide structure is about 1.4 μm, and the maximum length d2 of the crystal grain S along the direction parallel to the crystallization guide structure is about 0.3 μm, and the length along the direction perpendicular to the crystallization guide structure is much greater than the maximum length along the direction parallel to the crystallization guide structure.

[0060] FIG. 7 is a top view structural schematic diagram of the crystallization guide pattern provided by the embodiments of the present application.

[0061] In some embodiments, the crystal guiding pattern can also be a grid pattern during the manufacturing of the array substrate. For example, as shown in FIG. 7, the crystal guiding pattern includes first guiding structures F1, second guiding structures F2, third guiding structures F3 arranged in parallel, and fourth guiding structures F4, fifth guiding structures F5, sixth guiding structures F6 arranged in cross with the first guiding structures F1, the second guiding structures F2, the third guiding structures F3. Each of the first guiding structures F1, the second guiding structures F2, the third guiding structures F3 crosses each of the fourth guiding structures F4, the fifth guiding structures F5, the sixth guiding structures F6, defining a plurality of grid areas. In practice, part of the polysilicon grains can grow inwards of the grid areas along a direction perpendicular to the first guiding structures F1, the second guiding structures F2, the third guiding structures F3, and / or part of the grains can grow along a direction perpendicular to the fourth guiding structures F4, the fifth guiding structures F5, the sixth guiding structures F6, which are not limited herein. As shown in FIG. 7, the grid areas of the crystal guiding pattern can be square grids. In some embodiments, the grid areas of the crystal guiding pattern can also be rectangular grids, circular grids, etc., which are not limited herein.

[0062] In some embodiments, as shown in FIG. 2, in the channel C of the first polysilicon thin film transistor T1, the ratio of the length W of the grains along the first direction x to the length L of the grains along the second direction y is greater than or equal to 5:1. The greater the ratio of the length W of the grains along the first direction x to the length L of the grains along the second direction y, the greater the size of the grains grown along the first direction x, and the fewer the number of grains and grain boundaries arranged in the first direction x of the channel C of the first polysilicon thin film transistor T1, and the higher the mobility of the first polysilicon thin film transistor T1.

[0063] In some embodiments, in the channel C of the first polysilicon thin film transistor T1, the length of the grains along the first direction x ranges from 1 μm to 10 μm, and preferably from 5 μm to 10 μm, for example 5 μm; and the length of the grains along the second direction is less than 1 μm, for example 0.5 μm. In practice, the size of the grains in the channel C of the first polysilicon thin film transistor T1 can be adjusted by adjusting the specific growth conditions of the grains and the shape, position and size of the mask opening during the etching process according to specific requirements, which are not limited herein.

[0064] In some embodiments, in the channel C of the first polysilicon thin film transistor T1, along the first direction x, the same grain s runs through the channel region C. That is, along the first direction x, only one grain is arranged in the channel C of the first polysilicon thin film transistor T1, and when the carriers migrate along the direction parallel to the first direction x, they only need to be transmitted within one grain and do not need to pass through the grain boundary between adjacent two grains, thereby greatly improving the mobility of the carriers. For example, along the first direction x, the length of the channel C of the first polysilicon thin film transistor T1 is usually greater than 2 μm, and thus in the manufacturing process, it is necessary to ensure that the grain s has a length greater than 2 μm along the first direction x to protect the grain s from being etched along the first direction x when etching.

[0065] In some embodiments, in the channel C of the first polysilicon thin film transistor T1, along the second direction y, a plurality of grains S are arranged side by side. Specifically, because the grains are limited by adjacent grains when growing along the second direction y in the channel C of the first polysilicon thin film transistor T1, the length of the grain growth in this direction is small, usually less than 1 μm. Because the width of the channel C of the first polysilicon thin film transistor T1 in the second direction y is usually greater than 2 μm, in this direction, the channel C usually has a plurality of grains arranged side by side.

[0066] In some embodiments, the array substrate further comprises a single-crystal silicon thin film transistor. The single-crystal silicon thin film transistor is located in the same film layer as the first polysilicon thin film transistor T1. The channel of the single-crystal silicon thin film transistor includes only one grain. Specifically, the single-crystal silicon thin film transistor is located in the same film layer as the first polysilicon thin film transistor T1, that is, the single-crystal silicon thin film transistor and the first polysilicon thin film transistor T1 are manufactured in the same film layer using the same mask. Specifically, as shown in FIG. 7, when the crystal guiding pattern is a square grid pattern, at the corner formed by the intersection of the adjacent two sides of the square, for example, at the position of the corner N formed by the intersection of the third guiding structure F3 and the sixth guiding structure F6, the grain nucleated on the third guiding structure F3 and the grain nucleated on the sixth guiding structure F6 fuse to form a large grain during the process of simultaneously growing into the square grid region. When the size of the grain is large enough, it can accommodate the entire channel of the thin film transistor, and thus when the channel of the thin film transistor is formed at the corner N, the channel can only contain one grain, thereby forming a single-crystal silicon thin film transistor through subsequent processes, and further improving the mobility of the carriers.

[0067] In some embodiments, the array substrate can further include a second polysilicon thin film transistor. The second polysilicon thin film transistor is located in the same layer as the first polysilicon thin film transistor. The difference between the second polysilicon thin film transistor and the first polysilicon thin film transistor is that, in the second polysilicon thin film transistor, not every grain has the characteristic that the length along the first direction is greater than the length along the second direction. Specifically, due to process reasons and the like during crystallization, the grains in the region where the channel of the second polysilicon thin film transistor is located do not have the characteristic that the length along the first direction is greater than the length along the second direction, thereby causing the difference between the second polysilicon thin film transistor and the first polysilicon thin film transistor.

[0068] In the embodiments of the present disclosure, the mobility of the first polysilicon thin film transistor T1 is greater than 200 cm 2 / (V·s). In one specific embodiment provided by the present disclosure, the specific performance of the first polysilicon thin film transistor T1 is shown in Table 1 as follows:

[0069] Table 1: Electrical performance of the first polysilicon thin film transistor

[0070] As can be seen from Table 1 above, in the array substrate provided by the embodiments of the present disclosure, the mobility of the first polysilicon thin film transistor T1 is greatly improved compared with the polysilicon thin film transistor in the related art, and the first polysilicon thin film transistor T1 has good switching performance.

[0071] FIG. 8 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the present disclosure; and FIG. 9 is a schematic diagram of a structure of a pixel driving circuit of the array substrate provided by an embodiment of the present disclosure.

[0072] In some embodiments, the array substrate further includes an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor. The oxide semiconductor thin film transistor is different from the polysilicon thin film transistor in that the active layer of the oxide semiconductor thin film transistor is made of an oxide semiconductor material. The amorphous silicon thin film transistor is different from the polysilicon thin film transistor in that the active layer of the amorphous silicon thin film transistor is made of amorphous silicon material. The mobility of the oxide semiconductor thin film transistor or the amorphous silicon thin film transistor is generally less than the mobility of the polysilicon thin film transistor.

[0073] When applied to a display panel, a pixel driving circuit for driving a pixel unit is provided in the array substrate. The pixel driving circuit usually includes a plurality of thin film transistors and a capacitor to form a 2T1C pixel driving circuit, a 4T1C pixel driving circuit, a 7T1C pixel driving circuit, or a 9T1C pixel driving circuit, etc. The plurality of thin film transistors in the pixel driving circuit are usually divided into drive thin film transistors (DTFT) for driving function and switching thin film transistors (STFT) for switching function. Since the drive thin film transistors have a higher requirement for mobility, the switching thin film transistors have a lower requirement for mobility, and thus the first polysilicon thin film transistor can be used as the drive thin film transistor, and the oxide semiconductor thin film transistor or the amorphous silicon thin film transistor can be used as the switching thin film transistor, which is not limited herein. For example, as shown in FIG. 9, a 6T1C pixel circuit is shown, in which the thin film transistors t1, t3, t4, t5, and t6 are used as switching thin film transistors for controlling the on / off state of the local circuit in the pixel circuit, the thin film transistor t2 is used as a drive thin film transistor for modulating the size of the drive current flowing to the light emitting device, the storage capacitor C is used for storing the control voltage of the control thin film transistor t2, and the thin film transistor t2 controls the amount of current supplied to the light emitting device B from the anode according to the control voltage stored in the storage capacitor C, thereby controlling the light emitting brightness of the light emitting device B. The thin film transistors t1, t3, t4, t5, and t6 can be oxide semiconductor thin film transistors or amorphous silicon thin film transistors, and the thin film transistor t2 can be a first polysilicon thin film transistor.

[0074] In specific implementation, as shown in FIG. 8, the active layer of the oxide semiconductor thin film transistor or the amorphous silicon thin film transistor T2 is formed in a film layer different from the active layer of the first polysilicon thin film transistor.

[0075] In some embodiments, the array substrate further includes a buffer layer 2. The buffer layer 2 is located between the substrate 1 and the first polysilicon thin film transistor T1. The channel C of the first polysilicon thin film transistor T1 is formed on the buffer layer 2. The buffer layer 2 has the function of blocking the diffusion of metal ions in the substrate 1 into the channel C of the first polysilicon thin film transistor T1, and the function of improving the contact performance with the amorphous silicon layer a when the amorphous silicon layer a is deposited.

[0076] In specific implementation, the buffer layer 2 can adopt a laminated structure of a plurality of film layers. For example, as shown in FIG. 8, the buffer layer 2 can include a silicon nitride (SiN x ) layer 21 and an oxide layer 22 arranged in a stack. The silicon oxide layer 22 is located on the side of the silicon nitride layer 21 away from the substrate 1. The silicon nitride (SiN xThe layer 21 can effectively block metal ions in the substrate 1, and the oxide layer 22 is a good contact film layer of the amorphous silicon layer a. In a specific implementation, the silicon nitride layer 21 and the silicon oxide layer 22 can be sequentially deposited on the substrate 1 before the amorphous silicon layer a is deposited. The thickness of the silicon nitride layer 21 can be, for example, For example The thickness of the silicon oxide layer 22 can be, for example, For example This is not limited herein.

[0077] In some embodiments, the buffer layer 2 can also be a single-layer structure, or the buffer layer 2 can also include more film layers arranged in a stack, which is not limited herein.

[0078] In a second aspect, the present disclosure provides a display panel, including the array substrate provided in any of the foregoing embodiments. The display panel provided in the embodiments of the present disclosure has the same or similar technical effects as the array substrate provided in any of the foregoing embodiments in a specific implementation, and details are not repeated herein.

[0079] In a specific implementation, the display panel provided in the embodiments of the present disclosure can be an organic light emitting diode (OLED) display panel, a mini light emitting diode (Mini LED) display panel, or a micro light emitting diode (Micro LED) display panel, etc., which is not limited herein.

[0080] FIG. 10 is a flowchart of a manufacturing method of the array substrate provided in the embodiments of the present disclosure.

[0081] In a third aspect, the present disclosure further provides a manufacturing method of an array substrate. As shown in FIG. 10, the manufacturing method of the array substrate provided in the embodiments of the present disclosure specifically includes the following steps:

[0082] S101: forming a crystallization guide pattern on one side of a substrate; the crystallization guide pattern includes a crystallization guide structure and a crystallization region defined by the crystallization guide structure;

[0083] S102: forming an amorphous silicon layer on the side of the crystallization guide pattern away from the substrate;

[0084] S103: performing a laser annealing process on the amorphous silicon layer, so that the amorphous silicon layer is crystallized and grown into a polycrystalline silicon layer;

[0085] S104: etching the polycrystalline silicon layer in the crystallization region to form a channel of a first polycrystalline silicon thin film transistor.

[0086] The manufacturing method of the array substrate provided by the embodiment of the present disclosure has the characteristics that the crystal grains in the channel C of the first polysilicon thin film transistor T have a length along the length direction of the channel region and a length along the width direction of the channel region, which is beneficial to improve the carrier mobility of the first polysilicon thin film transistor, beneficial to reduce the size of the thin film transistor, and when applied to a display panel, can improve the aperture ratio of the display panel, improve the resolution and refresh rate of the display panel, and further improve the user experience.

[0087] In some embodiments, the material of the crystallization guiding structure is metal. The crystallization guiding structure has a temperature resistance greater than or equal to 450°C.

[0088] The structure of the array substrate provided by the embodiment of the present disclosure has been described in detail in the foregoing description of the present disclosure, and therefore the manufacturing method of the array substrate provided by the embodiment of the present disclosure can be adjusted by referring to the specific structure of the array substrate provided by the foregoing embodiments of the present disclosure in the specific implementation, and will not be described here.

[0089] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0090] Obviously, those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The array substrate comprises: a substrate; a first polysilicon thin film transistor located on the substrate; a plurality of crystal grains are included in a channel of the first polysilicon thin film transistor; the length of a crystal grain along a first direction is greater than the length of the crystal grain along a second direction in the channel of the first polysilicon thin film transistor; the first direction is the length direction of the channel region, and the second direction is the width direction of the channel region.

2. The array substrate of claim 1, wherein, The ratio of the length of a crystal grain along the first direction to the length of the crystal grain along the second direction in the channel of the first polysilicon thin film transistor is greater than or equal to 5:

1.

3. The array substrate of claim 1 or 2, wherein, The length of a crystal grain along the first direction is 1 μm to 10 μm, and the length of the crystal grain along the second direction is less than 1 μm in the channel of the first polysilicon thin film transistor.

4. The array substrate according to any one of claims 1 to 3, wherein, The same crystal grain penetrates the channel region along the first direction in the channel of the first polysilicon thin film transistor. A plurality of crystal grains are arranged side by side along the second direction in the channel of the first polysilicon thin film transistor.

5. The array substrate according to any one of claims 1 to 4, wherein, The array substrate further comprises:

6. The array substrate according to any one of claims 1 to 5, wherein, The mobility of the first poly-silicon thin film transistor is greater than 200 cm 2 (V-s).

7. The array substrate according to any one of claims 1 to 6, wherein, a single crystal silicon thin film transistor located on the same layer as the first polysilicon thin film transistor; only one crystal grain is included in a channel of the single crystal silicon thin film transistor. The array substrate further comprises:

8. The array substrate according to any one of claims 1 to 7, wherein, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor; the first polysilicon thin film transistor serves as a driving thin film transistor; the oxide semiconductor thin film transistor or the amorphous silicon thin film transistor serves as a switching thin film transistor. The array substrate further comprises:

9. The array substrate of claim 8, wherein, a buffer layer located between the substrate and the first polysilicon thin film transistor; a channel of the first polysilicon thin film transistor is formed on the buffer layer. The buffer layer comprises: a silicon nitride layer; 10. A display panel, wherein, a silicon oxide layer located on the side of the silicon nitride layer away from the substrate.

11. A method for manufacturing an array substrate, wherein, The array substrate comprises any one of claims 1 to 9. The array substrate comprises: forming a crystallization guide pattern on one side of a substrate; the crystallization guide pattern comprises a crystallization guide structure and a crystallization region defined by the crystallization guide structure; forming an amorphous silicon layer on the side of the crystallization guide pattern away from the substrate; performing a laser annealing process on the amorphous silicon layer to crystallize and grow the amorphous silicon layer into a polysilicon layer; 12. The method of claim 11, wherein, etching the polysilicon layer in the crystallization region to form a channel of a first polysilicon thin film transistor. The material of the crystallization guide structure is metal; the crystallization guide structure has a temperature resistance greater than or equal to 450 °C.

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