Communication method and apparatus of virtual machine, storage medium and electronic device

Abstract

The application provides a communication method and device of a virtual machine, a storage medium and an electronic device, and the method comprises the following steps: determining a first virtual machine and a second virtual machine to be communicated in a heterogeneous virtual chip of a host computer, wherein a guest computer of the host computer comprises the first virtual machine and the second virtual machine, the first virtual machine applies a processor of a first architecture, and the second virtual machine applies a processor of a second architecture; starting the first virtual machine and the second virtual machine, and initializing and configuring a virtual ring buffer vring for the first virtual machine and the second virtual machine on the host computer; determining first data to be transmitted by the first virtual machine; and transmitting the first data to the second virtual machine through the vring. Through the embodiment, the technical problem of low communication efficiency between heterogeneous CPUs across architectures in a heterogeneous virtual chip in the prior art is solved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more specifically, to a virtual machine communication method and apparatus, storage medium, and electronic device. Background Technology

[0002] In related technologies, virtualization technology mainly focuses on virtual resource management within homogeneous systems or single SoCs (System on Chip), such as KVM (Kernel-based Virtual Machine) virtualization for ARM A cores or emulation operation of MCUs (microcontroller units) (such as QEMU (Quick EMUlator) and TCG (Tiny Code Generator) modes), which achieve communication within the system through mechanisms such as shared memory and VirtIO (virtual input / output).

[0003] For heterogeneous chip architectures, a common technique is vsock + rpmsg to implement APM's IPC virtualization. vsock (virtual socket) and RPMsg (remote processor messaging) are two technologies commonly used in heterogeneous systems or virtualized environments to implement inter-processor communication (IPC). The vsock + rpmsg technique has the following drawbacks: 1. rpmsg and vsock are two different technologies with different interfaces and protocols. They are combined to implement AMP (Asymmetric Multiprocessing) IPC. When A core and M core communicate bidirectionally, the conversion between rpmsg and vsock information is required, which is why the vsock + rpmsg solution requires a proxy system for each of the A and M cores; 2. rpmsg only supports point-to-point communication, with each point-to-point communication being called a pair of cores. In a heterogeneous SoC, each pair of M cores-A cores and M cores-M cores requires a separate "statically allocated shared memory + interrupt number," which is cumbersome and resource-intensive. The situation is completely different when using vsock technology between A cores, making it impossible to achieve any combination of AA / AM / MM communication that can be dynamically added or removed; 3. Since the protocol data of vsock and rpmsg must be converted in shared memory and then kick (front-end notification) / notify (back-end notification), there are real-time issues; 4. rpmsg directly exposes the channel as a character tty, so the upper-layer application still sees a "serial port" file instead of a standard network, block device, etc., resulting in low cross-platform portability.

[0004] No efficient and accurate solution has yet been found to address the aforementioned issues in the relevant technologies. Summary of the Invention

[0005] This invention provides a communication method and apparatus for virtual machines, a storage medium, and an electronic device to solve technical problems in related technologies.

[0006] According to an embodiment of the present invention, a communication method for virtual machines is provided, comprising: determining a first virtual machine and a second virtual machine to communicate in heterogeneous virtual chips of a host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor of a first architecture, and the second virtual machine uses a processor of a second architecture; starting the first virtual machine and the second virtual machine, and initializing and configuring vring for the first virtual machine and the second virtual machine on the host machine; determining a first data to be transmitted by the first virtual machine; and transmitting the first data to the second virtual machine through the vring.

[0007] Optionally, initializing and configuring a vring for the first virtual machine and the second virtual machine on the host machine includes: performing GPA alignment on the first virtual machine and the second virtual machine; after GPA alignment, creating and mapping shared memory on the host machine; creating and configuring a vring on the shared memory; and adding communication logic to the vring, wherein the communication logic includes read / write logic, synchronization logic, and notification logic.

[0008] Optionally, GPA alignment for the first virtual machine and the second virtual machine includes: determining the common physical address range of the inter-core communication mechanism (IPC) of the heterogeneous virtual chip; and performing GPA alignment for the first virtual machine and the second virtual machine based on the common physical address range.

[0009] Optionally, transmitting the first data to the second virtual machine via the vring includes: responding to an IPC request from the first virtual machine by calling the virtual interface core communication driver of the first virtual machine; sending the first data to the virtual interface core communication driver; controlling the virtual interface core communication driver to transmit the first data to the vring; and controlling the virtual interface core communication driver to send a kick signal to the second virtual machine to notify the second virtual machine to read the first data from the vring.

[0010] Optionally, controlling the virtual interface inter-core communication driver to transmit the first data to the vring includes: controlling the virtual interface inter-core communication driver to locate the vring via MMIO; writing the first data into the vring; and performing a kick action, wherein the kick action is used to trigger a kick signal.

[0011] Optionally, controlling the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine includes one of the following: controlling the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine via a signal; controlling the virtual interface inter-core communication driver to synchronize the kick signal to the second virtual machine via shared memory.

[0012] Optionally, after transmitting the first data to the second virtual machine via the vring, the method further includes: responding to a kick signal to sense the second data to be transmitted by the second virtual machine; and reading the second data into the first virtual machine according to the kick signal.

[0013] Optionally, reading the second data into the first virtual machine according to the kick signal includes: injecting the kick signal into the virtual processor of the first virtual machine to cause the virtual processor to trigger an interrupt signal; responding to the interrupt signal, calling the virtual interface inter-core communication driver of the first virtual machine; and controlling the virtual interface inter-core communication driver to read the second data from the vring through mmio.

[0014] Optionally, the host machine's CPU is an x86 architecture or an arm64 architecture.

[0015] Optionally, the first virtual machine and the second virtual machine are respectively ARM A-core virtual machines and ARM M-core virtual machines, or the first virtual machine and the second virtual machine are both ARM A-core virtual machines, or the first virtual machine and the second virtual machine are both ARM M-core virtual machines.

[0016] According to another embodiment of the present invention, a communication device for virtual machines is provided, comprising: a first determining module, configured to determine a first virtual machine and a second virtual machine to communicate in heterogeneous virtualization chips of a host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor of a first architecture, and the second virtual machine uses a processor of a second architecture; a configuration module, configured to start the first virtual machine and the second virtual machine, and initialize and configure vring for the first virtual machine and the second virtual machine on the host machine; a second determining module, configured to determine a first data to be transmitted by the first virtual machine; and a transmission module, configured to transmit the first data to the second virtual machine through the vring.

[0017] Optionally, the configuration module includes: an alignment unit for performing Generalized Address Alignment (GPA) alignment on the first virtual machine and the second virtual machine; a creation unit for creating and mapping shared memory on the host machine after GPA alignment; a configuration unit for creating and configuring a vring on the shared memory; and an addition unit for adding communication logic to the vring, wherein the communication logic includes read / write logic, synchronization logic, and notification logic.

[0018] Optionally, the alignment unit includes: a determining subunit for determining the common physical address range of the inter-core communication mechanism (IPC) of the heterogeneous virtual chip; and an alignment subunit for performing GPA alignment on the first virtual machine and the second virtual machine based on the common physical address range.

[0019] Optionally, the transmission module includes: a calling unit, configured to respond to an IPC request from the first virtual machine and call the virtual interface core communication driver of the first virtual machine; a sending unit, configured to send the first data to the virtual interface core communication driver; a transmission unit, configured to control the virtual interface core communication driver to transmit the first data to the vring; and a notification unit, configured to control the virtual interface core communication driver to send a kick signal to the second virtual machine to notify the second virtual machine to read the first data from the vring.

[0020] Optionally, the transmission unit includes: a lookup subunit for controlling the virtual interface inter-core communication driver to look up the vring via mmio; and a write subunit for writing the first data into the vring and performing a kick action, wherein the kick action is used to trigger a kick signal.

[0021] Optionally, the notification unit includes one of the following: a transmission subunit, used to control the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine via a signal; and a synchronization subunit, used to control the virtual interface inter-core communication driver to synchronize the kick signal to the second virtual machine via shared memory.

[0022] Optionally, the method further includes: a sensing module, configured to sense second data to be transmitted by the second virtual machine in response to a kick signal after the transmission module transmits the first data to the second virtual machine via the vring; and a reading module, configured to read the second data into the first virtual machine according to the kick signal.

[0023] Optionally, the read-in module includes: an injection unit for injecting the kick signal into the virtual processor of the first virtual machine to trigger an interrupt signal; a calling unit for responding to the interrupt signal and calling the virtual interface inter-core communication driver of the first virtual machine; and a reading unit for controlling the virtual interface inter-core communication driver to read the second data from the vring via mmio.

[0024] Optionally, the host machine's CPU is an x86 architecture or an arm64 architecture.

[0025] Optionally, the first virtual machine and the second virtual machine are respectively ARM A-core virtual machines and ARM M-core virtual machines, or the first virtual machine and the second virtual machine are both ARM A-core virtual machines, or the first virtual machine and the second virtual machine are both ARM M-core virtual machines.

[0026] According to another aspect of the embodiments of this application, a storage medium is also provided, the storage medium including a stored program that executes the above steps when the program is run.

[0027] According to another aspect of the embodiments of this application, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above method by running the programs stored in the memory.

[0028] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the above-described method.

[0029] The beneficial effects of this invention are:

[0030] 1. virtio-mmio uses a unified protocol and interface, operates on a common vring, and does not require information protocol conversion between A cores and M cores, nor does it require a proxy system. The concept of IPC is simple and unified, and the interface provided for upper-layer applications is also simple and unified.

[0031] 2. Supports convenient AA / AM / MM core combinations. Adding inter-core communication only requires adding a reusable virtio device and virtio driver, providing strong scalability;

[0032] 3. Mutual notification of shared vrings, relying on the AMP IPC interrupt signal kick / notify, can achieve sub-microsecond notification latency, meeting real-time requirements;

[0033] 4. Based on the characteristics of vring itself, it can handle large-capacity data exchange between different virtual machines in heterogeneous virtual chips and achieve high bandwidth performance. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0035] Figure 1 This is a hardware structure block diagram of a car according to an embodiment of the present invention;

[0036] Figure 2 This is a flowchart of a virtual machine communication method according to an embodiment of the present invention;

[0037] Figure 3 This is an overall architecture diagram of an embodiment of the present invention;

[0038] Figure 4 This is a framework diagram of the platform bus driver for the virtual interface inter-core communication mechanism in this embodiment of the invention;

[0039] Figure 5 This is a framework diagram driven by the virtual interface inter-core communication mechanism in this embodiment of the invention;

[0040] Figure 6 This is a structural block diagram of a virtual machine communication device according to an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] Example 1

[0044] The method embodiment provided in Embodiment 1 of this application can be executed in an automobile, computer, server, autonomous driving / assisted driving / intelligent driving controller, or similar processing device. Taking its operation in an automobile as an example, Figure 1 This is a hardware structure block diagram of a car according to an embodiment of the present invention. For example... Figure 1 As shown, a car may include one or more ( Figure 1 Only one is shown in the image. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. Optionally, the vehicle may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned automobile. For example, the automobile may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0045] The memory 104 can be used to store automotive programs, such as application software programs and modules, like the automotive program corresponding to a communication method for a virtual machine in an automotive system according to an embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the automotive program stored in the memory 104, thereby implementing the aforementioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the vehicle via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0046] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a vehicle's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0047] This embodiment provides a communication method for virtual machines. Figure 2 This is a flowchart of a virtual machine communication method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0048] Step S201: Determine the first virtual machine and the second virtual machine to communicate in the heterogeneous virtual chip of the host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor with a first architecture, and the second virtual machine uses a processor with a second architecture.

[0049] Optionally, the chip architecture of the first virtual machine and the second virtual machine may be the same or different. For example, the first virtual SoC is an ARM A core and the second virtual SoC is an ARM M core, or both the first virtual machine and the second virtual machine are ARM A core virtual machines, or both the first virtual machine and the second virtual machine are ARM M core virtual machines. The ARM A core virtual machine can be an MPU (Microprocessor Unit), and the ARM M core virtual machine can be an MCU (Microcontroller Unit).

[0050] In this embodiment, the first virtual machine and the second virtual machine are based on two similar or different virtualization technologies. The implementation methods of the two different virtualization interrupt technologies are described below:

[0051] The first virtualization technology (QEMU, Quick EMUlator) executes its interrupt handlers by translating and parsing instructions one by one, resulting in some performance loss. Instruction set translation is the foundation of MCU virtualization technology. The process of implementing instruction set translation virtualization includes: First, the virtual clock device calls the simulated hardware interrupt callback function to send an interrupt to the virtual CPU; Second, the virtual CPU sets the interrupt bit; Third, the virtual CPU detects the interrupt bit, simulates hardware operation, and saves the interrupt status information; Fourth, the virtual CPU reads the interrupt handler; Fifth, the virtual CPU parses the interrupt handler, generates intermediate code (IR), optimizes the IR, generates executable instructions for the host machine, and executes the binary file generated by the host machine.

[0052] The second virtualization technology (KVM, Kernel-based Virtual Machine) is hardware-assisted virtualization. Because the execution of interrupt handlers based on this technology uses the physical CPU, its performance is close to that of real physical interrupts. Traditional hardware-assisted virtualization is implemented through interrupt injection. Although it has higher performance than pure software implementation, it still has performance bottlenecks. Taking x86 interrupt injection virtualization as an example, the implementation process includes: First, the virtual interrupt controller uses inter-core interrupts (IPI) to return the virtual machine from Guest mode (virtual machine mode) to host mode (VMM virtual machine monitor mode), and the virtual machine enters Hypervisor mode; Second, the interrupt vector information, mainly the interrupt vector table information, is written to the vmcs area; Third, the virtual machine is started using the vmresume or vmlaunch instructions.

[0053] Figure 3 This is an overall architecture diagram of an embodiment of the present invention, including a virtual system, a host system, and host hardware. The virtual system includes a first virtual machine (A core) and a second virtual machine (M core). The host system is a Linux system, in which vring runs in shared memory. The host system runs a first machine emulator qemu vm1 that interacts with the first virtual machine (synchronization / notification kick) and a second machine emulator qemu vm2 that interacts with the second virtual machine (synchronization / kick). qemu vm1 and qemu vm2 can perform read and write operations on vring.

[0054] Step S202: Start the first virtual machine and the second virtual machine, and initialize and configure vring for the first virtual machine and the second virtual machine on the host machine;

[0055] In this embodiment, the vring (Virtqueue Ring) is a circular buffer within Virtio (Virtual I / O, a standard I / O device framework in a virtualized environment, providing an efficient and unified virtual device interface), often shortened to virtual circular buffer. It's used for efficient data transfer between virtual devices and drivers, serving as the data transfer carrier between two virtual machines. The vring's storage logic includes: a Descriptor Table: storing buffer descriptors provided by the Guest, each descriptor containing information such as the data's physical address and length; an Available Ring: used by the Guest to announce newly available buffers to the Host; and a Used Ring: used by the Host to report processed buffers to the Guest.

[0056] In this embodiment, Vring is further configured with communication logic in order to enable interaction between virtual machines, based on the storage logic. This includes read-write (rw) logic, synchronization (sync) logic, and notification (kick) logic.

[0057] Step S203: Determine the first data to be transmitted by the first virtual machine;

[0058] Optionally, the first data is the data to be delivered to the second virtual machine in the heterogeneous virtual chip.

[0059] Step S204: The first data is transmitted to the second virtual machine via the vring.

[0060] Through the above steps, a first virtual machine and a second virtual machine to communicate in the heterogeneous virtual chip of the host machine are identified. The guest machine of the host machine includes the first virtual machine and the second virtual machine. The first virtual machine uses a processor with a first architecture, and the second virtual machine uses a processor with a second architecture. The first virtual machine and the second virtual machine are started, and vring is initialized and configured for the first virtual machine and the second virtual machine on the host machine. The first data to be transmitted by the first virtual machine is determined. The first data is transmitted to the second virtual machine through the vring. There is no need for information protocol conversion and proxy between virtual machines with different processor architectures, which solves the technical problem of low communication efficiency between heterogeneous CPUs across architectures in the prior art.

[0061] In one embodiment of this example, initializing and configuring a vring for the first virtual machine and the second virtual machine on the host machine includes: performing GPA alignment on the first virtual machine and the second virtual machine; after GPA alignment, creating and mapping shared memory on the host machine; creating and configuring a vring on the shared memory; and adding communication logic to the vring, wherein the communication logic includes read / write logic, synchronization logic, and notification logic.

[0062] The first and second virtual machines, as host processes, need to initialize their virtio (virtual interface, device abstraction layer in the paravirtualized hypervisor) IPC devices during startup, including: a. GPA (General Purpose Addresses) alignment; b. allocating and mapping shared memory; c. creating and configuring vring; d. adding rw / sync / kick logic to vring.

[0063] In one example, GPA alignment of the first virtual machine and the second virtual machine includes: determining the common physical address range of the inter-core communication mechanism (IPC) of the heterogeneous virtual chip; and performing GPA alignment of the first virtual machine and the second virtual machine based on the common physical address range.

[0064] To implement a semi-virtualized (virtio-mmio, Virtio Memory-Mapped I / O) scheme for IPC (Inter-Processor Communication) on AMP devices (heterogeneous virtual chips), the first step is to align the GPA (Gross Address Range) of the virtio-mmio IPC device (host machine) during mmio mapping. After GPA alignment, both IPC parties can operate on the vrings within shared memory. AMP hardware supports IPC and preserves a common physical address range for IPC functionality; this physical address range is the basis for GPA alignment of the virtio-mmio IPC device.

[0065] The virtio-mmio IPC device can be broken down into three functionalities: the virtio-mmio IPC device primarily handles MMIO mapping and GPA alignment; the QEMU backend in the host needs to manage shared memory; and vring creation, reading and writing, cross-virtual machine synchronization, and kick actions are handled. These three functionalities can be all written into the virtio-mmio IPC device or separated. When separated, MMIO mapping operates at the virtio protocol device layer; shared memory operates at the virtio device layer backend; and vring management and kick operations operate at the virtio protocol transport layer.

[0066] The virtio-mmio IPC device implementation only uses the AMP I / O range and its breakpoints. This embodiment does not need to call the logic specified by AMP's hardware I / O. This embodiment is semi-customized; therefore, this device has no driver in the guest environment and requires a semi-customized, self-written driver. For Linux virtual machines, a platform bus virtio-IPC device driver needs to be written. For RTOS / bare-metal virtual machines, a system-specific virtio-IPC device driver needs to be written. When there is an AMP (Asymmetric Multiprocessing) IPC (Inter-Processor Communication) requirement, the application should call the virtio-IPC driver. Once the virtio IPC driver is written for each operating system, it can be reused or easily ported to similar systems.

[0067] The virtual interface inter-core communication driver in this embodiment includes a virtual interface inter-core communication mechanism platform bus driver (virtio IPC platformbus driver) and a virtual interface inter-core communication mechanism driver (virtio IPC driver), which are applied to virtual machines with A-core and M-core respectively. Figure 4 This is a framework diagram of the platform bus driver for the virtual interface inter-core communication mechanism in this embodiment of the invention. It includes a virtual bus driver (virtio lPC virtiobus driver) and a platform bus virtual interface controller driver (platform bus virtio controller driver). They interact through the virtual interface bus (virtiobus). The functions of the virtual bus driver for the virtual interface inter-core communication mechanism include: processing by virtual interface inter-core communication devices through a virtual ring buffer, such as rw / sync / interrupt / kick; and detection and information acquisition by virtual interface inter-core communication devices, such as vring sensing. Figure 5This is a framework diagram of the virtual interface inter-core communication mechanism driver in this embodiment of the invention. It includes the virtual interface inter-core communication mechanism driver, and its functions include: virtual interface inter-core communication devices processing through a virtual ring buffer, such as rw / sync / interrupt / kick; virtual interface inter-core communication device detection and information acquisition, such as vring sensing.

[0068] In one embodiment of this example, transmitting the first data to the second virtual machine via the vring includes: responding to an IPC request from the first virtual machine by calling the virtual interface inter-core communication driver of the first virtual machine; sending the first data to the virtual interface inter-core communication driver; controlling the virtual interface inter-core communication driver to transmit the first data to the vring; and controlling the virtual interface inter-core communication driver to send a kick signal to the second virtual machine to notify the second virtual machine to read the first data from the vring.

[0069] In one example, controlling the virtual interface inter-core communication driver to transmit the first data to the vring includes: controlling the virtual interface inter-core communication driver to locate the vring via mmio; writing the first data into the vring; and performing a kick action, wherein the kick action is used to trigger a kick signal.

[0070] Optionally, controlling the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine includes one of the following: controlling the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine via a signal; controlling the virtual interface inter-core communication driver to synchronize the kick signal to the second virtual machine via shared memory.

[0071] Taking the data transfer from the first virtual machine (guest1) application to the second virtual machine (guest2) application as an example, the process during the two virtual runtimes includes: a. The guest1 application's IPC request and data are sent to the virtio IPC driver; b. The virtio IPC driver detects the vring through MMIO, writes the data to the vring without contention, and executes a kick action; c. The virtio IPC driver transmits the kick signal through signals or a shared memory + synchronization structure; d. Guest2 receives the kick signal and injects it into the vCPU (virtual processor); e. The guest2 driver receives an interrupt and executes the virtio IPC driver's action of reading the vring through MMIO; f. The data reaches the guest2 application.

[0072] In one implementation scenario of this embodiment, after transmitting the first data to the second virtual machine via the vring, the method further includes: responding to a kick signal to sense the second data to be transmitted by the second virtual machine; and reading the second data into the first virtual machine according to the kick signal.

[0073] Optionally, reading the second data into the first virtual machine according to the kick signal includes: injecting the kick signal into the virtual processor of the first virtual machine to cause the virtual processor to trigger an interrupt signal; responding to the interrupt signal, calling the virtual interface inter-core communication driver of the first virtual machine; and controlling the virtual interface inter-core communication driver to read the second data from the vring through mmio.

[0074] In this embodiment, the first virtual machine and the second virtual machine can transfer data to each other. That is, the first virtual machine can transmit first data to the second virtual machine through vring, and can also receive second data transmitted by the second virtual machine through vring.

[0075] Optionally, the CPU of the host (server) is an x86 architecture or an arm64 architecture.

[0076] When the host is an x86 architecture, shared memory management can use ivshmem (Inter-VM SharedMemory, a device provided by the QEMU / KVM virtualization platform for enabling shared memory communication between the host and virtual machines or multiple virtual machines) technology, or the traditional Linux shared memory interface. When the host is an x86 architecture, the execution of the A-core can only use the same code-native translation and emulation method as the M-core. Kick can only inject interrupts into the emulated CPU. When the host is an arm64 architecture, shared memory management can only use the traditional Linux shared memory interface. When the host is an arm64 architecture, and the host's CPU and the guest's A-core CPU are the same, the guest's A-core can enable virtualization extensions using KVM, which will have higher performance than the A-core's code-native translation and emulation. In this case, for the A-core, Kick can only inject interrupts into KVM. When the host is an arm64 architecture, and the host's CPU and the guest's A-core CPU are different, the execution of the A-core can only use the same code-native translation and emulation method as the M-core. Kick can only inject interrupts into the emulated CPU.

[0077] For Linux operating systems in virtual machines, the shared memory interface uses a unique identifier, the base key and shmid, which operate in master-slave mode. It requires specifying which memory is allocated first and which is shared later, thus it is simplex. To enable a core to function as both master and slave, the bidirectional master-slave memory sharing relationship between AM / MM / AA combinations needs to be pre-handled.

[0078] This embodiment provides a unified inter-core communication virtualization scheme based on virtio for heterogeneous SoCs, suitable for interoperability communication between multiprocessor systems with heterogeneous architectures such as ARM A-cores and MCUs (e.g., ARM M-cores) in a virtualized environment. Inter-core communication employs virtio-mmio technology, using vring as shared memory. Interrupt signals from the AMP's IPC module are used for kick / notify communication between A-cores, A-cores and M-cores, and M-cores.

[0079] The scheme in this embodiment simplifies and unifies the concept of AMP IPC, eliminating the need to consider differences between AMs and providing a unified model. Both virtio devices / drivers and vrings can be easily extended, exhibiting high scalability. vrings and interrupts bring high performance and real-time capabilities, achieving high performance. Virtio provides low coupling with the actual AMP IPC hardware, requiring only the use of the AMP IPC's interrupt number core I / O address space, thus exhibiting low coupling.

[0080] The solution in this embodiment is applicable to high-performance bandwidth scenarios, scenarios with frequent interaction with virtual machines, resource-constrained scenarios with high efficiency requirements, real-time scenarios, and scenarios with a unified software stack concept.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0082] Example 2

[0083] This embodiment also provides a communication device for a virtual machine, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0084] Figure 6 This is a structural block diagram of a virtual machine communication device according to an embodiment of the present invention, such as... Figure 6 As shown, the device includes:

[0085] The first determining module 61 is used to determine the first virtual machine and the second virtual machine to communicate in the heterogeneous virtual chip of the host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor with a first architecture, and the second virtual machine uses a processor with a second architecture.

[0086] Configuration module 62 is used to start the first virtual machine and the second virtual machine, and initialize and configure vring for the first virtual machine and the second virtual machine on the host machine;

[0087] The second determining module 63 is used to determine the first data to be transmitted by the first virtual machine;

[0088] The transmission module 64 is used to transmit the first data to the second virtual machine via the vring.

[0089] Optionally, the configuration module includes: an alignment unit for performing Generalized Address Alignment (GPA) alignment on the first virtual machine and the second virtual machine; a creation unit for creating and mapping shared memory on the host machine after GPA alignment; a configuration unit for creating and configuring a vring on the shared memory; and an addition unit for adding communication logic to the vring, wherein the communication logic includes read / write logic, synchronization logic, and notification logic.

[0090] Optionally, the alignment unit includes: a determining subunit for determining the common physical address range of the inter-core communication mechanism (IPC) of the heterogeneous virtual chip; and an alignment subunit for performing GPA alignment on the first virtual machine and the second virtual machine based on the common physical address range.

[0091] Optionally, the transmission module includes: a calling unit, configured to respond to an IPC request from the first virtual machine and call the virtual interface core communication driver of the first virtual machine; a sending unit, configured to send the first data to the virtual interface core communication driver; a transmission unit, configured to control the virtual interface core communication driver to transmit the first data to the vring; and a notification unit, configured to control the virtual interface core communication driver to send a kick signal to the second virtual machine to notify the second virtual machine to read the first data from the vring.

[0092] Optionally, the transmission unit includes: a lookup subunit for controlling the virtual interface inter-core communication driver to look up the vring via mmio; and a write subunit for writing the first data into the vring and performing a kick action, wherein the kick action is used to trigger a kick signal.

[0093] Optionally, the notification unit includes one of the following: a transmission subunit, used to control the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine via a signal; and a synchronization subunit, used to control the virtual interface inter-core communication driver to synchronize the kick signal to the second virtual machine via shared memory.

[0094] Optionally, the method further includes: a sensing module, configured to sense second data to be transmitted by the second virtual machine in response to a kick signal after the transmission module transmits the first data to the second virtual machine via the vring; and a reading module, configured to read the second data into the first virtual machine according to the kick signal.

[0095] Optionally, the read-in module includes: an injection unit for injecting the kick signal into the virtual processor of the first virtual machine to trigger an interrupt signal; a calling unit for responding to the interrupt signal and calling the virtual interface inter-core communication driver of the first virtual machine; and a reading unit for controlling the virtual interface inter-core communication driver to read the second data from the vring via mmio.

[0096] Optionally, the host machine's CPU is an x86 architecture or an arm64 architecture.

[0097] Optionally, the first virtual machine and the second virtual machine are respectively ARM A-core virtual machines and ARM M-core virtual machines, or the first virtual machine and the second virtual machine are both ARM A-core virtual machines, or the first virtual machine and the second virtual machine are both ARM M-core virtual machines.

[0098] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0099] Example 3

[0100] Embodiments of the present invention also provide a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0101] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0102] S1, determine the first virtual machine and the second virtual machine to communicate in the heterogeneous virtual chip of the host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor of a first architecture, and the second virtual machine uses a processor of a second architecture;

[0103] S2, start the first virtual machine and the second virtual machine, and initialize the vring configuration for the first virtual machine and the second virtual machine on the host machine;

[0104] S3, determine the first data to be transmitted by the first virtual machine;

[0105] S4, the first data is transmitted to the second virtual machine via the vring.

[0106] Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0107] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0108] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0109] Optionally, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0110] S1, determine the first virtual machine and the second virtual machine to communicate in the heterogeneous virtual chip of the host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor of a first architecture, and the second virtual machine uses a processor of a second architecture;

[0111] S2, start the first virtual machine and the second virtual machine, and initialize the vring configuration for the first virtual machine and the second virtual machine on the host machine;

[0112] S3, determine the first data to be transmitted by the first virtual machine;

[0113] S4, the first data is transmitted to the second virtual machine via the vring.

[0114] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0115] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0117] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0118] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A communication method for a virtual machine, characterized in that, include: The host machine's heterogeneous virtual machine chip is used to identify a first virtual machine and a second virtual machine that need to communicate, wherein the host machine's guest includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor with a first architecture, and the second virtual machine uses a processor with a second architecture. Start the first virtual machine and the second virtual machine, and initialize and configure the virtual ring buffer vring for the first virtual machine and the second virtual machine on the host machine; Determine the first data to be transmitted by the first virtual machine; The first data is transmitted to the second virtual machine via the vring; The initial configuration of vrings for the first and second virtual machines on the host machine includes: performing GPA alignment on the first and second virtual machines; creating and mapping shared memory on the host machine after GPA alignment; creating and configuring vrings on the shared memory; adding communication logic to the vrings, wherein the communication logic includes read / write logic, synchronization logic, and notification logic; and performing GPA alignment on the first and second virtual machines includes: determining the common physical address range of the inter-core communication mechanism (IPC) of the heterogeneous virtual chip; and performing GPA alignment on the first and second virtual machines based on the common physical address range.

2. The method according to claim 1, characterized in that, Transmitting the first data to the second virtual machine via the vring includes: In response to the IPC request of the first virtual machine, the virtual interface inter-core communication driver of the first virtual machine is invoked; The first data is sent to the virtual interface inter-core communication driver; The virtual interface inter-core communication driver is controlled to transmit the first data to the vring; The virtual interface inter-core communication driver controls the transmission of a kick signal to the second virtual machine to notify the second virtual machine to read the first data from the vring.

3. The method according to claim 2, characterized in that, Controlling the virtual interface inter-core communication driver to transmit the first data to the vring includes: The inter-core communication driver controlling the virtual interface locates the vring via memory-mapped input / output (MMIO). The first data is written into the vring, and a kick action is performed, wherein the kick action is used to trigger a kick signal.

4. The method according to claim 2, characterized in that, Controlling the virtual interface inter-core communication driver to transmit a kick signal to the second virtual machine includes one of the following: The virtual interface inter-core communication driver controls the transmission of a kick signal to the second virtual machine via a signal. The inter-core communication driver controlling the virtual interface synchronizes the kick signal to the second virtual machine via shared memory.

5. The method according to claim 1, characterized in that, After transmitting the first data to the second virtual machine via the vring, the method further includes: Responding to the kick signal, the second virtual machine senses the second data to be transmitted. The second data is read into the first virtual machine according to the kick signal.

6. The method according to claim 5, characterized in that, Reading the second data into the first virtual machine according to the kick signal includes: The kick signal is injected into the virtual processor of the first virtual machine to cause the virtual processor to trigger an interrupt signal; In response to the interrupt signal, the virtual interface inter-core communication driver of the first virtual machine is invoked; The inter-core communication driver controlling the virtual interface reads the second data from the vring via mmio.

7. The method according to any one of claims 1 to 6, characterized in that, The host machine's processor CPU is an x86 architecture or an arm64 architecture.

8. The method according to any one of claims 1 to 6, characterized in that, The first virtual machine and the second virtual machine are respectively ARM A-core virtual machines and ARM M-core virtual machines, or the first virtual machine and the second virtual machine are both ARM A-core virtual machines, or the first virtual machine and the second virtual machine are both ARM M-core virtual machines.

9. A communication device for a virtual machine, characterized in that, include: The first determining module is used to determine the first virtual machine and the second virtual machine to communicate in the heterogeneous virtual chip of the host machine, wherein the guest machine of the host machine includes the first virtual machine and the second virtual machine, the first virtual machine uses a processor of a first architecture, and the second virtual machine uses a processor of a second architecture. The configuration module is used to start the first virtual machine and the second virtual machine, and initialize the configuration of vring for the first virtual machine and the second virtual machine on the host machine; The second determining module is used to determine the first data to be transmitted by the first virtual machine; The transmission module is used to transmit the first data to the second virtual machine via the vring; The configuration module includes: an alignment unit for performing General Purpose Address (GPA) alignment on the first virtual machine and the second virtual machine; a creation unit for creating and mapping shared memory on the host machine after GPA alignment; a configuration unit for creating and configuring a virtual ring on the shared memory; and an addition unit for adding communication logic to the virtual ring, wherein the communication logic includes read / write logic, synchronization logic, and notification logic. The alignment unit includes: a determination subunit for determining the common physical address range of the inter-core communication mechanism (IPC) of the heterogeneous virtual machine; and an alignment subunit for performing GPA alignment on the first virtual machine and the second virtual machine based on the common physical address range.

10. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 8 when it is run.

11. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method as described in any one of claims 1 to 8.

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